vdec.c 70 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/of.h>
  9. #include <linux/wait.h>
  10. #include <linux/list.h>
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/uaccess.h>
  14. #include <linux/cdev.h>
  15. #include <linux/slab.h>
  16. #include <linux/of_address.h>
  17. #include <linux/sched.h>
  18. #include <linux/sched/signal.h>
  19. #include <linux/version.h>
  20. #include <linux/kfifo.h>
  21. #include <linux/kthread.h>
  22. #include <asm/io.h>
  23. #include <soc/starfive/vic7100.h>
  24. #include "../../../vpuapi/vpuconfig.h"
  25. #include "vpu.h"
  26. //#define ENABLE_DEBUG_MSG
  27. #ifdef ENABLE_DEBUG_MSG
  28. #define DPRINTK(args...) printk(KERN_INFO args);
  29. #else
  30. #define DPRINTK(args...)
  31. #endif
  32. /* definitions to be changed as customer configuration */
  33. /* if you want to have clock gating scheme frame by frame */
  34. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  35. /* if the driver want to use interrupt service from kernel ISR */
  36. #define VPU_SUPPORT_ISR
  37. #ifdef VPU_SUPPORT_ISR
  38. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  39. //#define VPU_IRQ_CONTROL
  40. #endif
  41. /* if clktree is work,try this...*/
  42. //#define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  43. /* if the platform driver knows the name of this driver */
  44. /* VPU_PLATFORM_DEVICE_NAME */
  45. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  46. /* if this driver knows the dedicated video memory address */
  47. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  48. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  49. #define VPU_CLK_NAME "vcodec"
  50. #define VPU_DEV_NAME "vdec"
  51. /* if the platform driver knows this driver */
  52. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  53. #define VPU_REG_BASE_ADDR 0x118F0000
  54. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  55. #ifdef VPU_SUPPORT_ISR
  56. #define VPU_IRQ_NUM (23)
  57. #endif
  58. /* this definition is only for chipsnmedia FPGA board env */
  59. /* so for SOC env of customers can be ignored */
  60. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  61. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  62. #endif
  63. struct device *vpu_dev;
  64. typedef struct vpu_drv_context_t {
  65. struct fasync_struct *async_queue;
  66. #ifdef SUPPORT_MULTI_INST_INTR
  67. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  68. #else
  69. unsigned long interrupt_reason;
  70. #endif
  71. u32 open_count; /*!<< device reference count. Not instance count */
  72. } vpu_drv_context_t;
  73. /* To track the allocated memory buffer */
  74. typedef struct vpudrv_buffer_pool_t {
  75. struct list_head list;
  76. struct vpudrv_buffer_t vb;
  77. struct file *filp;
  78. } vpudrv_buffer_pool_t;
  79. /* To track the instance index and buffer in instance pool */
  80. typedef struct vpudrv_instanace_list_t {
  81. struct list_head list;
  82. unsigned long inst_idx;
  83. unsigned long core_idx;
  84. struct file *filp;
  85. } vpudrv_instanace_list_t;
  86. typedef struct vpudrv_instance_pool_t {
  87. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  88. } vpudrv_instance_pool_t;
  89. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  90. typedef struct vpu_clkgen_t {
  91. void __iomem *en_ctrl;
  92. uint32_t rst_mask;
  93. } vpu_clkgen_t;
  94. #endif
  95. typedef struct vpu_clk_t {
  96. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  97. void __iomem *rst_ctrl;
  98. void __iomem *rst_status;
  99. uint32_t en_shift;
  100. uint32_t en_mask;
  101. vpu_clkgen_t apb_clk;
  102. vpu_clkgen_t axi_clk;
  103. vpu_clkgen_t bpu_clk;
  104. vpu_clkgen_t vce_clk;
  105. vpu_clkgen_t aximem_128b;
  106. #else
  107. struct clk *apb_clk;
  108. struct clk *axi_clk;
  109. struct clk *bpu_clk;
  110. struct clk *vce_clk;
  111. struct clk *aximem_128b;
  112. #endif
  113. void __iomem *clkgen;
  114. phys_addr_t pmu_base;
  115. void __iomem *noc_bus;
  116. bool noc_ctrl;
  117. } vpu_clk_t;
  118. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  119. #include "vmm.h"
  120. static video_mm_t s_vmem;
  121. static vpudrv_buffer_t s_video_memory = {0};
  122. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  123. static int vpu_hw_reset(void);
  124. static void vpu_clk_disable(vpu_clk_t *clk);
  125. static int vpu_clk_enable(vpu_clk_t *clk);
  126. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  127. static void vpu_clk_put(vpu_clk_t *clk);
  128. /* end customer definition */
  129. static vpudrv_buffer_t s_instance_pool = {0};
  130. static vpudrv_buffer_t s_common_memory = {0};
  131. static vpu_drv_context_t s_vpu_drv_context;
  132. static int s_vpu_major;
  133. static struct cdev s_vpu_cdev;
  134. static vpu_clk_t *s_vpu_clk;
  135. static int s_vpu_open_ref_count;
  136. #ifdef VPU_SUPPORT_ISR
  137. static int s_vpu_irq = VPU_IRQ_NUM;
  138. #endif
  139. static vpudrv_buffer_t s_vpu_register = {0};
  140. #ifdef SUPPORT_MULTI_INST_INTR
  141. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  142. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  143. typedef struct kfifo kfifo_t;
  144. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  145. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  146. #else
  147. static int s_interrupt_flag;
  148. static wait_queue_head_t s_interrupt_wait_q;
  149. #endif
  150. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  151. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  152. static DECLARE_MUTEX(s_vpu_sem);
  153. #else
  154. static DEFINE_SEMAPHORE(s_vpu_sem);
  155. #endif
  156. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  157. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  158. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  159. //#ifdef CONFIG_PM
  160. /* implement to power management functions */
  161. #define BIT_BASE 0x0000
  162. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  163. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  164. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  165. #define BIT_INT_STS (BIT_BASE + 0x010)
  166. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  167. #define BIT_INT_REASON (BIT_BASE + 0x174)
  168. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  169. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  170. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  171. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  172. /* WAVE5 registers */
  173. #define W5_REG_BASE 0x0000
  174. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  175. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  176. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  177. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  178. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  179. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  180. #ifdef SUPPORT_MULTI_INST_INTR
  181. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  182. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  183. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  184. typedef enum {
  185. INT_WAVE5_INIT_VPU = 0,
  186. INT_WAVE5_WAKEUP_VPU = 1,
  187. INT_WAVE5_SLEEP_VPU = 2,
  188. INT_WAVE5_CREATE_INSTANCE = 3,
  189. INT_WAVE5_FLUSH_INSTANCE = 4,
  190. INT_WAVE5_DESTORY_INSTANCE = 5,
  191. INT_WAVE5_INIT_SEQ = 6,
  192. INT_WAVE5_SET_FRAMEBUF = 7,
  193. INT_WAVE5_DEC_PIC = 8,
  194. INT_WAVE5_ENC_PIC = 8,
  195. INT_WAVE5_ENC_SET_PARAM = 9,
  196. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  197. INT_WAVE5_ENC_SRC_RELEASE = 10,
  198. #endif
  199. INT_WAVE5_ENC_LOW_LATENCY = 13,
  200. INT_WAVE5_DEC_QUERY = 14,
  201. INT_WAVE5_BSBUF_EMPTY = 15,
  202. INT_WAVE5_BSBUF_FULL = 15,
  203. } Wave5InterruptBit;
  204. #endif
  205. /* WAVE5 INIT, WAKEUP */
  206. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  207. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  208. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  209. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  210. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  211. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  212. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  213. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  214. #define W5_REMAP_CODE_INDEX 0
  215. /* WAVE5 registers */
  216. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  217. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  218. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  219. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  220. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  221. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  222. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  223. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  224. /* Product register */
  225. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  226. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  227. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  228. #endif
  229. //#endif //CONFIG_PM
  230. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  231. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  232. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  233. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  234. {
  235. if (!vb)
  236. return -1;
  237. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  238. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  239. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  240. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  241. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  242. return -1;
  243. }
  244. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  245. #else
  246. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  247. if ((void *)(vb->base) == NULL) {
  248. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  249. return -1;
  250. }
  251. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  252. #endif
  253. return 0;
  254. }
  255. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  256. {
  257. if (!vb)
  258. return;
  259. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  260. if (vb->base)
  261. vmem_free(&s_vmem, vb->phys_addr, 0);
  262. #else
  263. if (vb->base)
  264. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  265. #endif
  266. }
  267. static int vpu_free_instances(struct file *filp)
  268. {
  269. vpudrv_instanace_list_t *vil, *n;
  270. vpudrv_instance_pool_t *vip;
  271. void *vip_base;
  272. int instance_pool_size_per_core;
  273. void *vdi_mutexes_base;
  274. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  275. DPRINTK("[VPUDRV] vpu_free_instances\n");
  276. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  277. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  278. {
  279. if (vil->filp == filp) {
  280. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  281. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  282. vip = (vpudrv_instance_pool_t *)vip_base;
  283. if (vip) {
  284. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  285. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  286. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  287. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  288. if (vdi_mutexes_base) {
  289. int i;
  290. for (i = 0; i < 4; i++) {
  291. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  292. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  293. }
  294. }
  295. }
  296. s_vpu_open_ref_count--;
  297. list_del(&vil->list);
  298. kfree(vil);
  299. }
  300. }
  301. return 1;
  302. }
  303. static int vpu_free_buffers(struct file *filp)
  304. {
  305. vpudrv_buffer_pool_t *pool, *n;
  306. vpudrv_buffer_t vb;
  307. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  308. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  309. {
  310. if (pool->filp == filp) {
  311. vb = pool->vb;
  312. if (vb.base) {
  313. vpu_free_dma_buffer(&vb);
  314. list_del(&pool->list);
  315. kfree(pool);
  316. }
  317. }
  318. }
  319. return 0;
  320. }
  321. #ifdef SUPPORT_MULTI_INST_INTR
  322. static inline u32 get_inst_idx(u32 reg_val)
  323. {
  324. u32 inst_idx;
  325. int i;
  326. for (i=0; i < MAX_NUM_INSTANCE; i++)
  327. {
  328. if(((reg_val >> i)&0x01) == 1)
  329. break;
  330. }
  331. inst_idx = i;
  332. return inst_idx;
  333. }
  334. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  335. {
  336. s32 inst_idx;
  337. u32 reg_val;
  338. u32 int_reason;
  339. int_reason = *reason;
  340. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  341. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  342. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  343. {
  344. reg_val = (empty_inst & 0xffff);
  345. inst_idx = get_inst_idx(reg_val);
  346. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  347. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  348. goto GET_VPU_INST_IDX_HANDLED;
  349. }
  350. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  351. {
  352. reg_val = (seq_inst & 0xffff);
  353. inst_idx = get_inst_idx(reg_val);
  354. *reason = (1 << INT_WAVE5_INIT_SEQ);
  355. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  356. goto GET_VPU_INST_IDX_HANDLED;
  357. }
  358. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  359. {
  360. reg_val = (done_inst & 0xffff);
  361. inst_idx = get_inst_idx(reg_val);
  362. *reason = (1 << INT_WAVE5_DEC_PIC);
  363. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  364. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  365. {
  366. u32 ll_inst_idx;
  367. reg_val = (done_inst >> 16);
  368. ll_inst_idx = get_inst_idx(reg_val);
  369. if (ll_inst_idx == inst_idx)
  370. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  371. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  372. }
  373. goto GET_VPU_INST_IDX_HANDLED;
  374. }
  375. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  376. {
  377. reg_val = (seq_inst & 0xffff);
  378. inst_idx = get_inst_idx(reg_val);
  379. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  380. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  381. goto GET_VPU_INST_IDX_HANDLED;
  382. }
  383. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  384. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  385. {
  386. reg_val = (done_inst & 0xffff);
  387. inst_idx = get_inst_idx(reg_val);
  388. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  389. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  390. goto GET_VPU_INST_IDX_HANDLED;
  391. }
  392. #endif
  393. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  394. {
  395. reg_val = (done_inst >> 16);
  396. inst_idx = get_inst_idx(reg_val);
  397. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  398. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  399. goto GET_VPU_INST_IDX_HANDLED;
  400. }
  401. inst_idx = -1;
  402. *reason = 0;
  403. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  404. GET_VPU_INST_IDX_HANDLED:
  405. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  406. return inst_idx;
  407. }
  408. #endif
  409. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  410. {
  411. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  412. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  413. int core;
  414. int product_code;
  415. #ifdef SUPPORT_MULTI_INST_INTR
  416. u32 intr_reason;
  417. s32 intr_inst_index;
  418. #endif
  419. DPRINTK("[VPUDRV][+]%s\n", __func__);
  420. #ifdef VPU_IRQ_CONTROL
  421. disable_irq_nosync(s_vpu_irq);
  422. #endif
  423. #ifdef SUPPORT_MULTI_INST_INTR
  424. intr_inst_index = 0;
  425. intr_reason = 0;
  426. #endif
  427. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  428. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  429. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  430. continue;
  431. }
  432. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  433. if (PRODUCT_CODE_W_SERIES(product_code)) {
  434. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  435. #ifdef SUPPORT_MULTI_INST_INTR
  436. u32 empty_inst;
  437. u32 done_inst;
  438. u32 seq_inst;
  439. u32 i, reason, reason_clr;
  440. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  441. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  442. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  443. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  444. reason_clr = reason;
  445. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  446. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  447. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  448. intr_reason = reason;
  449. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  450. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  451. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  452. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  453. empty_inst = empty_inst & ~(1 << intr_inst_index);
  454. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  455. if (0 == empty_inst) {
  456. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  457. }
  458. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  459. }
  460. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  461. {
  462. done_inst = done_inst & ~(1 << intr_inst_index);
  463. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  464. if (0 == done_inst) {
  465. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  466. }
  467. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  468. }
  469. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  470. {
  471. seq_inst = seq_inst & ~(1 << intr_inst_index);
  472. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  473. if (0 == seq_inst) {
  474. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  475. }
  476. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  477. }
  478. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  479. {
  480. done_inst = (done_inst >> 16);
  481. done_inst = done_inst & ~(1 << intr_inst_index);
  482. done_inst = (done_inst << 16);
  483. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  484. if (0 == done_inst) {
  485. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  486. }
  487. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  488. }
  489. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  490. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  491. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  492. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  493. }
  494. else
  495. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  496. }
  497. else {
  498. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  499. }
  500. }
  501. else {
  502. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  503. }
  504. }
  505. if (0 != reason)
  506. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  507. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  508. #else
  509. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  510. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  511. #endif
  512. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  513. }
  514. }
  515. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  516. if (ReadVpuRegister(BIT_INT_STS)) {
  517. #ifdef SUPPORT_MULTI_INST_INTR
  518. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  519. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  520. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  521. #else
  522. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  523. #endif
  524. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  525. }
  526. }
  527. else {
  528. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  529. continue;
  530. }
  531. #ifdef SUPPORT_MULTI_INST_INTR
  532. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  533. #else
  534. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  535. #endif
  536. }
  537. if (dev->async_queue)
  538. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  539. #ifdef SUPPORT_MULTI_INST_INTR
  540. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  541. s_interrupt_flag[intr_inst_index]= 1;
  542. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  543. }
  544. #else
  545. s_interrupt_flag = 1;
  546. wake_up_interruptible(&s_interrupt_wait_q);
  547. #endif
  548. DPRINTK("[VPUDRV][-]%s\n", __func__);
  549. return IRQ_HANDLED;
  550. }
  551. static int vpu_open(struct inode *inode, struct file *filp)
  552. {
  553. DPRINTK("[VPUDRV][+] %s\n", __func__);
  554. spin_lock(&s_vpu_lock);
  555. s_vpu_drv_context.open_count++;
  556. filp->private_data = (void *)(&s_vpu_drv_context);
  557. spin_unlock(&s_vpu_lock);
  558. DPRINTK("[VPUDRV][-] %s\n", __func__);
  559. return 0;
  560. }
  561. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  562. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  563. {
  564. int ret = 0;
  565. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  566. switch (cmd) {
  567. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  568. {
  569. vpudrv_buffer_pool_t *vbp;
  570. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  571. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  572. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  573. if (!vbp) {
  574. up(&s_vpu_sem);
  575. return -ENOMEM;
  576. }
  577. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  578. if (ret) {
  579. kfree(vbp);
  580. up(&s_vpu_sem);
  581. return -EFAULT;
  582. }
  583. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  584. if (ret == -1) {
  585. ret = -ENOMEM;
  586. kfree(vbp);
  587. up(&s_vpu_sem);
  588. break;
  589. }
  590. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  591. if (ret) {
  592. kfree(vbp);
  593. ret = -EFAULT;
  594. up(&s_vpu_sem);
  595. break;
  596. }
  597. vbp->filp = filp;
  598. spin_lock(&s_vpu_lock);
  599. list_add(&vbp->list, &s_vbp_head);
  600. spin_unlock(&s_vpu_lock);
  601. up(&s_vpu_sem);
  602. }
  603. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  604. }
  605. break;
  606. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  607. {
  608. vpudrv_buffer_pool_t *vbp, *n;
  609. vpudrv_buffer_t vb;
  610. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  611. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  612. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  613. if (ret) {
  614. up(&s_vpu_sem);
  615. return -EACCES;
  616. }
  617. if (vb.base)
  618. vpu_free_dma_buffer(&vb);
  619. spin_lock(&s_vpu_lock);
  620. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  621. {
  622. if (vbp->vb.base == vb.base) {
  623. list_del(&vbp->list);
  624. kfree(vbp);
  625. break;
  626. }
  627. }
  628. spin_unlock(&s_vpu_lock);
  629. up(&s_vpu_sem);
  630. }
  631. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  632. }
  633. break;
  634. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  635. {
  636. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  637. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  638. if (s_video_memory.base != 0) {
  639. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  640. if (ret != 0)
  641. ret = -EFAULT;
  642. } else {
  643. ret = -EFAULT;
  644. }
  645. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  646. #endif
  647. }
  648. break;
  649. case VDI_IOCTL_WAIT_INTERRUPT:
  650. {
  651. vpudrv_intr_info_t info;
  652. #ifdef SUPPORT_MULTI_INST_INTR
  653. u32 intr_inst_index;
  654. u32 intr_reason_in_q;
  655. u32 interrupt_flag_in_q;
  656. #endif
  657. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  658. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  659. if (ret != 0)
  660. {
  661. return -EFAULT;
  662. }
  663. #ifdef SUPPORT_MULTI_INST_INTR
  664. intr_inst_index = info.intr_inst_index;
  665. intr_reason_in_q = 0;
  666. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  667. if (interrupt_flag_in_q > 0)
  668. {
  669. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  670. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  671. goto INTERRUPT_REMAIN_IN_QUEUE;
  672. }
  673. #endif
  674. #ifdef SUPPORT_MULTI_INST_INTR
  675. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  676. kt = ktime_set(0, info.timeout*1000*1000);
  677. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  678. #else
  679. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  680. #endif
  681. #else
  682. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  683. #endif
  684. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  685. if (ret == -ETIME) {
  686. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  687. break;
  688. }
  689. #endif
  690. if (!ret) {
  691. ret = -ETIME;
  692. break;
  693. }
  694. if (signal_pending(current)) {
  695. ret = -ERESTARTSYS;
  696. break;
  697. }
  698. #ifdef SUPPORT_MULTI_INST_INTR
  699. intr_reason_in_q = 0;
  700. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  701. if (interrupt_flag_in_q > 0) {
  702. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  703. }
  704. else {
  705. dev->interrupt_reason[intr_inst_index] = 0;
  706. }
  707. #endif
  708. #ifdef SUPPORT_MULTI_INST_INTR
  709. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  710. #else
  711. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  712. #endif
  713. #ifdef SUPPORT_MULTI_INST_INTR
  714. INTERRUPT_REMAIN_IN_QUEUE:
  715. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  716. s_interrupt_flag[intr_inst_index] = 0;
  717. dev->interrupt_reason[intr_inst_index] = 0;
  718. #else
  719. info.intr_reason = dev->interrupt_reason;
  720. s_interrupt_flag = 0;
  721. dev->interrupt_reason = 0;
  722. #endif
  723. #ifdef VPU_IRQ_CONTROL
  724. enable_irq(s_vpu_irq);
  725. #endif
  726. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  727. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  728. if (ret != 0)
  729. {
  730. return -EFAULT;
  731. }
  732. }
  733. break;
  734. case VDI_IOCTL_SET_CLOCK_GATE:
  735. {
  736. u32 clkgate;
  737. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  738. if (get_user(clkgate, (u32 __user *) arg))
  739. return -EFAULT;
  740. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  741. if (clkgate)
  742. vpu_clk_enable(s_vpu_clk);
  743. else
  744. vpu_clk_disable(s_vpu_clk);
  745. #endif
  746. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  747. }
  748. break;
  749. case VDI_IOCTL_GET_INSTANCE_POOL:
  750. {
  751. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  752. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  753. if (s_instance_pool.base != 0) {
  754. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  755. if (ret != 0)
  756. ret = -EFAULT;
  757. } else {
  758. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  759. if (ret == 0) {
  760. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  761. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  762. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  763. s_instance_pool.phys_addr = s_instance_pool.base;
  764. if (s_instance_pool.base != 0)
  765. #else
  766. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  767. #endif
  768. {
  769. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  770. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  771. if (ret == 0) {
  772. /* success to get memory for instance pool */
  773. up(&s_vpu_sem);
  774. break;
  775. }
  776. }
  777. }
  778. ret = -EFAULT;
  779. }
  780. up(&s_vpu_sem);
  781. }
  782. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  783. }
  784. break;
  785. case VDI_IOCTL_GET_COMMON_MEMORY:
  786. {
  787. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  788. if (s_common_memory.base != 0) {
  789. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  790. if (ret != 0)
  791. ret = -EFAULT;
  792. } else {
  793. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  794. if (ret == 0) {
  795. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  796. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  797. if (ret == 0) {
  798. /* success to get memory for common memory */
  799. break;
  800. }
  801. }
  802. }
  803. ret = -EFAULT;
  804. }
  805. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  806. }
  807. break;
  808. case VDI_IOCTL_OPEN_INSTANCE:
  809. {
  810. vpudrv_inst_info_t inst_info;
  811. vpudrv_instanace_list_t *vil, *n;
  812. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  813. if (!vil)
  814. return -ENOMEM;
  815. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  816. return -EFAULT;
  817. vil->inst_idx = inst_info.inst_idx;
  818. vil->core_idx = inst_info.core_idx;
  819. vil->filp = filp;
  820. spin_lock(&s_vpu_lock);
  821. list_add(&vil->list, &s_inst_list_head);
  822. inst_info.inst_open_count = 0; /* counting the current open instance number */
  823. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  824. {
  825. if (vil->core_idx == inst_info.core_idx)
  826. inst_info.inst_open_count++;
  827. }
  828. #ifdef SUPPORT_MULTI_INST_INTR
  829. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  830. #endif
  831. spin_unlock(&s_vpu_lock);
  832. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  833. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  834. kfree(vil);
  835. return -EFAULT;
  836. }
  837. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  838. }
  839. break;
  840. case VDI_IOCTL_CLOSE_INSTANCE:
  841. {
  842. vpudrv_inst_info_t inst_info;
  843. vpudrv_instanace_list_t *vil, *n;
  844. u32 found = 0;
  845. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  846. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  847. return -EFAULT;
  848. spin_lock(&s_vpu_lock);
  849. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  850. {
  851. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  852. list_del(&vil->list);
  853. kfree(vil);
  854. found = 1;
  855. break;
  856. }
  857. }
  858. if (0 == found) {
  859. spin_unlock(&s_vpu_lock);
  860. return -EINVAL;
  861. }
  862. inst_info.inst_open_count = 0; /* counting the current open instance number */
  863. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  864. {
  865. if (vil->core_idx == inst_info.core_idx)
  866. inst_info.inst_open_count++;
  867. }
  868. #ifdef SUPPORT_MULTI_INST_INTR
  869. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  870. #endif
  871. spin_unlock(&s_vpu_lock);
  872. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  873. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  874. return -EFAULT;
  875. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  876. }
  877. break;
  878. case VDI_IOCTL_GET_INSTANCE_NUM:
  879. {
  880. vpudrv_inst_info_t inst_info;
  881. vpudrv_instanace_list_t *vil, *n;
  882. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  883. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  884. if (ret != 0)
  885. break;
  886. spin_lock(&s_vpu_lock);
  887. inst_info.inst_open_count = 0;
  888. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  889. {
  890. if (vil->core_idx == inst_info.core_idx)
  891. inst_info.inst_open_count++;
  892. }
  893. spin_unlock(&s_vpu_lock);
  894. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  895. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  896. }
  897. break;
  898. case VDI_IOCTL_RESET:
  899. {
  900. vpu_hw_reset();
  901. }
  902. break;
  903. case VDI_IOCTL_GET_REGISTER_INFO:
  904. {
  905. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  906. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  907. if (ret != 0)
  908. ret = -EFAULT;
  909. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  910. }
  911. break;
  912. case VDI_IOCTL_FLUSH_DCACHE:
  913. {
  914. vpudrv_flush_cache_t cache_info;
  915. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  916. if (ret != 0)
  917. ret = -EFAULT;
  918. if(cache_info.flag)
  919. starfive_flush_dcache(cache_info.start,cache_info.size);
  920. break;
  921. }
  922. default:
  923. {
  924. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  925. }
  926. break;
  927. }
  928. return ret;
  929. }
  930. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  931. {
  932. return -1;
  933. }
  934. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  935. {
  936. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  937. if (!buf) {
  938. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  939. return -EFAULT;
  940. }
  941. if (len == sizeof(vpu_bit_firmware_info_t)) {
  942. vpu_bit_firmware_info_t *bit_firmware_info;
  943. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  944. if (!bit_firmware_info) {
  945. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  946. return -EFAULT;
  947. }
  948. if (copy_from_user(bit_firmware_info, buf, len)) {
  949. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  950. return -EFAULT;
  951. }
  952. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  953. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  954. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  955. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  956. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  957. return -ENODEV;
  958. }
  959. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  960. kfree(bit_firmware_info);
  961. return len;
  962. }
  963. kfree(bit_firmware_info);
  964. }
  965. return -1;
  966. }
  967. static int vpu_release(struct inode *inode, struct file *filp)
  968. {
  969. int ret = 0;
  970. u32 open_count;
  971. #ifdef SUPPORT_MULTI_INST_INTR
  972. int i;
  973. #endif
  974. DPRINTK("[VPUDRV] vpu_release\n");
  975. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  976. /* found and free the not handled buffer by user applications */
  977. vpu_free_buffers(filp);
  978. /* found and free the not closed instance by user applications */
  979. vpu_free_instances(filp);
  980. spin_lock(&s_vpu_lock);
  981. s_vpu_drv_context.open_count--;
  982. open_count = s_vpu_drv_context.open_count;
  983. spin_unlock(&s_vpu_lock);
  984. if (open_count == 0) {
  985. #ifdef SUPPORT_MULTI_INST_INTR
  986. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  987. kfifo_reset(&s_interrupt_pending_q[i]);
  988. }
  989. #endif
  990. if (s_instance_pool.base) {
  991. DPRINTK("[VPUDRV] free instance pool\n");
  992. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  993. vfree((const void *)s_instance_pool.base);
  994. #else
  995. vpu_free_dma_buffer(&s_instance_pool);
  996. #endif
  997. s_instance_pool.base = 0;
  998. }
  999. }
  1000. }
  1001. up(&s_vpu_sem);
  1002. return 0;
  1003. }
  1004. static int vpu_fasync(int fd, struct file *filp, int mode)
  1005. {
  1006. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1007. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1008. }
  1009. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1010. {
  1011. unsigned long pfn;
  1012. vm->vm_flags |= VM_IO | VM_RESERVED;
  1013. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1014. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1015. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1016. }
  1017. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1018. {
  1019. vm->vm_flags |= VM_IO | VM_RESERVED;
  1020. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1021. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1022. }
  1023. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1024. {
  1025. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1026. int ret;
  1027. long length = vm->vm_end - vm->vm_start;
  1028. unsigned long start = vm->vm_start;
  1029. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1030. unsigned long pfn;
  1031. vm->vm_flags |= VM_RESERVED;
  1032. /* loop over all pages, map it page individually */
  1033. while (length > 0)
  1034. {
  1035. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1036. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1037. return ret;
  1038. }
  1039. start += PAGE_SIZE;
  1040. vmalloc_area_ptr += PAGE_SIZE;
  1041. length -= PAGE_SIZE;
  1042. }
  1043. return 0;
  1044. #else
  1045. vm->vm_flags |= VM_RESERVED;
  1046. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1047. #endif
  1048. }
  1049. /*!
  1050. * @brief memory map interface for vpu file operation
  1051. * @return 0 on success or negative error code on error
  1052. */
  1053. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1054. {
  1055. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1056. if (vm->vm_pgoff == 0)
  1057. return vpu_map_to_instance_pool_memory(fp, vm);
  1058. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1059. return vpu_map_to_register(fp, vm);
  1060. return vpu_map_to_physical_memory(fp, vm);
  1061. #else
  1062. if (vm->vm_pgoff) {
  1063. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1064. return vpu_map_to_instance_pool_memory(fp, vm);
  1065. return vpu_map_to_physical_memory(fp, vm);
  1066. } else {
  1067. return vpu_map_to_register(fp, vm);
  1068. }
  1069. #endif
  1070. }
  1071. struct file_operations vpu_fops = {
  1072. .owner = THIS_MODULE,
  1073. .open = vpu_open,
  1074. .read = vpu_read,
  1075. .write = vpu_write,
  1076. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1077. .unlocked_ioctl = vpu_ioctl,
  1078. .release = vpu_release,
  1079. .fasync = vpu_fasync,
  1080. .mmap = vpu_mmap,
  1081. };
  1082. static int vpu_probe(struct platform_device *pdev)
  1083. {
  1084. int err = 0;
  1085. struct resource *res = NULL;
  1086. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1087. struct resource res_cma;
  1088. struct device_node *node;
  1089. #endif
  1090. DPRINTK("[VPUDRV] vpu_probe\n");
  1091. if(pdev){
  1092. vpu_dev = &pdev->dev;
  1093. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1094. //vpu_dev->dma_ops = NULL;
  1095. dev_info(vpu_dev,"device init.\n");
  1096. }
  1097. if (pdev)
  1098. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1099. if (res) {/* if platform driver is implemented */
  1100. s_vpu_register.phys_addr = res->start;
  1101. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1102. s_vpu_register.size = res->end - res->start;
  1103. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1104. } else {
  1105. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1106. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1107. s_vpu_register.size = VPU_REG_SIZE;
  1108. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1109. }
  1110. /* get the major number of the character device */
  1111. if ((alloc_chrdev_region(&s_vpu_major, 0, 1, VPU_DEV_NAME)) < 0) {
  1112. err = -EBUSY;
  1113. printk(KERN_ERR "could not allocate major number\n");
  1114. goto ERROR_PROVE_DEVICE;
  1115. }
  1116. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1117. /* initialize the device structure and register the device with the kernel */
  1118. cdev_init(&s_vpu_cdev, &vpu_fops);
  1119. if ((cdev_add(&s_vpu_cdev, s_vpu_major, 1)) < 0) {
  1120. err = -EBUSY;
  1121. printk(KERN_ERR "could not allocate chrdev\n");
  1122. goto ERROR_PROVE_DEVICE;
  1123. }
  1124. if (pdev)
  1125. s_vpu_clk = vpu_clk_get(pdev);
  1126. else
  1127. s_vpu_clk = vpu_clk_get(NULL);
  1128. if (!s_vpu_clk)
  1129. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1130. else
  1131. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1132. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1133. #else
  1134. vpu_clk_enable(s_vpu_clk);
  1135. #endif
  1136. #ifdef VPU_SUPPORT_ISR
  1137. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1138. if (pdev)
  1139. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1140. if (res) {/* if platform driver is implemented */
  1141. s_vpu_irq = res->start;
  1142. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1143. } else {
  1144. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1145. }
  1146. #else
  1147. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1148. #endif
  1149. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1150. if (err) {
  1151. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1152. goto ERROR_PROVE_DEVICE;
  1153. }
  1154. #endif
  1155. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1156. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1157. if(node){
  1158. dev_info(vpu_dev, "Get mem form memory-region\n");
  1159. of_address_to_resource(node, 0, &res_cma);
  1160. s_video_memory.size = resource_size(&res_cma);
  1161. s_video_memory.phys_addr = res_cma.start;
  1162. }else{
  1163. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1164. return 0;
  1165. }
  1166. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1167. if (!s_video_memory.base) {
  1168. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1169. goto ERROR_PROVE_DEVICE;
  1170. }
  1171. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1172. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1173. goto ERROR_PROVE_DEVICE;
  1174. }
  1175. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1176. #else
  1177. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1178. #endif
  1179. return 0;
  1180. ERROR_PROVE_DEVICE:
  1181. if (s_vpu_major)
  1182. unregister_chrdev_region(s_vpu_major, 1);
  1183. if (s_vpu_register.virt_addr)
  1184. iounmap((void *)s_vpu_register.virt_addr);
  1185. return err;
  1186. }
  1187. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1188. static int vpu_remove(struct platform_device *pdev)
  1189. {
  1190. DPRINTK("[VPUDRV] vpu_remove\n");
  1191. if (s_instance_pool.base) {
  1192. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1193. vfree((const void *)s_instance_pool.base);
  1194. #else
  1195. vpu_free_dma_buffer(&s_instance_pool);
  1196. #endif
  1197. s_instance_pool.base = 0;
  1198. }
  1199. if (s_common_memory.base) {
  1200. vpu_free_dma_buffer(&s_common_memory);
  1201. s_common_memory.base = 0;
  1202. }
  1203. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1204. if (s_video_memory.base) {
  1205. iounmap((void *)s_video_memory.base);
  1206. s_video_memory.base = 0;
  1207. vmem_exit(&s_vmem);
  1208. }
  1209. #endif
  1210. if (s_vpu_major > 0) {
  1211. cdev_del(&s_vpu_cdev);
  1212. unregister_chrdev_region(s_vpu_major, 1);
  1213. s_vpu_major = 0;
  1214. }
  1215. #ifdef VPU_SUPPORT_ISR
  1216. if (s_vpu_irq)
  1217. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1218. #endif
  1219. if (s_vpu_register.virt_addr)
  1220. iounmap((void *)s_vpu_register.virt_addr);
  1221. vpu_clk_put(s_vpu_clk);
  1222. return 0;
  1223. }
  1224. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1225. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1226. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1227. #define W5_CMD_INIT_VPU (0x0001)
  1228. #define W5_CMD_SLEEP_VPU (0x0004)
  1229. #define W5_CMD_WAKEUP_VPU (0x0002)
  1230. static void Wave5BitIssueCommand(int core, u32 cmd)
  1231. {
  1232. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1233. WriteVpuRegister(W5_COMMAND, cmd);
  1234. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1235. return;
  1236. }
  1237. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1238. {
  1239. int i;
  1240. int core;
  1241. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1242. int product_code;
  1243. DPRINTK("[VPUDRV] vpu_suspend\n");
  1244. vpu_clk_enable(s_vpu_clk);
  1245. if (s_vpu_open_ref_count > 0) {
  1246. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1247. if (s_bit_firmware_info[core].size == 0)
  1248. continue;
  1249. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1250. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1251. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1252. if (time_after(jiffies, timeout)) {
  1253. DPRINTK("SLEEP_VPU BUSY timeout");
  1254. goto DONE_SUSPEND;
  1255. }
  1256. }
  1257. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1258. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1259. if (time_after(jiffies, timeout)) {
  1260. DPRINTK("SLEEP_VPU BUSY timeout");
  1261. goto DONE_SUSPEND;
  1262. }
  1263. }
  1264. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1265. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1266. goto DONE_SUSPEND;
  1267. }
  1268. }
  1269. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1270. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1271. if (time_after(jiffies, timeout))
  1272. goto DONE_SUSPEND;
  1273. }
  1274. for (i = 0; i < 64; i++)
  1275. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1276. }
  1277. else {
  1278. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1279. goto DONE_SUSPEND;
  1280. }
  1281. }
  1282. }
  1283. vpu_clk_disable(s_vpu_clk);
  1284. return 0;
  1285. DONE_SUSPEND:
  1286. vpu_clk_disable(s_vpu_clk);
  1287. return -EAGAIN;
  1288. }
  1289. static int vpu_resume(struct platform_device *pdev)
  1290. {
  1291. int i;
  1292. int core;
  1293. u32 val;
  1294. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1295. int product_code;
  1296. unsigned long code_base;
  1297. u32 code_size;
  1298. u32 remap_size;
  1299. int regVal;
  1300. u32 hwOption = 0;
  1301. DPRINTK("[VPUDRV] vpu_resume\n");
  1302. vpu_clk_enable(s_vpu_clk);
  1303. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1304. if (s_bit_firmware_info[core].size == 0) {
  1305. continue;
  1306. }
  1307. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1308. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1309. code_base = s_common_memory.phys_addr;
  1310. /* ALIGN TO 4KB */
  1311. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1312. if (code_size < s_bit_firmware_info[core].size*2) {
  1313. goto DONE_WAKEUP;
  1314. }
  1315. regVal = 0;
  1316. WriteVpuRegister(W5_PO_CONF, regVal);
  1317. /* Reset All blocks */
  1318. regVal = 0x7ffffff;
  1319. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1320. /* Waiting reset done */
  1321. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1322. if (time_after(jiffies, timeout))
  1323. goto DONE_WAKEUP;
  1324. }
  1325. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1326. /* remap page size */
  1327. remap_size = (code_size >> 12) & 0x1ff;
  1328. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1329. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1330. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1331. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1332. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1333. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1334. WriteVpuRegister(W5_CODE_PARAM, 0);
  1335. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1336. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1337. /* Interrupt */
  1338. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1339. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1340. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1341. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1342. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1343. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1344. }
  1345. else {
  1346. // decoder
  1347. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1348. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1349. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1350. }
  1351. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1352. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1353. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1354. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1355. if (time_after(jiffies, timeout))
  1356. goto DONE_WAKEUP;
  1357. }
  1358. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1359. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1360. goto DONE_WAKEUP;
  1361. }
  1362. }
  1363. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1364. WriteVpuRegister(BIT_CODE_RUN, 0);
  1365. /*---- LOAD BOOT CODE*/
  1366. for (i = 0; i < 512; i++) {
  1367. val = s_bit_firmware_info[core].bit_code[i];
  1368. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1369. }
  1370. for (i = 0 ; i < 64 ; i++)
  1371. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1372. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1373. WriteVpuRegister(BIT_CODE_RESET, 1);
  1374. WriteVpuRegister(BIT_CODE_RUN, 1);
  1375. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1376. if (time_after(jiffies, timeout))
  1377. goto DONE_WAKEUP;
  1378. }
  1379. }
  1380. else {
  1381. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1382. goto DONE_WAKEUP;
  1383. }
  1384. }
  1385. if (s_vpu_open_ref_count == 0)
  1386. vpu_clk_disable(s_vpu_clk);
  1387. DONE_WAKEUP:
  1388. if (s_vpu_open_ref_count > 0)
  1389. vpu_clk_enable(s_vpu_clk);
  1390. return 0;
  1391. }
  1392. #else
  1393. #define vpu_suspend NULL
  1394. #define vpu_resume NULL
  1395. #endif /* !CONFIG_PM */
  1396. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1397. static const struct of_device_id cm_vpu_match[] = {
  1398. {
  1399. .compatible = "c&m,cm511-vpu",
  1400. },
  1401. {
  1402. .compatible = "starfive,vdec",
  1403. },
  1404. {
  1405. /* end of table */
  1406. },
  1407. };
  1408. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1409. static struct platform_driver vpu_driver = {
  1410. .driver = {
  1411. .name = VPU_PLATFORM_DEVICE_NAME,
  1412. .of_match_table = cm_vpu_match,
  1413. },
  1414. .probe = vpu_probe,
  1415. .remove = vpu_remove,
  1416. .suspend = vpu_suspend,
  1417. .resume = vpu_resume,
  1418. };
  1419. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1420. static int __init vpu_init(void)
  1421. {
  1422. int res;
  1423. #ifdef SUPPORT_MULTI_INST_INTR
  1424. int i;
  1425. #endif
  1426. DPRINTK("[VPUDRV] begin vpu_init\n");
  1427. #ifdef SUPPORT_MULTI_INST_INTR
  1428. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1429. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1430. }
  1431. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1432. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1433. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1434. if (res) {
  1435. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1436. }
  1437. }
  1438. #else
  1439. init_waitqueue_head(&s_interrupt_wait_q);
  1440. #endif
  1441. s_common_memory.base = 0;
  1442. s_instance_pool.base = 0;
  1443. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1444. res = platform_driver_register(&vpu_driver);
  1445. #else
  1446. res = vpu_probe(NULL);
  1447. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1448. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1449. return res;
  1450. }
  1451. static void __exit vpu_exit(void)
  1452. {
  1453. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1454. DPRINTK("[VPUDRV] vpu_exit\n");
  1455. platform_driver_unregister(&vpu_driver);
  1456. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1457. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1458. #else
  1459. vpu_clk_disable(s_vpu_clk);
  1460. #endif
  1461. vpu_clk_put(s_vpu_clk);
  1462. if (s_instance_pool.base) {
  1463. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1464. vfree((const void *)s_instance_pool.base);
  1465. #else
  1466. vpu_free_dma_buffer(&s_instance_pool);
  1467. #endif
  1468. s_instance_pool.base = 0;
  1469. }
  1470. if (s_common_memory.base) {
  1471. vpu_free_dma_buffer(&s_common_memory);
  1472. s_common_memory.base = 0;
  1473. }
  1474. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1475. if (s_video_memory.base) {
  1476. iounmap((void *)s_video_memory.base);
  1477. s_video_memory.base = 0;
  1478. vmem_exit(&s_vmem);
  1479. }
  1480. #endif
  1481. if (s_vpu_major > 0) {
  1482. cdev_del(&s_vpu_cdev);
  1483. unregister_chrdev_region(s_vpu_major, 1);
  1484. s_vpu_major = 0;
  1485. }
  1486. #ifdef VPU_SUPPORT_ISR
  1487. if (s_vpu_irq)
  1488. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1489. #endif
  1490. #ifdef SUPPORT_MULTI_INST_INTR
  1491. {
  1492. int i;
  1493. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1494. kfifo_free(&s_interrupt_pending_q[i]);
  1495. }
  1496. }
  1497. #endif
  1498. if (s_vpu_register.virt_addr) {
  1499. iounmap((void *)s_vpu_register.virt_addr);
  1500. s_vpu_register.virt_addr = 0x00;
  1501. }
  1502. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1503. return;
  1504. }
  1505. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1506. MODULE_DESCRIPTION("VPU linux driver");
  1507. MODULE_LICENSE("GPL");
  1508. module_init(vpu_init);
  1509. module_exit(vpu_exit);
  1510. /* clk&reset for starfive jh7110*/
  1511. #define PMU_BASE_ADDR 0x17030000
  1512. #define PMU_VDEC_MASK (0x1 << 3)
  1513. static void pmu_pd_set(vpu_clk_t *clk, int on_off, uint32_t pd_flag)
  1514. {
  1515. const uint32_t flag_off = 0x0c;
  1516. const uint32_t sw_off = 0x44;
  1517. void __iomem *base = ioremap(clk->pmu_base, 0x100);
  1518. writel(pd_flag, base + flag_off);
  1519. writel(0xff, base + sw_off);
  1520. if (on_off) {
  1521. writel(0x05, base + sw_off);
  1522. writel(0x50, base + sw_off);
  1523. } else {
  1524. writel(0x0a, base + sw_off);
  1525. writel(0xa0, base + sw_off);
  1526. }
  1527. iounmap(base);
  1528. }
  1529. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1530. #define CLK_ENABLE_DATA 1
  1531. #define CLK_DISABLE_DATA 0
  1532. #define CLK_EN_SHIFT 31
  1533. #define CLK_EN_MASK 0x80000000U
  1534. #define SAIF_BD_APBS_BASE 0x13020000
  1535. #define WAVE511_CLK_AXI_CTRL 0x118U
  1536. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1537. #define WAVE511_CLK_VCE_CTRL 0x120U
  1538. #define WAVE511_CLK_APB_CTRL 0x124U
  1539. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1540. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1541. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1542. #define RSTN_AXI_MASK (0x1 << 15)
  1543. #define RSTN_BPU_MASK (0x1 << 16)
  1544. #define RSTN_VCE_MASK (0x1 << 17)
  1545. #define RSTN_APB_MASK (0x1 << 18)
  1546. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1547. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1548. uint32_t shift, uint32_t mask)
  1549. {
  1550. u32 tmp;
  1551. tmp = readl(addr);
  1552. tmp = (tmp & mask) >> shift;
  1553. return tmp;
  1554. }
  1555. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1556. uint32_t shift, uint32_t mask)
  1557. {
  1558. uint32_t tmp;
  1559. tmp = readl(addr);
  1560. tmp &= ~mask;
  1561. tmp |= (data << shift) & mask;
  1562. writel(tmp, addr);
  1563. }
  1564. static void saif_assert_rst(volatile void __iomem *addr,
  1565. const volatile void __iomem *addr_status, uint32_t mask)
  1566. {
  1567. uint32_t tmp;
  1568. tmp = readl(addr);
  1569. tmp |= mask;
  1570. writel(tmp, addr);
  1571. do {
  1572. tmp = readl(addr_status);
  1573. } while ((tmp & mask) != 0);
  1574. }
  1575. static void saif_clear_rst(volatile void __iomem *addr,
  1576. const volatile void __iomem *addr_status, uint32_t mask)
  1577. {
  1578. uint32_t tmp;
  1579. tmp = readl(addr);
  1580. tmp &= ~mask;
  1581. writel(tmp, addr);
  1582. do {
  1583. tmp = readl(addr_status);
  1584. } while ((tmp & mask) != mask);
  1585. }
  1586. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1587. {
  1588. if (enable)
  1589. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1590. else
  1591. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1592. }
  1593. static void vpu_aximem_128b_control(vpu_clk_t *clk, bool enable)
  1594. {
  1595. if (enable) {
  1596. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1597. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1598. } else {
  1599. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1600. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1601. }
  1602. }
  1603. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1604. {
  1605. if (enable) {
  1606. /*enable*/
  1607. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1608. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1609. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1610. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1611. /*clr-reset*/
  1612. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1613. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1614. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1615. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1616. } else {
  1617. /*assert-reset*/
  1618. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1619. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1620. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1621. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1622. /*disable*/
  1623. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1624. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1625. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1626. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1627. }
  1628. }
  1629. static void vpu_clk_reset(vpu_clk_t *clk)
  1630. {
  1631. /*assert-reset*/
  1632. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1633. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1634. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1635. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1636. /*clr-reset*/
  1637. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1638. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1639. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1640. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1641. }
  1642. int vpu_hw_reset(void)
  1643. {
  1644. if (!s_vpu_clk)
  1645. return -1;
  1646. vpu_clk_reset(s_vpu_clk);
  1647. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1648. return 0;
  1649. }
  1650. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1651. {
  1652. if (!pdev)
  1653. return -ENXIO;
  1654. vpu_clk->pmu_base = PMU_BASE_ADDR;
  1655. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1656. if (IS_ERR(vpu_clk->clkgen)) {
  1657. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1658. return PTR_ERR(vpu_clk->clkgen);
  1659. }
  1660. /* clkgen define */
  1661. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1662. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1663. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1664. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1665. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1666. vpu_clk->en_mask = CLK_EN_MASK;
  1667. vpu_clk->en_shift = CLK_EN_SHIFT;
  1668. /* rstgen define */
  1669. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1670. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1671. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1672. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1673. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1674. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1675. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1676. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1677. vpu_clk->noc_ctrl = true;
  1678. return 0;
  1679. }
  1680. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1681. {
  1682. vpu_clk_t *vpu_clk;
  1683. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1684. if (!vpu_clk)
  1685. return NULL;
  1686. if (vpu_of_clk_get(pdev, vpu_clk))
  1687. goto err_get_clk;
  1688. return vpu_clk;
  1689. err_get_clk:
  1690. kfree(vpu_clk);
  1691. return NULL;
  1692. }
  1693. static void vpu_clk_put(vpu_clk_t *clk)
  1694. {
  1695. iounmap(clk->clkgen);
  1696. }
  1697. static int vpu_clk_enable(vpu_clk_t *clk)
  1698. {
  1699. if (clk == NULL || IS_ERR(clk))
  1700. return -1;
  1701. pmu_pd_set(clk, true, PMU_VDEC_MASK);
  1702. vpu_clk_control(clk, true);
  1703. vpu_aximem_128b_control(clk, true);
  1704. if (clk->noc_ctrl == true)
  1705. vpu_noc_vdec_bus_control(clk, true);
  1706. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1707. return 0;
  1708. }
  1709. static void vpu_clk_disable(vpu_clk_t *clk)
  1710. {
  1711. if (clk == NULL || IS_ERR(clk))
  1712. return;
  1713. vpu_aximem_128b_control(clk, false);
  1714. vpu_clk_control(clk, false);
  1715. pmu_pd_set(clk, false, PMU_VDEC_MASK);
  1716. if (clk->noc_ctrl == true)
  1717. vpu_noc_vdec_bus_control(clk, false);
  1718. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1719. }
  1720. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1721. static int clk_check_err(struct clk *clk)
  1722. {
  1723. return !!(clk == NULL || IS_ERR(clk));
  1724. }
  1725. int vpu_hw_reset(void)
  1726. {
  1727. /*to do*/
  1728. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1729. return 0;
  1730. }
  1731. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1732. {
  1733. struct resource *pmu;
  1734. struct device *dev = &pdev->dev;
  1735. pmu = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
  1736. if (IS_ERR(pmu))
  1737. dev_warn(dev, "get pmu failed.\n");
  1738. vpu_clk->pmu_base = pmu->start;
  1739. vpu_clk->apb_clk = devm_clk_get(dev, "apb_clk");
  1740. if (clk_check_err(vpu_clk->apb_clk)) {
  1741. dev_err(dev, "apb_clk get failed.\n");
  1742. return PTR_ERR(vpu_clk->apb_clk);
  1743. }
  1744. vpu_clk->axi_clk = devm_clk_get(dev, "axi_clk");
  1745. if (clk_check_err(vpu_clk->axi_clk)) {
  1746. dev_err(dev, "axi_clk get failed.\n");
  1747. return PTR_ERR(vpu_clk->axi_clk);
  1748. }
  1749. vpu_clk->bpu_clk = devm_clk_get(dev, "bpu_clk");
  1750. if (clk_check_err(vpu_clk->bpu_clk)) {
  1751. dev_err(dev, "bpu_clk get failed.\n");
  1752. return PTR_ERR(vpu_clk->bpu_clk);
  1753. }
  1754. vpu_clk->vce_clk = devm_clk_get(dev, "vce_clk");
  1755. if (clk_check_err(vpu_clk->vce_clk)) {
  1756. dev_err(dev, "vce_clk get failed.\n");
  1757. return PTR_ERR(vpu_clk->vce_clk);
  1758. }
  1759. vpu_clk->aximem_128b = devm_clk_get(dev, "aximem_128b");
  1760. if (clk_check_err(vpu_clk->aximem_128b)) {
  1761. dev_err(dev, "aximem_128b get failed.\n");
  1762. return PTR_ERR(vpu_clk->aximem_128b);
  1763. }
  1764. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl")) {
  1765. vpu_clk->noc_bus = devm_platform_ioremap_resource_byname(pdev, "noc_bus");
  1766. if (IS_ERR(vpu_clk->noc_bus)) {
  1767. dev_err(&pdev->dev, "get noc_bus failed.\n");
  1768. return PTR_ERR(vpu_clk->noc_bus);
  1769. }
  1770. vpu_clk->noc_ctrl = true;
  1771. }
  1772. return 0;
  1773. }
  1774. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1775. {
  1776. vpu_clk_t *vpu_clk;
  1777. if (!pdev)
  1778. return NULL;
  1779. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1780. if (!vpu_clk)
  1781. return NULL;
  1782. if (vpu_of_clk_get(pdev, vpu_clk))
  1783. goto err_of_clk_get;
  1784. return vpu_clk;
  1785. err_of_clk_get:
  1786. kfree(vpu_clk);
  1787. return NULL;
  1788. }
  1789. static void vpu_clk_put(vpu_clk_t *clk)
  1790. {
  1791. if (!(clk_check_err(clk->apb_clk)))
  1792. clk_put(clk->apb_clk);
  1793. if (!(clk_check_err(clk->axi_clk)))
  1794. clk_put(clk->axi_clk);
  1795. if (!(clk_check_err(clk->bpu_clk)))
  1796. clk_put(clk->bpu_clk);
  1797. if (!(clk_check_err(clk->vce_clk)))
  1798. clk_put(clk->vce_clk);
  1799. if (!(clk_check_err(clk->aximem_128b)))
  1800. clk_put(clk->aximem_128b);
  1801. }
  1802. static int vpu_clk_enable(vpu_clk_t *clk)
  1803. {
  1804. pmu_pd_set(clk, true, PMU_VDEC_MASK);
  1805. if (!(clk_check_err(clk->apb_clk)))
  1806. clk_prepare_enable(clk->apb_clk);
  1807. if (!(clk_check_err(clk->axi_clk)))
  1808. clk_prepare_enable(clk->axi_clk);
  1809. if (!(clk_check_err(clk->bpu_clk)))
  1810. clk_prepare_enable(clk->bpu_clk);
  1811. if (!(clk_check_err(clk->vce_clk)))
  1812. clk_prepare_enable(clk->vce_clk);
  1813. if (!(clk_check_err(clk->aximem_128b)))
  1814. clk_prepare_enable(clk->aximem_128b);
  1815. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1816. return 0;
  1817. }
  1818. static void vpu_clk_disable(vpu_clk_t *clk)
  1819. {
  1820. if (!(clk_check_err(clk->apb_clk)))
  1821. clk_disable_unprepare(clk->apb_clk);
  1822. if (!(clk_check_err(clk->axi_clk)))
  1823. clk_disable_unprepare(clk->axi_clk);
  1824. if (!(clk_check_err(clk->bpu_clk)))
  1825. clk_disable_unprepare(clk->bpu_clk);
  1826. if (!(clk_check_err(clk->vce_clk)))
  1827. clk_disable_unprepare(clk->vce_clk);
  1828. if (!(clk_check_err(clk->aximem_128b)))
  1829. clk_disable_unprepare(clk->aximem_128b);
  1830. pmu_pd_set(clk, false, PMU_VDEC_MASK);
  1831. }
  1832. #endif