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Merge branch 'update-readme' into starfive-hardknott

dubhe: Update README.md

Updated several depreciated steps such as the github repo and branch, and
the dependency packages. The 'dubhe-image-initramfs' is also changed to
'qspi-image' instead.

Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
Jun Yuan Tan 2 лет назад
Родитель
Сommit
03295923de
100 измененных файлов с 25621 добавлено и 7684 удалено
  1. 5 3
      conf/machine/starfive-dubhe.conf
  2. 29 0
      recipes-benchmark/dhrystone/dhrystone/0001-dhrystone-Edit-compiler-flags.patch
  3. 1 1
      recipes-benchmark/dhrystone/dhrystone_2.1.bb
  4. 0 29
      recipes-benchmark/dhrystone/files/0001-Edit-Makefile-to-add-compiler-flags.patch
  5. 52 0
      recipes-core/glibc/cross-localedef-native_2.35.bb
  6. 12 0
      recipes-core/glibc/glibc-collateral.inc
  7. 25 0
      recipes-core/glibc/glibc-common.inc
  8. 20 0
      recipes-core/glibc/glibc-ld.inc
  9. 103 0
      recipes-core/glibc/glibc-locale.inc
  10. 1 0
      recipes-core/glibc/glibc-locale_2.35.bb
  11. 16 0
      recipes-core/glibc/glibc-mtrace.inc
  12. 1 0
      recipes-core/glibc/glibc-mtrace_2.35.bb
  13. 16 0
      recipes-core/glibc/glibc-package.inc
  14. 23 0
      recipes-core/glibc/glibc-scripts.inc
  15. 1 0
      recipes-core/glibc/glibc-scripts_2.35.bb
  16. 32 0
      recipes-core/glibc/glibc-tests.inc
  17. 35 0
      recipes-core/glibc/glibc-testsuite_2.35.bb
  18. 8 0
      recipes-core/glibc/glibc-version.inc
  19. 52 0
      recipes-core/glibc/glibc.inc
  20. 59 0
      recipes-core/glibc/glibc/0001-Add-array_length-support.patch
  21. 43 0
      recipes-core/glibc/glibc/0001-CVE-2021-38604.patch
  22. 79 0
      recipes-core/glibc/glibc/0001-fix-create-thread-failed-in-unprivileged-process-BZ-.patch
  23. 1130 0
      recipes-core/glibc/glibc/0001-localedef-Add-hardlink-resolver-from-util-linux.patch
  24. 150 0
      recipes-core/glibc/glibc/0002-CVE-2021-38604.patch
  25. 238 0
      recipes-core/glibc/glibc/0002-localedef-fix-ups-hardlink-to-make-it-compile.patch
  26. 65 0
      recipes-core/glibc/glibc/0003-nativesdk-glibc-Look-for-host-system-ld.so.cache-as-.patch
  27. 46 0
      recipes-core/glibc/glibc/0004-nativesdk-glibc-Fix-buffer-overrun-with-a-relocated-.patch
  28. 153 0
      recipes-core/glibc/glibc/0005-nativesdk-glibc-Raise-the-size-of-arrays-containing-.patch
  29. 39 0
      recipes-core/glibc/glibc/0006-nativesdk-glibc-Allow-64-bit-atomics-for-x86.patch
  30. 100 0
      recipes-core/glibc/glibc/0007-nativesdk-glibc-Make-relocatable-install-for-locales.patch
  31. 32 0
      recipes-core/glibc/glibc/0008-nativesdk-glibc-Fall-back-to-faccessat-on-faccess2-r.patch
  32. 1581 0
      recipes-core/glibc/glibc/0009-fsl-e500-e5500-e6500-603e-fsqrt-implementation.patch
  33. 205 0
      recipes-core/glibc/glibc/0010-ppc-sqrt-Fix-undefined-reference-to-__sqrt_finite.patch
  34. 384 0
      recipes-core/glibc/glibc/0011-__ieee754_sqrt-f-are-now-inline-functions-and-call-o.patch
  35. 58 0
      recipes-core/glibc/glibc/0012-Quote-from-bug-1443-which-explains-what-the-patch-do.patch
  36. 33 0
      recipes-core/glibc/glibc/0013-eglibc-run-libm-err-tab.pl-with-specific-dirs-in-S.patch
  37. 58 0
      recipes-core/glibc/glibc/0014-__ieee754_sqrt-f-are-now-inline-functions-and-call-o.patch
  38. 39 0
      recipes-core/glibc/glibc/0015-sysdeps-gnu-configure.ac-handle-correctly-libc_cv_ro.patch
  39. 260 0
      recipes-core/glibc/glibc/0016-yes-within-the-path-sets-wrong-config-variables.patch
  40. 34 0
      recipes-core/glibc/glibc/0017-timezone-re-written-tzselect-as-posix-sh.patch
  41. 72 0
      recipes-core/glibc/glibc/0018-Remove-bash-dependency-for-nscd-init-script.patch
  42. 616 0
      recipes-core/glibc/glibc/0019-eglibc-Cross-building-and-testing-instructions.patch
  43. 97 0
      recipes-core/glibc/glibc/0020-eglibc-Help-bootstrap-cross-toolchain.patch
  44. 53 0
      recipes-core/glibc/glibc/0021-eglibc-Resolve-__fpscr_values-on-SH4.patch
  45. 560 0
      recipes-core/glibc/glibc/0022-eglibc-Forward-port-cross-locale-generation-support.patch
  46. 80 0
      recipes-core/glibc/glibc/0024-localedef-add-to-archive-uses-a-hard-coded-locale-pa.patch
  47. 53 0
      recipes-core/glibc/glibc/0025-elf-dl-deps.c-Make-_dl_build_local_scope-breadth-fir.patch
  48. 31 0
      recipes-core/glibc/glibc/0026-intl-Emit-no-lines-in-bison-generated-files.patch
  49. 53 0
      recipes-core/glibc/glibc/0027-locale-prevent-maybe-uninitialized-errors-with-Os-BZ.patch
  50. 29 0
      recipes-core/glibc/glibc/0028-readlib-Add-OECORE_KNOWN_INTERPRETER_NAMES-to-known-.patch
  51. 67 0
      recipes-core/glibc/glibc/0029-wordsize.h-Unify-the-header-between-arm-and-aarch64.patch
  52. 48 0
      recipes-core/glibc/glibc/0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch
  53. 184 0
      recipes-core/glibc/glibc/CVE-2021-43396.patch
  54. 80 0
      recipes-core/glibc/glibc/check-test-wrapper
  55. 1 0
      recipes-core/glibc/glibc/etc/ld.so.conf
  56. 11 0
      recipes-core/glibc/glibc/generate-supported.mk
  57. 177 0
      recipes-core/glibc/glibc/makedbs.sh
  58. 131 0
      recipes-core/glibc/glibc_2.35.bb
  59. 331 0
      recipes-core/glibc/ldconfig-native-2.12.1/32and64bit.patch
  60. 8 0
      recipes-core/glibc/ldconfig-native-2.12.1/README
  61. 116 0
      recipes-core/glibc/ldconfig-native-2.12.1/add-64-bit-flag-for-ELF64-entries.patch
  62. 79 0
      recipes-core/glibc/ldconfig-native-2.12.1/add-riscv-support.patch
  63. 454 0
      recipes-core/glibc/ldconfig-native-2.12.1/endian-ness_handling.patch
  64. 47 0
      recipes-core/glibc/ldconfig-native-2.12.1/endian-ness_handling_fix.patch
  65. 113 0
      recipes-core/glibc/ldconfig-native-2.12.1/endianess-header.patch
  66. 24 0
      recipes-core/glibc/ldconfig-native-2.12.1/flag_fix.patch
  67. 37 0
      recipes-core/glibc/ldconfig-native-2.12.1/ldconfig-default-to-all-multilib-dirs.patch
  68. BIN
      recipes-core/glibc/ldconfig-native-2.12.1/ldconfig-native-2.12.1.tar.bz2
  69. 471 0
      recipes-core/glibc/ldconfig-native-2.12.1/ldconfig.patch
  70. 36 0
      recipes-core/glibc/ldconfig-native-2.12.1/ldconfig_aux-cache_path_fix.patch
  71. 19 0
      recipes-core/glibc/ldconfig-native-2.12.1/no-aux-cache.patch
  72. 36 0
      recipes-core/glibc/ldconfig-native_2.12.1.bb
  73. 50 0
      recipes-devtools/binutils/binutils-2.37.inc
  74. 32 0
      recipes-devtools/binutils/binutils-cross-canadian.inc
  75. 0 38
      recipes-devtools/binutils/binutils-cross-canadian_2.36.bbappend
  76. 3 0
      recipes-devtools/binutils/binutils-cross-canadian_2.37.bb
  77. 81 0
      recipes-devtools/binutils/binutils-cross-testsuite_2.37.bb
  78. 38 0
      recipes-devtools/binutils/binutils-cross.inc
  79. 0 38
      recipes-devtools/binutils/binutils-cross_2.36.bbappend
  80. 3 0
      recipes-devtools/binutils/binutils-cross_2.37.bb
  81. 0 38
      recipes-devtools/binutils/binutils-crosssdk_2.36.bbappend
  82. 13 0
      recipes-devtools/binutils/binutils-crosssdk_2.37.bb
  83. 184 0
      recipes-devtools/binutils/binutils.inc
  84. 75 0
      recipes-devtools/binutils/binutils/0001-binutils-crosssdk-Generate-relocatable-SDKs.patch
  85. 927 0
      recipes-devtools/binutils/binutils/0001-merge-from-dubhe-pr-06-30-to-support-b0.94.patch
  86. 0 25
      recipes-devtools/binutils/binutils/0001-resolve-bug-1-unsupported-zvmo-extension.patch
  87. 0 1001
      recipes-devtools/binutils/binutils/0002-Add-support-for-B-extension.patch
  88. 59 0
      recipes-devtools/binutils/binutils/0002-binutils-cross-Do-not-generate-linker-script-directo.patch
  89. 14220 0
      recipes-devtools/binutils/binutils/0002-merge-from-dubhe-pr-06-30-to-support-vector1.0.patch
  90. 95 0
      recipes-devtools/binutils/binutils/0003-binutils-nativesdk-Search-for-alternative-ld.so.conf.patch
  91. 55 0
      recipes-devtools/binutils/binutils/0003-fix-unrecoginized-b-ext-issue.patch
  92. 0 523
      recipes-devtools/binutils/binutils/0004-add-missed-sysroff-file.patch
  93. 41 0
      recipes-devtools/binutils/binutils/0004-configure-widen-the-regexp-for-SH-architectures.patch
  94. 24 0
      recipes-devtools/binutils/binutils/0004-set-v-ext-version-to-1.0-draft.patch
  95. 4 4
      recipes-devtools/binutils/binutils/0005-Point-scripts-location-to-libdir.patch
  96. 27 0
      recipes-devtools/binutils/binutils/0005-fix-incorrect-RCLASS_MAX.patch
  97. 0 5703
      recipes-devtools/binutils/binutils/0005-support-Dubhe-V-extension.patch
  98. 0 281
      recipes-devtools/binutils/binutils/0006-Add-pseudo-instructions-for-B-extension.patch
  99. 321 0
      recipes-devtools/binutils/binutils/0006-Merge-B-instruction-from-0p94-to-1.0.patch
  100. 37 0
      recipes-devtools/binutils/binutils/0006-Only-generate-an-RPATH-entry-if-LD_RUN_PATH-is-not-e.patch

+ 5 - 3
conf/machine/starfive-dubhe.conf

@@ -54,11 +54,13 @@ PREFERRED_PROVIDER_virtual/kernel ?= "linux-starfive-dev"
 RISCV_SBI_PLAT = "generic"
 RISCV_SBI_PAYLOAD = "Image-initramfs-starfive-dubhe.bin"
 
-PREFERRED_VERSION_qemu = "6.1.0"
-PREFERRED_VERSION_qemu-native = "6.1.0"
-PREFERRED_VERSION_nativesdk-qemu = "6.1.0"
+QEMUVERSION = "6.0.0"
 QEMU_EXTRAOPTIONS_riscv64 = " -cpu rv64,x-b=true"
 
+GCCVERSION = "11.%"
+BINUVERSION = "2.37%"
+GLIBCVERSION = "2.35"
+
 #
 ###IMAGE_FSTYPES += "wic.gz wic.bmap ext4 cpio"
 

+ 29 - 0
recipes-benchmark/dhrystone/dhrystone/0001-dhrystone-Edit-compiler-flags.patch

@@ -0,0 +1,29 @@
+From f204001c9478facc466400be5089ed8bf1a77ce8 Mon Sep 17 00:00:00 2001
+From: Jun Yuan Tan <junyuan.tan@starfivetech.com>
+Date: Fri, 29 Oct 2021 10:42:16 +0800
+Subject: [PATCH] dhrystone: Edit compiler flags
+
+This patch is needed for adding compiler flags for Dhrystone
+
+Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
+---
+ Makefile | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 6fb3e5a..6640037 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,10 +1,10 @@
+ DHRY-LFLAGS =
+ 
+ DHRY-CFLAGS := -O3 -DTIME -DNOENUM -Wno-implicit -save-temps
+-DHRY-CFLAGS += -fno-builtin-printf -fno-common -falign-functions=4
++DHRY-CFLAGS += -mabi=lp64d -O3 -fno-common -funroll-loops -fno-inline -funroll-all-loops -falign-jumps=8 -falign-loops=8 -finline-limit=1000 -falign-functions=8 -ffast-math -fno-tree-loop-distribute-patterns --param fsm-scale-path-stmts=3 -mcmodel=medany -fno-builtin-printf -lrt
+ 
+ #Uncomment below for FPGA run, default DHRY_ITERS is 2000 for RTL
+-#DHRY-CFLAGS += -DDHRY_ITERS=20000000
++DHRY-CFLAGS += -DDHRY_ITERS=20000000
+ 
+ SRC = dhry_1.c dhry_2.c strcmp.S
+ HDR = dhry.h

+ 1 - 1
recipes-benchmark/dhrystone/dhrystone_2.1.bb

@@ -5,7 +5,7 @@ LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/PD;md5=b3597d1
 INHIBIT_PACKAGE_STRIP = "1"
 
 SRC_URI = "git://github.com/sifive/benchmark-dhrystone.git \
-           file://0001-Edit-Makefile-to-add-compiler-flags.patch \
+           file://0001-dhrystone-Edit-compiler-flags.patch \
            "
 SRCREV = "0ddff533cc9052c524990d5ace4560372053314b"
 

+ 0 - 29
recipes-benchmark/dhrystone/files/0001-Edit-Makefile-to-add-compiler-flags.patch

@@ -1,29 +0,0 @@
-From 62f00defc2fbee9cb76d7a424df7281fcec748c7 Mon Sep 17 00:00:00 2001
-From: junyuantan <junyuan.tan@starfivetech.com>
-Date: Mon, 16 Aug 2021 17:41:19 +0800
-Subject: [PATCH] Edit Makefile to add compiler flags
-
-This patch is needed for adding compiler flags for Coremark
-
-Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
----
- Makefile | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/Makefile b/Makefile
-index 6fb3e5a..2454959 100644
---- a/Makefile
-+++ b/Makefile
-@@ -1,10 +1,10 @@
- DHRY-LFLAGS =
- 
- DHRY-CFLAGS := -O3 -DTIME -DNOENUM -Wno-implicit -save-temps
--DHRY-CFLAGS += -fno-builtin-printf -fno-common -falign-functions=4
-+DHRY-CFLAGS += -mabi=lp64d -O3 -fno-common -funroll-loops -finline-functions -funroll-all-loops -falign-jumps=8 -falign-loops=8 -finline-limit=1000 -falign-functions=8 -ffast-math -fno-tree-loop-distribute-patterns --param fsm-scale-path-stmts=3 -mcmodel=medany -fno-builtin-printf -lrt
- 
- #Uncomment below for FPGA run, default DHRY_ITERS is 2000 for RTL
--#DHRY-CFLAGS += -DDHRY_ITERS=20000000
-+DHRY-CFLAGS += -DDHRY_ITERS=20000000
- 
- SRC = dhry_1.c dhry_2.c strcmp.S
- HDR = dhry.h

+ 52 - 0
recipes-core/glibc/cross-localedef-native_2.35.bb

@@ -0,0 +1,52 @@
+SUMMARY = "Cross locale generation tool for glibc"
+HOMEPAGE = "http://www.gnu.org/software/libc/libc.html"
+SECTION = "libs"
+LICENSE = "LGPL-2.1"
+
+LIC_FILES_CHKSUM = "file://LICENSES;md5=1541fd8f5e8f1579512bf05f533371ba \
+      file://COPYING;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
+      file://posix/rxspencer/COPYRIGHT;md5=dc5485bb394a13b2332ec1c785f5d83a \
+      file://COPYING.LIB;md5=4fbd65380cdd255951079008b364516c"
+
+require glibc-version.inc
+
+# Tell autotools that we're working in the localedef directory
+#
+AUTOTOOLS_SCRIPT_PATH = "${S}/localedef"
+
+inherit autotools
+inherit native
+
+FILESEXTRAPATHS =. "${FILE_DIRNAME}/${PN}:${FILE_DIRNAME}/glibc:"
+
+SRC_URI = "${GLIBC_GIT_URI};branch=${SRCBRANCH};name=glibc \
+           git://github.com/kraj/localedef;branch=master;name=localedef;destsuffix=git/localedef;protocol=https \
+           \
+           file://0001-localedef-Add-hardlink-resolver-from-util-linux.patch \
+           file://0002-localedef-fix-ups-hardlink-to-make-it-compile.patch \
+           \
+           file://0017-timezone-re-written-tzselect-as-posix-sh.patch \
+           file://0018-Remove-bash-dependency-for-nscd-init-script.patch \
+           file://0019-eglibc-Cross-building-and-testing-instructions.patch \
+           file://0020-eglibc-Help-bootstrap-cross-toolchain.patch \
+           file://0021-eglibc-Resolve-__fpscr_values-on-SH4.patch \
+           file://0022-eglibc-Forward-port-cross-locale-generation-support.patch \
+           file://0024-localedef-add-to-archive-uses-a-hard-coded-locale-pa.patch \
+           file://0001-Add-array_length-support.patch \
+"
+# Makes for a rather long rev (22 characters), but...
+#
+SRCREV_FORMAT = "glibc_localedef"
+
+S = "${WORKDIR}/git"
+
+EXTRA_OECONF = "--with-glibc=${S}"
+CFLAGS += "-fgnu89-inline -std=gnu99 -DIS_IN\(x\)='0'"
+
+
+
+do_install() {
+	install -d ${D}${bindir}
+	install -m 0755 ${B}/localedef ${D}${bindir}/cross-localedef
+	install -m 0755 ${B}/cross-localedef-hardlink ${D}${bindir}/cross-localedef-hardlink
+}

+ 12 - 0
recipes-core/glibc/glibc-collateral.inc

@@ -0,0 +1,12 @@
+require glibc-common.inc
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/GPL-2.0-only;md5=801f80980d171dd6425610833a22dbe6 \
+                     file://${COMMON_LICENSE_DIR}/LGPL-2.1-only;md5=1a6d268fd218675ffea8be556788b780"
+
+deltask do_fetch
+deltask do_unpack
+deltask do_patch
+do_configure[noexec] = "1"
+do_compile[noexec] = "1"
+
+do_install[depends] += "virtual/${MLPREFIX}libc:do_stash_locale"

+ 25 - 0
recipes-core/glibc/glibc-common.inc

@@ -0,0 +1,25 @@
+SUMMARY = "GLIBC (GNU C Library)"
+DESCRIPTION = "The GNU C Library is used as the system C library in most systems with the Linux kernel."
+HOMEPAGE = "http://www.gnu.org/software/libc/libc.html"
+SECTION = "libs"
+LICENSE = "GPLv2 & LGPLv2.1"
+
+LIC_FILES_CHKSUM ?= "file://LICENSES;md5=1541fd8f5e8f1579512bf05f533371ba \
+      file://COPYING;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
+      file://posix/rxspencer/COPYRIGHT;md5=dc5485bb394a13b2332ec1c785f5d83a \
+      file://COPYING.LIB;md5=4fbd65380cdd255951079008b364516c"
+
+CVE_PRODUCT = "glibc"
+
+INHIBIT_DEFAULT_DEPS = "1"
+
+ARM_INSTRUCTION_SET_armv4 = "arm"
+ARM_INSTRUCTION_SET_armv5 = "arm"
+ARM_INSTRUCTION_SET_armv6 = "arm"
+#
+# We will skip parsing glibc when target system C library selection is not glibc
+# this helps in easing out parsing for non-glibc system libraries
+#
+COMPATIBLE_HOST_libc-musl_class-target = "null"
+
+PV = "2.35"

+ 20 - 0
recipes-core/glibc/glibc-ld.inc

@@ -0,0 +1,20 @@
+inherit linuxloader
+
+GLIBC_GETLOADER = "${@get_linuxloader(d)}"
+
+def glibc_dl_info(d):
+    infos = {'ldconfig':set(), 'lddrewrite':set()}
+
+    loaders = all_multilib_tune_values(d, "GLIBC_GETLOADER").split()
+    for loader in loaders:
+        infos['ldconfig'].add('{"' + loader + '",' + "FLAG_ELF_LIBC6" + ' }')
+        infos['lddrewrite'].add(loader)
+
+    infos['ldconfig'] = ','.join(sorted(infos['ldconfig']))
+    infos['lddrewrite'] = ' '.join(sorted(infos['lddrewrite']))
+    return infos
+
+EGLIBC_KNOWN_INTERPRETER_NAMES = "${@glibc_dl_info(d)['ldconfig']}"
+RTLDLIST = "${@glibc_dl_info(d)['lddrewrite']}"
+RTLDLIST_class-nativesdk = "${base_libdir}/${@bb.utils.contains('SDK_ARCH', 'x86_64', 'ld-linux-x86-64.so.2', 'ld-linux.so.2', d)}"
+glibc_dl_info[vardepsexclude] = "OVERRIDES"

+ 103 - 0
recipes-core/glibc/glibc-locale.inc

@@ -0,0 +1,103 @@
+require glibc-collateral.inc
+
+SUMMARY = "Locale data from glibc"
+
+BPN = "glibc"
+LOCALEBASEPN = "${MLPREFIX}glibc"
+
+# glibc-collateral.inc inhibits all default deps, but do_package needs objcopy
+# ERROR: objcopy failed with exit code 127 (cmd was 'i586-webos-linux-objcopy' --only-keep-debug 'glibc-locale/2.17-r0/package/usr/lib/gconv/IBM1166.so' 'glibc-locale/2.17-r0/package/usr/lib/gconv/.debug/IBM1166.so')
+# ERROR: Function failed: split_and_strip_files
+BINUTILSDEP = "virtual/${MLPREFIX}${TARGET_PREFIX}binutils:do_populate_sysroot"
+BINUTILSDEP_class-nativesdk = "virtual/${TARGET_PREFIX}binutils-crosssdk:do_populate_sysroot"
+do_package[depends] += "${BINUTILSDEP}"
+
+DEPENDS += "virtual/libc"
+
+# Binary locales are generated at build time if ENABLE_BINARY_LOCALE_GENERATION
+# is set. The idea is to avoid running localedef on the target (at first boot)
+# to decrease initial boot time and avoid localedef being killed by the OOM
+# killer which used to effectively break i18n on machines with < 128MB RAM.
+
+# default to disabled
+ENABLE_BINARY_LOCALE_GENERATION ?= "0"
+ENABLE_BINARY_LOCALE_GENERATION_pn-nativesdk-glibc-locale = "1"
+
+#enable locale generation on these arches
+# BINARY_LOCALE_ARCHES is a space separated list of regular expressions
+BINARY_LOCALE_ARCHES ?= "arc arm.* aarch64 i[3-6]86 x86_64 powerpc mips mips64 riscv32 riscv64"
+
+# set "1" to use cross-localedef for locale generation
+# set "0" for qemu emulation of native localedef for locale generation
+LOCALE_GENERATION_WITH_CROSS-LOCALEDEF = "1"
+
+PROVIDES = "virtual/libc-locale"
+
+PACKAGES = "localedef ${PN}-dbg"
+
+PACKAGES_DYNAMIC = "^locale-base-.* \
+                    ^glibc-gconv-.* ^glibc-charmap-.* ^glibc-localedata-.* ^glibc-binary-localedata-.* \
+                    ^${MLPREFIX}glibc-gconv$"
+
+# Create a glibc-binaries package
+ALLOW_EMPTY_${BPN}-binaries = "1"
+PACKAGES += "${BPN}-binaries"
+RRECOMMENDS_${BPN}-binaries =  "${@" ".join([p for p in d.getVar('PACKAGES').split() if p.find("glibc-binary") != -1])}"
+
+# Create a glibc-charmaps package
+ALLOW_EMPTY_${BPN}-charmaps = "1"
+PACKAGES += "${BPN}-charmaps"
+RRECOMMENDS_${BPN}-charmaps =  "${@" ".join([p for p in d.getVar('PACKAGES').split() if p.find("glibc-charmap") != -1])}"
+
+# Create a glibc-gconvs package
+ALLOW_EMPTY_${BPN}-gconvs = "1"
+PACKAGES += "${BPN}-gconvs"
+RRECOMMENDS_${BPN}-gconvs =  "${@" ".join([p for p in d.getVar('PACKAGES').split() if p.find("glibc-gconv") != -1])}"
+
+# Create a glibc-localedatas package
+ALLOW_EMPTY_${BPN}-localedatas = "1"
+PACKAGES += "${BPN}-localedatas"
+RRECOMMENDS_${BPN}-localedatas =  "${@" ".join([p for p in d.getVar('PACKAGES').split() if p.find("glibc-localedata") != -1])}"
+
+DESCRIPTION_localedef = "glibc: compile locale definition files"
+
+# glibc-gconv is dynamically added into PACKAGES, thus
+# FILES_glibc-gconv will not be automatically extended in multilib.
+# Explicitly add ${MLPREFIX} for FILES_glibc-gconv.
+FILES_${MLPREFIX}glibc-gconv = "${libdir}/gconv/*"
+FILES_localedef = "${bindir}/localedef"
+
+LOCALETREESRC = "${COMPONENTS_DIR}/${PACKAGE_ARCH}/glibc-stash-locale"
+
+copy_locale_files() {
+	local dir=$1 mode=$2
+
+	[ -e "${LOCALETREESRC}$dir" ] || return 0
+
+	for d in . $(find "${LOCALETREESRC}$dir" -type d -printf '%P '); do
+		install -d ${D}$dir/$d
+		find "${LOCALETREESRC}$dir/$d" -maxdepth 1 -type f \
+			-exec install -m $mode -t "${D}$dir/$d" {} \;
+	done
+}
+
+do_install() {
+	copy_locale_files ${bindir} 0755
+	copy_locale_files ${localedir} 0644
+	if [ ${PACKAGE_NO_GCONV} -eq 0 ]; then
+		copy_locale_files ${libdir}/gconv 0755
+		copy_locale_files ${datadir}/i18n 0644
+	else
+		# Remove the libdir if it is empty when gconv is not copied
+		find ${D}${libdir} -type d -empty -delete
+	fi
+	copy_locale_files ${datadir}/locale 0644
+	install -m 0644 ${LOCALETREESRC}/SUPPORTED ${WORKDIR}/SUPPORTED
+}
+
+inherit libc-package
+
+BBCLASSEXTEND = "nativesdk"
+
+# Don't scan for CVEs as glibc will be scanned
+CVE_PRODUCT = ""

+ 1 - 0
recipes-core/glibc/glibc-locale_2.35.bb

@@ -0,0 +1 @@
+require glibc-locale.inc

+ 16 - 0
recipes-core/glibc/glibc-mtrace.inc

@@ -0,0 +1,16 @@
+require glibc-collateral.inc
+
+SUMMARY = "mtrace utility provided by glibc"
+DESCRIPTION = "mtrace utility provided by glibc"
+RDEPENDS_${PN} = "perl"
+RPROVIDES_${PN} = "libc-mtrace"
+
+SRC = "${COMPONENTS_DIR}/${PACKAGE_ARCH}/glibc-stash-locale/scripts"
+
+do_install() {
+	install -d -m 0755 ${D}${bindir}
+	install -m 0755 ${SRC}/mtrace ${D}${bindir}/
+}
+
+# Don't scan for CVEs as glibc will be scanned
+CVE_PRODUCT = ""

+ 1 - 0
recipes-core/glibc/glibc-mtrace_2.35.bb

@@ -0,0 +1 @@
+require glibc-mtrace.inc

Разница между файлами не показана из-за своего большого размера
+ 16 - 0
recipes-core/glibc/glibc-package.inc


+ 23 - 0
recipes-core/glibc/glibc-scripts.inc

@@ -0,0 +1,23 @@
+require glibc-collateral.inc
+
+SUMMARY = "utility scripts provided by glibc"
+DESCRIPTION = "utility scripts provided by glibc"
+RDEPENDS_${PN} = "bash glibc-mtrace"
+
+SRC = "${COMPONENTS_DIR}/${PACKAGE_ARCH}/glibc-stash-locale/scripts"
+
+bashscripts = "sotruss xtrace"
+
+do_install() {
+	install -d -m 0755 ${D}${bindir}
+	for i in ${bashscripts}; do
+		install -m 0755 ${SRC}/$i ${D}${bindir}/
+	done
+}
+
+# sotruss script requires sotruss-lib.so (given by libsotruss package), 
+# to produce trace of the library calls.
+RDEPENDS_${PN} += "libsotruss"
+
+# Don't scan for CVEs as glibc will be scanned
+CVE_PRODUCT = ""

+ 1 - 0
recipes-core/glibc/glibc-scripts_2.35.bb

@@ -0,0 +1 @@
+require glibc-scripts.inc

+ 32 - 0
recipes-core/glibc/glibc-tests.inc

@@ -0,0 +1,32 @@
+EXCLUDE_FROM_WORLD = "1"
+
+# handle PN differences
+FILESEXTRAPATHS_prepend := "${THISDIR}/glibc:"
+
+# setup depends
+INHIBIT_DEFAULT_DEPS = ""
+
+python () {
+    libc = d.getVar("PREFERRED_PROVIDER_virtual/libc")
+    libclocale = d.getVar("PREFERRED_PROVIDER_virtual/libc-locale")
+    if libc != "glibc" or libclocale != "glibc-locale":
+        raise bb.parse.SkipRecipe("glibc-testsuite requires that virtual/libc is glibc")
+}
+
+DEPENDS += "glibc-locale libgcc gcc-runtime"
+
+# remove the initial depends
+DEPENDS_remove = "libgcc-initial"
+
+do_check[dirs] += "${B}"
+do_check () {
+    # clean out previous test results
+    oe_runmake tests-clean
+    # makefiles don't clean entirely (and also sometimes fails due to too many args)
+    find ${B} -type f -name "*.out" -delete
+    find ${B} -type f -name "*.test-result" -delete
+    find ${B}/catgets -name "*.cat" -delete
+    find ${B}/conform -name "symlist-*" -delete
+    [ ! -e ${B}/timezone/testdata ] || rm -rf ${B}/timezone/testdata
+}
+addtask do_check after do_compile

+ 35 - 0
recipes-core/glibc/glibc-testsuite_2.35.bb

@@ -0,0 +1,35 @@
+require glibc_${PV}.bb
+require glibc-tests.inc
+
+inherit qemu
+
+SRC_URI += "file://check-test-wrapper"
+
+# strip provides
+PROVIDES = ""
+
+DEPENDS += "${@'qemu-native' if d.getVar('TOOLCHAIN_TEST_TARGET') == 'user' else ''}"
+
+TOOLCHAIN_TEST_TARGET ??= "user"
+TOOLCHAIN_TEST_HOST ??= "localhost"
+TOOLCHAIN_TEST_HOST_USER ??= "root"
+TOOLCHAIN_TEST_HOST_PORT ??= "2222"
+
+do_check[nostamp] = "1"
+do_check_append () {
+    chmod 0755 ${WORKDIR}/check-test-wrapper
+
+    oe_runmake -i \
+        QEMU_SYSROOT="${RECIPE_SYSROOT}" \
+        QEMU_OPTIONS="${@qemu_target_binary(d)} ${QEMU_OPTIONS}" \
+        SSH_HOST="${TOOLCHAIN_TEST_HOST}" \
+        SSH_HOST_USER="${TOOLCHAIN_TEST_HOST_USER}" \
+        SSH_HOST_PORT="${TOOLCHAIN_TEST_HOST_PORT}" \
+        test-wrapper="${WORKDIR}/check-test-wrapper ${TOOLCHAIN_TEST_TARGET}" \
+        check
+}
+
+inherit nopackages
+deltask do_stash_locale
+deltask do_install
+deltask do_populate_sysroot

+ 8 - 0
recipes-core/glibc/glibc-version.inc

@@ -0,0 +1,8 @@
+SRCBRANCH ?= "master"
+PV = "2.35"
+SRCREV_glibc ?= "90f0ac10a74b2d43b5a65aab4be40565e359be43"
+SRCREV_localedef ?= "95c0221703ad970a52445e9eaf91c4aff35eebef"
+
+GLIBC_GIT_URI ?= "git://sourceware.org/git/glibc.git"
+
+UPSTREAM_CHECK_GITTAGREGEX = "(?P<pver>\d+\.\d+(\.(?!90)\d+)*)"

+ 52 - 0
recipes-core/glibc/glibc.inc

@@ -0,0 +1,52 @@
+require glibc-common.inc
+require glibc-ld.inc
+
+DEPENDS = "virtual/${TARGET_PREFIX}gcc libgcc-initial linux-libc-headers"
+
+PROVIDES = "virtual/libc"
+PROVIDES += "virtual/libintl virtual/libiconv"
+inherit autotools texinfo systemd
+
+LEAD_SONAME = "libc.so"
+
+# msgfmt could come from gettext-native but we don't depend on that and
+# disable for reproducibility
+CACHED_CONFIGUREVARS += " \
+  ac_cv_path_BASH_SHELL=${base_bindir}/bash \
+  ac_cv_prog_MSGFMT= \
+  libc_cv_slibdir=${base_libdir} \
+  libc_cv_rootsbindir=${base_sbindir} \
+  libc_cv_localedir=${localedir} \
+  libc_cv_ssp_strong=no \
+  libc_cv_ssp_all=no \
+  libc_cv_ssp=no \
+  libc_cv_include_x86_isa_level=no \
+"
+
+# ifunc doesn't appear to work on mips, casuses libbfd assertion failures
+CACHED_CONFIGUREVARS_append_mipsarch = " libc_cv_ld_gnu_indirect_function=no"
+
+GLIBC_EXTRA_OECONF ?= ""
+GLIBC_EXTRA_OECONF_class-nativesdk = ""
+
+# glibc uses PARALLELMFLAGS variable to pass parallel build info so transfer
+# PARALLEL_MAKE into PARALLELMFLAGS and empty out PARALLEL_MAKE
+EGLIBCPARALLELISM := "PARALLELMFLAGS="${PARALLEL_MAKE}""
+EXTRA_OEMAKE[vardepsexclude] += "EGLIBCPARALLELISM"
+EXTRA_OEMAKE += "${EGLIBCPARALLELISM}"
+PARALLEL_MAKE = ""
+
+# glibc make-syscalls.sh has a number of issues with /bin/dash and
+# it's output which make calls via the SHELL also has issues, so
+# ensure make uses /bin/bash
+EXTRA_OEMAKE += "SHELL=/bin/bash"
+
+do_configure_prepend() {
+	sed -e "s#/bin/bash#/bin/sh#" -i ${S}/elf/ldd.bash.in
+}
+
+# Enable backtrace from abort()
+do_configure_append_arm () {
+	echo "CFLAGS-abort.c = -fasynchronous-unwind-tables" >> ${B}/configparms
+	echo "CFLAGS-raise.c = -fasynchronous-unwind-tables" >> ${B}/configparms
+}

+ 59 - 0
recipes-core/glibc/glibc/0001-Add-array_length-support.patch

@@ -0,0 +1,59 @@
+From ce34f0e215324455bbb1e4b18f5723b081cae801 Mon Sep 17 00:00:00 2001
+From: Jun Yuan Tan <junyuan.tan@starfivetech.com>
+Date: Tue, 23 Nov 2021 12:08:27 +0800
+Subject: [PATCH 1/1] Add array_length support
+
+This is needed to build localedef from glibc 2.35 in master branch.
+(Commit f5117c6504888fab5423282a4607c552b90fd3f9)
+
+Signed-off-by: Jun Yuan Tan <junyuan.tan@starfivetech.com>
+---
+ localedef/include/array_length.h | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+ create mode 100644 localedef/include/array_length.h
+
+diff --git a/localedef/include/array_length.h b/localedef/include/array_length.h
+new file mode 100644
+index 0000000..12c5126
+--- /dev/null
++++ b/localedef/include/array_length.h
+@@ -0,0 +1,36 @@
++/* The array_length and array_end macros.
++   Copyright (C) 2017-2021 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, see
++   <https://www.gnu.org/licenses/>.  */
++
++#ifndef _ARRAY_LENGTH_H
++#define _ARRAY_LENGTH_H
++
++/* array_length (VAR) is the number of elements in the array VAR.  VAR
++   must evaluate to an array, not a pointer.  */
++#define array_length(var)                                               \
++  (sizeof (var) / sizeof ((var)[0])                                     \
++   + 0 * sizeof (struct {                                               \
++       _Static_assert (!__builtin_types_compatible_p                    \
++                       (__typeof (var), __typeof (&(var)[0])),          \
++                       "argument must be an array");                    \
++   }))
++
++/* array_end (VAR) is a pointer one past the end of the array VAR.
++   VAR must evaluate to an array, not a pointer.  */
++#define array_end(var) (&(var)[array_length (var)])
++
++#endif /* _ARRAY_LENGTH_H */
+-- 
+2.33.1
+

+ 43 - 0
recipes-core/glibc/glibc/0001-CVE-2021-38604.patch

@@ -0,0 +1,43 @@
+From b805aebd42364fe696e417808a700fdb9800c9e8 Mon Sep 17 00:00:00 2001
+From: Nikita Popov <npv1310@gmail.com>
+Date: Mon, 9 Aug 2021 20:17:34 +0530
+Subject: [PATCH] librt: fix NULL pointer dereference (bug 28213)
+
+Helper thread frees copied attribute on NOTIFY_REMOVED message
+received from the OS kernel.  Unfortunately, it fails to check whether
+copied attribute actually exists (data.attr != NULL).  This worked
+earlier because free() checks passed pointer before actually
+attempting to release corresponding memory.  But
+__pthread_attr_destroy assumes pointer is not NULL.
+
+So passing NULL pointer to __pthread_attr_destroy will result in
+segmentation fault.  This scenario is possible if
+notification->sigev_notify_attributes == NULL (which means default
+thread attributes should be used).
+
+Upstream-Status: Backport [https://sourceware.org/git/?p=glibc.git;a=commit;h=b805aebd42364fe696e417808a700fdb9800c9e8]
+CVE: CVE-2021-38604
+
+Signed-off-by: Nikita Popov <npv1310@gmail.com>
+Reviewed-by: Siddhesh Poyarekar <siddhesh@sourceware.org>
+Signed-off-by: Vinay Kumar <vinay.m.engg@gmail.com>
+---
+ sysdeps/unix/sysv/linux/mq_notify.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sysdeps/unix/sysv/linux/mq_notify.c b/sysdeps/unix/sysv/linux/mq_notify.c
+index 9799dcdaa4..eccae2e4c6 100644
+--- a/sysdeps/unix/sysv/linux/mq_notify.c
++++ b/sysdeps/unix/sysv/linux/mq_notify.c
+@@ -131,7 +131,7 @@ helper_thread (void *arg)
+ 	       to wait until it is done with it.  */
+ 	    (void) __pthread_barrier_wait (&notify_barrier);
+ 	}
+-      else if (data.raw[NOTIFY_COOKIE_LEN - 1] == NOTIFY_REMOVED)
++      else if (data.raw[NOTIFY_COOKIE_LEN - 1] == NOTIFY_REMOVED && data.attr != NULL)
+ 	{
+ 	  /* The only state we keep is the copy of the thread attributes.  */
+ 	  __pthread_attr_destroy (data.attr);
+-- 
+2.31.1
+

+ 79 - 0
recipes-core/glibc/glibc/0001-fix-create-thread-failed-in-unprivileged-process-BZ-.patch

@@ -0,0 +1,79 @@
+From a8bc44936202692edcd82a48c07d7cf27d6ed8ee Mon Sep 17 00:00:00 2001
+From: Hongxu Jia <hongxu.jia@windriver.com>
+Date: Sun, 29 Aug 2021 20:49:16 +0800
+Subject: [PATCH] fix create thread failed in unprivileged process [BZ #28287]
+
+Since commit [d8ea0d0168 Add an internal wrapper for clone, clone2 and clone3]
+applied, start a unprivileged container (docker run without --privileged),
+it creates a thread failed in container.
+
+In commit d8ea0d0168, it calls __clone3 if HAVE_CLONE3_WAPPER is defined.  If
+__clone3 returns -1 with ENOSYS, fall back to clone or clone2.
+
+As known from [1], cloneXXX fails with EPERM if CLONE_NEWCGROUP,
+CLONE_NEWIPC, CLONE_NEWNET, CLONE_NEWNS, CLONE_NEWPID, or CLONE_NEWUTS
+was specified by an unprivileged process (process without CAP_SYS_ADMIN)
+
+[1] https://man7.org/linux/man-pages/man2/clone3.2.html
+
+So if __clone3 returns -1 with EPERM, fall back to clone or clone2 could
+fix the issue. Here are the test steps:
+
+1) Prepare test code
+cat > conftest.c <<ENDOF
+ #include <pthread.h>
+ #include <stdio.h>
+
+int check_me = 0;
+void* func(void* data) {check_me = 42; printf("start thread: check_me %d\n", check_me); return &check_me;}
+int main()
+{
+  pthread_t t;
+  void *ret;
+  pthread_create (&t, 0, func, 0);
+  pthread_join (t, &ret);
+  printf("check_me %d, p %p\n", check_me, &ret);
+  return (check_me != 42 || ret != &check_me);
+}
+
+ENDOF
+
+2) Compile
+gcc -o conftest -pthread conftest.c
+
+3) Start a container with glibc 2.34 installed
+[skip details]
+docker run -it <container-image-name> bash
+
+4) Run conftest without this patch
+$ ./conftest
+check_me 0, p 0x7ffd91ccd400
+
+5) Run conftest with this patch
+$ ./conftest
+start thread: check_me 42
+check_me 42, p 0x7ffe253c6f20
+
+Upstream-Status: Submitted [libc-alpha@sourceware.org]
+
+Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
+---
+ sysdeps/unix/sysv/linux/clone-internal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sysdeps/unix/sysv/linux/clone-internal.c b/sysdeps/unix/sysv/linux/clone-internal.c
+index 979f7880be..97101994e8 100644
+--- a/sysdeps/unix/sysv/linux/clone-internal.c
++++ b/sysdeps/unix/sysv/linux/clone-internal.c
+@@ -52,7 +52,7 @@ __clone_internal (struct clone_args *cl_args,
+   /* Try clone3 first.  */
+   int saved_errno = errno;
+   ret = __clone3 (cl_args, sizeof (*cl_args), func, arg);
+-  if (ret != -1 || errno != ENOSYS)
++  if (ret != -1 || (errno != ENOSYS && errno != EPERM))
+     return ret;
+ 
+   /* NB: Restore errno since errno may be checked against non-zero
+-- 
+2.30.2
+

+ 1130 - 0
recipes-core/glibc/glibc/0001-localedef-Add-hardlink-resolver-from-util-linux.patch

@@ -0,0 +1,1130 @@
+From d34ba0833cd811f8869a6262044af55f9e7b59d8 Mon Sep 17 00:00:00 2001
+From: Jason Wessel <jason.wessel@windriver.com>
+Date: Sat, 7 Dec 2019 09:59:22 -0800
+Subject: [PATCH] localedef: Add hardlink resolver from util-linux
+
+The hard link resolver that is built into localedef cannot be run in
+parallel.  It will search sibling directories (which are be processed
+in parallel) and perform a creation of a .tmp file and remove the
+original and move the .tmp file in.  The problem is that if a probe
+occurs a hard link can be requested to the file that is being removed.
+This will lead to a stray copy or potentially, on a loaded system
+cause race condition which pseudo cannot deal with, where it is left
+with a hard link request to a file that no longer exists.  In this
+situation psuedo will inherit the permissions of what ever the target
+inode had to offer.
+
+In short, there are two problems:
+
+1) You will be left with stray copies when using the hard link
+resolution that is built in while running in parallel with
+localedef.
+
+2) When running under pseudo the possibility exists for uid/gid
+leakage when the source file is removed before the hard link can
+be completed.
+
+The solution is to call localedef with --no-hard-links and separately
+process the hardlinks at a later point.  To do this requires the
+inclusion of the hardlink utility found in modern versions of
+util-linux.  Most host systems do not have this, so it will be
+included with the cross-localedef binary.
+
+[YOCTO #11299]
+[YOCTO #12434]
+
+Upstream-Status: Pending
+
+Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ locale/programs/c.h                        | 407 ++++++++++++++++
+ locale/programs/cross-localedef-hardlink.c | 528 +++++++++++++++++++++
+ locale/programs/xalloc.h                   | 129 +++++
+ 3 files changed, 1064 insertions(+)
+ create mode 100644 locale/programs/c.h
+ create mode 100644 locale/programs/cross-localedef-hardlink.c
+ create mode 100644 locale/programs/xalloc.h
+
+diff --git a/locale/programs/c.h b/locale/programs/c.h
+new file mode 100644
+index 0000000000..d0a402e90e
+--- /dev/null
++++ b/locale/programs/c.h
+@@ -0,0 +1,407 @@
++/*
++ * Fundamental C definitions.
++ */
++
++#ifndef UTIL_LINUX_C_H
++#define UTIL_LINUX_C_H
++
++#include <limits.h>
++#include <stddef.h>
++#include <stdint.h>
++#include <stdio.h>
++#include <unistd.h>
++#include <stdarg.h>
++#include <stdlib.h>
++#include <string.h>
++#include <errno.h>
++
++#include <assert.h>
++
++#ifdef HAVE_ERR_H
++# include <err.h>
++#endif
++
++#ifdef HAVE_SYS_SYSMACROS_H
++# include <sys/sysmacros.h>     /* for major, minor */
++#endif
++
++#ifndef LOGIN_NAME_MAX
++# define LOGIN_NAME_MAX 256
++#endif
++
++#ifndef NAME_MAX
++# define NAME_MAX PATH_MAX
++#endif
++
++/*
++ * __GNUC_PREREQ is deprecated in favour of __has_attribute() and
++ * __has_feature(). The __has macros are supported by clang and gcc>=5.
++ */
++#ifndef __GNUC_PREREQ
++# if defined __GNUC__ && defined __GNUC_MINOR__
++#  define __GNUC_PREREQ(maj, min) \
++	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
++# else
++#  define __GNUC_PREREQ(maj, min) 0
++# endif
++#endif
++
++#ifdef __GNUC__
++
++/* &a[0] degrades to a pointer: a different type from an array */
++# define __must_be_array(a) \
++	UL_BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(__typeof__(a), __typeof__(&a[0])))
++
++# define ignore_result(x) __extension__ ({ \
++	__typeof__(x) __dummy __attribute__((__unused__)) = (x); (void) __dummy; \
++})
++
++#else /* !__GNUC__ */
++# define __must_be_array(a)	0
++# define __attribute__(_arg_)
++# define ignore_result(x) ((void) (x))
++#endif /* !__GNUC__ */
++
++/*
++ * It evaluates to 1 if the attribute/feature is supported by the current
++ * compilation targed. Fallback for old compilers.
++ */
++#ifndef __has_attribute
++  #define __has_attribute(x) 0
++#endif
++
++#ifndef __has_feature
++  #define __has_feature(x) 0
++#endif
++
++/*
++ * Function attributes
++ */
++#ifndef __ul_alloc_size
++# if (__has_attribute(alloc_size) && __has_attribute(warn_unused_result)) || __GNUC_PREREQ (4, 3)
++#  define __ul_alloc_size(s) __attribute__((alloc_size(s), warn_unused_result))
++# else
++#  define __ul_alloc_size(s)
++# endif
++#endif
++
++#ifndef __ul_calloc_size
++# if (__has_attribute(alloc_size) && __has_attribute(warn_unused_result)) || __GNUC_PREREQ (4, 3)
++#  define __ul_calloc_size(n, s) __attribute__((alloc_size(n, s), warn_unused_result))
++# else
++#  define __ul_calloc_size(n, s)
++# endif
++#endif
++
++#if __has_attribute(returns_nonnull) || __GNUC_PREREQ (4, 9)
++# define __ul_returns_nonnull __attribute__((returns_nonnull))
++#else
++# define __ul_returns_nonnull
++#endif
++
++/*
++ * Force a compilation error if condition is true, but also produce a
++ * result (of value 0 and type size_t), so the expression can be used
++ * e.g. in a structure initializer (or wherever else comma expressions
++ * aren't permitted).
++ */
++#define UL_BUILD_BUG_ON_ZERO(e) __extension__ (sizeof(struct { int:-!!(e); }))
++#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:-!!(e); }))
++
++#ifndef ARRAY_SIZE
++# define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
++#endif
++
++#ifndef PATH_MAX
++# define PATH_MAX 4096
++#endif
++
++#ifndef TRUE
++# define TRUE 1
++#endif
++
++#ifndef FALSE
++# define FALSE 0
++#endif
++
++#ifndef min
++# define min(x, y) __extension__ ({		\
++	__typeof__(x) _min1 = (x);		\
++	__typeof__(y) _min2 = (y);		\
++	(void) (&_min1 == &_min2);		\
++	_min1 < _min2 ? _min1 : _min2; })
++#endif
++
++#ifndef max
++# define max(x, y) __extension__ ({		\
++	__typeof__(x) _max1 = (x);		\
++	__typeof__(y) _max2 = (y);		\
++	(void) (&_max1 == &_max2);		\
++	_max1 > _max2 ? _max1 : _max2; })
++#endif
++
++#ifndef cmp_numbers
++# define cmp_numbers(x, y) __extension__ ({	\
++	__typeof__(x) _a = (x);			\
++	__typeof__(y) _b = (y);			\
++	(void) (&_a == &_b);			\
++	_a == _b ? 0 : _a > _b ? 1 : -1; })
++#endif
++
++#ifndef offsetof
++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
++#endif
++
++/*
++ * container_of - cast a member of a structure out to the containing structure
++ * @ptr:	the pointer to the member.
++ * @type:	the type of the container struct this is embedded in.
++ * @member:	the name of the member within the struct.
++ */
++#ifndef container_of
++#define container_of(ptr, type, member) __extension__ ({	\
++	const __typeof__( ((type *)0)->member ) *__mptr = (ptr); \
++	(type *)( (char *)__mptr - offsetof(type,member) );})
++#endif
++
++#ifndef HAVE_PROGRAM_INVOCATION_SHORT_NAME
++# ifdef HAVE___PROGNAME
++extern char *__progname;
++#  define program_invocation_short_name __progname
++# else
++#  ifdef HAVE_GETEXECNAME
++#   define program_invocation_short_name \
++		prog_inv_sh_nm_from_file(getexecname(), 0)
++#  else
++#   define program_invocation_short_name \
++		prog_inv_sh_nm_from_file(__FILE__, 1)
++#  endif
++static char prog_inv_sh_nm_buf[256];
++static inline char *
++prog_inv_sh_nm_from_file(char *f, char stripext)
++{
++	char *t;
++
++	if ((t = strrchr(f, '/')) != NULL)
++		t++;
++	else
++		t = f;
++
++	strncpy(prog_inv_sh_nm_buf, t, sizeof(prog_inv_sh_nm_buf) - 1);
++	prog_inv_sh_nm_buf[sizeof(prog_inv_sh_nm_buf) - 1] = '\0';
++
++	if (stripext && (t = strrchr(prog_inv_sh_nm_buf, '.')) != NULL)
++		*t = '\0';
++
++	return prog_inv_sh_nm_buf;
++}
++# endif
++#endif
++
++
++#ifndef HAVE_ERR_H
++static inline void
++errmsg(char doexit, int excode, char adderr, const char *fmt, ...)
++{
++	fprintf(stderr, "%s: ", program_invocation_short_name);
++	if (fmt != NULL) {
++		va_list argp;
++		va_start(argp, fmt);
++		vfprintf(stderr, fmt, argp);
++		va_end(argp);
++		if (adderr)
++			fprintf(stderr, ": ");
++	}
++	if (adderr)
++		fprintf(stderr, "%m");
++	fprintf(stderr, "\n");
++	if (doexit)
++		exit(excode);
++}
++
++#ifndef HAVE_ERR
++# define err(E, FMT...) errmsg(1, E, 1, FMT)
++#endif
++
++#ifndef HAVE_ERRX
++# define errx(E, FMT...) errmsg(1, E, 0, FMT)
++#endif
++
++#ifndef HAVE_WARN
++# define warn(FMT...) errmsg(0, 0, 1, FMT)
++#endif
++
++#ifndef HAVE_WARNX
++# define warnx(FMT...) errmsg(0, 0, 0, FMT)
++#endif
++#endif /* !HAVE_ERR_H */
++
++
++/* Don't use inline function to avoid '#include "nls.h"' in c.h
++ */
++#define errtryhelp(eval) __extension__ ({ \
++	fprintf(stderr, _("Try '%s --help' for more information.\n"), \
++			program_invocation_short_name); \
++	exit(eval); \
++})
++
++/* After failed execvp() */
++#define EX_EXEC_FAILED		126	/* Program located, but not usable. */
++#define EX_EXEC_ENOENT		127	/* Could not find program to exec.  */
++#define errexec(name)	err(errno == ENOENT ? EX_EXEC_ENOENT : EX_EXEC_FAILED, \
++			_("failed to execute %s"), name)
++
++
++static inline __attribute__((const)) int is_power_of_2(unsigned long num)
++{
++	return (num != 0 && ((num & (num - 1)) == 0));
++}
++
++#ifndef HAVE_LOFF_T
++typedef int64_t loff_t;
++#endif
++
++#if !defined(HAVE_DIRFD) && (!defined(HAVE_DECL_DIRFD) || HAVE_DECL_DIRFD == 0) && defined(HAVE_DIR_DD_FD)
++#include <sys/types.h>
++#include <dirent.h>
++static inline int dirfd(DIR *d)
++{
++	return d->dd_fd;
++}
++#endif
++
++/*
++ * Fallback defines for old versions of glibc
++ */
++#include <fcntl.h>
++
++#ifdef O_CLOEXEC
++#define UL_CLOEXECSTR	"e"
++#else
++#define UL_CLOEXECSTR	""
++#endif
++
++#ifndef O_CLOEXEC
++#define O_CLOEXEC 0
++#endif
++
++#ifdef __FreeBSD_kernel__
++#ifndef F_DUPFD_CLOEXEC
++#define F_DUPFD_CLOEXEC	17	/* Like F_DUPFD, but FD_CLOEXEC is set */
++#endif
++#endif
++
++
++#ifndef AI_ADDRCONFIG
++#define AI_ADDRCONFIG 0x0020
++#endif
++
++#ifndef IUTF8
++#define IUTF8 0040000
++#endif
++
++/*
++ * MAXHOSTNAMELEN replacement
++ */
++static inline size_t get_hostname_max(void)
++{
++	long len = sysconf(_SC_HOST_NAME_MAX);
++
++	if (0 < len)
++		return len;
++
++#ifdef MAXHOSTNAMELEN
++	return MAXHOSTNAMELEN;
++#elif HOST_NAME_MAX
++	return HOST_NAME_MAX;
++#endif
++	return 64;
++}
++
++
++/*
++ * Constant strings for usage() functions. For more info see
++ * Documentation/{howto-usage-function.txt,boilerplate.c}
++ */
++#define USAGE_HEADER     ("\nUsage:\n")
++#define USAGE_OPTIONS    ("\nOptions:\n")
++#define USAGE_FUNCTIONS  ("\nFunctions:\n")
++#define USAGE_COMMANDS   ("\nCommands:\n")
++#define USAGE_COLUMNS    ("\nAvailable output columns:\n")
++#define USAGE_SEPARATOR    "\n"
++
++#define USAGE_OPTSTR_HELP     ("display this help")
++#define USAGE_OPTSTR_VERSION  ("display version")
++
++#define USAGE_HELP_OPTIONS(marg_dsc) \
++		"%-" #marg_dsc "s%s\n" \
++		"%-" #marg_dsc "s%s\n" \
++		, " -h, --help",    USAGE_OPTSTR_HELP \
++		, " -V, --version", USAGE_OPTSTR_VERSION
++
++#define USAGE_MAN_TAIL(_man)   ("\nFor more details see %s.\n"), _man
++
++#define UTIL_LINUX_VERSION ("%s from %s\n"), program_invocation_short_name, PACKAGE_STRING
++
++#define print_version(eval) __extension__ ({ \
++		printf(UTIL_LINUX_VERSION); \
++		exit(eval); \
++})
++
++/*
++ * scanf modifiers for "strings allocation"
++ */
++#ifdef HAVE_SCANF_MS_MODIFIER
++#define UL_SCNsA	"%ms"
++#elif defined(HAVE_SCANF_AS_MODIFIER)
++#define UL_SCNsA	"%as"
++#endif
++
++/*
++ * seek stuff
++ */
++#ifndef SEEK_DATA
++# define SEEK_DATA	3
++#endif
++#ifndef SEEK_HOLE
++# define SEEK_HOLE	4
++#endif
++
++
++/*
++ * Macros to convert #define'itions to strings, for example
++ * #define XYXXY 42
++ * printf ("%s=%s\n", stringify(XYXXY), stringify_value(XYXXY));
++ */
++#define stringify_value(s) stringify(s)
++#define stringify(s) #s
++
++/*
++ * UL_ASAN_BLACKLIST is a macro to tell AddressSanitizer (a compile-time
++ * instrumentation shipped with Clang and GCC) to not instrument the
++ * annotated function.  Furthermore, it will prevent the compiler from
++ * inlining the function because inlining currently breaks the blacklisting
++ * mechanism of AddressSanitizer.
++ */
++#if __has_feature(address_sanitizer) && __has_attribute(no_sanitize_memory) && __has_attribute(no_sanitize_address)
++# define UL_ASAN_BLACKLIST __attribute__((noinline)) __attribute__((no_sanitize_memory)) __attribute__((no_sanitize_address))
++#else
++# define UL_ASAN_BLACKLIST	/* nothing */
++#endif
++
++/*
++ * Note that sysconf(_SC_GETPW_R_SIZE_MAX) returns *initial* suggested size for
++ * pwd buffer and in some cases it is not large enough. See POSIX and
++ * getpwnam_r man page for more details.
++ */
++#define UL_GETPW_BUFSIZ	(16 * 1024)
++
++/*
++ * Darwin or other BSDs may only have MAP_ANON. To get it on Darwin we must
++ * define _DARWIN_C_SOURCE before including sys/mman.h. We do this in config.h.
++ */
++#if !defined MAP_ANONYMOUS && defined MAP_ANON
++# define MAP_ANONYMOUS  (MAP_ANON)
++#endif
++
++#endif /* UTIL_LINUX_C_H */
+diff --git a/locale/programs/cross-localedef-hardlink.c b/locale/programs/cross-localedef-hardlink.c
+new file mode 100644
+index 0000000000..63615896b0
+--- /dev/null
++++ b/locale/programs/cross-localedef-hardlink.c
+@@ -0,0 +1,528 @@
++/*
++ * hardlink - consolidate duplicate files via hardlinks
++ *
++ * Copyright (C) 2018 Red Hat, Inc. All rights reserved.
++ * Written by Jakub Jelinek <jakub@redhat.com>
++ *
++ * Copyright (C) 2019 Karel Zak <kzak@redhat.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it would be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <sys/types.h>
++#include <stdlib.h>
++#include <getopt.h>
++#include <stdio.h>
++#include <unistd.h>
++#include <sys/stat.h>
++#include <sys/mman.h>
++#include <string.h>
++#include <dirent.h>
++#include <fcntl.h>
++#include <errno.h>
++#ifdef HAVE_PCRE
++# define PCRE2_CODE_UNIT_WIDTH 8
++# include <pcre2.h>
++#endif
++
++#include "c.h"
++#include "xalloc.h"
++#include "nls.h"
++#include "closestream.h"
++
++#define NHASH   (1<<17)  /* Must be a power of 2! */
++#define NBUF    64
++
++struct hardlink_file;
++
++struct hardlink_hash {
++	struct hardlink_hash *next;
++	struct hardlink_file *chain;
++	off_t size;
++	time_t mtime;
++};
++
++struct hardlink_dir {
++	struct hardlink_dir *next;
++	char name[];
++};
++
++struct hardlink_file {
++	struct hardlink_file *next;
++	ino_t ino;
++	dev_t dev;
++	unsigned int cksum;
++	char name[];
++};
++
++struct hardlink_dynstr {
++	char *buf;
++	size_t alloc;
++};
++
++struct hardlink_ctl {
++	struct hardlink_dir *dirs;
++	struct hardlink_hash *hps[NHASH];
++	char iobuf1[BUFSIZ];
++	char iobuf2[BUFSIZ];
++	/* summary counters */
++	unsigned long long ndirs;
++	unsigned long long nobjects;
++	unsigned long long nregfiles;
++	unsigned long long ncomp;
++	unsigned long long nlinks;
++	unsigned long long nsaved;
++	/* current device */
++	dev_t dev;
++	/* flags */
++	unsigned int verbose;
++	unsigned int
++		no_link:1,
++		content_only:1,
++		force:1;
++};
++/* ctl is in global scope due use in atexit() */
++struct hardlink_ctl global_ctl;
++
++__attribute__ ((always_inline))
++static inline unsigned int hash(off_t size, time_t mtime)
++{
++	return (size ^ mtime) & (NHASH - 1);
++}
++
++__attribute__ ((always_inline))
++static inline int stcmp(struct stat *st1, struct stat *st2, int content_scope)
++{
++	if (content_scope)
++		return st1->st_size != st2->st_size;
++
++	return st1->st_mode != st2->st_mode
++		|| st1->st_uid != st2->st_uid
++		|| st1->st_gid != st2->st_gid
++		|| st1->st_size != st2->st_size
++		|| st1->st_mtime != st2->st_mtime;
++}
++
++static void print_summary(void)
++{
++	struct hardlink_ctl const *const ctl = &global_ctl;
++
++	if (!ctl->verbose)
++		return;
++
++	if (ctl->verbose > 1 && ctl->nlinks)
++		fputc('\n', stdout);
++
++	printf(_("Directories:   %9lld\n"), ctl->ndirs);
++	printf(_("Objects:       %9lld\n"), ctl->nobjects);
++	printf(_("Regular files: %9lld\n"), ctl->nregfiles);
++	printf(_("Comparisons:   %9lld\n"), ctl->ncomp);
++	printf(  "%s%9lld\n", (ctl->no_link ?
++	       _("Would link:    ") :
++	       _("Linked:        ")), ctl->nlinks);
++	printf(  "%s %9lld\n", (ctl->no_link ?
++	       _("Would save:   ") :
++	       _("Saved:        ")), ctl->nsaved);
++}
++
++static void __attribute__((__noreturn__)) usage(void)
++{
++	fputs(USAGE_HEADER, stdout);
++	printf(_(" %s [options] directory...\n"), program_invocation_short_name);
++
++	fputs(USAGE_SEPARATOR, stdout);
++	puts(_("Consolidate duplicate files using hardlinks."));
++
++	fputs(USAGE_OPTIONS, stdout);
++	puts(_(" -c, --content          compare only contents, ignore permission, etc."));
++	puts(_(" -n, --dry-run          don't actually link anything"));
++	puts(_(" -v, --verbose          print summary after hardlinking"));
++	puts(_(" -vv                    print every hardlinked file and summary"));
++	puts(_(" -f, --force            force hardlinking across filesystems"));
++	puts(_(" -x, --exclude <regex>  exclude files matching pattern"));
++
++	fputs(USAGE_SEPARATOR, stdout);
++	printf(USAGE_HELP_OPTIONS(16)); /* char offset to align option descriptions */
++	printf(USAGE_MAN_TAIL("hardlink(1)"));
++	exit(EXIT_SUCCESS);
++}
++
++__attribute__ ((always_inline))
++static inline size_t add2(size_t a, size_t b)
++{
++	size_t sum = a + b;
++
++	if (sum < a)
++		errx(EXIT_FAILURE, _("integer overflow"));
++	return sum;
++}
++
++__attribute__ ((always_inline))
++static inline size_t add3(size_t a, size_t b, size_t c)
++{
++	return add2(add2(a, b), c);
++}
++
++static void growstr(struct hardlink_dynstr *str, size_t newlen)
++{
++	if (newlen < str->alloc)
++		return;
++	str->buf = xrealloc(str->buf, str->alloc = add2(newlen, 1));
++}
++
++static void process_path(struct hardlink_ctl *ctl, const char *name)
++{
++	struct stat st, st2, st3;
++	const size_t namelen = strlen(name);
++
++	ctl->nobjects++;
++	if (lstat(name, &st))
++		return;
++
++	if (st.st_dev != ctl->dev && !ctl->force) {
++		if (ctl->dev)
++			errx(EXIT_FAILURE,
++			     _("%s is on different filesystem than the rest "
++			       "(use -f option to override)."), name);
++		ctl->dev = st.st_dev;
++	}
++	if (S_ISDIR(st.st_mode)) {
++		struct hardlink_dir *dp = xmalloc(add3(sizeof(*dp), namelen, 1));
++		memcpy(dp->name, name, namelen + 1);
++		dp->next = ctl->dirs;
++		ctl->dirs = dp;
++
++	} else if (S_ISREG(st.st_mode)) {
++		int fd, i;
++		struct hardlink_file *fp, *fp2;
++		struct hardlink_hash *hp;
++		const char *n1, *n2;
++		unsigned int buf[NBUF];
++		int cksumsize = sizeof(buf);
++		unsigned int cksum;
++		time_t mtime = ctl->content_only ? 0 : st.st_mtime;
++		unsigned int hsh = hash(st.st_size, mtime);
++		off_t fsize;
++
++		ctl->nregfiles++;
++		if (ctl->verbose > 1)
++			printf("%s\n", name);
++
++		fd = open(name, O_RDONLY);
++		if (fd < 0)
++			return;
++
++		if ((size_t)st.st_size < sizeof(buf)) {
++			cksumsize = st.st_size;
++			memset(((char *)buf) + cksumsize, 0,
++			       (sizeof(buf) - cksumsize) % sizeof(buf[0]));
++		}
++		if (read(fd, buf, cksumsize) != cksumsize) {
++			close(fd);
++			return;
++		}
++		cksumsize = (cksumsize + sizeof(buf[0]) - 1) / sizeof(buf[0]);
++		for (i = 0, cksum = 0; i < cksumsize; i++) {
++			if (cksum + buf[i] < cksum)
++				cksum += buf[i] + 1;
++			else
++				cksum += buf[i];
++		}
++		for (hp = ctl->hps[hsh]; hp; hp = hp->next) {
++			if (hp->size == st.st_size && hp->mtime == mtime)
++				break;
++		}
++		if (!hp) {
++			hp = xmalloc(sizeof(*hp));
++			hp->size = st.st_size;
++			hp->mtime = mtime;
++			hp->chain = NULL;
++			hp->next = ctl->hps[hsh];
++			ctl->hps[hsh] = hp;
++		}
++		for (fp = hp->chain; fp; fp = fp->next) {
++			if (fp->cksum == cksum)
++				break;
++		}
++		for (fp2 = fp; fp2 && fp2->cksum == cksum; fp2 = fp2->next) {
++			if (fp2->ino == st.st_ino && fp2->dev == st.st_dev) {
++				close(fd);
++				return;
++			}
++		}
++		for (fp2 = fp; fp2 && fp2->cksum == cksum; fp2 = fp2->next) {
++
++			if (!lstat(fp2->name, &st2) && S_ISREG(st2.st_mode) &&
++			    !stcmp(&st, &st2, ctl->content_only) &&
++			    st2.st_ino != st.st_ino &&
++			    st2.st_dev == st.st_dev) {
++
++				int fd2 = open(fp2->name, O_RDONLY);
++				if (fd2 < 0)
++					continue;
++
++				if (fstat(fd2, &st2) || !S_ISREG(st2.st_mode)
++				    || st2.st_size == 0) {
++					close(fd2);
++					continue;
++				}
++				ctl->ncomp++;
++				lseek(fd, 0, SEEK_SET);
++
++				for (fsize = st.st_size; fsize > 0;
++				     fsize -= (off_t)sizeof(ctl->iobuf1)) {
++					ssize_t xsz;
++					ssize_t rsize = fsize > (ssize_t) sizeof(ctl->iobuf1) ?
++							(ssize_t) sizeof(ctl->iobuf1) : fsize;
++
++					if ((xsz = read(fd, ctl->iobuf1, rsize)) != rsize)
++						warn(_("cannot read %s"), name);
++					else if ((xsz = read(fd2, ctl->iobuf2, rsize)) != rsize)
++						warn(_("cannot read %s"), fp2->name);
++
++					if (xsz != rsize) {
++						close(fd);
++						close(fd2);
++						return;
++					}
++					if (memcmp(ctl->iobuf1, ctl->iobuf2, rsize))
++						break;
++				}
++				close(fd2);
++				if (fsize > 0)
++					continue;
++				if (lstat(name, &st3)) {
++					warn(_("cannot stat %s"), name);
++					close(fd);
++					return;
++				}
++				st3.st_atime = st.st_atime;
++				if (stcmp(&st, &st3, 0)) {
++					warnx(_("file %s changed underneath us"), name);
++					close(fd);
++					return;
++				}
++				n1 = fp2->name;
++				n2 = name;
++
++				if (!ctl->no_link) {
++					const char *suffix =
++					    ".$$$___cleanit___$$$";
++					const size_t suffixlen = strlen(suffix);
++					size_t n2len = strlen(n2);
++					struct hardlink_dynstr nam2 = { NULL, 0 };
++
++					growstr(&nam2, add2(n2len, suffixlen));
++					memcpy(nam2.buf, n2, n2len);
++					memcpy(&nam2.buf[n2len], suffix,
++					       suffixlen + 1);
++					/* First create a temporary link to n1 under a new name */
++					if (link(n1, nam2.buf)) {
++						warn(_("failed to hardlink %s to %s (create temporary link as %s failed)"),
++							n1, n2, nam2.buf);
++						free(nam2.buf);
++						continue;
++					}
++					/* Then rename into place over the existing n2 */
++					if (rename(nam2.buf, n2)) {
++						warn(_("failed to hardlink %s to %s (rename temporary link to %s failed)"),
++							n1, n2, n2);
++						/* Something went wrong, try to remove the now redundant temporary link */
++						if (unlink(nam2.buf))
++							warn(_("failed to remove temporary link %s"), nam2.buf);
++						free(nam2.buf);
++						continue;
++					}
++					free(nam2.buf);
++				}
++				ctl->nlinks++;
++				if (st3.st_nlink > 1) {
++					/* We actually did not save anything this time, since the link second argument
++					   had some other links as well.  */
++					if (ctl->verbose > 1)
++						printf(_(" %s %s to %s\n"),
++							(ctl->no_link ? _("Would link") : _("Linked")),
++							n1, n2);
++				} else {
++					ctl->nsaved += ((st.st_size + 4095) / 4096) * 4096;
++					if (ctl->verbose > 1)
++						printf(_(" %s %s to %s, %s %jd\n"),
++							(ctl->no_link ? _("Would link") : _("Linked")),
++							n1, n2,
++							(ctl->no_link ? _("would save") : _("saved")),
++							(intmax_t)st.st_size);
++				}
++				close(fd);
++				return;
++			}
++		}
++		fp2 = xmalloc(add3(sizeof(*fp2), namelen, 1));
++		close(fd);
++		fp2->ino = st.st_ino;
++		fp2->dev = st.st_dev;
++		fp2->cksum = cksum;
++		memcpy(fp2->name, name, namelen + 1);
++
++		if (fp) {
++			fp2->next = fp->next;
++			fp->next = fp2;
++		} else {
++			fp2->next = hp->chain;
++			hp->chain = fp2;
++		}
++		return;
++	}
++}
++
++int main(int argc, char **argv)
++{
++	int ch;
++	int i;
++#ifdef HAVE_PCRE
++	int errornumber;
++	PCRE2_SIZE erroroffset;
++	pcre2_code *re = NULL;
++	PCRE2_SPTR exclude_pattern = NULL;
++	pcre2_match_data *match_data = NULL;
++#endif
++	struct hardlink_dynstr nam1 = { NULL, 0 };
++	struct hardlink_ctl *ctl = &global_ctl;
++
++	static const struct option longopts[] = {
++		{ "content",    no_argument, NULL, 'c' },
++		{ "dry-run",    no_argument, NULL, 'n' },
++		{ "exclude",    required_argument, NULL, 'x' },
++		{ "force",      no_argument, NULL, 'f' },
++		{ "help",       no_argument, NULL, 'h' },
++		{ "verbose",    no_argument, NULL, 'v' },
++		{ "version",    no_argument, NULL, 'V' },
++		{ NULL, 0, NULL, 0 },
++	};
++
++	setlocale(LC_ALL, "");
++	bindtextdomain(PACKAGE, LOCALEDIR);
++	textdomain(PACKAGE);
++	close_stdout_atexit();
++
++	while ((ch = getopt_long(argc, argv, "cnvfx:Vh", longopts, NULL)) != -1) {
++		switch (ch) {
++		case 'n':
++			ctl->no_link = 1;
++			break;
++		case 'v':
++			ctl->verbose++;
++			break;
++		case 'c':
++			ctl->content_only = 1;
++			break;
++		case 'f':
++			ctl->force = 1;
++			break;
++		case 'x':
++#ifdef HAVE_PCRE
++			exclude_pattern = (PCRE2_SPTR) optarg;
++#else
++			errx(EXIT_FAILURE,
++			     _("option --exclude not supported (built without pcre2)"));
++#endif
++			break;
++		case 'V':
++			print_version(EXIT_SUCCESS);
++		case 'h':
++			usage();
++		default:
++			errtryhelp(EXIT_FAILURE);
++		}
++	}
++
++	if (optind == argc) {
++		warnx(_("no directory specified"));
++		errtryhelp(EXIT_FAILURE);
++	}
++
++#ifdef HAVE_PCRE
++	if (exclude_pattern) {
++		re = pcre2_compile(exclude_pattern, /* the pattern */
++				   PCRE2_ZERO_TERMINATED, /* indicates pattern is zero-terminate */
++				   0, /* default options */
++				   &errornumber, &erroroffset, NULL); /* use default compile context */
++		if (!re) {
++			PCRE2_UCHAR buffer[256];
++			pcre2_get_error_message(errornumber, buffer,
++						sizeof(buffer));
++			errx(EXIT_FAILURE, _("pattern error at offset %d: %s"),
++				(int)erroroffset, buffer);
++		}
++		match_data = pcre2_match_data_create_from_pattern(re, NULL);
++	}
++#endif
++	atexit(print_summary);
++
++	for (i = optind; i < argc; i++)
++		process_path(ctl, argv[i]);
++
++	while (ctl->dirs) {
++		DIR *dh;
++		struct dirent *di;
++		struct hardlink_dir *dp = ctl->dirs;
++		size_t nam1baselen = strlen(dp->name);
++
++		ctl->dirs = dp->next;
++		growstr(&nam1, add2(nam1baselen, 1));
++		memcpy(nam1.buf, dp->name, nam1baselen);
++		free(dp);
++		nam1.buf[nam1baselen++] = '/';
++		nam1.buf[nam1baselen] = 0;
++		dh = opendir(nam1.buf);
++
++		if (dh == NULL)
++			continue;
++		ctl->ndirs++;
++
++		while ((di = readdir(dh)) != NULL) {
++			if (!di->d_name[0])
++				continue;
++			if (di->d_name[0] == '.') {
++				if (!di->d_name[1] || !strcmp(di->d_name, ".."))
++					continue;
++			}
++#ifdef HAVE_PCRE
++			if (re && pcre2_match(re, /* compiled regex */
++					      (PCRE2_SPTR) di->d_name, strlen(di->d_name), 0, /* start at offset 0 */
++					      0, /* default options */
++					      match_data, /* block for storing the result */
++					      NULL) /* use default match context */
++			    >=0) {
++				if (ctl->verbose) {
++					nam1.buf[nam1baselen] = 0;
++					printf(_("Skipping %s%s\n"), nam1.buf, di->d_name);
++				}
++				continue;
++			}
++#endif
++			{
++				size_t subdirlen;
++				growstr(&nam1,
++					add2(nam1baselen, subdirlen =
++					     strlen(di->d_name)));
++				memcpy(&nam1.buf[nam1baselen], di->d_name,
++				       add2(subdirlen, 1));
++			}
++			process_path(ctl, nam1.buf);
++		}
++		closedir(dh);
++	}
++
++	return 0;
++}
+diff --git a/locale/programs/xalloc.h b/locale/programs/xalloc.h
+new file mode 100644
+index 0000000000..0129a85e2e
+--- /dev/null
++++ b/locale/programs/xalloc.h
+@@ -0,0 +1,129 @@
++/*
++ * Copyright (C) 2010 Davidlohr Bueso <dave@gnu.org>
++ *
++ * This file may be redistributed under the terms of the
++ * GNU Lesser General Public License.
++ *
++ * General memory allocation wrappers for malloc, realloc, calloc and strdup
++ */
++
++#ifndef UTIL_LINUX_XALLOC_H
++#define UTIL_LINUX_XALLOC_H
++
++#include <stdlib.h>
++#include <string.h>
++
++#include "c.h"
++
++#ifndef XALLOC_EXIT_CODE
++# define XALLOC_EXIT_CODE EXIT_FAILURE
++#endif
++
++static inline void __attribute__((__noreturn__))
++__err_oom(const char *file, unsigned int line)
++{
++	err(XALLOC_EXIT_CODE, "%s: %u: cannot allocate memory", file, line);
++}
++
++#define err_oom()	__err_oom(__FILE__, __LINE__)
++
++static inline __ul_alloc_size(1) __ul_returns_nonnull
++void *xmalloc(const size_t size)
++{
++        void *ret = malloc(size);
++
++        if (!ret && size)
++                err(XALLOC_EXIT_CODE, "cannot allocate %zu bytes", size);
++        return ret;
++}
++
++static inline __ul_alloc_size(2) __ul_returns_nonnull
++void *xrealloc(void *ptr, const size_t size)
++{
++        void *ret = realloc(ptr, size);
++
++        if (!ret && size)
++                err(XALLOC_EXIT_CODE, "cannot allocate %zu bytes", size);
++        return ret;
++}
++
++static inline __ul_calloc_size(1, 2) __ul_returns_nonnull
++void *xcalloc(const size_t nelems, const size_t size)
++{
++        void *ret = calloc(nelems, size);
++
++        if (!ret && size && nelems)
++                err(XALLOC_EXIT_CODE, "cannot allocate %zu bytes", size);
++        return ret;
++}
++
++static inline char __attribute__((warn_unused_result)) __ul_returns_nonnull
++*xstrdup(const char *str)
++{
++        char *ret;
++
++        if (!str)
++                return NULL;
++
++        ret = strdup(str);
++
++        if (!ret)
++                err(XALLOC_EXIT_CODE, "cannot duplicate string");
++        return ret;
++}
++
++static inline char * __attribute__((warn_unused_result)) __ul_returns_nonnull
++xstrndup(const char *str, size_t size)
++{
++        char *ret;
++
++        if (!str)
++                return NULL;
++
++        ret = strndup(str, size);
++
++        if (!ret)
++                err(XALLOC_EXIT_CODE, "cannot duplicate string");
++        return ret;
++}
++
++
++static inline int __attribute__ ((__format__(printf, 2, 3)))
++    xasprintf(char **strp, const char *fmt, ...)
++{
++	int ret;
++	va_list args;
++	va_start(args, fmt);
++	ret = vasprintf(&(*strp), fmt, args);
++	va_end(args);
++	if (ret < 0)
++		err(XALLOC_EXIT_CODE, "cannot allocate string");
++	return ret;
++}
++
++static inline int  __attribute__ ((__format__(printf, 2, 0)))
++xvasprintf(char **strp, const char *fmt, va_list ap)
++{
++	int ret = vasprintf(&(*strp), fmt, ap);
++	if (ret < 0)
++		err(XALLOC_EXIT_CODE, "cannot allocate string");
++	return ret;
++}
++
++
++static inline char * __attribute__((warn_unused_result)) xgethostname(void)
++{
++	char *name;
++	size_t sz = get_hostname_max() + 1;
++
++	name = xmalloc(sizeof(char) * sz);
++
++	if (gethostname(name, sz) != 0) {
++		free(name);
++		return NULL;
++	}
++	name[sz - 1] = '\0';
++	return name;
++}
++
++#endif

+ 150 - 0
recipes-core/glibc/glibc/0002-CVE-2021-38604.patch

@@ -0,0 +1,150 @@
+From 4cc79c217744743077bf7a0ec5e0a4318f1e6641 Mon Sep 17 00:00:00 2001
+From: Nikita Popov <npv1310@gmail.com>
+Date: Thu, 12 Aug 2021 16:09:50 +0530
+Subject: [PATCH] librt: add test (bug 28213)
+
+This test implements following logic:
+1) Create POSIX message queue.
+   Register a notification with mq_notify (using NULL attributes).
+   Then immediately unregister the notification with mq_notify.
+   Helper thread in a vulnerable version of glibc
+   should cause NULL pointer dereference after these steps.
+2) Once again, register the same notification.
+   Try to send a dummy message.
+   Test is considered successfulif the dummy message
+   is successfully received by the callback function.
+
+Upstream-Status: Backport [https://sourceware.org/git/?p=glibc.git;a=commit;h=4cc79c217744743077bf7a0ec5e0a4318f1e6641]
+CVE: CVE-2021-38604
+
+Signed-off-by: Nikita Popov <npv1310@gmail.com>
+Reviewed-by: Siddhesh Poyarekar <siddhesh@sourceware.org>
+Signed-off-by: Vinay Kumar <vinay.m.engg@gmail.com>
+---
+ rt/Makefile      |   1 +
+ rt/tst-bz28213.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 102 insertions(+)
+ create mode 100644 rt/tst-bz28213.c
+
+diff --git a/rt/Makefile b/rt/Makefile
+index 113cea03a5..910e775995 100644
+--- a/rt/Makefile
++++ b/rt/Makefile
+@@ -74,6 +74,7 @@ tests := tst-shm tst-timer tst-timer2 \
+ 	 tst-aio7 tst-aio8 tst-aio9 tst-aio10 \
+ 	 tst-mqueue1 tst-mqueue2 tst-mqueue3 tst-mqueue4 \
+ 	 tst-mqueue5 tst-mqueue6 tst-mqueue7 tst-mqueue8 tst-mqueue9 \
++	 tst-bz28213 \
+ 	 tst-timer3 tst-timer4 tst-timer5 \
+ 	 tst-cpuclock2 tst-cputimer1 tst-cputimer2 tst-cputimer3 \
+ 	 tst-shm-cancel \
+diff --git a/rt/tst-bz28213.c b/rt/tst-bz28213.c
+new file mode 100644
+index 0000000000..0c096b5a0a
+--- /dev/null
++++ b/rt/tst-bz28213.c
+@@ -0,0 +1,101 @@
++/* Bug 28213: test for NULL pointer dereference in mq_notify.
++   Copyright (C) The GNU Toolchain Authors.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, see
++   <https://www.gnu.org/licenses/>.  */
++
++#include <errno.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <fcntl.h>
++#include <unistd.h>
++#include <mqueue.h>
++#include <signal.h>
++#include <stdlib.h>
++#include <string.h>
++#include <support/check.h>
++
++static mqd_t m = -1;
++static const char msg[] = "hello";
++
++static void
++check_bz28213_cb (union sigval sv)
++{
++  char buf[sizeof (msg)];
++
++  (void) sv;
++
++  TEST_VERIFY_EXIT ((size_t) mq_receive (m, buf, sizeof (buf), NULL)
++		    == sizeof (buf));
++  TEST_VERIFY_EXIT (memcmp (buf, msg, sizeof (buf)) == 0);
++
++  exit (0);
++}
++
++static void
++check_bz28213 (void)
++{
++  struct sigevent sev;
++
++  memset (&sev, '\0', sizeof (sev));
++  sev.sigev_notify = SIGEV_THREAD;
++  sev.sigev_notify_function = check_bz28213_cb;
++
++  /* Step 1: Register & unregister notifier.
++     Helper thread should receive NOTIFY_REMOVED notification.
++     In a vulnerable version of glibc, NULL pointer dereference follows. */
++  TEST_VERIFY_EXIT (mq_notify (m, &sev) == 0);
++  TEST_VERIFY_EXIT (mq_notify (m, NULL) == 0);
++
++  /* Step 2: Once again, register notification.
++     Try to send one message.
++     Test is considered successful, if the callback does exit (0). */
++  TEST_VERIFY_EXIT (mq_notify (m, &sev) == 0);
++  TEST_VERIFY_EXIT (mq_send (m, msg, sizeof (msg), 1) == 0);
++
++  /* Wait... */
++  pause ();
++}
++
++static int
++do_test (void)
++{
++  static const char m_name[] = "/bz28213_queue";
++  struct mq_attr m_attr;
++
++  memset (&m_attr, '\0', sizeof (m_attr));
++  m_attr.mq_maxmsg = 1;
++  m_attr.mq_msgsize = sizeof (msg);
++
++  m = mq_open (m_name,
++               O_RDWR | O_CREAT | O_EXCL,
++               0600,
++               &m_attr);
++
++  if (m < 0)
++    {
++      if (errno == ENOSYS)
++        FAIL_UNSUPPORTED ("POSIX message queues are not implemented\n");
++      FAIL_EXIT1 ("Failed to create POSIX message queue: %m\n");
++    }
++
++  TEST_VERIFY_EXIT (mq_unlink (m_name) == 0);
++
++  check_bz28213 ();
++
++  return 0;
++}
++
++#include <support/test-driver.c>
+-- 
+2.31.1
+

+ 238 - 0
recipes-core/glibc/glibc/0002-localedef-fix-ups-hardlink-to-make-it-compile.patch

@@ -0,0 +1,238 @@
+From d7bb36a9a27e5e4c3be6378493b41286513750e9 Mon Sep 17 00:00:00 2001
+From: Jason Wessel <jason.wessel@windriver.com>
+Date: Sat, 7 Dec 2019 10:01:37 -0800
+Subject: [PATCH] localedef: fix-ups hardlink to make it compile
+
+Upstream-Status: Pending
+Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ locale/programs/c.h                        |  2 +-
+ locale/programs/cross-localedef-hardlink.c | 79 +++++++++++-----------
+ 2 files changed, 39 insertions(+), 42 deletions(-)
+
+diff --git a/locale/programs/c.h b/locale/programs/c.h
+index d0a402e90e..1804d31c73 100644
+--- a/locale/programs/c.h
++++ b/locale/programs/c.h
+@@ -240,7 +240,7 @@ errmsg(char doexit, int excode, char adderr, const char *fmt, ...)
+ /* Don't use inline function to avoid '#include "nls.h"' in c.h
+  */
+ #define errtryhelp(eval) __extension__ ({ \
+-	fprintf(stderr, _("Try '%s --help' for more information.\n"), \
++	fprintf(stderr, ("Try '%s --help' for more information.\n"), \
+ 			program_invocation_short_name); \
+ 	exit(eval); \
+ })
+diff --git a/locale/programs/cross-localedef-hardlink.c b/locale/programs/cross-localedef-hardlink.c
+index 63615896b0..726e6dd948 100644
+--- a/locale/programs/cross-localedef-hardlink.c
++++ b/locale/programs/cross-localedef-hardlink.c
+@@ -20,6 +20,8 @@
+  * with this program; if not, write to the Free Software Foundation, Inc.,
+  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+  */
++
++#undef HAVE_PCRE
+ #include <sys/types.h>
+ #include <stdlib.h>
+ #include <getopt.h>
+@@ -38,8 +40,8 @@
+ 
+ #include "c.h"
+ #include "xalloc.h"
+-#include "nls.h"
+-#include "closestream.h"
++//#include "nls.h"
++//#include "closestream.h"
+ 
+ #define NHASH   (1<<17)  /* Must be a power of 2! */
+ #define NBUF    64
+@@ -124,33 +126,33 @@ static void print_summary(void)
+ 	if (ctl->verbose > 1 && ctl->nlinks)
+ 		fputc('\n', stdout);
+ 
+-	printf(_("Directories:   %9lld\n"), ctl->ndirs);
+-	printf(_("Objects:       %9lld\n"), ctl->nobjects);
+-	printf(_("Regular files: %9lld\n"), ctl->nregfiles);
+-	printf(_("Comparisons:   %9lld\n"), ctl->ncomp);
++	printf(("Directories:   %9lld\n"), ctl->ndirs);
++	printf(("Objects:       %9lld\n"), ctl->nobjects);
++	printf(("Regular files: %9lld\n"), ctl->nregfiles);
++	printf(("Comparisons:   %9lld\n"), ctl->ncomp);
+ 	printf(  "%s%9lld\n", (ctl->no_link ?
+-	       _("Would link:    ") :
+-	       _("Linked:        ")), ctl->nlinks);
++	       ("Would link:    ") :
++	       ("Linked:        ")), ctl->nlinks);
+ 	printf(  "%s %9lld\n", (ctl->no_link ?
+-	       _("Would save:   ") :
+-	       _("Saved:        ")), ctl->nsaved);
++	       ("Would save:   ") :
++	       ("Saved:        ")), ctl->nsaved);
+ }
+ 
+ static void __attribute__((__noreturn__)) usage(void)
+ {
+ 	fputs(USAGE_HEADER, stdout);
+-	printf(_(" %s [options] directory...\n"), program_invocation_short_name);
++	printf((" %s [options] directory...\n"), program_invocation_short_name);
+ 
+ 	fputs(USAGE_SEPARATOR, stdout);
+-	puts(_("Consolidate duplicate files using hardlinks."));
++	puts(("Consolidate duplicate files using hardlinks."));
+ 
+ 	fputs(USAGE_OPTIONS, stdout);
+-	puts(_(" -c, --content          compare only contents, ignore permission, etc."));
+-	puts(_(" -n, --dry-run          don't actually link anything"));
+-	puts(_(" -v, --verbose          print summary after hardlinking"));
+-	puts(_(" -vv                    print every hardlinked file and summary"));
+-	puts(_(" -f, --force            force hardlinking across filesystems"));
+-	puts(_(" -x, --exclude <regex>  exclude files matching pattern"));
++	puts((" -c, --content          compare only contents, ignore permission, etc."));
++	puts((" -n, --dry-run          don't actually link anything"));
++	puts((" -v, --verbose          print summary after hardlinking"));
++	puts((" -vv                    print every hardlinked file and summary"));
++	puts((" -f, --force            force hardlinking across filesystems"));
++	puts((" -x, --exclude <regex>  exclude files matching pattern"));
+ 
+ 	fputs(USAGE_SEPARATOR, stdout);
+ 	printf(USAGE_HELP_OPTIONS(16)); /* char offset to align option descriptions */
+@@ -164,7 +166,7 @@ static inline size_t add2(size_t a, size_t b)
+ 	size_t sum = a + b;
+ 
+ 	if (sum < a)
+-		errx(EXIT_FAILURE, _("integer overflow"));
++		errx(EXIT_FAILURE, ("integer overflow"));
+ 	return sum;
+ }
+ 
+@@ -193,7 +195,7 @@ static void process_path(struct hardlink_ctl *ctl, const char *name)
+ 	if (st.st_dev != ctl->dev && !ctl->force) {
+ 		if (ctl->dev)
+ 			errx(EXIT_FAILURE,
+-			     _("%s is on different filesystem than the rest "
++			     ("%s is on different filesystem than the rest "
+ 			       "(use -f option to override)."), name);
+ 		ctl->dev = st.st_dev;
+ 	}
+@@ -287,9 +289,9 @@ static void process_path(struct hardlink_ctl *ctl, const char *name)
+ 							(ssize_t) sizeof(ctl->iobuf1) : fsize;
+ 
+ 					if ((xsz = read(fd, ctl->iobuf1, rsize)) != rsize)
+-						warn(_("cannot read %s"), name);
++						warn(("cannot read %s"), name);
+ 					else if ((xsz = read(fd2, ctl->iobuf2, rsize)) != rsize)
+-						warn(_("cannot read %s"), fp2->name);
++						warn(("cannot read %s"), fp2->name);
+ 
+ 					if (xsz != rsize) {
+ 						close(fd);
+@@ -303,13 +305,13 @@ static void process_path(struct hardlink_ctl *ctl, const char *name)
+ 				if (fsize > 0)
+ 					continue;
+ 				if (lstat(name, &st3)) {
+-					warn(_("cannot stat %s"), name);
++					warn(("cannot stat %s"), name);
+ 					close(fd);
+ 					return;
+ 				}
+ 				st3.st_atime = st.st_atime;
+ 				if (stcmp(&st, &st3, 0)) {
+-					warnx(_("file %s changed underneath us"), name);
++					warnx(("file %s changed underneath us"), name);
+ 					close(fd);
+ 					return;
+ 				}
+@@ -329,18 +331,18 @@ static void process_path(struct hardlink_ctl *ctl, const char *name)
+ 					       suffixlen + 1);
+ 					/* First create a temporary link to n1 under a new name */
+ 					if (link(n1, nam2.buf)) {
+-						warn(_("failed to hardlink %s to %s (create temporary link as %s failed)"),
++						warn(("failed to hardlink %s to %s (create temporary link as %s failed)"),
+ 							n1, n2, nam2.buf);
+ 						free(nam2.buf);
+ 						continue;
+ 					}
+ 					/* Then rename into place over the existing n2 */
+ 					if (rename(nam2.buf, n2)) {
+-						warn(_("failed to hardlink %s to %s (rename temporary link to %s failed)"),
++						warn(("failed to hardlink %s to %s (rename temporary link to %s failed)"),
+ 							n1, n2, n2);
+ 						/* Something went wrong, try to remove the now redundant temporary link */
+ 						if (unlink(nam2.buf))
+-							warn(_("failed to remove temporary link %s"), nam2.buf);
++							warn(("failed to remove temporary link %s"), nam2.buf);
+ 						free(nam2.buf);
+ 						continue;
+ 					}
+@@ -351,16 +353,16 @@ static void process_path(struct hardlink_ctl *ctl, const char *name)
+ 					/* We actually did not save anything this time, since the link second argument
+ 					   had some other links as well.  */
+ 					if (ctl->verbose > 1)
+-						printf(_(" %s %s to %s\n"),
+-							(ctl->no_link ? _("Would link") : _("Linked")),
++						printf((" %s %s to %s\n"),
++							(ctl->no_link ? ("Would link") : ("Linked")),
+ 							n1, n2);
+ 				} else {
+ 					ctl->nsaved += ((st.st_size + 4095) / 4096) * 4096;
+ 					if (ctl->verbose > 1)
+-						printf(_(" %s %s to %s, %s %jd\n"),
+-							(ctl->no_link ? _("Would link") : _("Linked")),
++						printf((" %s %s to %s, %s %jd\n"),
++							(ctl->no_link ? ("Would link") : ("Linked")),
+ 							n1, n2,
+-							(ctl->no_link ? _("would save") : _("saved")),
++							(ctl->no_link ? ("would save") : ("saved")),
+ 							(intmax_t)st.st_size);
+ 				}
+ 				close(fd);
+@@ -410,11 +412,6 @@ int main(int argc, char **argv)
+ 		{ NULL, 0, NULL, 0 },
+ 	};
+ 
+-	setlocale(LC_ALL, "");
+-	bindtextdomain(PACKAGE, LOCALEDIR);
+-	textdomain(PACKAGE);
+-	close_stdout_atexit();
+-
+ 	while ((ch = getopt_long(argc, argv, "cnvfx:Vh", longopts, NULL)) != -1) {
+ 		switch (ch) {
+ 		case 'n':
+@@ -434,7 +431,7 @@ int main(int argc, char **argv)
+ 			exclude_pattern = (PCRE2_SPTR) optarg;
+ #else
+ 			errx(EXIT_FAILURE,
+-			     _("option --exclude not supported (built without pcre2)"));
++			     ("option --exclude not supported (built without pcre2)"));
+ #endif
+ 			break;
+ 		case 'V':
+@@ -447,7 +444,7 @@ int main(int argc, char **argv)
+ 	}
+ 
+ 	if (optind == argc) {
+-		warnx(_("no directory specified"));
++		warnx(("no directory specified"));
+ 		errtryhelp(EXIT_FAILURE);
+ 	}
+ 
+@@ -461,7 +458,7 @@ int main(int argc, char **argv)
+ 			PCRE2_UCHAR buffer[256];
+ 			pcre2_get_error_message(errornumber, buffer,
+ 						sizeof(buffer));
+-			errx(EXIT_FAILURE, _("pattern error at offset %d: %s"),
++			errx(EXIT_FAILURE, ("pattern error at offset %d: %s"),
+ 				(int)erroroffset, buffer);
+ 		}
+ 		match_data = pcre2_match_data_create_from_pattern(re, NULL);
+@@ -506,7 +503,7 @@ int main(int argc, char **argv)
+ 			    >=0) {
+ 				if (ctl->verbose) {
+ 					nam1.buf[nam1baselen] = 0;
+-					printf(_("Skipping %s%s\n"), nam1.buf, di->d_name);
++					printf(("Skipping %s%s\n"), nam1.buf, di->d_name);
+ 				}
+ 				continue;
+ 			}

+ 65 - 0
recipes-core/glibc/glibc/0003-nativesdk-glibc-Look-for-host-system-ld.so.cache-as-.patch

@@ -0,0 +1,65 @@
+From 776a53db6afba8a7ff4412aba88b0679227877f9 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 01:48:24 +0000
+Subject: [PATCH] nativesdk-glibc: Look for host system ld.so.cache as well
+
+Upstream-Status: Inappropriate [embedded specific]
+
+The default lib search path order is:
+
+  1) LD_LIBRARY_PATH
+  2) RPATH from the binary
+  3) ld.so.cache
+  4) default search paths embedded in the linker
+
+For nativesdk binaries which are being used alongside binaries on a host system, we
+need the search paths to firstly search the shipped nativesdk libs but then also
+cover the host system. For example we want the host system's libGL and this may be
+in a non-standard location like /usr/lib/mesa. The only place the location is know
+about is in the ld.so.cache of the host system.
+
+Since nativesdk has a simple structure and doesn't need to use a cache itself, we
+repurpose the cache for use as a last resort in finding host system binaries. This
+means we need to switch the order of 3 and 4 above to make this work effectively.
+
+RP 14/10/2010
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ elf/dl-load.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/elf/dl-load.c b/elf/dl-load.c
+index a08df001af..d09daf9e41 100644
+--- a/elf/dl-load.c
++++ b/elf/dl-load.c
+@@ -2196,6 +2196,14 @@ _dl_map_object (struct link_map *loader, const char *name,
+             }
+         }
+ 
++      /* try the default path.  */
++      if (fd == -1
++	  && ((l = loader ?: GL(dl_ns)[nsid]._ns_loaded) == NULL
++	   || __builtin_expect (!(l->l_flags_1 & DF_1_NODEFLIB), 1))
++	 && __rtld_search_dirs.dirs != (void *) -1)
++	fd = open_path (name, namelen, mode & __RTLD_SECURE, &__rtld_search_dirs,
++			&realname, &fb, l, LA_SER_DEFAULT, &found_other_class);
++      /* Finally try ld.so.cache */
+ #ifdef USE_LDCONFIG
+       if (fd == -1
+ 	  && (__glibc_likely ((mode & __RTLD_SECURE) == 0)
+@@ -2254,14 +2262,6 @@ _dl_map_object (struct link_map *loader, const char *name,
+ 	}
+ #endif
+ 
+-      /* Finally, try the default path.  */
+-      if (fd == -1
+-	  && ((l = loader ?: GL(dl_ns)[nsid]._ns_loaded) == NULL
+-	      || __glibc_likely (!(l->l_flags_1 & DF_1_NODEFLIB)))
+-	  && __rtld_search_dirs.dirs != (void *) -1)
+-	fd = open_path (name, namelen, mode, &__rtld_search_dirs,
+-			&realname, &fb, l, LA_SER_DEFAULT, &found_other_class);
+-
+       /* Add another newline when we are tracing the library loading.  */
+       if (__glibc_unlikely (GLRO(dl_debug_mask) & DL_DEBUG_LIBS))
+ 	_dl_debug_printf ("\n");

+ 46 - 0
recipes-core/glibc/glibc/0004-nativesdk-glibc-Fix-buffer-overrun-with-a-relocated-.patch

@@ -0,0 +1,46 @@
+From df18bae1eeee55ecb9db36d13fe67c58355682eb Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 01:50:00 +0000
+Subject: [PATCH] nativesdk-glibc: Fix buffer overrun with a relocated SDK
+
+When ld-linux-*.so.2 is relocated to a path that is longer than the
+original fixed location, the dynamic loader will crash in open_path
+because it implicitly assumes that max_dirnamelen is a fixed size that
+never changes.
+
+The allocated buffer will not be large enough to contain the directory
+path string which is larger than the fixed location provided at build
+time.
+
+Upstream-Status: Inappropriate [OE SDK specific]
+
+Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ elf/dl-load.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/elf/dl-load.c b/elf/dl-load.c
+index d09daf9e41..2c6270e2a7 100644
+--- a/elf/dl-load.c
++++ b/elf/dl-load.c
+@@ -1892,7 +1892,19 @@ open_path (const char *name, size_t namelen, int mode,
+        given on the command line when rtld is run directly.  */
+     return -1;
+ 
++  do
++    {
++      struct r_search_path_elem *this_dir = *dirs;
++      if (this_dir->dirnamelen > max_dirnamelen)
++	{
++	  max_dirnamelen = this_dir->dirnamelen;
++	}
++    }
++  while (*++dirs != NULL);
++
+   buf = alloca (max_dirnamelen + max_capstrlen + namelen);
++
++  dirs = sps->dirs;
+   do
+     {
+       struct r_search_path_elem *this_dir = *dirs;

+ 153 - 0
recipes-core/glibc/glibc/0005-nativesdk-glibc-Raise-the-size-of-arrays-containing-.patch

@@ -0,0 +1,153 @@
+From 6af8ce8eceed86addbc188f773a2d36d83ee4042 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 01:51:38 +0000
+Subject: [PATCH] nativesdk-glibc: Raise the size of arrays containing dl paths
+
+This patch puts the dynamic loader path in the binaries, SYSTEM_DIRS strings
+and lengths as well as ld.so.cache path in the dynamic loader to specific
+sections in memory. The sections that contain paths have been allocated a 4096
+byte section, which is the maximum path length in linux. This will allow the
+relocating script to parse the ELF binary, detect the section and easily replace
+the strings in a certain path.
+
+Upstream-Status: Inappropriate [SDK specific]
+
+Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ elf/dl-cache.c             | 4 ++++
+ elf/dl-load.c              | 4 ++--
+ elf/dl-usage.c             | 6 ++++--
+ elf/interp.c               | 2 +-
+ elf/ldconfig.c             | 3 +++
+ elf/rtld.c                 | 1 +
+ iconv/gconv_conf.c         | 2 +-
+ sysdeps/generic/dl-cache.h | 4 ----
+ 8 files changed, 16 insertions(+), 10 deletions(-)
+
+diff --git a/elf/dl-cache.c b/elf/dl-cache.c
+index 2b8da8650d..3d9787bda4 100644
+--- a/elf/dl-cache.c
++++ b/elf/dl-cache.c
+@@ -355,6 +355,10 @@ search_cache (const char *string_table, uint32_t string_table_size,
+   return best;
+ }
+ 
++const char LD_SO_CACHE[4096] __attribute__ ((section (".ldsocache"))) =
++		SYSCONFDIR "/ld.so.cache";
++
++
+ int
+ _dl_cache_libcmp (const char *p1, const char *p2)
+ {
+diff --git a/elf/dl-load.c b/elf/dl-load.c
+index 2c6270e2a7..23018d2f7e 100644
+--- a/elf/dl-load.c
++++ b/elf/dl-load.c
+@@ -115,8 +115,8 @@ enum { ncapstr = 1, max_capstrlen = 0 };
+    gen-trusted-dirs.awk.  */
+ #include "trusted-dirs.h"
+ 
+-static const char system_dirs[] = SYSTEM_DIRS;
+-static const size_t system_dirs_len[] =
++static const char system_dirs[4096] __attribute__ ((section (".sysdirs"))) = SYSTEM_DIRS;
++volatile static const size_t system_dirs_len[] __attribute__ ((section (".sysdirslen"))) =
+ {
+   SYSTEM_DIRS_LEN
+ };
+diff --git a/elf/dl-usage.c b/elf/dl-usage.c
+index 5ad3a72559..88f26d3692 100644
+--- a/elf/dl-usage.c
++++ b/elf/dl-usage.c
+@@ -25,6 +25,8 @@
+ #include <dl-procinfo.h>
+ #include <dl-hwcaps.h>
+ 
++extern const char LD_SO_CACHE[4096] __attribute__ ((section (".ldsocache")));
++
+ void
+ _dl_usage (const char *argv0, const char *wrong_option)
+ {
+@@ -244,7 +246,7 @@ setting environment variables (which would be inherited by subprocesses).\n\
+   --list                list all dependencies and how they are resolved\n\
+   --verify              verify that given object really is a dynamically linked\n\
+                         object we can handle\n\
+-  --inhibit-cache       Do not use " LD_SO_CACHE "\n\
++  --inhibit-cache       Do not use %s\n\
+   --library-path PATH   use given PATH instead of content of the environment\n\
+                         variable LD_LIBRARY_PATH\n\
+   --glibc-hwcaps-prepend LIST\n\
+@@ -267,7 +269,7 @@ setting environment variables (which would be inherited by subprocesses).\n\
+ \n\
+ This program interpreter self-identifies as: " RTLD "\n\
+ ",
+-              argv0);
++              argv0, LD_SO_CACHE);
+   print_search_path_for_help (state);
+   print_hwcaps_subdirectories (state);
+   print_legacy_hwcap_directories ();
+diff --git a/elf/interp.c b/elf/interp.c
+index 91966702ca..dc86c20e83 100644
+--- a/elf/interp.c
++++ b/elf/interp.c
+@@ -18,5 +18,5 @@
+ 
+ #include <runtime-linker.h>
+ 
+-const char __invoke_dynamic_linker__[] __attribute__ ((section (".interp")))
++const char __invoke_dynamic_linker__[4096] __attribute__ ((section (".interp")))
+   = RUNTIME_LINKER;
+diff --git a/elf/ldconfig.c b/elf/ldconfig.c
+index 1037e8d0cf..ffdac84952 100644
+--- a/elf/ldconfig.c
++++ b/elf/ldconfig.c
+@@ -177,6 +177,9 @@ static struct argp argp =
+   options, parse_opt, NULL, doc, NULL, more_help, NULL
+ };
+ 
++
++extern const char LD_SO_CACHE[4096] __attribute__ ((section (".ldsocache")));
++
+ /* Check if string corresponds to an important hardware capability or
+    a platform.  */
+ static int
+diff --git a/elf/rtld.c b/elf/rtld.c
+index fbbd60b446..fce9940f80 100644
+--- a/elf/rtld.c
++++ b/elf/rtld.c
+@@ -185,6 +185,7 @@ dso_name_valid_for_suid (const char *p)
+     }
+   return *p != '\0';
+ }
++extern const char LD_SO_CACHE[4096] __attribute__ ((section (".ldsocache")));
+ 
+ static void
+ audit_list_init (struct audit_list *list)
+diff --git a/iconv/gconv_conf.c b/iconv/gconv_conf.c
+index 62bee28769..67b60dc88c 100644
+--- a/iconv/gconv_conf.c
++++ b/iconv/gconv_conf.c
+@@ -36,7 +36,7 @@
+ #include <gconv_parseconfdir.h>
+ 
+ /* This is the default path where we look for module lists.  */
+-static const char default_gconv_path[] = GCONV_PATH;
++static char default_gconv_path[4096] __attribute__ ((section (".gccrelocprefix"))) = GCONV_PATH;
+ 
+ /* Type to represent search path.  */
+ struct path_elem
+diff --git a/sysdeps/generic/dl-cache.h b/sysdeps/generic/dl-cache.h
+index 964d50a486..94bf68ca9d 100644
+--- a/sysdeps/generic/dl-cache.h
++++ b/sysdeps/generic/dl-cache.h
+@@ -34,10 +34,6 @@
+   ((flags) == 1 || (flags) == _DL_CACHE_DEFAULT_ID)
+ #endif
+ 
+-#ifndef LD_SO_CACHE
+-# define LD_SO_CACHE SYSCONFDIR "/ld.so.cache"
+-#endif
+-
+ #ifndef add_system_dir
+ # define add_system_dir(dir) add_dir (dir)
+ #endif

+ 39 - 0
recipes-core/glibc/glibc/0006-nativesdk-glibc-Allow-64-bit-atomics-for-x86.patch

@@ -0,0 +1,39 @@
+From b30f380cd88ae181a4a6a3a4784206ffe3ccd19b Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Thu, 31 Dec 2015 14:35:35 -0800
+Subject: [PATCH] nativesdk-glibc: Allow 64 bit atomics for x86
+
+The fix consist of allowing 64bit atomic ops for x86.
+This should be safe for i586 and newer CPUs.
+It also makes the synchronization more efficient.
+
+Upstream-Status: Inappropriate [OE-Specific]
+
+Signed-off-by: Juro Bystricky <juro.bystricky@intel.com>
+Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/x86/atomic-machine.h | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h
+index 695222e4fa..9d39bfdbd5 100644
+--- a/sysdeps/x86/atomic-machine.h
++++ b/sysdeps/x86/atomic-machine.h
+@@ -52,15 +52,14 @@ typedef uintmax_t uatomic_max_t;
+ #define LOCK_PREFIX "lock;"
+ 
+ #define USE_ATOMIC_COMPILER_BUILTINS	1
++# define __HAVE_64B_ATOMICS		1
+ 
+ #ifdef __x86_64__
+-# define __HAVE_64B_ATOMICS		1
+ # define SP_REG				"rsp"
+ # define SEG_REG			"fs"
+ # define BR_CONSTRAINT			"q"
+ # define IBR_CONSTRAINT			"iq"
+ #else
+-# define __HAVE_64B_ATOMICS		0
+ # define SP_REG				"esp"
+ # define SEG_REG			"gs"
+ # define BR_CONSTRAINT			"r"

+ 100 - 0
recipes-core/glibc/glibc/0007-nativesdk-glibc-Make-relocatable-install-for-locales.patch

@@ -0,0 +1,100 @@
+From 24bffe9c2645cd6542e29cb57786dc703cced07b Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 3 Aug 2018 09:55:12 -0700
+Subject: [PATCH] nativesdk-glibc: Make relocatable install for locales
+
+The glibc locale path is hard-coded to the install prefix, but in SDKs we need
+to be able to relocate the binaries.  Expand the strings to 4K and put them in a
+magic segment that we can relocate at install time.
+
+Upstream-Status: Inappropriate (OE-specific)
+
+Signed-off-by: Ross Burton <ross.burton@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ locale/findlocale.c      | 4 ++--
+ locale/loadarchive.c     | 2 +-
+ locale/localeinfo.h      | 2 +-
+ locale/programs/locale.c | 7 ++++---
+ 4 files changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/locale/findlocale.c b/locale/findlocale.c
+index ab09122b0c..f42cc75780 100644
+--- a/locale/findlocale.c
++++ b/locale/findlocale.c
+@@ -56,7 +56,7 @@ struct __locale_data *const _nl_C[] attribute_hidden =
+    which are somehow addressed.  */
+ struct loaded_l10nfile *_nl_locale_file_list[__LC_LAST];
+ 
+-const char _nl_default_locale_path[] attribute_hidden = COMPLOCALEDIR;
++char _nl_default_locale_path[4096] attribute_hidden __attribute__ ((section (".gccrelocprefix"))) = COMPLOCALEDIR;
+ 
+ /* Checks if the name is actually present, that is, not NULL and not
+    empty.  */
+@@ -166,7 +166,7 @@ _nl_find_locale (const char *locale_path, size_t locale_path_len,
+ 
+       /* Nothing in the archive.  Set the default path to search below.  */
+       locale_path = _nl_default_locale_path;
+-      locale_path_len = sizeof _nl_default_locale_path;
++      locale_path_len = strlen(locale_path) + 1;
+     }
+   else
+     /* We really have to load some data.  First see whether the name is
+diff --git a/locale/loadarchive.c b/locale/loadarchive.c
+index 512769eaec..436619091b 100644
+--- a/locale/loadarchive.c
++++ b/locale/loadarchive.c
+@@ -42,7 +42,7 @@
+ 
+ 
+ /* Name of the locale archive file.  */
+-static const char archfname[] = COMPLOCALEDIR "/locale-archive";
++static const char archfname[4096] __attribute__ ((section (".gccrelocprefix"))) = COMPLOCALEDIR "/locale-archive";
+ 
+ /* Size of initial mapping window, optimal if large enough to
+    cover the header plus the initial locale.  */
+diff --git a/locale/localeinfo.h b/locale/localeinfo.h
+index b3d4da0185..22f9dc1140 100644
+--- a/locale/localeinfo.h
++++ b/locale/localeinfo.h
+@@ -331,7 +331,7 @@ _nl_lookup_word (locale_t l, int category, int item)
+ }
+ 
+ /* Default search path if no LOCPATH environment variable.  */
+-extern const char _nl_default_locale_path[] attribute_hidden;
++extern char _nl_default_locale_path[4096] attribute_hidden;
+ 
+ /* Load the locale data for CATEGORY from the file specified by *NAME.
+    If *NAME is "", use environment variables as specified by POSIX, and
+diff --git a/locale/programs/locale.c b/locale/programs/locale.c
+index ca0a95be99..6b98895203 100644
+--- a/locale/programs/locale.c
++++ b/locale/programs/locale.c
+@@ -632,6 +632,7 @@ nameentcmp (const void *a, const void *b)
+ 		  ((const struct nameent *) b)->name);
+ }
+ 
++static char _write_archive_locales_path[4096] attribute_hidden __attribute__ ((section (".gccrelocprefix"))) = ARCHIVE_NAME;
+ 
+ static int
+ write_archive_locales (void **all_datap, char *linebuf)
+@@ -645,7 +646,7 @@ write_archive_locales (void **all_datap, char *linebuf)
+   int fd, ret = 0;
+   uint32_t cnt;
+ 
+-  fd = open64 (ARCHIVE_NAME, O_RDONLY);
++  fd = open64 (_write_archive_locales_path, O_RDONLY);
+   if (fd < 0)
+     return 0;
+ 
+@@ -700,8 +701,8 @@ write_archive_locales (void **all_datap, char *linebuf)
+ 	  if (cnt)
+ 	    putchar_unlocked ('\n');
+ 
+-	  printf ("locale: %-15.15s archive: " ARCHIVE_NAME "\n%s\n",
+-		  names[cnt].name, linebuf);
++	  printf ("locale: %-15.15s archive: %s\n%s\n",
++		  names[cnt].name, _write_archive_locales_path, linebuf);
+ 
+ 	  locrec = (struct locrecent *) (addr + names[cnt].locrec_offset);
+ 

+ 32 - 0
recipes-core/glibc/glibc/0008-nativesdk-glibc-Fall-back-to-faccessat-on-faccess2-r.patch

@@ -0,0 +1,32 @@
+From 2761400989bcbf11e10bc85f90c3a2ba1305c4ae Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Sat, 6 Mar 2021 14:48:56 -0800
+Subject: [PATCH] nativesdk-glibc: Fall back to faccessat on faccess2 returns
+ EPERM
+
+Fedora-specific workaround for systemd-nspawn
+
+Upstream-Status: Inappropriate [Distro Specific]
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/unix/sysv/linux/faccessat.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/sysdeps/unix/sysv/linux/faccessat.c b/sysdeps/unix/sysv/linux/faccessat.c
+index 13160d3249..ee3ddc9b79 100644
+--- a/sysdeps/unix/sysv/linux/faccessat.c
++++ b/sysdeps/unix/sysv/linux/faccessat.c
+@@ -30,7 +30,11 @@ __faccessat (int fd, const char *file, int mode, int flag)
+ #if __ASSUME_FACCESSAT2
+   return ret;
+ #else
+-  if (ret == 0 || errno != ENOSYS)
++  /* Fedora-specific workaround:
++     As a workround for a broken systemd-nspawn that returns
++     EPERM when a syscall is not allowed instead of ENOSYS
++     we must check for EPERM here and fall back to faccessat.  */
++  if (ret == 0 || !(errno == ENOSYS || errno == EPERM))
+     return ret;
+ 
+   if (flag & ~(AT_SYMLINK_NOFOLLOW | AT_EACCESS))

+ 1581 - 0
recipes-core/glibc/glibc/0009-fsl-e500-e5500-e6500-603e-fsqrt-implementation.patch

@@ -0,0 +1,1581 @@
+From 74923ca4b1ae0ed5a2478e7d265b37534f6815d7 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:01:50 +0000
+Subject: [PATCH] fsl e500/e5500/e6500/603e fsqrt implementation
+
+Upstream-Status: Pending
+Signed-off-by: Edmar Wienskoski <edmar@freescale.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c   | 134 ++++++++++++++++++
+ sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c  | 101 +++++++++++++
+ sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c | 134 ++++++++++++++++++
+ .../powerpc/powerpc32/e500mc/fpu/e_sqrtf.c    | 101 +++++++++++++
+ sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c  | 134 ++++++++++++++++++
+ sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c | 101 +++++++++++++
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c  | 134 ++++++++++++++++++
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c | 101 +++++++++++++
+ sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c  | 134 ++++++++++++++++++
+ sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c | 101 +++++++++++++
+ sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c  | 134 ++++++++++++++++++
+ sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c | 101 +++++++++++++
+ .../linux/powerpc/powerpc32/603e/fpu/Implies  |   1 +
+ .../powerpc/powerpc32/e300c3/fpu/Implies      |   2 +
+ .../powerpc/powerpc32/e500mc/fpu/Implies      |   1 +
+ .../linux/powerpc/powerpc32/e5500/fpu/Implies |   1 +
+ .../linux/powerpc/powerpc32/e6500/fpu/Implies |   1 +
+ .../linux/powerpc/powerpc64/e5500/fpu/Implies |   1 +
+ .../linux/powerpc/powerpc64/e6500/fpu/Implies |   1 +
+ 19 files changed, 1418 insertions(+)
+ create mode 100644 sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+ create mode 100644 sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+ create mode 100644 sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+ create mode 100644 sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+ create mode 100644 sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+ create mode 100644 sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+ create mode 100644 sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+ create mode 100644 sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+ create mode 100644 sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+ create mode 100644 sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+ create mode 100644 sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+ create mode 100644 sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc32/603e/fpu/Implies
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc32/e300c3/fpu/Implies
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc32/e500mc/fpu/Implies
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc32/e5500/fpu/Implies
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc32/e6500/fpu/Implies
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc64/e5500/fpu/Implies
+ create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc64/e6500/fpu/Implies
+
+diff --git a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+new file mode 100644
+index 0000000000..71e516d1c8
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+@@ -0,0 +1,134 @@
++/* Double-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float two108 = 3.245185536584267269e+32;
++static const float twom54 = 5.551115123125782702e-17;
++static const float half = 0.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the actual square root and half of its reciprocal
++   simultaneously.  */
++
++#ifdef __STDC__
++double
++__ieee754_sqrt (double b)
++#else
++double
++__ieee754_sqrt (b)
++     double b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++      double y, g, h, d, r;
++      ieee_double_shape_type u;
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          u.value = b;
++
++          relax_fenv_state ();
++
++          __asm__ ("frsqrte %[estimate], %[x]\n"
++                   : [estimate] "=f" (y) : [x] "f" (b));
++
++          /* Following Muller et al, page 168, equation 5.20.
++
++             h goes to 1/(2*sqrt(b))
++             g goes to sqrt(b).
++
++             We need three iterations to get within 1ulp.  */
++
++          /* Indicate that these can be performed prior to the branch.  GCC
++             insists on sinking them below the branch, however; it seems like
++             they'd be better before the branch so that we can cover any latency
++             from storing the argument and loading its high word.  Oh well.  */
++
++          g = b * y;
++          h = 0.5 * y;
++
++          /* Handle small numbers by scaling.  */
++          if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
++            return __ieee754_sqrt (b * two108) * twom54;
++
++#define FMADD(a_, c_, b_)                                               \
++          ({ double __r;                                                \
++          __asm__ ("fmadd %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++#define FNMSUB(a_, c_, b_)                                          \
++          ({ double __r;                                                \
++          __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          /* g is now +/- 1ulp, or exactly equal to, the square root of b.  */
++
++          /* Final refinement.  */
++          d = FNMSUB (g, g, b);
++
++          fesetenv_register (fe);
++          return FMADD (d, h, g);
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_wash (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+new file mode 100644
+index 0000000000..26fa067abf
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+@@ -0,0 +1,101 @@
++/* Single-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float threehalf = 1.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the reciprocal square root and use that to compute the actual
++   square root.  */
++
++#ifdef __STDC__
++float
++__ieee754_sqrtf (float b)
++#else
++float
++__ieee754_sqrtf (b)
++     float b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++#define FMSUB(a_, c_, b_)                                               \
++      ({ double __r;                                                    \
++        __asm__ ("fmsub %[r], %[a], %[c], %[b]\n"                       \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++#define FNMSUB(a_, c_, b_)                                              \
++      ({ double __r;                                                    \
++        __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                      \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          double y, x;
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          relax_fenv_state ();
++
++          /* Compute y = 1.5 * b - b.  Uses fewer constants than y = 0.5 * b.  */
++          y = FMSUB (threehalf, b, b);
++
++          /* Initial estimate.  */
++          __asm__ ("frsqrte %[x], %[b]\n" : [x] "=f" (x) : [b] "f" (b));
++
++          /* Iterate.  x_{n+1} = x_n * (1.5 - y * (x_n * x_n)).  */
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++
++          /* All done.  */
++          fesetenv_register (fe);
++          return x * b;
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_washf (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+new file mode 100644
+index 0000000000..71e516d1c8
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+@@ -0,0 +1,134 @@
++/* Double-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float two108 = 3.245185536584267269e+32;
++static const float twom54 = 5.551115123125782702e-17;
++static const float half = 0.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the actual square root and half of its reciprocal
++   simultaneously.  */
++
++#ifdef __STDC__
++double
++__ieee754_sqrt (double b)
++#else
++double
++__ieee754_sqrt (b)
++     double b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++      double y, g, h, d, r;
++      ieee_double_shape_type u;
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          u.value = b;
++
++          relax_fenv_state ();
++
++          __asm__ ("frsqrte %[estimate], %[x]\n"
++                   : [estimate] "=f" (y) : [x] "f" (b));
++
++          /* Following Muller et al, page 168, equation 5.20.
++
++             h goes to 1/(2*sqrt(b))
++             g goes to sqrt(b).
++
++             We need three iterations to get within 1ulp.  */
++
++          /* Indicate that these can be performed prior to the branch.  GCC
++             insists on sinking them below the branch, however; it seems like
++             they'd be better before the branch so that we can cover any latency
++             from storing the argument and loading its high word.  Oh well.  */
++
++          g = b * y;
++          h = 0.5 * y;
++
++          /* Handle small numbers by scaling.  */
++          if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
++            return __ieee754_sqrt (b * two108) * twom54;
++
++#define FMADD(a_, c_, b_)                                               \
++          ({ double __r;                                                \
++          __asm__ ("fmadd %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++#define FNMSUB(a_, c_, b_)                                          \
++          ({ double __r;                                                \
++          __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          /* g is now +/- 1ulp, or exactly equal to, the square root of b.  */
++
++          /* Final refinement.  */
++          d = FNMSUB (g, g, b);
++
++          fesetenv_register (fe);
++          return FMADD (d, h, g);
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_wash (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+new file mode 100644
+index 0000000000..26fa067abf
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+@@ -0,0 +1,101 @@
++/* Single-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float threehalf = 1.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the reciprocal square root and use that to compute the actual
++   square root.  */
++
++#ifdef __STDC__
++float
++__ieee754_sqrtf (float b)
++#else
++float
++__ieee754_sqrtf (b)
++     float b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++#define FMSUB(a_, c_, b_)                                               \
++      ({ double __r;                                                    \
++        __asm__ ("fmsub %[r], %[a], %[c], %[b]\n"                       \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++#define FNMSUB(a_, c_, b_)                                              \
++      ({ double __r;                                                    \
++        __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                      \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          double y, x;
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          relax_fenv_state ();
++
++          /* Compute y = 1.5 * b - b.  Uses fewer constants than y = 0.5 * b.  */
++          y = FMSUB (threehalf, b, b);
++
++          /* Initial estimate.  */
++          __asm__ ("frsqrte %[x], %[b]\n" : [x] "=f" (x) : [b] "f" (b));
++
++          /* Iterate.  x_{n+1} = x_n * (1.5 - y * (x_n * x_n)).  */
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++
++          /* All done.  */
++          fesetenv_register (fe);
++          return x * b;
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_washf (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+new file mode 100644
+index 0000000000..71e516d1c8
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+@@ -0,0 +1,134 @@
++/* Double-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float two108 = 3.245185536584267269e+32;
++static const float twom54 = 5.551115123125782702e-17;
++static const float half = 0.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the actual square root and half of its reciprocal
++   simultaneously.  */
++
++#ifdef __STDC__
++double
++__ieee754_sqrt (double b)
++#else
++double
++__ieee754_sqrt (b)
++     double b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++      double y, g, h, d, r;
++      ieee_double_shape_type u;
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          u.value = b;
++
++          relax_fenv_state ();
++
++          __asm__ ("frsqrte %[estimate], %[x]\n"
++                   : [estimate] "=f" (y) : [x] "f" (b));
++
++          /* Following Muller et al, page 168, equation 5.20.
++
++             h goes to 1/(2*sqrt(b))
++             g goes to sqrt(b).
++
++             We need three iterations to get within 1ulp.  */
++
++          /* Indicate that these can be performed prior to the branch.  GCC
++             insists on sinking them below the branch, however; it seems like
++             they'd be better before the branch so that we can cover any latency
++             from storing the argument and loading its high word.  Oh well.  */
++
++          g = b * y;
++          h = 0.5 * y;
++
++          /* Handle small numbers by scaling.  */
++          if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
++            return __ieee754_sqrt (b * two108) * twom54;
++
++#define FMADD(a_, c_, b_)                                               \
++          ({ double __r;                                                \
++          __asm__ ("fmadd %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++#define FNMSUB(a_, c_, b_)                                          \
++          ({ double __r;                                                \
++          __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          /* g is now +/- 1ulp, or exactly equal to, the square root of b.  */
++
++          /* Final refinement.  */
++          d = FNMSUB (g, g, b);
++
++          fesetenv_register (fe);
++          return FMADD (d, h, g);
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_wash (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+new file mode 100644
+index 0000000000..26fa067abf
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+@@ -0,0 +1,101 @@
++/* Single-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float threehalf = 1.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the reciprocal square root and use that to compute the actual
++   square root.  */
++
++#ifdef __STDC__
++float
++__ieee754_sqrtf (float b)
++#else
++float
++__ieee754_sqrtf (b)
++     float b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++#define FMSUB(a_, c_, b_)                                               \
++      ({ double __r;                                                    \
++        __asm__ ("fmsub %[r], %[a], %[c], %[b]\n"                       \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++#define FNMSUB(a_, c_, b_)                                              \
++      ({ double __r;                                                    \
++        __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                      \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          double y, x;
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          relax_fenv_state ();
++
++          /* Compute y = 1.5 * b - b.  Uses fewer constants than y = 0.5 * b.  */
++          y = FMSUB (threehalf, b, b);
++
++          /* Initial estimate.  */
++          __asm__ ("frsqrte %[x], %[b]\n" : [x] "=f" (x) : [b] "f" (b));
++
++          /* Iterate.  x_{n+1} = x_n * (1.5 - y * (x_n * x_n)).  */
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++
++          /* All done.  */
++          fesetenv_register (fe);
++          return x * b;
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_washf (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+new file mode 100644
+index 0000000000..71e516d1c8
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+@@ -0,0 +1,134 @@
++/* Double-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float two108 = 3.245185536584267269e+32;
++static const float twom54 = 5.551115123125782702e-17;
++static const float half = 0.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the actual square root and half of its reciprocal
++   simultaneously.  */
++
++#ifdef __STDC__
++double
++__ieee754_sqrt (double b)
++#else
++double
++__ieee754_sqrt (b)
++     double b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++      double y, g, h, d, r;
++      ieee_double_shape_type u;
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          u.value = b;
++
++          relax_fenv_state ();
++
++          __asm__ ("frsqrte %[estimate], %[x]\n"
++                   : [estimate] "=f" (y) : [x] "f" (b));
++
++          /* Following Muller et al, page 168, equation 5.20.
++
++             h goes to 1/(2*sqrt(b))
++             g goes to sqrt(b).
++
++             We need three iterations to get within 1ulp.  */
++
++          /* Indicate that these can be performed prior to the branch.  GCC
++             insists on sinking them below the branch, however; it seems like
++             they'd be better before the branch so that we can cover any latency
++             from storing the argument and loading its high word.  Oh well.  */
++
++          g = b * y;
++          h = 0.5 * y;
++
++          /* Handle small numbers by scaling.  */
++          if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
++            return __ieee754_sqrt (b * two108) * twom54;
++
++#define FMADD(a_, c_, b_)                                               \
++          ({ double __r;                                                \
++          __asm__ ("fmadd %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++#define FNMSUB(a_, c_, b_)                                          \
++          ({ double __r;                                                \
++          __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          /* g is now +/- 1ulp, or exactly equal to, the square root of b.  */
++
++          /* Final refinement.  */
++          d = FNMSUB (g, g, b);
++
++          fesetenv_register (fe);
++          return FMADD (d, h, g);
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_wash (b);
++}
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+new file mode 100644
+index 0000000000..26fa067abf
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+@@ -0,0 +1,101 @@
++/* Single-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float threehalf = 1.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the reciprocal square root and use that to compute the actual
++   square root.  */
++
++#ifdef __STDC__
++float
++__ieee754_sqrtf (float b)
++#else
++float
++__ieee754_sqrtf (b)
++     float b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++#define FMSUB(a_, c_, b_)                                               \
++      ({ double __r;                                                    \
++        __asm__ ("fmsub %[r], %[a], %[c], %[b]\n"                       \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++#define FNMSUB(a_, c_, b_)                                              \
++      ({ double __r;                                                    \
++        __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                      \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          double y, x;
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          relax_fenv_state ();
++
++          /* Compute y = 1.5 * b - b.  Uses fewer constants than y = 0.5 * b.  */
++          y = FMSUB (threehalf, b, b);
++
++          /* Initial estimate.  */
++          __asm__ ("frsqrte %[x], %[b]\n" : [x] "=f" (x) : [b] "f" (b));
++
++          /* Iterate.  x_{n+1} = x_n * (1.5 - y * (x_n * x_n)).  */
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++
++          /* All done.  */
++          fesetenv_register (fe);
++          return x * b;
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_washf (b);
++}
+diff --git a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+new file mode 100644
+index 0000000000..71e516d1c8
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+@@ -0,0 +1,134 @@
++/* Double-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float two108 = 3.245185536584267269e+32;
++static const float twom54 = 5.551115123125782702e-17;
++static const float half = 0.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the actual square root and half of its reciprocal
++   simultaneously.  */
++
++#ifdef __STDC__
++double
++__ieee754_sqrt (double b)
++#else
++double
++__ieee754_sqrt (b)
++     double b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++      double y, g, h, d, r;
++      ieee_double_shape_type u;
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          u.value = b;
++
++          relax_fenv_state ();
++
++          __asm__ ("frsqrte %[estimate], %[x]\n"
++                   : [estimate] "=f" (y) : [x] "f" (b));
++
++          /* Following Muller et al, page 168, equation 5.20.
++
++             h goes to 1/(2*sqrt(b))
++             g goes to sqrt(b).
++
++             We need three iterations to get within 1ulp.  */
++
++          /* Indicate that these can be performed prior to the branch.  GCC
++             insists on sinking them below the branch, however; it seems like
++             they'd be better before the branch so that we can cover any latency
++             from storing the argument and loading its high word.  Oh well.  */
++
++          g = b * y;
++          h = 0.5 * y;
++
++          /* Handle small numbers by scaling.  */
++          if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
++            return __ieee754_sqrt (b * two108) * twom54;
++
++#define FMADD(a_, c_, b_)                                               \
++          ({ double __r;                                                \
++          __asm__ ("fmadd %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++#define FNMSUB(a_, c_, b_)                                          \
++          ({ double __r;                                                \
++          __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          /* g is now +/- 1ulp, or exactly equal to, the square root of b.  */
++
++          /* Final refinement.  */
++          d = FNMSUB (g, g, b);
++
++          fesetenv_register (fe);
++          return FMADD (d, h, g);
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_wash (b);
++}
+diff --git a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+new file mode 100644
+index 0000000000..26fa067abf
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+@@ -0,0 +1,101 @@
++/* Single-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float threehalf = 1.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the reciprocal square root and use that to compute the actual
++   square root.  */
++
++#ifdef __STDC__
++float
++__ieee754_sqrtf (float b)
++#else
++float
++__ieee754_sqrtf (b)
++     float b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++#define FMSUB(a_, c_, b_)                                               \
++      ({ double __r;                                                    \
++        __asm__ ("fmsub %[r], %[a], %[c], %[b]\n"                       \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++#define FNMSUB(a_, c_, b_)                                              \
++      ({ double __r;                                                    \
++        __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                      \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          double y, x;
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          relax_fenv_state ();
++
++          /* Compute y = 1.5 * b - b.  Uses fewer constants than y = 0.5 * b.  */
++          y = FMSUB (threehalf, b, b);
++
++          /* Initial estimate.  */
++          __asm__ ("frsqrte %[x], %[b]\n" : [x] "=f" (x) : [b] "f" (b));
++
++          /* Iterate.  x_{n+1} = x_n * (1.5 - y * (x_n * x_n)).  */
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++
++          /* All done.  */
++          fesetenv_register (fe);
++          return x * b;
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_washf (b);
++}
+diff --git a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+new file mode 100644
+index 0000000000..71e516d1c8
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+@@ -0,0 +1,134 @@
++/* Double-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float two108 = 3.245185536584267269e+32;
++static const float twom54 = 5.551115123125782702e-17;
++static const float half = 0.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the actual square root and half of its reciprocal
++   simultaneously.  */
++
++#ifdef __STDC__
++double
++__ieee754_sqrt (double b)
++#else
++double
++__ieee754_sqrt (b)
++     double b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++      double y, g, h, d, r;
++      ieee_double_shape_type u;
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          u.value = b;
++
++          relax_fenv_state ();
++
++          __asm__ ("frsqrte %[estimate], %[x]\n"
++                   : [estimate] "=f" (y) : [x] "f" (b));
++
++          /* Following Muller et al, page 168, equation 5.20.
++
++             h goes to 1/(2*sqrt(b))
++             g goes to sqrt(b).
++
++             We need three iterations to get within 1ulp.  */
++
++          /* Indicate that these can be performed prior to the branch.  GCC
++             insists on sinking them below the branch, however; it seems like
++             they'd be better before the branch so that we can cover any latency
++             from storing the argument and loading its high word.  Oh well.  */
++
++          g = b * y;
++          h = 0.5 * y;
++
++          /* Handle small numbers by scaling.  */
++          if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
++            return __ieee754_sqrt (b * two108) * twom54;
++
++#define FMADD(a_, c_, b_)                                               \
++          ({ double __r;                                                \
++          __asm__ ("fmadd %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++#define FNMSUB(a_, c_, b_)                                          \
++          ({ double __r;                                                \
++          __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                     \
++                   : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++          __r;})
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          r = FNMSUB (g, h, half);
++          g = FMADD (g, r, g);
++          h = FMADD (h, r, h);
++
++          /* g is now +/- 1ulp, or exactly equal to, the square root of b.  */
++
++          /* Final refinement.  */
++          d = FNMSUB (g, g, b);
++
++          fesetenv_register (fe);
++          return FMADD (d, h, g);
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_wash (b);
++}
+diff --git a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+new file mode 100644
+index 0000000000..26fa067abf
+--- /dev/null
++++ b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+@@ -0,0 +1,101 @@
++/* Single-precision floating point square root.
++   Copyright (C) 2010 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <math.h>
++#include <math_private.h>
++#include <fenv_libc.h>
++#include <inttypes.h>
++
++#include <sysdep.h>
++#include <ldsodefs.h>
++
++static const ieee_float_shape_type a_nan = {.word = 0x7fc00000 };
++static const ieee_float_shape_type a_inf = {.word = 0x7f800000 };
++static const float threehalf = 1.5;
++
++/* The method is based on the descriptions in:
++
++   _The Handbook of Floating-Pointer Arithmetic_ by Muller et al., chapter 5;
++   _IA-64 and Elementary Functions: Speed and Precision_ by Markstein, chapter 9
++
++   We find the reciprocal square root and use that to compute the actual
++   square root.  */
++
++#ifdef __STDC__
++float
++__ieee754_sqrtf (float b)
++#else
++float
++__ieee754_sqrtf (b)
++     float b;
++#endif
++{
++  if (__builtin_expect (b > 0, 1))
++    {
++#define FMSUB(a_, c_, b_)                                               \
++      ({ double __r;                                                    \
++        __asm__ ("fmsub %[r], %[a], %[c], %[b]\n"                       \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++#define FNMSUB(a_, c_, b_)                                              \
++      ({ double __r;                                                    \
++        __asm__ ("fnmsub %[r], %[a], %[c], %[b]\n"                      \
++                 : [r] "=f" (__r) : [a] "f" (a_), [c] "f" (c_), [b] "f" (b_)); \
++        __r;})
++
++      if (__builtin_expect (b != a_inf.value, 1))
++        {
++          double y, x;
++          fenv_t fe;
++
++          fe = fegetenv_register ();
++
++          relax_fenv_state ();
++
++          /* Compute y = 1.5 * b - b.  Uses fewer constants than y = 0.5 * b.  */
++          y = FMSUB (threehalf, b, b);
++
++          /* Initial estimate.  */
++          __asm__ ("frsqrte %[x], %[b]\n" : [x] "=f" (x) : [b] "f" (b));
++
++          /* Iterate.  x_{n+1} = x_n * (1.5 - y * (x_n * x_n)).  */
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++          x = x * FNMSUB (y, x * x, threehalf);
++
++          /* All done.  */
++          fesetenv_register (fe);
++          return x * b;
++        }
++    }
++  else if (b < 0)
++    {
++      /* For some reason, some PowerPC32 processors don't implement
++         FE_INVALID_SQRT.  */
++#ifdef FE_INVALID_SQRT
++      feraiseexcept (FE_INVALID_SQRT);
++
++      fenv_union_t u = { .fenv = fegetenv_register () };
++      if ((u.l & FE_INVALID) == 0)
++#endif
++	feraiseexcept (FE_INVALID);
++      b = a_nan.value;
++    }
++  return f_washf (b);
++}
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/603e/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc32/603e/fpu/Implies
+new file mode 100644
+index 0000000000..b103b4dea5
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/603e/fpu/Implies
+@@ -0,0 +1 @@
++powerpc/powerpc32/603e/fpu
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/e300c3/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e300c3/fpu/Implies
+new file mode 100644
+index 0000000000..64db17fada
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e300c3/fpu/Implies
+@@ -0,0 +1,2 @@
++# e300c3 is a variant of 603e so use the same optimizations for sqrt
++powerpc/powerpc32/603e/fpu
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/e500mc/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e500mc/fpu/Implies
+new file mode 100644
+index 0000000000..7eac5fcf02
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e500mc/fpu/Implies
+@@ -0,0 +1 @@
++powerpc/powerpc32/e500mc/fpu
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/e5500/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e5500/fpu/Implies
+new file mode 100644
+index 0000000000..264b2a7700
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e5500/fpu/Implies
+@@ -0,0 +1 @@
++powerpc/powerpc32/e5500/fpu
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/e6500/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e6500/fpu/Implies
+new file mode 100644
+index 0000000000..a25934467b
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/e6500/fpu/Implies
+@@ -0,0 +1 @@
++powerpc/powerpc32/e6500/fpu
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/e5500/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc64/e5500/fpu/Implies
+new file mode 100644
+index 0000000000..a7bc854be8
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/e5500/fpu/Implies
+@@ -0,0 +1 @@
++powerpc/powerpc64/e5500/fpu
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/e6500/fpu/Implies b/sysdeps/unix/sysv/linux/powerpc/powerpc64/e6500/fpu/Implies
+new file mode 100644
+index 0000000000..04ff8cc181
+--- /dev/null
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/e6500/fpu/Implies
+@@ -0,0 +1 @@
++powerpc/powerpc64/e6500/fpu

+ 205 - 0
recipes-core/glibc/glibc/0010-ppc-sqrt-Fix-undefined-reference-to-__sqrt_finite.patch

@@ -0,0 +1,205 @@
+From 5da3da7f2d276c2a6ae1b04419b28e96953803ec Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:15:07 +0000
+Subject: [PATCH] ppc/sqrt: Fix undefined reference to `__sqrt_finite'
+
+on ppc fixes the errors like below
+| ./.libs/libpulsecore-1.1.so: undefined reference to `__sqrt_finite'
+| collect2: ld returned 1 exit status
+
+Upstream-Status: Pending
+
+ChangeLog
+
+2012-01-06  Khem Raj  <raj.khem@gmail.com>
+
+        * sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c: Add __*_finite alias.
+        Remove cruft.
+        * sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c: Ditto.
+        * sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c: Ditto.
+        * sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c: Ditto.
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c    | 7 +------
+ sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c   | 7 +------
+ sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c  | 1 +
+ sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c | 1 +
+ sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c   | 1 +
+ sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c  | 1 +
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c   | 1 +
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c  | 1 +
+ sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c   | 7 +------
+ sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c  | 7 +------
+ sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c   | 1 +
+ sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c  | 1 +
+ 12 files changed, 12 insertions(+), 24 deletions(-)
+
+diff --git a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+index 71e516d1c8..1795fd6c3e 100644
+--- a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+@@ -39,14 +39,8 @@ static const float half = 0.5;
+    We find the actual square root and half of its reciprocal
+    simultaneously.  */
+ 
+-#ifdef __STDC__
+ double
+ __ieee754_sqrt (double b)
+-#else
+-double
+-__ieee754_sqrt (b)
+-     double b;
+-#endif
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -132,3 +126,4 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+index 26fa067abf..a917f313ab 100644
+--- a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+@@ -37,14 +37,8 @@ static const float threehalf = 1.5;
+    We find the reciprocal square root and use that to compute the actual
+    square root.  */
+ 
+-#ifdef __STDC__
+ float
+ __ieee754_sqrtf (float b)
+-#else
+-float
+-__ieee754_sqrtf (b)
+-     float b;
+-#endif
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -99,3 +93,4 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+index 71e516d1c8..fc4a74990e 100644
+--- a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+@@ -132,3 +132,4 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+index 26fa067abf..9d175122a8 100644
+--- a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+@@ -99,3 +99,4 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+index 71e516d1c8..fc4a74990e 100644
+--- a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+@@ -132,3 +132,4 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+index 26fa067abf..9d175122a8 100644
+--- a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+@@ -99,3 +99,4 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+index 71e516d1c8..fc4a74990e 100644
+--- a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+@@ -132,3 +132,4 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+index 26fa067abf..9d175122a8 100644
+--- a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+@@ -99,3 +99,4 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+index 71e516d1c8..1795fd6c3e 100644
+--- a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+@@ -39,14 +39,8 @@ static const float half = 0.5;
+    We find the actual square root and half of its reciprocal
+    simultaneously.  */
+ 
+-#ifdef __STDC__
+ double
+ __ieee754_sqrt (double b)
+-#else
+-double
+-__ieee754_sqrt (b)
+-     double b;
+-#endif
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -132,3 +126,4 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+index 26fa067abf..a917f313ab 100644
+--- a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+@@ -37,14 +37,8 @@ static const float threehalf = 1.5;
+    We find the reciprocal square root and use that to compute the actual
+    square root.  */
+ 
+-#ifdef __STDC__
+ float
+ __ieee754_sqrtf (float b)
+-#else
+-float
+-__ieee754_sqrtf (b)
+-     float b;
+-#endif
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -99,3 +93,4 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+index 71e516d1c8..fc4a74990e 100644
+--- a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+@@ -132,3 +132,4 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+index 26fa067abf..9d175122a8 100644
+--- a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+@@ -99,3 +99,4 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++strong_alias (__ieee754_sqrtf, __sqrtf_finite)

+ 384 - 0
recipes-core/glibc/glibc/0011-__ieee754_sqrt-f-are-now-inline-functions-and-call-o.patch

@@ -0,0 +1,384 @@
+From 77f1c90d67a2f8852184fb8fd95cb0ed63065dc7 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:16:38 +0000
+Subject: [PATCH] __ieee754_sqrt{,f} are now inline functions and call out
+ __slow versions
+
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c    | 12 ++++++++++--
+ sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c   |  8 +++++++-
+ sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c  | 14 +++++++++++---
+ sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c | 12 ++++++++++--
+ sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c   | 14 +++++++++++---
+ sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c  | 12 ++++++++++--
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c   |  8 ++++++++
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c  |  8 ++++++++
+ sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c   | 12 ++++++++++--
+ sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c  |  9 ++++++++-
+ sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c   | 14 +++++++++++---
+ sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c  | 12 ++++++++++--
+ 12 files changed, 114 insertions(+), 21 deletions(-)
+
+diff --git a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+index 1795fd6c3e..daa83f3fe8 100644
+--- a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrt.c
+@@ -40,7 +40,7 @@ static const float half = 0.5;
+    simultaneously.  */
+ 
+ double
+-__ieee754_sqrt (double b)
++__slow_ieee754_sqrt (double b)
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -77,7 +77,7 @@ __ieee754_sqrt (double b)
+ 
+           /* Handle small numbers by scaling.  */
+           if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
+-            return __ieee754_sqrt (b * two108) * twom54;
++            return __slow_ieee754_sqrt (b * two108) * twom54;
+ 
+ #define FMADD(a_, c_, b_)                                               \
+           ({ double __r;                                                \
+@@ -126,4 +126,12 @@ __ieee754_sqrt (double b)
+     }
+   return f_wash (b);
+ }
++
++#undef __ieee754_sqrt
++double
++__ieee754_sqrt (double x)
++{
++   return __slow_ieee754_sqrt (x);
++}
++
+ strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+index a917f313ab..b812cf1705 100644
+--- a/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/603e/fpu/e_sqrtf.c
+@@ -38,7 +38,7 @@ static const float threehalf = 1.5;
+    square root.  */
+ 
+ float
+-__ieee754_sqrtf (float b)
++__slow_ieee754_sqrtf (float b)
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -93,4 +93,10 @@ __ieee754_sqrtf (float b)
+     }
+   return f_washf (b);
+ }
++#undef __ieee754_sqrtf
++float
++__ieee754_sqrtf (float x)
++{
++  return __slow_ieee754_sqrtf (x);
++}
+ strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+index fc4a74990e..7038a70b47 100644
+--- a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrt.c
+@@ -41,10 +41,10 @@ static const float half = 0.5;
+ 
+ #ifdef __STDC__
+ double
+-__ieee754_sqrt (double b)
++__slow_ieee754_sqrt (double b)
+ #else
+ double
+-__ieee754_sqrt (b)
++__slow_ieee754_sqrt (b)
+      double b;
+ #endif
+ {
+@@ -83,7 +83,7 @@ __ieee754_sqrt (b)
+ 
+           /* Handle small numbers by scaling.  */
+           if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
+-            return __ieee754_sqrt (b * two108) * twom54;
++            return __slow_ieee754_sqrt (b * two108) * twom54;
+ 
+ #define FMADD(a_, c_, b_)                                               \
+           ({ double __r;                                                \
+@@ -132,4 +132,12 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++
++#undef __ieee754_sqrt
++double
++__ieee754_sqrt (double x)
++{
++   return __slow_ieee754_sqrt (x);
++}
++
+ strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+index 9d175122a8..10de1f0cc3 100644
+--- a/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e500mc/fpu/e_sqrtf.c
+@@ -39,10 +39,10 @@ static const float threehalf = 1.5;
+ 
+ #ifdef __STDC__
+ float
+-__ieee754_sqrtf (float b)
++__slow_ieee754_sqrtf (float b)
+ #else
+ float
+-__ieee754_sqrtf (b)
++__slow_ieee754_sqrtf (b)
+      float b;
+ #endif
+ {
+@@ -99,4 +99,12 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++
++#undef __ieee754_sqrtf
++float
++__ieee754_sqrtf (float x)
++{
++  return __slow_ieee754_sqrtf (x);
++}
++
+ strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+index fc4a74990e..7038a70b47 100644
+--- a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrt.c
+@@ -41,10 +41,10 @@ static const float half = 0.5;
+ 
+ #ifdef __STDC__
+ double
+-__ieee754_sqrt (double b)
++__slow_ieee754_sqrt (double b)
+ #else
+ double
+-__ieee754_sqrt (b)
++__slow_ieee754_sqrt (b)
+      double b;
+ #endif
+ {
+@@ -83,7 +83,7 @@ __ieee754_sqrt (b)
+ 
+           /* Handle small numbers by scaling.  */
+           if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
+-            return __ieee754_sqrt (b * two108) * twom54;
++            return __slow_ieee754_sqrt (b * two108) * twom54;
+ 
+ #define FMADD(a_, c_, b_)                                               \
+           ({ double __r;                                                \
+@@ -132,4 +132,12 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++
++#undef __ieee754_sqrt
++double
++__ieee754_sqrt (double x)
++{
++   return __slow_ieee754_sqrt (x);
++}
++
+ strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+index 9d175122a8..10de1f0cc3 100644
+--- a/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e5500/fpu/e_sqrtf.c
+@@ -39,10 +39,10 @@ static const float threehalf = 1.5;
+ 
+ #ifdef __STDC__
+ float
+-__ieee754_sqrtf (float b)
++__slow_ieee754_sqrtf (float b)
+ #else
+ float
+-__ieee754_sqrtf (b)
++__slow_ieee754_sqrtf (b)
+      float b;
+ #endif
+ {
+@@ -99,4 +99,12 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++
++#undef __ieee754_sqrtf
++float
++__ieee754_sqrtf (float x)
++{
++  return __slow_ieee754_sqrtf (x);
++}
++
+ strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+index fc4a74990e..1c34244bd8 100644
+--- a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+@@ -132,4 +132,12 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++
++#undef __ieee754_sqrt
++double
++__ieee754_sqrt (double x)
++{
++   return __slow_ieee754_sqrt (x);
++}
++
+ strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+index 9d175122a8..812653558f 100644
+--- a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+@@ -99,4 +99,12 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++
++#undef __ieee754_sqrtf
++float
++__ieee754_sqrtf (float x)
++{
++  return __slow_ieee754_sqrtf (x);
++}
++
+ strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+index 1795fd6c3e..13a81973e3 100644
+--- a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrt.c
+@@ -40,7 +40,7 @@ static const float half = 0.5;
+    simultaneously.  */
+ 
+ double
+-__ieee754_sqrt (double b)
++__slow_ieee754_sqrt (double b)
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -77,7 +77,7 @@ __ieee754_sqrt (double b)
+ 
+           /* Handle small numbers by scaling.  */
+           if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
+-            return __ieee754_sqrt (b * two108) * twom54;
++            return __slow_ieee754_sqrt (b * two108) * twom54;
+ 
+ #define FMADD(a_, c_, b_)                                               \
+           ({ double __r;                                                \
+@@ -126,4 +126,12 @@ __ieee754_sqrt (double b)
+     }
+   return f_wash (b);
+ }
++
++#undef __ieee754_sqrt
++double
++__ieee754_sqrt (double x)
++{
++  return __slow_ieee754_sqrt (x);
++}
++
+ strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+index a917f313ab..fae2d81210 100644
+--- a/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc64/e5500/fpu/e_sqrtf.c
+@@ -38,7 +38,7 @@ static const float threehalf = 1.5;
+    square root.  */
+ 
+ float
+-__ieee754_sqrtf (float b)
++__slow_ieee754_sqrtf (float b)
+ {
+   if (__builtin_expect (b > 0, 1))
+     {
+@@ -93,4 +93,11 @@ __ieee754_sqrtf (float b)
+     }
+   return f_washf (b);
+ }
++#undef __ieee754_sqrtf
++float
++__ieee754_sqrtf (float x)
++{
++  return __slow_ieee754_sqrtf (x);
++}
++
+ strong_alias (__ieee754_sqrtf, __sqrtf_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+index fc4a74990e..7038a70b47 100644
+--- a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrt.c
+@@ -41,10 +41,10 @@ static const float half = 0.5;
+ 
+ #ifdef __STDC__
+ double
+-__ieee754_sqrt (double b)
++__slow_ieee754_sqrt (double b)
+ #else
+ double
+-__ieee754_sqrt (b)
++__slow_ieee754_sqrt (b)
+      double b;
+ #endif
+ {
+@@ -83,7 +83,7 @@ __ieee754_sqrt (b)
+ 
+           /* Handle small numbers by scaling.  */
+           if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
+-            return __ieee754_sqrt (b * two108) * twom54;
++            return __slow_ieee754_sqrt (b * two108) * twom54;
+ 
+ #define FMADD(a_, c_, b_)                                               \
+           ({ double __r;                                                \
+@@ -132,4 +132,12 @@ __ieee754_sqrt (b)
+     }
+   return f_wash (b);
+ }
++
++#undef __ieee754_sqrt
++double
++__ieee754_sqrt (double x)
++{
++   return __slow_ieee754_sqrt (x);
++}
++
+ strong_alias (__ieee754_sqrt, __sqrt_finite)
+diff --git a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+index 9d175122a8..10de1f0cc3 100644
+--- a/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc64/e6500/fpu/e_sqrtf.c
+@@ -39,10 +39,10 @@ static const float threehalf = 1.5;
+ 
+ #ifdef __STDC__
+ float
+-__ieee754_sqrtf (float b)
++__slow_ieee754_sqrtf (float b)
+ #else
+ float
+-__ieee754_sqrtf (b)
++__slow_ieee754_sqrtf (b)
+      float b;
+ #endif
+ {
+@@ -99,4 +99,12 @@ __ieee754_sqrtf (b)
+     }
+   return f_washf (b);
+ }
++
++#undef __ieee754_sqrtf
++float
++__ieee754_sqrtf (float x)
++{
++  return __slow_ieee754_sqrtf (x);
++}
++
+ strong_alias (__ieee754_sqrtf, __sqrtf_finite)

+ 58 - 0
recipes-core/glibc/glibc/0012-Quote-from-bug-1443-which-explains-what-the-patch-do.patch

@@ -0,0 +1,58 @@
+From add514edf4299d1bf540d85d0aa0bd5fe0d46b78 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:20:09 +0000
+Subject: [PATCH] Quote from bug 1443 which explains what the patch does :
+
+  We build some random program and link it with -lust.  When we run it,
+  it dies with a SIGSEGV before reaching main().
+
+  Libust.so depends on liburcu-bp.so from the usermode-rcu package.
+  Although libust.so is not prelinked, liburcu-bp.so IS prelinked; this
+  is critical.
+
+  Libust.so uses a TLS / __thread variable that is defined in liburcu-
+  bp.so.  There are special ARM-specific relocation types that allow two
+  shared libraries to share thread-specific data.  This is critical too.
+
+  One more critical issue: although liburcu-bp.so is prelinked, we can't
+  load it at its prelinked address, because we also link against
+  librt.so, and librt.so uses that address.
+
+  The dynamic linker is forced to relink liburcu-bp.so at a different
+  address.  In the course of relinking, it processes the special ARM
+  relocation record mentioned above.  The prelinker has already filled
+  in the information, which is a short offset into a table of thread-
+  specific data that is allocated per-thread for each library that uses
+  TLS.  Because the normal behavior of a relocation is to add the symbol
+  value to an addend stored at the address being relocated, we end up
+  adding the short offset to itself, doubling it.
+
+  Now we have an awkward situation.  The libust.so library doesn't know
+  about the addend, so its TLS data for this element is correct.  The
+  liburcu-bp.so library has a different offset for the element.  When we
+  go to initialize the element for the first time in liburcu-bp.so, we
+  write the address of the result at the doubled (broken) offset.
+  Later, when we refer to the address from libust.so, we check the value
+  at the correct offset, but it's NULL, so we eat hot SIGSEGV.
+
+Upstream-Status: Pending
+
+Signed-off-by: Andrei Dinu <andrei.adrianx.dinu@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/arm/dl-machine.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sysdeps/arm/dl-machine.h b/sysdeps/arm/dl-machine.h
+index ff5e09e207..d68bfe5cbe 100644
+--- a/sysdeps/arm/dl-machine.h
++++ b/sysdeps/arm/dl-machine.h
+@@ -510,7 +510,7 @@ elf_machine_rel (struct link_map *map, const Elf32_Rel *reloc,
+ 
+ 	case R_ARM_TLS_DTPOFF32:
+ 	  if (sym != NULL)
+-	    *reloc_addr += sym->st_value;
++	    *reloc_addr = sym->st_value;
+ 	  break;
+ 
+ 	case R_ARM_TLS_TPOFF32:

+ 33 - 0
recipes-core/glibc/glibc/0013-eglibc-run-libm-err-tab.pl-with-specific-dirs-in-S.patch

@@ -0,0 +1,33 @@
+From c5047b8f7d1a17324cfa02b99f07a70ebcec2cf2 Mon Sep 17 00:00:00 2001
+From: Ting Liu <b28495@freescale.com>
+Date: Wed, 19 Dec 2012 04:39:57 -0600
+Subject: [PATCH] eglibc: run libm-err-tab.pl with specific dirs in ${S}
+
+libm-err-tab.pl will parse all the files named "libm-test-ulps"
+in the given dir recursively. To avoid parsing the one in
+${S}/.pc/ (it does exist after eglibc adds aarch64 support,
+${S}/.pc/aarch64-0001-glibc-fsf-v1-eaf6f205.patch/ports/sysdeps/
+aarch64/libm-test-ulps), run libm-err-tab.pl with specific dirs
+in ${S}.
+
+Upstream-Status: inappropriate [OE specific]
+
+Signed-off-by: Ting Liu <b28495@freescale.com>
+---
+ manual/Makefile | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/manual/Makefile b/manual/Makefile
+index e83444341e..aa2645bc55 100644
+--- a/manual/Makefile
++++ b/manual/Makefile
+@@ -103,7 +103,8 @@ $(objpfx)stamp-libm-err: $(..)math/gen-libm-test.py \
+ 			 $(wildcard $(foreach dir,$(sysdirs),\
+ 						  $(dir)/libm-test-ulps))
+ 	pwd=`pwd`; \
+-	$(PYTHON) $< -s $$pwd/.. -m $(objpfx)libm-err-tmp
++	$(PYTHON) $< -s $$pwd/../ports -m $(objpfx)libm-err-tmp
++	$(PYTHON) $< -s $$pwd/../sysdeps -m $(objpfx)libm-err-tmp
+ 	$(move-if-change) $(objpfx)libm-err-tmp $(objpfx)libm-err.texi
+ 	touch $@
+ 

+ 58 - 0
recipes-core/glibc/glibc/0014-__ieee754_sqrt-f-are-now-inline-functions-and-call-o.patch

@@ -0,0 +1,58 @@
+From 133870f12ba36686dd8df1311fac32a4c5b28579 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:24:46 +0000
+Subject: [PATCH] __ieee754_sqrt{,f} are now inline functions and call out
+ __slow versions
+
+Upstream-Status: Pending
+
+Signed-off-by: chunrong guo <B40290@freescale.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c  | 6 +++---
+ sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c | 4 ++--
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+index 1c34244bd8..7038a70b47 100644
+--- a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrt.c
+@@ -41,10 +41,10 @@ static const float half = 0.5;
+ 
+ #ifdef __STDC__
+ double
+-__ieee754_sqrt (double b)
++__slow_ieee754_sqrt (double b)
+ #else
+ double
+-__ieee754_sqrt (b)
++__slow_ieee754_sqrt (b)
+      double b;
+ #endif
+ {
+@@ -83,7 +83,7 @@ __ieee754_sqrt (b)
+ 
+           /* Handle small numbers by scaling.  */
+           if (__builtin_expect ((u.parts.msw & 0x7ff00000) <= 0x02000000, 0))
+-            return __ieee754_sqrt (b * two108) * twom54;
++            return __slow_ieee754_sqrt (b * two108) * twom54;
+ 
+ #define FMADD(a_, c_, b_)                                               \
+           ({ double __r;                                                \
+diff --git a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+index 812653558f..10de1f0cc3 100644
+--- a/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
++++ b/sysdeps/powerpc/powerpc32/e6500/fpu/e_sqrtf.c
+@@ -39,10 +39,10 @@ static const float threehalf = 1.5;
+ 
+ #ifdef __STDC__
+ float
+-__ieee754_sqrtf (float b)
++__slow_ieee754_sqrtf (float b)
+ #else
+ float
+-__ieee754_sqrtf (b)
++__slow_ieee754_sqrtf (b)
+      float b;
+ #endif
+ {

+ 39 - 0
recipes-core/glibc/glibc/0015-sysdeps-gnu-configure.ac-handle-correctly-libc_cv_ro.patch

@@ -0,0 +1,39 @@
+From b4613f814ba7ba5db95d18116172f81a83ac8f5b Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:27:10 +0000
+Subject: [PATCH] sysdeps/gnu/configure.ac: handle correctly
+ $libc_cv_rootsbindir
+
+Upstream-Status:Pending
+
+Signed-off-by: Matthieu Crapet <Matthieu.Crapet@ingenico.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/gnu/configure    | 2 +-
+ sysdeps/gnu/configure.ac | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sysdeps/gnu/configure b/sysdeps/gnu/configure
+index c15d1087e8..37cc983f2a 100644
+--- a/sysdeps/gnu/configure
++++ b/sysdeps/gnu/configure
+@@ -32,6 +32,6 @@ case "$prefix" in
+   else
+     libc_cv_localstatedir=$localstatedir
+    fi
+-  libc_cv_rootsbindir=/sbin
++  test -n "$libc_cv_rootsbindir" || libc_cv_rootsbindir=/sbin
+   ;;
+ esac
+diff --git a/sysdeps/gnu/configure.ac b/sysdeps/gnu/configure.ac
+index 634fe4de2a..3db1697f4f 100644
+--- a/sysdeps/gnu/configure.ac
++++ b/sysdeps/gnu/configure.ac
+@@ -21,6 +21,6 @@ case "$prefix" in
+   else
+     libc_cv_localstatedir=$localstatedir
+    fi
+-  libc_cv_rootsbindir=/sbin
++  test -n "$libc_cv_rootsbindir" || libc_cv_rootsbindir=/sbin
+   ;;
+ esac

+ 260 - 0
recipes-core/glibc/glibc/0016-yes-within-the-path-sets-wrong-config-variables.patch

@@ -0,0 +1,260 @@
+From 7be3e82b66394a7b242e56c6fc609e858b8e2436 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:31:06 +0000
+Subject: [PATCH] 'yes' within the path sets wrong config variables
+
+It seems that the 'AC_EGREP_CPP(yes...' example is quite popular
+but being such a short word to grep it is likely to produce
+false-positive matches with the path it is configured into.
+
+The change is to use a more elaborated string to grep for.
+
+Upstream-Status: Submitted [libc-alpha@sourceware.org]
+
+Signed-off-by: Benjamin Esquivel <benjamin.esquivel@linux.intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/aarch64/configure                              | 4 ++--
+ sysdeps/aarch64/configure.ac                           | 4 ++--
+ sysdeps/arm/configure                                  | 4 ++--
+ sysdeps/arm/configure.ac                               | 4 ++--
+ sysdeps/mips/configure                                 | 4 ++--
+ sysdeps/mips/configure.ac                              | 4 ++--
+ sysdeps/nios2/configure                                | 4 ++--
+ sysdeps/nios2/configure.ac                             | 4 ++--
+ sysdeps/unix/sysv/linux/mips/configure                 | 4 ++--
+ sysdeps/unix/sysv/linux/mips/configure.ac              | 4 ++--
+ sysdeps/unix/sysv/linux/powerpc/powerpc64/configure    | 8 ++++----
+ sysdeps/unix/sysv/linux/powerpc/powerpc64/configure.ac | 8 ++++----
+ 12 files changed, 28 insertions(+), 28 deletions(-)
+
+diff --git a/sysdeps/aarch64/configure b/sysdeps/aarch64/configure
+index 4c1fac49f3..597314f476 100644
+--- a/sysdeps/aarch64/configure
++++ b/sysdeps/aarch64/configure
+@@ -157,12 +157,12 @@ else
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+ #ifdef __AARCH64EB__
+-                      yes
++                      is_aarch64_be
+                      #endif
+ 
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "is_aarch64_be" >/dev/null 2>&1; then :
+   libc_cv_aarch64_be=yes
+ else
+   libc_cv_aarch64_be=no
+diff --git a/sysdeps/aarch64/configure.ac b/sysdeps/aarch64/configure.ac
+index 3347c13fa1..4af163c0b6 100644
+--- a/sysdeps/aarch64/configure.ac
++++ b/sysdeps/aarch64/configure.ac
+@@ -17,8 +17,8 @@ AC_DEFINE(SUPPORT_STATIC_PIE)
+ # the dynamic linker via %ifdef.
+ AC_CACHE_CHECK([for big endian],
+   [libc_cv_aarch64_be],
+-  [AC_EGREP_CPP(yes,[#ifdef __AARCH64EB__
+-                      yes
++  [AC_EGREP_CPP(is_aarch64_be,[#ifdef __AARCH64EB__
++                      is_aarch64_be
+                      #endif
+   ], libc_cv_aarch64_be=yes, libc_cv_aarch64_be=no)])
+ if test $libc_cv_aarch64_be = yes; then
+diff --git a/sysdeps/arm/configure b/sysdeps/arm/configure
+index 431e843b2b..e152461138 100644
+--- a/sysdeps/arm/configure
++++ b/sysdeps/arm/configure
+@@ -151,12 +151,12 @@ else
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+ #ifdef __ARM_PCS_VFP
+-		      yes
++		      use_arm_pcs_vfp
+ 		     #endif
+ 
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "use_arm_pcs_vfp" >/dev/null 2>&1; then :
+   libc_cv_arm_pcs_vfp=yes
+ else
+   libc_cv_arm_pcs_vfp=no
+diff --git a/sysdeps/arm/configure.ac b/sysdeps/arm/configure.ac
+index 90cdd69c75..05a262ba00 100644
+--- a/sysdeps/arm/configure.ac
++++ b/sysdeps/arm/configure.ac
+@@ -15,8 +15,8 @@ AC_DEFINE(PI_STATIC_AND_HIDDEN)
+ # the dynamic linker via %ifdef.
+ AC_CACHE_CHECK([whether the compiler is using the ARM hard-float ABI],
+   [libc_cv_arm_pcs_vfp],
+-  [AC_EGREP_CPP(yes,[#ifdef __ARM_PCS_VFP
+-		      yes
++  [AC_EGREP_CPP(use_arm_pcs_vfp,[#ifdef __ARM_PCS_VFP
++		      use_arm_pcs_vfp
+ 		     #endif
+   ], libc_cv_arm_pcs_vfp=yes, libc_cv_arm_pcs_vfp=no)])
+ if test $libc_cv_arm_pcs_vfp = yes; then
+diff --git a/sysdeps/mips/configure b/sysdeps/mips/configure
+index 4e13248c03..f14af952d0 100644
+--- a/sysdeps/mips/configure
++++ b/sysdeps/mips/configure
+@@ -143,11 +143,11 @@ else
+ /* end confdefs.h.  */
+ dnl
+ #ifdef __mips_nan2008
+-yes
++use_mips_nan2008
+ #endif
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "use_mips_nan2008" >/dev/null 2>&1; then :
+   libc_cv_mips_nan2008=yes
+ else
+   libc_cv_mips_nan2008=no
+diff --git a/sysdeps/mips/configure.ac b/sysdeps/mips/configure.ac
+index bcbdaffd9f..ad3057f4cc 100644
+--- a/sysdeps/mips/configure.ac
++++ b/sysdeps/mips/configure.ac
+@@ -6,9 +6,9 @@ dnl position independent way.
+ dnl AC_DEFINE(PI_STATIC_AND_HIDDEN)
+ 
+ AC_CACHE_CHECK([whether the compiler is using the 2008 NaN encoding],
+-  libc_cv_mips_nan2008, [AC_EGREP_CPP(yes, [dnl
++  libc_cv_mips_nan2008, [AC_EGREP_CPP(use_mips_nan2008, [dnl
+ #ifdef __mips_nan2008
+-yes
++use_mips_nan2008
+ #endif], libc_cv_mips_nan2008=yes, libc_cv_mips_nan2008=no)])
+ if test x$libc_cv_mips_nan2008 = xyes; then
+   AC_DEFINE(HAVE_MIPS_NAN2008)
+diff --git a/sysdeps/nios2/configure b/sysdeps/nios2/configure
+index 14c8a3a014..dde3814ef2 100644
+--- a/sysdeps/nios2/configure
++++ b/sysdeps/nios2/configure
+@@ -142,12 +142,12 @@ else
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+ #ifdef __nios2_big_endian__
+-                      yes
++                      is_nios2_be
+                      #endif
+ 
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "is_nios2_be" >/dev/null 2>&1; then :
+   libc_cv_nios2_be=yes
+ else
+   libc_cv_nios2_be=no
+diff --git a/sysdeps/nios2/configure.ac b/sysdeps/nios2/configure.ac
+index f05f43802b..dc8639902d 100644
+--- a/sysdeps/nios2/configure.ac
++++ b/sysdeps/nios2/configure.ac
+@@ -4,8 +4,8 @@ GLIBC_PROVIDES dnl See aclocal.m4 in the top level source directory.
+ # Nios II big endian is not yet supported.
+ AC_CACHE_CHECK([for big endian],
+   [libc_cv_nios2_be],
+-  [AC_EGREP_CPP(yes,[#ifdef __nios2_big_endian__
+-                      yes
++  [AC_EGREP_CPP(is_nios2_be,[#ifdef __nios2_big_endian__
++                      is_nios2_be
+                      #endif
+   ], libc_cv_nios2_be=yes, libc_cv_nios2_be=no)])
+ if test $libc_cv_nios2_be = yes; then
+diff --git a/sysdeps/unix/sysv/linux/mips/configure b/sysdeps/unix/sysv/linux/mips/configure
+index f25f2a3a65..1b7483e6c6 100644
+--- a/sysdeps/unix/sysv/linux/mips/configure
++++ b/sysdeps/unix/sysv/linux/mips/configure
+@@ -414,11 +414,11 @@ else
+ /* end confdefs.h.  */
+ dnl
+ #ifdef __mips_nan2008
+-yes
++use_mips_nan2008
+ #endif
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "use_mips_nan2008" >/dev/null 2>&1; then :
+   libc_cv_mips_nan2008=yes
+ else
+   libc_cv_mips_nan2008=no
+diff --git a/sysdeps/unix/sysv/linux/mips/configure.ac b/sysdeps/unix/sysv/linux/mips/configure.ac
+index 049a0f4bdf..005526d4e8 100644
+--- a/sysdeps/unix/sysv/linux/mips/configure.ac
++++ b/sysdeps/unix/sysv/linux/mips/configure.ac
+@@ -105,9 +105,9 @@ AC_COMPILE_IFELSE(
+ LIBC_CONFIG_VAR([mips-mode-switch],[${libc_mips_mode_switch}])
+ 
+ AC_CACHE_CHECK([whether the compiler is using the 2008 NaN encoding],
+-  libc_cv_mips_nan2008, [AC_EGREP_CPP(yes, [dnl
++  libc_cv_mips_nan2008, [AC_EGREP_CPP(use_mips_nan2008, [dnl
+ #ifdef __mips_nan2008
+-yes
++use_mips_nan2008
+ #endif], libc_cv_mips_nan2008=yes, libc_cv_mips_nan2008=no)])
+ 
+ libc_mips_nan=
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure b/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure
+index ae7f254da4..874519000b 100644
+--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure
+@@ -155,12 +155,12 @@ else
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+ #if _CALL_ELF == 2
+-                      yes
++                      use_ppc_elfv2_abi
+                      #endif
+ 
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "use_ppc_elfv2_abi" >/dev/null 2>&1; then :
+   libc_cv_ppc64_elfv2_abi=yes
+ else
+   libc_cv_ppc64_elfv2_abi=no
+@@ -188,12 +188,12 @@ else
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+ /* end confdefs.h.  */
+ #ifdef _CALL_ELF
+-                         yes
++                         is_def_call_elf
+                        #endif
+ 
+ _ACEOF
+ if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+-  $EGREP "yes" >/dev/null 2>&1; then :
++  $EGREP "is_def_call_elf" >/dev/null 2>&1; then :
+   libc_cv_ppc64_def_call_elf=yes
+ else
+   libc_cv_ppc64_def_call_elf=no
+diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure.ac b/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure.ac
+index f9cba6e15d..b21f72f1e4 100644
+--- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure.ac
++++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/configure.ac
+@@ -6,8 +6,8 @@ LIBC_SLIBDIR_RTLDDIR([lib64], [lib64])
+ # Define default-abi according to compiler flags.
+ AC_CACHE_CHECK([whether the compiler is using the PowerPC64 ELFv2 ABI],
+   [libc_cv_ppc64_elfv2_abi],
+-  [AC_EGREP_CPP(yes,[#if _CALL_ELF == 2
+-                      yes
++  [AC_EGREP_CPP(use_ppc_elfv2_abi,[#if _CALL_ELF == 2
++                      use_ppc_elfv2_abi
+                      #endif
+   ], libc_cv_ppc64_elfv2_abi=yes, libc_cv_ppc64_elfv2_abi=no)])
+ if test $libc_cv_ppc64_elfv2_abi = yes; then
+@@ -19,8 +19,8 @@ else
+   # Compiler that do not support ELFv2 ABI does not define _CALL_ELF
+   AC_CACHE_CHECK([whether the compiler defines _CALL_ELF],
+     [libc_cv_ppc64_def_call_elf],
+-    [AC_EGREP_CPP(yes,[#ifdef _CALL_ELF
+-                         yes
++    [AC_EGREP_CPP(is_def_call_elf,[#ifdef _CALL_ELF
++                         is_def_call_elf
+                        #endif
+     ], libc_cv_ppc64_def_call_elf=yes, libc_cv_ppc64_def_call_elf=no)])
+   if test $libc_cv_ppc64_def_call_elf = no; then

+ 34 - 0
recipes-core/glibc/glibc/0017-timezone-re-written-tzselect-as-posix-sh.patch

@@ -0,0 +1,34 @@
+From 2731fa0c7463cd160361a8ac92f3bd7f984d953d Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:33:03 +0000
+Subject: [PATCH] timezone: re-written tzselect as posix sh
+
+To avoid the bash dependency.
+
+Upstream-Status: Pending
+
+Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ timezone/tzselect.ksh | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/timezone/tzselect.ksh b/timezone/tzselect.ksh
+index 18fce27e24..7705df83d7 100755
+--- a/timezone/tzselect.ksh
++++ b/timezone/tzselect.ksh
+@@ -1,4 +1,4 @@
+-#!/bin/bash
++#!/bin/sh
+ # Ask the user about the time zone, and output the resulting TZ value to stdout.
+ # Interact with the user via stderr and stdin.
+ 
+@@ -34,7 +34,7 @@ REPORT_BUGS_TO=tz@iana.org
+ 
+ # Specify default values for environment variables if they are unset.
+ : ${AWK=awk}
+-: ${TZDIR=`pwd`}
++: ${TZDIR=$(pwd)}
+ 
+ # Output one argument as-is to standard output.
+ # Safer than 'echo', which can mishandle '\' or leading '-'.

+ 72 - 0
recipes-core/glibc/glibc/0018-Remove-bash-dependency-for-nscd-init-script.patch

@@ -0,0 +1,72 @@
+From 412d33bbfe42a10a9b1f62afcc73fe121a0363b0 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Thu, 31 Dec 2015 14:33:02 -0800
+Subject: [PATCH] Remove bash dependency for nscd init script
+
+The nscd init script uses #! /bin/bash but only really uses one bashism
+(translated strings), so remove them and switch the shell to #!/bin/sh.
+
+Upstream-Status: Pending
+
+Signed-off-by: Ross Burton <ross.burton@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ nscd/nscd.init | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/nscd/nscd.init b/nscd/nscd.init
+index a882da7d8b..b02986ec15 100644
+--- a/nscd/nscd.init
++++ b/nscd/nscd.init
+@@ -1,4 +1,4 @@
+-#!/bin/bash
++#!/bin/sh
+ #
+ # nscd:		Starts the Name Switch Cache Daemon
+ #
+@@ -49,7 +49,7 @@ prog=nscd
+ start () {
+     [ -d /var/run/nscd ] || mkdir /var/run/nscd
+     [ -d /var/db/nscd ] || mkdir /var/db/nscd
+-    echo -n $"Starting $prog: "
++    echo -n "Starting $prog: "
+     daemon /usr/sbin/nscd
+     RETVAL=$?
+     echo
+@@ -58,7 +58,7 @@ start () {
+ }
+ 
+ stop () {
+-    echo -n $"Stopping $prog: "
++    echo -n "Stopping $prog: "
+     /usr/sbin/nscd -K
+     RETVAL=$?
+     if [ $RETVAL -eq 0 ]; then
+@@ -67,9 +67,9 @@ stop () {
+ 	# a non-privileged user
+ 	rm -f /var/run/nscd/nscd.pid
+ 	rm -f /var/run/nscd/socket
+-       	success $"$prog shutdown"
++	success "$prog shutdown"
+     else
+-       	failure $"$prog shutdown"
++	failure "$prog shutdown"
+     fi
+     echo
+     return $RETVAL
+@@ -103,13 +103,13 @@ case "$1" in
+ 	RETVAL=$?
+ 	;;
+     force-reload | reload)
+-    	echo -n $"Reloading $prog: "
++	echo -n "Reloading $prog: "
+ 	killproc /usr/sbin/nscd -HUP
+ 	RETVAL=$?
+ 	echo
+ 	;;
+     *)
+-	echo $"Usage: $0 {start|stop|status|restart|reload|condrestart}"
++	echo "Usage: $0 {start|stop|status|restart|reload|condrestart}"
+ 	RETVAL=1
+ 	;;
+ esac

+ 616 - 0
recipes-core/glibc/glibc/0019-eglibc-Cross-building-and-testing-instructions.patch

@@ -0,0 +1,616 @@
+From db9674ffc6583a508da1a3cb044c3ccf3febaea1 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:42:58 +0000
+Subject: [PATCH] eglibc: Cross building and testing instructions
+
+Ported from eglibc
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ GLIBC.cross-building | 383 +++++++++++++++++++++++++++++++++++++++++++
+ GLIBC.cross-testing  | 205 +++++++++++++++++++++++
+ 2 files changed, 588 insertions(+)
+ create mode 100644 GLIBC.cross-building
+ create mode 100644 GLIBC.cross-testing
+
+diff --git a/GLIBC.cross-building b/GLIBC.cross-building
+new file mode 100644
+index 0000000000..e6e0da1aaf
+--- /dev/null
++++ b/GLIBC.cross-building
+@@ -0,0 +1,383 @@
++                                                        -*- mode: text -*-
++
++                        Cross-Compiling GLIBC
++                  Jim Blandy <jimb@codesourcery.com>
++
++
++Introduction
++
++Most GNU tools have a simple build procedure: you run their
++'configure' script, and then you run 'make'.  Unfortunately, the
++process of cross-compiling the GNU C library is quite a bit more
++involved:
++
++1) Build a cross-compiler, with certain facilities disabled.
++
++2) Configure the C library using the compiler you built in step 1).
++   Build a few of the C run-time object files, but not the rest of the
++   library.  Install the library's header files and the run-time
++   object files, and create a dummy libc.so.
++
++3) Build a second cross-compiler, using the header files and object
++   files you installed in step 2.
++
++4) Configure, build, and install a fresh C library, using the compiler
++   built in step 3.
++
++5) Build a third cross-compiler, based on the C library built in step 4.
++
++The reason for this complexity is that, although GCC and the GNU C
++library are distributed separately, they are not actually independent
++of each other: GCC requires the C library's headers and some object
++files to compile its own libraries, while the C library depends on
++GCC's libraries.  GLIBC includes features and bug fixes to the stock
++GNU C library that simplify this process, but the fundamental
++interdependency stands.
++
++In this document, we explain how to cross-compile an GLIBC/GCC pair
++from source.  Our intended audience is developers who are already
++familiar with the GNU toolchain and comfortable working with
++cross-development tools.  While we do present a worked example to
++accompany the explanation, for clarity's sake we do not cover many of
++the options available to cross-toolchain users.
++
++
++Preparation
++
++GLIBC requires recent versions of the GNU binutils, GCC, and the
++Linux kernel.  The web page <http://www.eglibc.org/prerequisites>
++documents the current requirements, and lists patches needed for
++certain target architectures.  As of this writing, these build
++instructions have been tested with binutils 2.22.51, GCC 4.6.2,
++and Linux 3.1.
++
++First, let's set some variables, to simplify later commands.  We'll
++build GLIBC and GCC for an ARM target, known to the Linux kernel
++as 'arm', and we'll do the build on an Intel x86_64 Linux box:
++
++    $ build=x86_64-pc-linux-gnu
++    $ host=$build
++    $ target=arm-none-linux-gnueabi
++    $ linux_arch=arm
++
++We're using the aforementioned versions of Binutils, GCC, and Linux:
++
++    $ binutilsv=binutils-2.22.51
++    $ gccv=gcc-4.6.2
++    $ linuxv=linux-3.1
++
++We're carrying out the entire process under '~/cross-build', which
++contains unpacked source trees for binutils, gcc, and linux kernel,
++along with GLIBC svn trunk (which can be checked-out with
++'svn co http://www.eglibc.org/svn/trunk eglibc'):
++
++    $ top=$HOME/cross-build/$target
++    $ src=$HOME/cross-build/src
++    $ ls $src
++    binutils-2.22.51  glibc  gcc-4.6.2  linux-3.1
++
++We're going to place our build directories in a subdirectory 'obj',
++we'll install the cross-development toolchain in 'tools', and we'll
++place our sysroot (containing files to be installed on the target
++system) in 'sysroot':
++
++    $ obj=$top/obj
++    $ tools=$top/tools
++    $ sysroot=$top/sysroot
++
++
++Binutils
++
++Configuring and building binutils for the target is straightforward:
++
++    $ mkdir -p $obj/binutils
++    $ cd $obj/binutils
++    $ $src/$binutilsv/configure \
++    >     --target=$target \
++    >     --prefix=$tools \
++    >     --with-sysroot=$sysroot
++    $ make
++    $ make install
++
++
++The First GCC
++
++For our work, we need a cross-compiler targeting an ARM Linux
++system.  However, that configuration includes the shared library
++'libgcc_s.so', which is compiled against the GLIBC headers (which we
++haven't installed yet) and linked against 'libc.so' (which we haven't
++built yet).
++
++Fortunately, there are configuration options for GCC which tell it not
++to build 'libgcc_s.so'.  The '--without-headers' option is supposed to
++take care of this, but its implementation is incomplete, so you must
++also configure with the '--with-newlib' option.  While '--with-newlib'
++appears to mean "Use the Newlib C library", its effect is to tell the
++GCC build machinery, "Don't assume there is a C library available."
++
++We also need to disable some of the libraries that would normally be
++built along with GCC, and specify that only the compiler for the C
++language is needed.
++
++So, we create a build directory, configure, make, and install.
++
++    $ mkdir -p $obj/gcc1
++    $ cd $obj/gcc1
++    $ $src/$gccv/configure \
++    >     --target=$target \
++    >     --prefix=$tools \
++    >     --without-headers --with-newlib \
++    >     --disable-shared --disable-threads --disable-libssp \
++    >     --disable-libgomp --disable-libmudflap --disable-libquadmath \
++    >     --disable-decimal-float --disable-libffi \
++    >     --enable-languages=c
++    $ PATH=$tools/bin:$PATH make
++    $ PATH=$tools/bin:$PATH make install
++
++
++Linux Kernel Headers
++
++To configure GLIBC, we also need Linux kernel headers in place.
++Fortunately, the Linux makefiles have a target that installs them for
++us.  Since the process does modify the source tree a bit, we make a
++copy first:
++
++    $ cp -r $src/$linuxv $obj/linux
++    $ cd $obj/linux
++
++Now we're ready to install the headers into the sysroot:
++
++    $ PATH=$tools/bin:$PATH \
++    > make headers_install \
++    >      ARCH=$linux_arch CROSS_COMPILE=$target- \
++    >      INSTALL_HDR_PATH=$sysroot/usr
++
++
++GLIBC Headers and Preliminary Objects
++
++Using the cross-compiler we've just built, we can now configure GLIBC
++well enough to install the headers and build the object files that the
++full cross-compiler will need:
++
++    $ mkdir -p $obj/glibc-headers
++    $ cd $obj/glibc-headers
++    $ BUILD_CC=gcc \
++    > CC=$tools/bin/$target-gcc \
++    > CXX=$tools/bin/$target-g++ \
++    > AR=$tools/bin/$target-ar \
++    > RANLIB=$tools/bin/$target-ranlib \
++    > $src/glibc/libc/configure \
++    >     --prefix=/usr \
++    >     --with-headers=$sysroot/usr/include \
++    >     --build=$build \
++    >     --host=$target \
++    >     --disable-profile --without-gd --without-cvs \
++    >     --enable-add-ons=nptl,libidn,../ports
++
++The option '--prefix=/usr' may look strange, but you should never
++configure GLIBC with a prefix other than '/usr': in various places,
++GLIBC's build system checks whether the prefix is '/usr', and does
++special handling only if that is the case.  Unless you use this
++prefix, you will get a sysroot that does not use the standard Linux
++directory layouts and cannot be used as a basis for the root
++filesystem on your target system compatibly with normal GLIBC
++installations.
++
++The '--with-headers' option tells GLIBC where the Linux headers have
++been installed.
++
++The '--enable-add-ons=nptl,libidn,../ports' option tells GLIBC to look
++for the listed glibc add-ons. Most notably the ports add-on (located
++just above the libc sources in the GLIBC svn tree) is required to
++support ARM targets.
++
++We can now use the 'install-headers' makefile target to install the
++headers:
++
++    $ make install-headers install_root=$sysroot \
++    >                      install-bootstrap-headers=yes
++
++The 'install_root' variable indicates where the files should actually
++be installed; its value is treated as the parent of the '--prefix'
++directory we passed to the configure script, so the headers will go in
++'$sysroot/usr/include'.  The 'install-bootstrap-headers' variable
++requests special handling for certain tricky header files.
++
++Next, there are a few object files needed to link shared libraries,
++which we build and install by hand:
++
++    $ mkdir -p $sysroot/usr/lib
++    $ make csu/subdir_lib
++    $ cp csu/crt1.o csu/crti.o csu/crtn.o $sysroot/usr/lib
++
++Finally, 'libgcc_s.so' requires a 'libc.so' to link against.  However,
++since we will never actually execute its code, it doesn't matter what
++it contains.  So, treating '/dev/null' as a C source file, we produce
++a dummy 'libc.so' in one step:
++
++    $ $tools/bin/$target-gcc -nostdlib -nostartfiles -shared -x c /dev/null \
++    >                        -o $sysroot/usr/lib/libc.so
++
++
++The Second GCC
++
++With the GLIBC headers and selected object files installed, we can
++now build a GCC that is capable of compiling GLIBC.  We configure,
++build, and install the second GCC, again building only the C compiler,
++and avoiding libraries we won't use:
++
++    $ mkdir -p $obj/gcc2
++    $ cd $obj/gcc2
++    $ $src/$gccv/configure \
++    >     --target=$target \
++    >     --prefix=$tools \
++    >     --with-sysroot=$sysroot \
++    >     --disable-libssp --disable-libgomp --disable-libmudflap \
++    >     --disable-libffi --disable-libquadmath \
++    >     --enable-languages=c
++    $ PATH=$tools/bin:$PATH make
++    $ PATH=$tools/bin:$PATH make install
++
++
++GLIBC, Complete
++
++With the second compiler built and installed, we're now ready for the
++full GLIBC build:
++
++    $ mkdir -p $obj/glibc
++    $ cd $obj/glibc
++    $ BUILD_CC=gcc \
++    > CC=$tools/bin/$target-gcc \
++    > CXX=$tools/bin/$target-g++ \
++    > AR=$tools/bin/$target-ar \
++    > RANLIB=$tools/bin/$target-ranlib \
++    > $src/glibc/libc/configure \
++    >     --prefix=/usr \
++    >     --with-headers=$sysroot/usr/include \
++    >     --with-kconfig=$obj/linux/scripts/kconfig \
++    >     --build=$build \
++    >     --host=$target \
++    >     --disable-profile --without-gd --without-cvs \
++    >     --enable-add-ons=nptl,libidn,../ports
++
++Note the additional '--with-kconfig' option. This tells GLIBC where to
++find the host config tools used by the kernel 'make config' and 'make
++menuconfig'.  These tools can be re-used by GLIBC for its own 'make
++*config' support, which will create 'option-groups.config' for you.
++But first make sure those tools have been built by running some
++dummy 'make *config' calls in the kernel directory:
++
++    $ cd $obj/linux
++    $ PATH=$tools/bin:$PATH make config \
++    >      ARCH=$linux_arch CROSS_COMPILE=$target- \
++    $ PATH=$tools/bin:$PATH make menuconfig \
++    >      ARCH=$linux_arch CROSS_COMPILE=$target- \
++
++Now we can configure and build the full GLIBC:
++
++    $ cd $obj/glibc
++    $ PATH=$tools/bin:$PATH make defconfig
++    $ PATH=$tools/bin:$PATH make menuconfig
++    $ PATH=$tools/bin:$PATH make
++    $ PATH=$tools/bin:$PATH make install install_root=$sysroot
++
++At this point, we have a complete GLIBC installation in '$sysroot',
++with header files, library files, and most of the C runtime startup
++files in place.
++
++
++The Third GCC
++
++Finally, we recompile GCC against this full installation, enabling
++whatever languages and libraries we would like to use:
++
++    $ mkdir -p $obj/gcc3
++    $ cd $obj/gcc3
++    $ $src/$gccv/configure \
++    >     --target=$target \
++    >     --prefix=$tools \
++    >     --with-sysroot=$sysroot \
++    >     --enable-__cxa_atexit \
++    >     --disable-libssp --disable-libgomp --disable-libmudflap \
++    >     --enable-languages=c,c++
++    $ PATH=$tools/bin:$PATH make
++    $ PATH=$tools/bin:$PATH make install
++
++The '--enable-__cxa_atexit' option tells GCC what sort of C++
++destructor support to expect from the C library; it's required with
++GLIBC.
++
++And since GCC's installation process isn't designed to help construct
++sysroot trees, we must manually copy certain libraries into place in
++the sysroot.
++
++    $ cp -d $tools/$target/lib/libgcc_s.so* $sysroot/lib
++    $ cp -d $tools/$target/lib/libstdc++.so* $sysroot/usr/lib
++
++
++Trying Things Out
++
++At this point, '$tools' contains a cross toolchain ready to use
++the GLIBC installation in '$sysroot':
++
++    $ cat > hello.c <<EOF
++    > #include <stdio.h>
++    > int
++    > main (int argc, char **argv)
++    > {
++    >   puts ("Hello, world!");
++    >   return 0;
++    > }
++    > EOF
++    $ $tools/bin/$target-gcc -Wall hello.c -o hello
++    $ cat > c++-hello.cc <<EOF
++    > #include <iostream>
++    > int
++    > main (int argc, char **argv)
++    > {
++    >   std::cout << "Hello, C++ world!" << std::endl;
++    >   return 0;
++    > }
++    > EOF
++    $ $tools/bin/$target-g++ -Wall c++-hello.cc -o c++-hello
++
++
++We can use 'readelf' to verify that these are indeed executables for
++our target, using our dynamic linker:
++
++    $ $tools/bin/$target-readelf -hl hello
++    ELF Header:
++    ...
++      Type:                              EXEC (Executable file)
++      Machine:                           ARM
++
++    ...
++    Program Headers:
++      Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
++      PHDR           0x000034 0x10000034 0x10000034 0x00100 0x00100 R E 0x4
++      INTERP         0x000134 0x00008134 0x00008134 0x00013 0x00013 R   0x1
++          [Requesting program interpreter: /lib/ld-linux.so.3]
++      LOAD           0x000000 0x00008000 0x00008000 0x0042c 0x0042c R E 0x8000
++    ...
++
++Looking at the dynamic section of the installed 'libgcc_s.so', we see
++that the 'NEEDED' entry for the C library does include the '.6'
++suffix, indicating that was linked against our fully build GLIBC, and
++not our dummy 'libc.so':
++
++    $ $tools/bin/$target-readelf -d $sysroot/lib/libgcc_s.so.1
++    Dynamic section at offset 0x1083c contains 24 entries:
++      Tag        Type                         Name/Value
++     0x00000001 (NEEDED)                     Shared library: [libc.so.6]
++     0x0000000e (SONAME)                     Library soname: [libgcc_s.so.1]
++    ...
++
++
++And on the target machine, we can run our programs:
++
++    $ $sysroot/lib/ld.so.1 --library-path $sysroot/lib:$sysroot/usr/lib \
++    > ./hello
++    Hello, world!
++    $ $sysroot/lib/ld.so.1 --library-path $sysroot/lib:$sysroot/usr/lib \
++    > ./c++-hello
++    Hello, C++ world!
+diff --git a/GLIBC.cross-testing b/GLIBC.cross-testing
+new file mode 100644
+index 0000000000..b67b468466
+--- /dev/null
++++ b/GLIBC.cross-testing
+@@ -0,0 +1,205 @@
++                                                        -*- mode: text -*-
++
++                      Cross-Testing With GLIBC
++                  Jim Blandy <jimb@codesourcery.com>
++
++
++Introduction
++
++Developers writing software for embedded systems often use a desktop
++or other similarly capable computer for development, but need to run
++tests on the embedded system, or perhaps on a simulator.  When
++configured for cross-compilation, the stock GNU C library simply
++disables running tests altogether: the command 'make tests' builds
++test programs, but does not run them.  GLIBC, however, provides
++facilities for compiling tests and generating data files on the build
++system, but running the test programs themselves on a remote system or
++simulator.
++
++
++Test environment requirements
++
++The test environment must meet certain conditions for GLIBC's
++cross-testing facilities to work:
++
++- Shared filesystems.  The 'build' system, on which you configure and
++  compile GLIBC, and the 'host' system, on which you intend to run
++  GLIBC, must share a filesystem containing the GLIBC build and
++  source trees.  Files must appear at the same paths on both systems.
++
++- Remote-shell like invocation.  There must be a way to run a program
++  on the host system from the build system, passing it properly quoted
++  command-line arguments, setting environment variables, and
++  inheriting the caller's standard input and output.
++
++
++Usage
++
++To use GLIBC's cross-testing support, provide values for the
++following Make variables when you invoke 'make':
++
++- cross-test-wrapper
++
++  This should be the name of the cross-testing wrapper command, along
++  with any arguments.
++
++- cross-localedef
++
++  This should be the name of a cross-capable localedef program, like
++  that included in the GLIBC 'localedef' module, along with any
++  arguments needed.
++
++These are each explained in detail below.
++
++
++The Cross-Testing Wrapper
++
++To run test programs reliably, the stock GNU C library takes care to
++ensure that test programs use the newly compiled dynamic linker and
++shared libraries, and never the host system's installed libraries.  To
++accomplish this, it runs the tests by explicitly invoking the dynamic
++linker from the build tree, passing it a list of build tree
++directories to search for shared libraries, followed by the name of
++the executable to run and its arguments.
++
++For example, where one might normally run a test program like this:
++
++    $ ./tst-foo arg1 arg2
++
++the GNU C library might run that program like this:
++
++    $ $objdir/elf/ld-linux.so.3 --library-path $objdir \
++      ./tst-foo arg1 arg2
++
++(where $objdir is the path to the top of the build tree, and the
++trailing backslash indicates a continuation of the command).  In other
++words, each test program invocation is 'wrapped up' inside an explicit
++invocation of the dynamic linker, which must itself execute the test
++program, having loaded shared libraries from the appropriate
++directories.
++
++To support cross-testing, GLIBC allows the developer to optionally
++set the 'cross-test-wrapper' Make variable to another wrapper command,
++to which it passes the entire dynamic linker invocation shown above as
++arguments.  For example, if the developer supplies a wrapper of
++'my-wrapper hostname', then GLIBC would run the test above as
++follows:
++
++    $ my-wrapper hostname \
++      $objdir/elf/ld-linux.so.3 --library-path $objdir \
++      ./tst-foo arg1 arg2
++
++The 'my-wrapper' command is responsible for executing the command
++given on the host system.
++
++Since tests are run in varying directories, the wrapper should either
++be in your command search path, or 'cross-test-wrapper' should give an
++absolute path for the wrapper.
++
++The wrapper must meet several requirements:
++
++- It must preserve the current directory.  As explained above, the
++  build directory tree must be visible on both the build and host
++  systems, at the same path.  The test wrapper must ensure that the
++  current directory it inherits is also inherited by the dynamic
++  linker (and thus the test program itself).
++
++- It must preserve environment variables' values.  Many GLIBC tests
++  set environment variables for test runs; in native testing, it
++  invokes programs like this:
++
++    $ GCONV_PATH=$objdir/iconvdata \
++      $objdir/elf/ld-linux.so.3 --library-path $objdir \
++      ./tst-foo arg1 arg2
++
++  With the cross-testing wrapper, that invocation becomes:
++
++    $ GCONV_PATH=$objdir/iconvdata \
++      my-wrapper hostname \
++      $objdir/elf/ld-linux.so.3 --library-path $objdir \
++      ./tst-foo arg1 arg2
++
++  Here, 'my-wrapper' must ensure that the value it sees for
++  'GCONV_PATH' will be seen by the dynamic linker, and thus 'tst-foo'
++  itself.  (The wrapper supplied with GLIBC simply preserves the
++  values of *all* enviroment variables, with a fixed set of
++  exceptions.)
++
++  If your wrapper is a shell script, take care to correctly propagate
++  environment variables whose values contain spaces and shell
++  metacharacters.
++
++- It must pass the command's arguments, unmodified.  The arguments
++  seen by the test program should be exactly those seen by the wrapper
++  (after whatever arguments are given to the wrapper itself).  The
++  GLIBC test framework performs all needed shell word splitting and
++  expansion (wildcard expansion, parameter substitution, and so on)
++  before invoking the wrapper; further expansion may break the tests.
++
++
++The 'cross-test-ssh.sh' script
++
++If you want to use 'ssh' (or something sufficiently similar) to run
++test programs on your host system, GLIBC includes a shell script,
++'scripts/cross-test-ssh.sh', which you can use as your wrapper
++command.  This script takes care of setting the test command's current
++directory, propagating environment variable values, and carrying
++command-line arguments, all across an 'ssh' connection.  You may even
++supply an alternative to 'ssh' on the command line, if needed.
++
++For more details, pass 'cross-test-ssh.sh' the '--help' option.
++
++
++The Cross-Compiling Locale Definition Command
++
++Some GLIBC tests rely on locales generated especially for the test
++process.  In a native configuration, these tests simply run the
++'localedef' command built by the normal GLIBC build process,
++'locale/localedef', to process and install their locales.  However, in
++a cross-compiling configuration, this 'localedef' is built for the
++host system, not the build system, and since it requires quite a bit
++of memory to run (we have seen it fail on systems with 64MiB of
++memory), it may not be practical to run it on the host system.
++
++If set, GLIBC uses the 'cross-localedef' Make variable as the command
++to run on the build system to process and install locales.  The
++localedef program built from the GLIBC 'localedef' module is
++suitable.
++
++The value of 'cross-localedef' may also include command-line arguments
++to be passed to the program; if you are using GLIBC's 'localedef',
++you may include endianness and 'uint32_t' alignment arguments here.
++
++
++Example
++
++In developing GLIBC's cross-testing facility, we invoked 'make' with
++the following script:
++
++    #!/bin/sh
++
++    srcdir=...
++    test_hostname=...
++    localedefdir=...
++    cross_gxx=...-g++
++
++    wrapper="$srcdir/scripts/cross-test-ssh.sh $test_hostname"
++    localedef="$localedefdir/localedef --little-endian --uint32-align=4"
++
++    make cross-test-wrapper="$wrapper" \
++         cross-localedef="$localedef" \
++         CXX="$cross_gxx" \
++         "$@"
++
++
++Other Cross-Testing Concerns
++
++Here are notes on some other issues which you may encounter in running
++the GLIBC tests in a cross-compiling environment:
++
++- Some tests require a C++ cross-compiler; you should set the 'CXX'
++  Make variable to the name of an appropriate cross-compiler.
++
++- Some tests require access to libstdc++.so.6 and libgcc_s.so.1; we
++  simply place copies of these libraries in the top GLIBC build
++  directory.

+ 97 - 0
recipes-core/glibc/glibc/0020-eglibc-Help-bootstrap-cross-toolchain.patch

@@ -0,0 +1,97 @@
+From 7856684f76c100155cad11b5b236fb31234b6e28 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:49:28 +0000
+Subject: [PATCH] eglibc: Help bootstrap cross toolchain
+
+Taken from EGLIBC, r1484 + r1525
+
+        2007-02-20  Jim Blandy  <jimb@codesourcery.com>
+
+                * Makefile (install-headers): Preserve old behavior: depend on
+                $(inst_includedir)/gnu/stubs.h only if install-bootstrap-headers
+                is set; otherwise, place gnu/stubs.h on the 'install-others' list.
+
+        2007-02-16  Jim Blandy  <jimb@codesourcery.com>
+
+                * Makefile: Amend make install-headers to install everything
+                necessary for building a cross-compiler.  Install gnu/stubs.h as
+                part of 'install-headers', not 'install-others'.
+                If install-bootstrap-headers is 'yes', install a dummy copy of
+                gnu/stubs.h, instead of computing the real thing.
+                * include/stubs-bootstrap.h: New file.
+
+Upstream-Status: Pending
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ Makefile                  | 22 +++++++++++++++++++++-
+ include/stubs-bootstrap.h | 12 ++++++++++++
+ 2 files changed, 33 insertions(+), 1 deletion(-)
+ create mode 100644 include/stubs-bootstrap.h
+
+diff --git a/Makefile b/Makefile
+index f98d5a9e67..c36d04da0f 100644
+--- a/Makefile
++++ b/Makefile
+@@ -79,9 +79,18 @@ subdir-dirs = include
+ vpath %.h $(subdir-dirs)
+ 
+ # What to install.
+-install-others = $(inst_includedir)/gnu/stubs.h
+ install-bin-script =
+ 
++# If we're bootstrapping, install a dummy gnu/stubs.h along with the
++# other headers, so 'make install-headers' produces a useable include
++# tree.  Otherwise, install gnu/stubs.h later, after the rest of the
++# build is done.
++ifeq ($(install-bootstrap-headers),yes)
++install-headers: $(inst_includedir)/gnu/stubs.h
++else
++install-others = $(inst_includedir)/gnu/stubs.h
++endif
++
+ ifeq (yes,$(build-shared))
+ headers += gnu/lib-names.h
+ endif
+@@ -415,6 +424,16 @@ others: $(common-objpfx)testrun.sh $(common-objpfx)debugglibc.sh
+ 
+ subdir-stubs := $(foreach dir,$(subdirs),$(common-objpfx)$(dir)/stubs)
+ 
++# gnu/stubs.h depends (via the subdir 'stubs' targets) on all the .o
++# files in EGLIBC.  For bootstrapping a GCC/EGLIBC pair, an empty
++# gnu/stubs.h is good enough.
++ifeq ($(install-bootstrap-headers),yes)
++$(inst_includedir)/gnu/stubs.h: include/stubs-bootstrap.h $(+force)
++	$(make-target-directory)
++	$(INSTALL_DATA) $< $@
++
++installed-stubs =
++else
+ ifndef abi-variants
+ installed-stubs = $(inst_includedir)/gnu/stubs.h
+ else
+@@ -441,6 +460,7 @@ $(inst_includedir)/gnu/stubs.h: $(+force)
+ 
+ install-others-nosubdir: $(installed-stubs)
+ endif
++endif
+ 
+ 
+ # Since stubs.h is never needed when building the library, we simplify the
+diff --git a/include/stubs-bootstrap.h b/include/stubs-bootstrap.h
+new file mode 100644
+index 0000000000..1d2b669aff
+--- /dev/null
++++ b/include/stubs-bootstrap.h
+@@ -0,0 +1,12 @@
++/* Placeholder stubs.h file for bootstrapping.
++
++   When bootstrapping a GCC/EGLIBC pair, GCC requires that the EGLIBC
++   headers be installed, but we can't fully build EGLIBC without that
++   GCC.  So we run the command:
++
++      make install-headers install-bootstrap-headers=yes
++
++   to install the headers GCC needs, but avoid building certain
++   difficult headers.  The <gnu/stubs.h> header depends, via the
++   EGLIBC subdir 'stubs' make targets, on every .o file in EGLIBC, but
++   an empty stubs.h like this will do fine for GCC.  */

+ 53 - 0
recipes-core/glibc/glibc/0021-eglibc-Resolve-__fpscr_values-on-SH4.patch

@@ -0,0 +1,53 @@
+From 111ab95a85314d1e70fb159a14250354cc69d899 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:55:53 +0000
+Subject: [PATCH] eglibc: Resolve __fpscr_values on SH4
+
+2010-09-29  Nobuhiro Iwamatsu  <iwamatsu@nigauri.org>
+            Andrew Stubbs  <ams@codesourcery.com>
+
+        Resolve SH's __fpscr_values to symbol in libc.so.
+
+        * sysdeps/sh/sh4/fpu/fpu_control.h: Add C++ __set_fpscr prototype.
+        * sysdeps/unix/sysv/linux/sh/Versions (GLIBC_2.2): Add __fpscr_values.
+        * sysdeps/unix/sysv/linux/sh/sysdep.S (___fpscr_values): New constant.
+
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/unix/sysv/linux/sh/Versions |  1 +
+ sysdeps/unix/sysv/linux/sh/sysdep.S | 11 +++++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/sysdeps/unix/sysv/linux/sh/Versions b/sysdeps/unix/sysv/linux/sh/Versions
+index 9c734ff755..974e33b4b1 100644
+--- a/sysdeps/unix/sysv/linux/sh/Versions
++++ b/sysdeps/unix/sysv/linux/sh/Versions
+@@ -3,6 +3,7 @@ libc {
+   GLIBC_2.2 {
+     # functions used in other libraries
+     __xstat64; __fxstat64; __lxstat64;
++    __fpscr_values;
+ 
+     # a*
+     alphasort64;
+diff --git a/sysdeps/unix/sysv/linux/sh/sysdep.S b/sysdeps/unix/sysv/linux/sh/sysdep.S
+index a18fbb2e8b..59421bfbb0 100644
+--- a/sysdeps/unix/sysv/linux/sh/sysdep.S
++++ b/sysdeps/unix/sysv/linux/sh/sysdep.S
+@@ -30,3 +30,14 @@ ENTRY (__syscall_error)
+ 
+ #define __syscall_error __syscall_error_1
+ #include <sysdeps/unix/sh/sysdep.S>
++
++       .data
++       .align 3
++       .globl ___fpscr_values
++       .type ___fpscr_values, @object
++       .size ___fpscr_values, 8
++___fpscr_values:
++       .long 0
++       .long 0x80000
++weak_alias (___fpscr_values, __fpscr_values)
++

+ 560 - 0
recipes-core/glibc/glibc/0022-eglibc-Forward-port-cross-locale-generation-support.patch

@@ -0,0 +1,560 @@
+From 4e5de801a39d66b8bd93d09f5912dcbe5db4ef04 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 01:33:49 +0000
+Subject: [PATCH] eglibc: Forward port cross locale generation support
+
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ locale/Makefile               |  3 +-
+ locale/catnames.c             | 46 +++++++++++++++++++++++++++
+ locale/localeinfo.h           |  2 +-
+ locale/programs/charmap-dir.c |  6 ++++
+ locale/programs/ld-collate.c  | 17 +++++-----
+ locale/programs/ld-ctype.c    | 27 ++++++++--------
+ locale/programs/ld-time.c     | 31 ++++++++++++------
+ locale/programs/linereader.c  |  2 +-
+ locale/programs/localedef.c   |  8 +++++
+ locale/programs/locfile.c     |  5 ++-
+ locale/programs/locfile.h     | 59 +++++++++++++++++++++++++++++++++--
+ locale/setlocale.c            | 29 -----------------
+ 12 files changed, 167 insertions(+), 68 deletions(-)
+ create mode 100644 locale/catnames.c
+
+diff --git a/locale/Makefile b/locale/Makefile
+index b7c60681fa..07c606cde3 100644
+--- a/locale/Makefile
++++ b/locale/Makefile
+@@ -26,7 +26,8 @@ headers		= langinfo.h locale.h bits/locale.h \
+ 		  bits/types/locale_t.h bits/types/__locale_t.h
+ routines	= setlocale findlocale loadlocale loadarchive \
+ 		  localeconv nl_langinfo nl_langinfo_l mb_cur_max \
+-		  newlocale duplocale freelocale uselocale
++		  newlocale duplocale freelocale uselocale \
++		  catnames
+ tests		= tst-C-locale tst-locname tst-duplocale
+ tests-container	= tst-localedef-path-norm
+ categories	= ctype messages monetary numeric time paper name \
+diff --git a/locale/catnames.c b/locale/catnames.c
+new file mode 100644
+index 0000000000..538f3f5edb
+--- /dev/null
++++ b/locale/catnames.c
+@@ -0,0 +1,46 @@
++/* Copyright (C) 2006  Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include "localeinfo.h"
++
++/* Define an array of category names (also the environment variable names).  */
++const struct catnamestr_t _nl_category_names attribute_hidden =
++  {
++#define DEFINE_CATEGORY(category, category_name, items, a) \
++    category_name,
++#include "categories.def"
++#undef DEFINE_CATEGORY
++  };
++
++const uint8_t _nl_category_name_idxs[__LC_LAST] attribute_hidden =
++  {
++#define DEFINE_CATEGORY(category, category_name, items, a) \
++    [category] = offsetof (struct catnamestr_t, CATNAMEMF (__LINE__)),
++#include "categories.def"
++#undef DEFINE_CATEGORY
++  };
++
++/* An array of their lengths, for convenience.  */
++const uint8_t _nl_category_name_sizes[] attribute_hidden =
++  {
++#define DEFINE_CATEGORY(category, category_name, items, a) \
++    [category] = sizeof (category_name) - 1,
++#include "categories.def"
++#undef	DEFINE_CATEGORY
++    [LC_ALL] = sizeof ("LC_ALL") - 1
++  };
+diff --git a/locale/localeinfo.h b/locale/localeinfo.h
+index 22f9dc1140..fa31b3c5ea 100644
+--- a/locale/localeinfo.h
++++ b/locale/localeinfo.h
+@@ -230,7 +230,7 @@ __libc_tsd_define (extern, locale_t, LOCALE)
+    unused.  We can manage this playing some tricks with weak references.
+    But with thread-local locale settings, it becomes quite ungainly unless
+    we can use __thread variables.  So only in that case do we attempt this.  */
+-#ifndef SHARED
++#if !defined SHARED && !defined IN_GLIBC_LOCALEDEF
+ # include <tls.h>
+ # define NL_CURRENT_INDIRECT	1
+ #endif
+diff --git a/locale/programs/charmap-dir.c b/locale/programs/charmap-dir.c
+index 4841bfd05d..ffcba1fd79 100644
+--- a/locale/programs/charmap-dir.c
++++ b/locale/programs/charmap-dir.c
+@@ -18,7 +18,9 @@
+ #include <errno.h>
+ #include <fcntl.h>
+ #include <libintl.h>
++#ifndef NO_UNCOMPRESS
+ #include <spawn.h>
++#endif
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+@@ -154,6 +156,7 @@ charmap_closedir (CHARMAP_DIR *cdir)
+   return closedir (dir);
+ }
+ 
++#ifndef NO_UNCOMPRESS
+ /* Creates a subprocess decompressing the given pathname, and returns
+    a stream reading its output (the decompressed data).  */
+ static
+@@ -202,6 +205,7 @@ fopen_uncompressed (const char *pathname, const char *compressor)
+     }
+   return NULL;
+ }
++#endif
+ 
+ /* Opens a charmap for reading, given its name (not an alias name).  */
+ FILE *
+@@ -224,6 +228,7 @@ charmap_open (const char *directory, const char *name)
+   if (stream != NULL)
+     return stream;
+ 
++#ifndef NO_UNCOMPRESS
+   memcpy (p, ".gz", 4);
+   stream = fopen_uncompressed (pathname, "gzip");
+   if (stream != NULL)
+@@ -233,6 +238,7 @@ charmap_open (const char *directory, const char *name)
+   stream = fopen_uncompressed (pathname, "bzip2");
+   if (stream != NULL)
+     return stream;
++#endif
+ 
+   return NULL;
+ }
+diff --git a/locale/programs/ld-collate.c b/locale/programs/ld-collate.c
+index b6406b775d..bfa4adba9c 100644
+--- a/locale/programs/ld-collate.c
++++ b/locale/programs/ld-collate.c
+@@ -349,7 +349,7 @@ new_element (struct locale_collate_t *collate, const char *mbs, size_t mbslen,
+     }
+   if (wcs != NULL)
+     {
+-      size_t nwcs = wcslen ((wchar_t *) wcs);
++      size_t nwcs = wcslen_uint32 (wcs);
+       uint32_t zero = 0;
+       /* Handle <U0000> as a single character.  */
+       if (nwcs == 0)
+@@ -1775,8 +1775,7 @@ symbol `%s' has the same encoding as"), (*eptr)->name);
+ 
+ 	      if ((*eptr)->nwcs == runp->nwcs)
+ 		{
+-		  int c = wmemcmp ((wchar_t *) (*eptr)->wcs,
+-				   (wchar_t *) runp->wcs, runp->nwcs);
++		  int c = wmemcmp_uint32 ((*eptr)->wcs, runp->wcs, runp->nwcs);
+ 
+ 		  if (c == 0)
+ 		    {
+@@ -2003,9 +2002,9 @@ add_to_tablewc (uint32_t ch, struct element_t *runp)
+ 	     one consecutive entry.  */
+ 	  if (runp->wcnext != NULL
+ 	      && runp->nwcs == runp->wcnext->nwcs
+-	      && wmemcmp ((wchar_t *) runp->wcs,
+-			  (wchar_t *)runp->wcnext->wcs,
+-			  runp->nwcs - 1) == 0
++	      && wmemcmp_uint32 (runp->wcs,
++				 runp->wcnext->wcs,
++				 runp->nwcs - 1) == 0
+ 	      && (runp->wcs[runp->nwcs - 1]
+ 		  == runp->wcnext->wcs[runp->nwcs - 1] + 1))
+ 	    {
+@@ -2029,9 +2028,9 @@ add_to_tablewc (uint32_t ch, struct element_t *runp)
+ 		runp = runp->wcnext;
+ 	      while (runp->wcnext != NULL
+ 		     && runp->nwcs == runp->wcnext->nwcs
+-		     && wmemcmp ((wchar_t *) runp->wcs,
+-				 (wchar_t *)runp->wcnext->wcs,
+-				 runp->nwcs - 1) == 0
++		     && wmemcmp_uint32 (runp->wcs,
++					runp->wcnext->wcs,
++					runp->nwcs - 1) == 0
+ 		     && (runp->wcs[runp->nwcs - 1]
+ 			 == runp->wcnext->wcs[runp->nwcs - 1] + 1));
+ 
+diff --git a/locale/programs/ld-ctype.c b/locale/programs/ld-ctype.c
+index 2fb579bbbf..d0be99581c 100644
+--- a/locale/programs/ld-ctype.c
++++ b/locale/programs/ld-ctype.c
+@@ -915,7 +915,7 @@ ctype_output (struct localedef_t *locale, const struct charmap_t *charmap,
+   allocate_arrays (ctype, charmap, ctype->repertoire);
+ 
+   default_missing_len = (ctype->default_missing
+-			 ? wcslen ((wchar_t *) ctype->default_missing)
++			 ? wcslen_uint32 (ctype->default_missing)
+ 			 : 0);
+ 
+   init_locale_data (&file, nelems);
+@@ -1927,7 +1927,7 @@ read_translit_entry (struct linereader *ldfile, struct locale_ctype_t *ctype,
+ 	    ignore = 1;
+ 	  else
+ 	    /* This value is usable.  */
+-	    obstack_grow (ob, to_wstr, wcslen ((wchar_t *) to_wstr) * 4);
++	    obstack_grow (ob, to_wstr, wcslen_uint32 (to_wstr) * 4);
+ 
+ 	  first = 0;
+ 	}
+@@ -2461,8 +2461,8 @@ with character code range values one must use the absolute ellipsis `...'"));
+ 	    }
+ 
+ 	handle_tok_digit:
+-	  class_bit = _ISwdigit;
+-	  class256_bit = _ISdigit;
++	  class_bit = BITw (tok_digit);
++	  class256_bit = BIT (tok_digit);
+ 	  handle_digits = 1;
+ 	  goto read_charclass;
+ 
+@@ -3904,8 +3904,7 @@ allocate_arrays (struct locale_ctype_t *ctype, const struct charmap_t *charmap,
+ 
+ 	  while (idx < number)
+ 	    {
+-	      int res = wcscmp ((const wchar_t *) sorted[idx]->from,
+-				(const wchar_t *) runp->from);
++	      int res = wcscmp_uint32 (sorted[idx]->from, runp->from);
+ 	      if (res == 0)
+ 		{
+ 		  replace = 1;
+@@ -3942,11 +3941,11 @@ allocate_arrays (struct locale_ctype_t *ctype, const struct charmap_t *charmap,
+       for (size_t cnt = 0; cnt < number; ++cnt)
+ 	{
+ 	  struct translit_to_t *srunp;
+-	  from_len += wcslen ((const wchar_t *) sorted[cnt]->from) + 1;
++	  from_len += wcslen_uint32 (sorted[cnt]->from) + 1;
+ 	  srunp = sorted[cnt]->to;
+ 	  while (srunp != NULL)
+ 	    {
+-	      to_len += wcslen ((const wchar_t *) srunp->str) + 1;
++	      to_len += wcslen_uint32 (srunp->str) + 1;
+ 	      srunp = srunp->next;
+ 	    }
+ 	  /* Plus one for the extra NUL character marking the end of
+@@ -3970,18 +3969,18 @@ allocate_arrays (struct locale_ctype_t *ctype, const struct charmap_t *charmap,
+ 	  ctype->translit_from_idx[cnt] = from_len;
+ 	  ctype->translit_to_idx[cnt] = to_len;
+ 
+-	  len = wcslen ((const wchar_t *) sorted[cnt]->from) + 1;
+-	  wmemcpy ((wchar_t *) &ctype->translit_from_tbl[from_len],
+-		   (const wchar_t *) sorted[cnt]->from, len);
++	  len = wcslen_uint32 (sorted[cnt]->from) + 1;
++	  wmemcpy_uint32 (&ctype->translit_from_tbl[from_len],
++			  sorted[cnt]->from, len);
+ 	  from_len += len;
+ 
+ 	  ctype->translit_to_idx[cnt] = to_len;
+ 	  srunp = sorted[cnt]->to;
+ 	  while (srunp != NULL)
+ 	    {
+-	      len = wcslen ((const wchar_t *) srunp->str) + 1;
+-	      wmemcpy ((wchar_t *) &ctype->translit_to_tbl[to_len],
+-		       (const wchar_t *) srunp->str, len);
++	      len = wcslen_uint32 (srunp->str) + 1;
++	      wmemcpy_uint32 (&ctype->translit_to_tbl[to_len],
++			      srunp->str, len);
+ 	      to_len += len;
+ 	      srunp = srunp->next;
+ 	    }
+diff --git a/locale/programs/ld-time.c b/locale/programs/ld-time.c
+index dcd2a2386d..6814740325 100644
+--- a/locale/programs/ld-time.c
++++ b/locale/programs/ld-time.c
+@@ -220,8 +220,10 @@ No definition for %s category found"), "LC_TIME");
+ 	}
+       else
+ 	{
++	  static const uint32_t wt_fmt_ampm[]
++	    = { '%','I',':','%','M',':','%','S',' ','%','p',0 };
+ 	  time->t_fmt_ampm = "%I:%M:%S %p";
+-	  time->wt_fmt_ampm = (const uint32_t *) L"%I:%M:%S %p";
++	  time->wt_fmt_ampm = wt_fmt_ampm;
+ 	}
+     }
+ 
+@@ -231,7 +233,7 @@ No definition for %s category found"), "LC_TIME");
+       const int days_per_month[12] = { 31, 29, 31, 30, 31, 30,
+ 				       31, 31, 30, 31 ,30, 31 };
+       size_t idx;
+-      wchar_t *wstr;
++      uint32_t *wstr;
+ 
+       time->era_entries =
+ 	(struct era_data *) xmalloc (time->num_era
+@@ -457,18 +459,18 @@ No definition for %s category found"), "LC_TIME");
+ 	    }
+ 
+ 	  /* Now generate the wide character name and format.  */
+-	  wstr = wcschr ((wchar_t *) time->wera[idx], L':');/* end direction */
+-	  wstr = wstr ? wcschr (wstr + 1, L':') : NULL;	/* end offset */
+-	  wstr = wstr ? wcschr (wstr + 1, L':') : NULL;	/* end start */
+-	  wstr = wstr ? wcschr (wstr + 1, L':') : NULL;	/* end end */
++	  wstr = wcschr_uint32 (time->wera[idx], L':'); /* end direction */
++	  wstr = wstr ? wcschr_uint32 (wstr + 1, L':') : NULL; /* end offset */
++	  wstr = wstr ? wcschr_uint32 (wstr + 1, L':') : NULL; /* end start */
++	  wstr = wstr ? wcschr_uint32 (wstr + 1, L':') : NULL; /* end end */
+ 	  if (wstr != NULL)
+ 	    {
+-	      time->era_entries[idx].wname = (uint32_t *) wstr + 1;
+-	      wstr = wcschr (wstr + 1, L':');	/* end name */
++	      time->era_entries[idx].wname = wstr + 1;
++	      wstr = wcschr_uint32 (wstr + 1, L':'); /* end name */
+ 	      if (wstr != NULL)
+ 		{
+ 		  *wstr = L'\0';
+-		  time->era_entries[idx].wformat = (uint32_t *) wstr + 1;
++		  time->era_entries[idx].wformat = wstr + 1;
+ 		}
+ 	      else
+ 		time->era_entries[idx].wname =
+@@ -527,7 +529,16 @@ No definition for %s category found"), "LC_TIME");
+   if (time->date_fmt == NULL)
+     time->date_fmt = "%a %b %e %H:%M:%S %Z %Y";
+   if (time->wdate_fmt == NULL)
+-    time->wdate_fmt = (const uint32_t *) L"%a %b %e %H:%M:%S %Z %Y";
++    {
++      static const uint32_t wdate_fmt[] =
++	{ '%','a',' ',
++	  '%','b',' ',
++	  '%','e',' ',
++	  '%','H',':','%','M',':','%','S',' ',
++	  '%','Z',' ',
++	  '%','Y',0 };
++      time->wdate_fmt = wdate_fmt;
++    }
+ }
+ 
+ 
+diff --git a/locale/programs/linereader.c b/locale/programs/linereader.c
+index 96d3ab66db..3af379d2c3 100644
+--- a/locale/programs/linereader.c
++++ b/locale/programs/linereader.c
+@@ -595,7 +595,7 @@ get_string (struct linereader *lr, const struct charmap_t *charmap,
+ {
+   int return_widestr = lr->return_widestr;
+   char *buf;
+-  wchar_t *buf2 = NULL;
++  uint32_t *buf2 = NULL;
+   size_t bufact;
+   size_t bufmax = 56;
+ 
+diff --git a/locale/programs/localedef.c b/locale/programs/localedef.c
+index 832c8fd1fc..fe689b3ae1 100644
+--- a/locale/programs/localedef.c
++++ b/locale/programs/localedef.c
+@@ -109,6 +109,7 @@ void (*argp_program_version_hook) (FILE *, struct argp_state *) = print_version;
+ #define OPT_NO_WARN 402
+ #define OPT_WARN 403
+ #define OPT_NO_HARD_LINKS 404
++#define OPT_UINT32_ALIGN 405
+ 
+ /* Definitions of arguments for argp functions.  */
+ static const struct argp_option options[] =
+@@ -153,6 +154,8 @@ static const struct argp_option options[] =
+     N_("Generate little-endian output") },
+   { "big-endian", OPT_BIG_ENDIAN, NULL, 0,
+     N_("Generate big-endian output") },
++  { "uint32-align", OPT_UINT32_ALIGN, "ALIGNMENT", 0,
++    N_("Set the target's uint32_t alignment in bytes (default 4)") },
+   { NULL, 0, NULL, 0, NULL }
+ };
+ 
+@@ -243,12 +246,14 @@ main (int argc, char *argv[])
+      ctype locale.  (P1003.2 4.35.5.2)  */
+   setlocale (LC_CTYPE, "POSIX");
+ 
++#ifndef NO_SYSCONF
+   /* Look whether the system really allows locale definitions.  POSIX
+      defines error code 3 for this situation so I think it must be
+      a fatal error (see P1003.2 4.35.8).  */
+   if (sysconf (_SC_2_LOCALEDEF) < 0)
+     record_error (3, 0, _("\
+ FATAL: system does not define `_POSIX2_LOCALEDEF'"));
++#endif
+ 
+   /* Process charmap file.  */
+   charmap = charmap_read (charmap_file, verbose, 1, be_quiet, 1);
+@@ -400,6 +405,9 @@ parse_opt (int key, char *arg, struct argp_state *state)
+       /* Do not hard link to other locales.  */
+       hard_links = false;
+       break;
++    case OPT_UINT32_ALIGN:
++      uint32_align_mask = strtol (arg, NULL, 0) - 1;
++      break;
+     case 'c':
+       force_output = 1;
+       break;
+diff --git a/locale/programs/locfile.c b/locale/programs/locfile.c
+index 0f1affa1d4..7d86fae801 100644
+--- a/locale/programs/locfile.c
++++ b/locale/programs/locfile.c
+@@ -544,6 +544,9 @@ compare_files (const char *filename1, const char *filename2, size_t size,
+    machine running localedef.  */
+ bool swap_endianness_p;
+ 
++/* The target's value of __align__(uint32_t) - 1.  */
++unsigned int uint32_align_mask = 3;
++
+ /* When called outside a start_locale_structure/end_locale_structure
+    or start_locale_prelude/end_locale_prelude block, record that the
+    next byte in FILE's obstack will be the first byte of a new element.
+@@ -621,7 +624,7 @@ add_locale_string (struct locale_file *file, const char *string)
+ void
+ add_locale_wstring (struct locale_file *file, const uint32_t *string)
+ {
+-  add_locale_uint32_array (file, string, wcslen ((const wchar_t *) string) + 1);
++  add_locale_uint32_array (file, string, wcslen_uint32 (string) + 1);
+ }
+ 
+ /* Record that FILE's next element is the 32-bit integer VALUE.  */
+diff --git a/locale/programs/locfile.h b/locale/programs/locfile.h
+index c986d599ec..222a779176 100644
+--- a/locale/programs/locfile.h
++++ b/locale/programs/locfile.h
+@@ -71,6 +71,8 @@ extern void write_all_categories (struct localedef_t *definitions,
+ 
+ extern bool swap_endianness_p;
+ 
++extern unsigned int uint32_align_mask;
++
+ /* Change the output to be big-endian if BIG_ENDIAN is true and
+    little-endian otherwise.  */
+ static inline void
+@@ -89,7 +91,8 @@ maybe_swap_uint32 (uint32_t value)
+ }
+ 
+ /* Likewise, but munge an array of N uint32_ts starting at ARRAY.  */
+-static inline void
++static void
++__attribute__ ((unused))
+ maybe_swap_uint32_array (uint32_t *array, size_t n)
+ {
+   if (swap_endianness_p)
+@@ -99,7 +102,8 @@ maybe_swap_uint32_array (uint32_t *array, size_t n)
+ 
+ /* Like maybe_swap_uint32_array, but the array of N elements is at
+    the end of OBSTACK's current object.  */
+-static inline void
++static void
++__attribute__ ((unused))
+ maybe_swap_uint32_obstack (struct obstack *obstack, size_t n)
+ {
+   maybe_swap_uint32_array ((uint32_t *) obstack_next_free (obstack) - n, n);
+@@ -276,4 +280,55 @@ extern void identification_output (struct localedef_t *locale,
+ 				   const struct charmap_t *charmap,
+ 				   const char *output_path);
+ 
++static size_t wcslen_uint32 (const uint32_t *str) __attribute__ ((unused));
++static uint32_t * wmemcpy_uint32 (uint32_t *s1, const uint32_t *s2, size_t n) __attribute__ ((unused));
++static uint32_t * wcschr_uint32 (const uint32_t *s, uint32_t ch) __attribute__ ((unused));
++static int wcscmp_uint32 (const uint32_t *s1, const uint32_t *s2) __attribute__ ((unused));
++static int wmemcmp_uint32 (const uint32_t *s1, const uint32_t *s2, size_t n) __attribute__ ((unused));
++
++static size_t
++wcslen_uint32 (const uint32_t *str)
++{
++  size_t len = 0;
++  while (str[len] != 0)
++    len++;
++  return len;
++}
++
++static  int
++wmemcmp_uint32 (const uint32_t *s1, const uint32_t *s2, size_t n)
++{
++  while (n-- != 0)
++    {
++      int diff = *s1++ - *s2++;
++      if (diff != 0)
++	return diff;
++    }
++  return 0;
++}
++
++static int
++wcscmp_uint32 (const uint32_t *s1, const uint32_t *s2)
++{
++  while (*s1 != 0 && *s1 == *s2)
++    s1++, s2++;
++  return *s1 - *s2;
++}
++
++static uint32_t *
++wmemcpy_uint32 (uint32_t *s1, const uint32_t *s2, size_t n)
++{
++  return memcpy (s1, s2, n * sizeof (uint32_t));
++}
++
++static uint32_t *
++wcschr_uint32 (const uint32_t *s, uint32_t ch)
++{
++  do
++    if (*s == ch)
++      return (uint32_t *) s;
++  while (*s++ != 0);
++  return 0;
++}
++
+ #endif /* locfile.h */
+diff --git a/locale/setlocale.c b/locale/setlocale.c
+index 19ed85ae8e..f28ca11446 100644
+--- a/locale/setlocale.c
++++ b/locale/setlocale.c
+@@ -63,35 +63,6 @@ static char *const _nl_current_used[] =
+ 
+ #endif
+ 
+-
+-/* Define an array of category names (also the environment variable names).  */
+-const struct catnamestr_t _nl_category_names attribute_hidden =
+-  {
+-#define DEFINE_CATEGORY(category, category_name, items, a) \
+-    category_name,
+-#include "categories.def"
+-#undef DEFINE_CATEGORY
+-  };
+-
+-const uint8_t _nl_category_name_idxs[__LC_LAST] attribute_hidden =
+-  {
+-#define DEFINE_CATEGORY(category, category_name, items, a) \
+-    [category] = offsetof (struct catnamestr_t, CATNAMEMF (__LINE__)),
+-#include "categories.def"
+-#undef DEFINE_CATEGORY
+-  };
+-
+-/* An array of their lengths, for convenience.  */
+-const uint8_t _nl_category_name_sizes[] attribute_hidden =
+-  {
+-#define DEFINE_CATEGORY(category, category_name, items, a) \
+-    [category] = sizeof (category_name) - 1,
+-#include "categories.def"
+-#undef	DEFINE_CATEGORY
+-    [LC_ALL] = sizeof ("LC_ALL") - 1
+-  };
+-
+-
+ #ifdef NL_CURRENT_INDIRECT
+ # define WEAK_POSTLOAD(postload) weak_extern (postload)
+ #else

+ 80 - 0
recipes-core/glibc/glibc/0024-localedef-add-to-archive-uses-a-hard-coded-locale-pa.patch

@@ -0,0 +1,80 @@
+From 13bc0e53cc91e102472d532f28b3d44c30d291fc Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 3 Aug 2018 09:42:06 -0700
+Subject: [PATCH] localedef --add-to-archive uses a hard-coded locale path
+
+it doesn't exist in normal use, and there's no way to pass an
+alternative filename.
+
+Add a fallback of $LOCALEARCHIVE from the environment, and allow
+creation of new locale archives that are not the system archive.
+
+Upstream-Status: Inappropriate (OE-specific)
+
+Signed-off-by: Ross Burton <ross.burton@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ locale/programs/locarchive.c | 35 +++++++++++++++++++++++++----------
+ 1 file changed, 25 insertions(+), 10 deletions(-)
+
+diff --git a/locale/programs/locarchive.c b/locale/programs/locarchive.c
+index f38e835c52..8d8f8699b2 100644
+--- a/locale/programs/locarchive.c
++++ b/locale/programs/locarchive.c
+@@ -340,12 +340,24 @@ enlarge_archive (struct locarhandle *ah, const struct locarhead *head)
+   struct namehashent *oldnamehashtab;
+   struct locarhandle new_ah;
+   size_t prefix_len = output_prefix ? strlen (output_prefix) : 0;
+-  char archivefname[prefix_len + sizeof (ARCHIVE_NAME)];
+-  char fname[prefix_len + sizeof (ARCHIVE_NAME) + sizeof (".XXXXXX") - 1];
++  char *archivefname;
++  char *fname;
++  char *envarchive = getenv("LOCALEARCHIVE");
+ 
+-  if (output_prefix)
+-    memcpy (archivefname, output_prefix, prefix_len);
+-  strcpy (archivefname + prefix_len, ARCHIVE_NAME);
++  if (envarchive != NULL)
++    {
++      archivefname = xmalloc(strlen(envarchive) + 1);
++      fname = xmalloc(strlen(envarchive) + sizeof (".XXXXXX"));
++      strcpy (archivefname, envarchive);
++    }
++  else
++    {
++      archivefname = xmalloc(prefix_len + sizeof (ARCHIVE_NAME));
++      fname = xmalloc(prefix_len + sizeof (ARCHIVE_NAME) + sizeof (".XXXXXX") - 1);
++      if (output_prefix)
++        memcpy (archivefname, output_prefix, prefix_len);
++      strcpy (archivefname + prefix_len, ARCHIVE_NAME);
++    }
+   strcpy (stpcpy (fname, archivefname), ".XXXXXX");
+ 
+   /* Not all of the old file has to be mapped.  Change this now this
+@@ -569,10 +581,13 @@ open_archive (struct locarhandle *ah, bool readonly)
+   /* If ah has a non-NULL fname open that otherwise open the default.  */
+   if (archivefname == NULL)
+     {
+-      archivefname = default_fname;
+-      if (output_prefix)
+-        memcpy (default_fname, output_prefix, prefix_len);
+-      strcpy (default_fname + prefix_len, ARCHIVE_NAME);
++      archivefname = getenv("LOCALEARCHIVE");
++      if (archivefname == NULL) {
++              archivefname = default_fname;
++              if (output_prefix)
++                memcpy (default_fname, output_prefix, prefix_len);
++              strcpy (default_fname + prefix_len, ARCHIVE_NAME);
++      }
+     }
+ 
+   while (1)
+@@ -585,7 +600,7 @@ open_archive (struct locarhandle *ah, bool readonly)
+ 	     the default locale archive we ignore the failure and
+ 	     list an empty archive, otherwise we print an error
+ 	     and exit.  */
+-	  if (errno == ENOENT && archivefname == default_fname)
++	  if (errno == ENOENT)
+ 	    {
+ 	      if (readonly)
+ 		{

+ 53 - 0
recipes-core/glibc/glibc/0025-elf-dl-deps.c-Make-_dl_build_local_scope-breadth-fir.patch

@@ -0,0 +1,53 @@
+From 50b605dece16606dd9d1c737e579c13725eab11d Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@windriver.com>
+Date: Thu, 18 Aug 2016 14:07:58 -0500
+Subject: [PATCH] elf/dl-deps.c: Make _dl_build_local_scope breadth first
+
+According to the ELF specification:
+
+When resolving symbolic references, the dynamic linker examines the symbol
+tables with a breadth-first search.
+
+This function was using a depth first search.  By doing so the conflict
+resolution reported to the prelinker (when LD_TRACE_PRELINKING=1 is set)
+was incorrect.  This caused problems when their were various circular
+dependencies between libraries.  The problem usually manifested itself by
+the wrong IFUNC being executed.
+
+[BZ# 20488]
+
+Upstream-Status: Submitted [libc-alpha]
+
+Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
+---
+ elf/dl-deps.c | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/elf/dl-deps.c b/elf/dl-deps.c
+index 087a49b212..c09f9334f2 100644
+--- a/elf/dl-deps.c
++++ b/elf/dl-deps.c
+@@ -73,13 +73,19 @@ _dl_build_local_scope (struct link_map **list, struct link_map *map)
+ {
+   struct link_map **p = list;
+   struct link_map **q;
++  struct link_map **r;
+ 
+   *p++ = map;
+   map->l_reserved = 1;
+-  if (map->l_initfini)
+-    for (q = map->l_initfini + 1; *q; ++q)
+-      if (! (*q)->l_reserved)
+-	p += _dl_build_local_scope (p, *q);
++
++  for (r = list; r < p; ++r)
++    if ((*r)->l_initfini)
++      for (q = (*r)->l_initfini + 1; *q; ++q)
++	if (! (*q)->l_reserved)
++	  {
++	    *p++ = *q;
++	    (*q)->l_reserved = 1;
++	  }
+   return p - list;
+ }
+ 

+ 31 - 0
recipes-core/glibc/glibc/0026-intl-Emit-no-lines-in-bison-generated-files.patch

@@ -0,0 +1,31 @@
+From 99ab34278a6ebec134267412b4f619f43e278dea Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 3 Aug 2018 09:44:00 -0700
+Subject: [PATCH] intl: Emit no lines in bison generated files
+
+Improve reproducibility:
+Do not put any #line preprocessor commands in bison generated files.
+These lines contain absolute paths containing file locations on
+the host build machine.
+
+Upstream-Status: Pending
+
+Signed-off-by: Juro Bystricky <juro.bystricky@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ intl/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/intl/Makefile b/intl/Makefile
+index 93478d87e8..b27a7935eb 100644
+--- a/intl/Makefile
++++ b/intl/Makefile
+@@ -155,7 +155,7 @@ $(objpfx)tst-gettext6.out: $(objpfx)tst-gettext.out
+ 
+ CPPFLAGS += -D'LOCALEDIR="$(localedir)"' \
+ 	    -D'LOCALE_ALIAS_PATH="$(localedir)"'
+-BISONFLAGS = --yacc --name-prefix=__gettext --output
++BISONFLAGS = --yacc --no-lines --name-prefix=__gettext --output
+ 
+ $(inst_localedir)/locale.alias: locale.alias $(+force)
+ 	$(do-install)

+ 53 - 0
recipes-core/glibc/glibc/0027-locale-prevent-maybe-uninitialized-errors-with-Os-BZ.patch

@@ -0,0 +1,53 @@
+From 3190ada9ecaec915794886a608221655c120f90c Mon Sep 17 00:00:00 2001
+From: Martin Jansa <martin.jansa@gmail.com>
+Date: Mon, 17 Dec 2018 21:36:18 +0000
+Subject: [PATCH] locale: prevent maybe-uninitialized errors with -Os [BZ
+ #19444]
+
+Fixes following error when building for aarch64 with -Os:
+| In file included from strcoll_l.c:43:
+| strcoll_l.c: In function '__strcoll_l':
+| ../locale/weight.h:31:26: error: 'seq2.back_us' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+|    int_fast32_t i = table[*(*cpp)++];
+|                           ^~~~~~~~~
+| strcoll_l.c:304:18: note: 'seq2.back_us' was declared here
+|    coll_seq seq1, seq2;
+|                   ^~~~
+| In file included from strcoll_l.c:43:
+| ../locale/weight.h:31:26: error: 'seq1.back_us' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+|    int_fast32_t i = table[*(*cpp)++];
+|                           ^~~~~~~~~
+| strcoll_l.c:304:12: note: 'seq1.back_us' was declared here
+|    coll_seq seq1, seq2;
+|             ^~~~
+
+        Partial fix for [BZ #19444]
+        * locale/weight.h: Fix build with -Os.
+
+Upstream-Status: Submitted [https://patchwork.ozlabs.org/patch/1014766]
+
+Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ locale/weight.h | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/locale/weight.h b/locale/weight.h
+index 723e1fefda..f5798d379a 100644
+--- a/locale/weight.h
++++ b/locale/weight.h
+@@ -28,7 +28,14 @@ findidx (const int32_t *table,
+ 	 const unsigned char *extra,
+ 	 const unsigned char **cpp, size_t len)
+ {
++  /* With GCC 8 when compiling with -Os the compiler warns that
++     seq1.back_us and seq2.back_us might be used uninitialized.
++     This uninitialized use is impossible for the same reason
++     as described in comments in locale/weightwc.h.  */
++  DIAG_PUSH_NEEDS_COMMENT;
++  DIAG_IGNORE_Os_NEEDS_COMMENT (8, "-Wmaybe-uninitialized");
+   int_fast32_t i = table[*(*cpp)++];
++  DIAG_POP_NEEDS_COMMENT;
+   const unsigned char *cp;
+   const unsigned char *usrc;
+ 

+ 29 - 0
recipes-core/glibc/glibc/0028-readlib-Add-OECORE_KNOWN_INTERPRETER_NAMES-to-known-.patch

@@ -0,0 +1,29 @@
+From 5d201a75918a0e181ee6206f701901fdb91baf81 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Wed, 18 Mar 2015 00:11:22 +0000
+Subject: [PATCH] readlib: Add OECORE_KNOWN_INTERPRETER_NAMES to known names
+
+This bolts in a hook for OE to pass its own version of interpreter
+names into glibc especially for multilib case, where it differs from any
+other distros
+
+Upstream-Status: Inappropriate [OE specific]
+
+Signed-off-by: Lianhao Lu <lianhao.lu@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ elf/readlib.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/elf/readlib.c b/elf/readlib.c
+index 7383c23249..e97ea9449d 100644
+--- a/elf/readlib.c
++++ b/elf/readlib.c
+@@ -51,6 +51,7 @@ static struct known_names interpreters[] =
+ #ifdef SYSDEP_KNOWN_INTERPRETER_NAMES
+   SYSDEP_KNOWN_INTERPRETER_NAMES
+ #endif
++  OECORE_KNOWN_INTERPRETER_NAMES
+ };
+ 
+ static struct known_names known_libs[] =

+ 67 - 0
recipes-core/glibc/glibc/0029-wordsize.h-Unify-the-header-between-arm-and-aarch64.patch

@@ -0,0 +1,67 @@
+From baba3c6021340a9070b734f931a15cea4cfe6c31 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 15 May 2020 17:05:45 -0700
+Subject: [PATCH] wordsize.h: Unify the header between arm and aarch64
+
+This helps OE multilibs to not sythesize this header which causes all
+kind of recursions and other issues since wordsize is fundamental header
+and ends up including itself in many case e.g. clang tidy, bpf etc.
+
+Upstream-Status: Inappropriate [ OE-Specific ]
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/aarch64/bits/wordsize.h          |  8 ++++++--
+ sysdeps/{aarch64 => arm}/bits/wordsize.h | 10 +++++++---
+ 2 files changed, 13 insertions(+), 5 deletions(-)
+ copy sysdeps/{aarch64 => arm}/bits/wordsize.h (80%)
+
+diff --git a/sysdeps/aarch64/bits/wordsize.h b/sysdeps/aarch64/bits/wordsize.h
+index 91da566b74..9a754514b3 100644
+--- a/sysdeps/aarch64/bits/wordsize.h
++++ b/sysdeps/aarch64/bits/wordsize.h
+@@ -17,12 +17,16 @@
+    License along with the GNU C Library; if not, see
+    <https://www.gnu.org/licenses/>.  */
+ 
+-#ifdef __LP64__
++#if defined (__aarch64__) && defined (__LP64__)
+ # define __WORDSIZE			64
+-#else
++#elif defined (__aarch64__)
+ # define __WORDSIZE			32
+ # define __WORDSIZE32_SIZE_ULONG	1
+ # define __WORDSIZE32_PTRDIFF_LONG	1
++#else
++# define __WORDSIZE			32
++# define __WORDSIZE32_SIZE_ULONG	0
++# define __WORDSIZE32_PTRDIFF_LONG	0
+ #endif
+ 
+ #define __WORDSIZE_TIME64_COMPAT32	0
+diff --git a/sysdeps/aarch64/bits/wordsize.h b/sysdeps/arm/bits/wordsize.h
+similarity index 80%
+copy from sysdeps/aarch64/bits/wordsize.h
+copy to sysdeps/arm/bits/wordsize.h
+index 91da566b74..34fcdef1f1 100644
+--- a/sysdeps/aarch64/bits/wordsize.h
++++ b/sysdeps/arm/bits/wordsize.h
+@@ -17,12 +17,16 @@
+    License along with the GNU C Library; if not, see
+    <https://www.gnu.org/licenses/>.  */
+ 
+-#ifdef __LP64__
++#if defined (__aarch64__) && defined (__LP64__)
+ # define __WORDSIZE			64
+-#else
++#elif defined (__aarch64__)
+ # define __WORDSIZE			32
+ # define __WORDSIZE32_SIZE_ULONG	1
+ # define __WORDSIZE32_PTRDIFF_LONG	1
++#else
++# define __WORDSIZE			32
++# define __WORDSIZE32_SIZE_ULONG	0
++# define __WORDSIZE32_PTRDIFF_LONG	0
+ #endif
+ 
+ #define __WORDSIZE_TIME64_COMPAT32	0

+ 48 - 0
recipes-core/glibc/glibc/0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch

@@ -0,0 +1,48 @@
+From 60aa53f547911163b42a1c436d695a15c87f34ee Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 7 Aug 2020 14:31:16 -0700
+Subject: [PATCH] powerpc: Do not ask compiler for finding arch
+
+This does not work well in cross compiling environments like OE
+and moreover it uses its own -mcpu/-march options via cflags
+
+Upstream-Status: Inappropriate [ OE-Specific]
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ sysdeps/powerpc/preconfigure    | 5 +----
+ sysdeps/powerpc/preconfigure.ac | 5 +----
+ 2 files changed, 2 insertions(+), 8 deletions(-)
+
+diff --git a/sysdeps/powerpc/preconfigure b/sysdeps/powerpc/preconfigure
+index dfe8e20399..bbff040f0f 100644
+--- a/sysdeps/powerpc/preconfigure
++++ b/sysdeps/powerpc/preconfigure
+@@ -29,10 +29,7 @@ esac
+ # directive which shows up, and try using it.
+ case "${machine}:${submachine}" in
+ *powerpc*:)
+-  archcpu=`echo "int foo () { return 0; }" \
+-	   | $CC $CFLAGS $CPPFLAGS -S -frecord-gcc-switches -xc -o - - \
+-	   | grep -E "mcpu=|.machine" -m 1 \
+-	   | sed -e "s/.*machine //" -e "s/.*mcpu=\(.*\)\"/\1/"`
++  archcpu=''
+   # Note if you add patterns here you must ensure that an appropriate
+   # directory exists in sysdeps/powerpc.  Likewise, if we find a
+   # cpu, don't let the generic configure append extra compiler options.
+diff --git a/sysdeps/powerpc/preconfigure.ac b/sysdeps/powerpc/preconfigure.ac
+index 6c63bd8257..3e925f1d48 100644
+--- a/sysdeps/powerpc/preconfigure.ac
++++ b/sysdeps/powerpc/preconfigure.ac
+@@ -29,10 +29,7 @@ esac
+ # directive which shows up, and try using it.
+ case "${machine}:${submachine}" in
+ *powerpc*:)
+-  archcpu=`echo "int foo () { return 0; }" \
+-	   | $CC $CFLAGS $CPPFLAGS -S -frecord-gcc-switches -xc -o - - \
+-	   | grep -E "mcpu=|[.]machine" -m 1 \
+-	   | sed -e "s/.*machine //" -e "s/.*mcpu=\(.*\)\"/\1/"`
++  archcpu=''
+   # Note if you add patterns here you must ensure that an appropriate
+   # directory exists in sysdeps/powerpc.  Likewise, if we find a
+   # cpu, don't let the generic configure append extra compiler options.

+ 184 - 0
recipes-core/glibc/glibc/CVE-2021-43396.patch

@@ -0,0 +1,184 @@
+From ff012870b2c02a62598c04daa1e54632e020fd7d Mon Sep 17 00:00:00 2001
+From: Nikita Popov <npv1310@gmail.com>
+Date: Tue, 2 Nov 2021 13:21:42 +0500
+Subject: [PATCH] gconv: Do not emit spurious NUL character in ISO-2022-JP-3
+ (bug 28524)
+
+Bugfix 27256 has introduced another issue:
+In conversion from ISO-2022-JP-3 encoding, it is possible
+to force iconv to emit extra NUL character on internal state reset.
+To do this, it is sufficient to feed iconv with escape sequence
+which switches active character set.
+The simplified check 'data->__statep->__count != ASCII_set'
+introduced by the aforementioned bugfix picks that case and
+behaves as if '\0' character has been queued thus emitting it.
+
+To eliminate this issue, these steps are taken:
+* Restore original condition
+'(data->__statep->__count & ~7) != ASCII_set'.
+It is necessary since bits 0-2 may contain
+number of buffered input characters.
+* Check that queued character is not NUL.
+Similar step is taken for main conversion loop.
+
+Bundled test case follows following logic:
+* Try to convert ISO-2022-JP-3 escape sequence
+switching active character set
+* Reset internal state by providing NULL as input buffer
+* Ensure that nothing has been converted.
+
+Signed-off-by: Nikita Popov <npv1310@gmail.com>
+
+CVE: CVE-2021-43396
+Upstream-Status: Backport [ff012870b2c02a62598c04daa1e54632e020fd7d]
+---
+ iconvdata/Makefile        |  5 +++-
+ iconvdata/bug-iconv15.c   | 60 +++++++++++++++++++++++++++++++++++++++
+ iconvdata/iso-2022-jp-3.c | 28 ++++++++++++------
+ 3 files changed, 84 insertions(+), 9 deletions(-)
+ create mode 100644 iconvdata/bug-iconv15.c
+
+Index: git/iconvdata/Makefile
+===================================================================
+--- git.orig/iconvdata/Makefile
++++ git/iconvdata/Makefile
+@@ -1,4 +1,5 @@
+ # Copyright (C) 1997-2021 Free Software Foundation, Inc.
++# Copyright (C) The GNU Toolchain Authors.
+ # This file is part of the GNU C Library.
+ 
+ # The GNU C Library is free software; you can redistribute it and/or
+@@ -74,7 +75,7 @@ ifeq (yes,$(build-shared))
+ tests = bug-iconv1 bug-iconv2 tst-loading tst-e2big tst-iconv4 bug-iconv4 \
+ 	tst-iconv6 bug-iconv5 bug-iconv6 tst-iconv7 bug-iconv8 bug-iconv9 \
+ 	bug-iconv10 bug-iconv11 bug-iconv12 tst-iconv-big5-hkscs-to-2ucs4 \
+-	bug-iconv13 bug-iconv14
++	bug-iconv13 bug-iconv14 bug-iconv15
+ ifeq ($(have-thread-library),yes)
+ tests += bug-iconv3
+ endif
+@@ -327,6 +328,8 @@ $(objpfx)bug-iconv12.out: $(addprefix $(
+ 			  $(addprefix $(objpfx),$(modules.so))
+ $(objpfx)bug-iconv14.out: $(addprefix $(objpfx), $(gconv-modules)) \
+ 			  $(addprefix $(objpfx),$(modules.so))
++$(objpfx)bug-iconv15.out: $(addprefix $(objpfx), $(gconv-modules)) \
++			  $(addprefix $(objpfx),$(modules.so))
+ 
+ $(objpfx)iconv-test.out: run-iconv-test.sh \
+ 			 $(addprefix $(objpfx), $(gconv-modules)) \
+Index: git/iconvdata/bug-iconv15.c
+===================================================================
+--- /dev/null
++++ git/iconvdata/bug-iconv15.c
+@@ -0,0 +1,60 @@
++/* Bug 28524: Conversion from ISO-2022-JP-3 with iconv
++   may emit spurious NUL character on state reset.
++   Copyright (C) The GNU Toolchain Authors.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, see
++   <https://www.gnu.org/licenses/>.  */
++
++#include <stddef.h>
++#include <iconv.h>
++#include <support/check.h>
++
++static int
++do_test (void)
++{
++  char in[] = "\x1b(I";
++  char *inbuf = in;
++  size_t inleft = sizeof (in) - 1;
++  char out[1];
++  char *outbuf = out;
++  size_t outleft = sizeof (out);
++  iconv_t cd;
++
++  cd = iconv_open ("UTF8", "ISO-2022-JP-3");
++  TEST_VERIFY_EXIT (cd != (iconv_t) -1);
++
++  /* First call to iconv should alter internal state.
++     Now, JISX0201_Kana_set is selected and
++     state value != ASCII_set.  */
++  TEST_VERIFY (iconv (cd, &inbuf, &inleft, &outbuf, &outleft) != (size_t) -1);
++
++  /* No bytes should have been added to
++     the output buffer at this point.  */
++  TEST_VERIFY (outbuf == out);
++  TEST_VERIFY (outleft == sizeof (out));
++
++  /* Second call shall emit spurious NUL character in unpatched glibc.  */
++  TEST_VERIFY (iconv (cd, NULL, NULL, &outbuf, &outleft) != (size_t) -1);
++
++  /* No characters are expected to be produced.  */
++  TEST_VERIFY (outbuf == out);
++  TEST_VERIFY (outleft == sizeof (out));
++
++  TEST_VERIFY_EXIT (iconv_close (cd) != -1);
++
++  return 0;
++}
++
++#include <support/test-driver.c>
+Index: git/iconvdata/iso-2022-jp-3.c
+===================================================================
+--- git.orig/iconvdata/iso-2022-jp-3.c
++++ git/iconvdata/iso-2022-jp-3.c
+@@ -1,5 +1,6 @@
+ /* Conversion module for ISO-2022-JP-3.
+    Copyright (C) 1998-2021 Free Software Foundation, Inc.
++   Copyright (C) The GNU Toolchain Authors.
+    This file is part of the GNU C Library.
+    Contributed by Ulrich Drepper <drepper@cygnus.com>, 1998,
+    and Bruno Haible <bruno@clisp.org>, 2002.
+@@ -81,20 +82,31 @@ enum
+    the output state to the initial state.  This has to be done during the
+    flushing.  */
+ #define EMIT_SHIFT_TO_INIT \
+-  if (data->__statep->__count != ASCII_set)			      \
++  if ((data->__statep->__count & ~7) != ASCII_set)			      \
+     {									      \
+       if (FROM_DIRECTION)						      \
+ 	{								      \
+-	  if (__glibc_likely (outbuf + 4 <= outend))			      \
++	  uint32_t ch = data->__statep->__count >> 6;			      \
++									      \
++	  if (__glibc_unlikely (ch != 0))				      \
+ 	    {								      \
+-	      /* Write out the last character.  */			      \
+-	      *((uint32_t *) outbuf) = data->__statep->__count >> 6;	      \
+-	      outbuf += sizeof (uint32_t);				      \
+-	      data->__statep->__count = ASCII_set;			\
++	      if (__glibc_likely (outbuf + 4 <= outend))		      \
++		{							      \
++		  /* Write out the last character.  */			      \
++		  put32u (outbuf, ch);					      \
++		  outbuf += 4;						      \
++		  data->__statep->__count &= 7;				      \
++		  data->__statep->__count |= ASCII_set;			      \
++		}							      \
++	      else							      \
++		/* We don't have enough room in the output buffer.  */	      \
++		status = __GCONV_FULL_OUTPUT;				      \
+ 	    }								      \
+ 	  else								      \
+-	    /* We don't have enough room in the output buffer.  */	      \
+-	    status = __GCONV_FULL_OUTPUT;				      \
++	    {								      \
++	      data->__statep->__count &= 7;				      \
++	      data->__statep->__count |= ASCII_set;			      \
++	    }								      \
+ 	}								      \
+       else								      \
+ 	{								      \

+ 80 - 0
recipes-core/glibc/glibc/check-test-wrapper

@@ -0,0 +1,80 @@
+#!/usr/bin/env python3
+import sys
+import os
+import subprocess
+import resource
+
+env = os.environ.copy()
+args = sys.argv[1:]
+targettype = args.pop(0)
+
+if targettype == "user":
+    qemuargs = os.environ.get("QEMU_OPTIONS", "").split()
+    if not os.path.exists(qemuargs[0]):
+        # ensure qemu args has a valid absolute path
+        for i in os.environ.get("PATH", "").split(":"):
+            if os.path.exists(os.path.join(i, qemuargs[0])):
+                qemuargs[0] = os.path.join(i, qemuargs[0])
+                break
+    sysroot = os.environ.get("QEMU_SYSROOT", None)
+    if not sysroot:
+        sys.exit(-1)
+    libpaths = [sysroot + "/usr/lib", sysroot + "/lib"]
+
+    if args[0] == "env":
+        args.pop(0)
+        if len(args) == 0:
+            args = ["env"]
+        else:
+            # process options
+            while args[0].startswith("-"):
+                opt = args.pop(0).lstrip("-")
+                if "i" in opt:
+                    env.clear()
+            # process environment vars
+            while "=" in args[0]:
+                key, val = args.pop(0).split("=", 1)
+                if key == "LD_LIBRARY_PATH":
+                    libpaths += val.split(":")
+                else:
+                    env[key] = val
+    if args[0] == "cp":
+        # ignore copies, the filesystem is the same
+        sys.exit(0)
+
+    qemuargs += ["-L", sysroot]
+    qemuargs += ["-E", "LD_LIBRARY_PATH={}".format(":".join(libpaths))]
+    command = qemuargs + args
+
+    # We've seen qemu-arm using up all system memory for some glibc
+    # tests e.g. nptl/tst-pthread-timedlock-lockloop
+    # Cap at 8GB since no test should need more than that
+    # (5GB adds 7 failures for qemuarm glibc test run)
+    limit = 8*1024*1024*1024
+    resource.setrlimit(resource.RLIMIT_AS, (limit, limit))
+
+elif targettype == "ssh":
+    host = os.environ.get("SSH_HOST", None)
+    user = os.environ.get("SSH_HOST_USER", None)
+    port = os.environ.get("SSH_HOST_PORT", None)
+
+    command = ["ssh", "-o", "UserKnownHostsFile=/dev/null", "-o", "StrictHostKeyChecking=no"]
+    if port:
+        command += ["-p", str(port)]
+    if not host:
+        sys.exit(-1)
+    command += ["{}@{}".format(user, host) if user else host]
+
+    # wrap and replace quotes for correct transformation on ssh
+    wrapped = " ".join(["'{0}'".format(i.replace("'", r"'\''")) for i in ["cd", os.getcwd()]]) + "; "
+    wrapped += " ".join(["'{0}'".format(i.replace("'", r"'\''")) for i in args])
+    command += ["sh", "-c", "\"{}\"".format(wrapped)]
+else:
+    sys.exit(-1)
+
+try:
+    r = subprocess.run(command, timeout = 1800, env = env)
+    sys.exit(r.returncode)
+except subprocess.TimeoutExpired:
+    sys.exit(-1)
+

+ 1 - 0
recipes-core/glibc/glibc/etc/ld.so.conf

@@ -0,0 +1 @@
+include /etc/ld.so.conf.d/*.conf

+ 11 - 0
recipes-core/glibc/glibc/generate-supported.mk

@@ -0,0 +1,11 @@
+#!/usr/bin/make
+
+include $(IN)
+
+all:
+	rm -f $(OUT)
+	touch $(OUT)
+	for locale in $(SUPPORTED-LOCALES); do \
+		[ $$locale = true ] && continue; \
+		echo $$locale | sed 's,/, ,' >> $(OUT); \
+	done

+ 177 - 0
recipes-core/glibc/glibc/makedbs.sh

@@ -0,0 +1,177 @@
+#!/bin/sh
+
+#
+# Make passwd.db, group.db, etc.
+#
+
+VAR_DB=/var/db
+
+# Use make if available
+if [ -x /usr/bin/make -o -x /bin/make ]; then
+	make -C $VAR_DB
+	exit 0
+fi
+
+# No make available, do it in hard way
+
+# passwd.db
+if [ -e /etc/passwd ]; then
+target=$VAR_DB/passwd.db
+echo -n "passwd... "
+awk 'BEGIN { FS=":"; OFS=":" } \
+ /^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print; \
+	   printf "=%s ", $$3; print }' /etc/passwd | \
+makedb --quiet -o $target -
+echo "done."
+fi
+
+# group.db
+if [ -e /etc/group ]; then
+target=$VAR_DB/group.db
+echo -n "group... "
+awk 'BEGIN { FS=":"; OFS=":" } \
+ /^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print; \
+	   printf "=%s ", $$3; print; \
+	   if ($$4 != "") { \
+	     split($$4, grmems, ","); \
+	     for (memidx in grmems) { \
+	       mem=grmems[memidx]; \
+	       if (members[mem] == "") \
+		 members[mem]=$$3; \
+	       else \
+		 members[mem]=members[mem] "," $$3; \
+	     } \
+	     delete grmems; } } \
+ END { for (mem in members) \
+	 printf ":%s %s %s\n", mem, mem, members[mem]; }' /etc/group | \
+makedb --quiet -o $target -
+echo "done."
+fi
+
+# ethers.db
+if [ -e /etc/ethers ]; then
+target=$VAR_DB/ethers.db
+echo -n "ethers... "
+awk '/^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print; \
+	   printf "=%s ", $$2; print }' /etc/ethers | \
+makedb --quiet -o $target -
+echo "done."
+fi
+
+# protocols.db
+if [ -e /etc/protocols ]; then
+target=$VAR_DB/protocols.db
+echo -n "protocols... "
+awk '/^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print; \
+	   printf "=%s ", $$2; print; \
+	   for (i = 3; i <= NF && !($$i ~ /^#/); ++i) \
+	     { printf ".%s ", $$i; print } }' /etc/protocols | \
+makedb --quiet -o $target -
+echo "done."
+fi
+
+# rpc.db
+if [ -e /etc/rpc ]; then
+target=$VAR_DB/rpc.db
+echo -n "rpc... "
+awk '/^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print; \
+	   printf "=%s ", $$2; print; \
+	   for (i = 3; i <= NF && !($$i ~ /^#/); ++i) \
+	     { printf ".%s ", $$i; print } }' /etc/rpc | \
+makedb --quiet -o $target -
+echo "done."
+fi
+
+# services.db
+if [ -e /etc/services ]; then
+target=$VAR_DB/services.db
+echo -n "services... "
+awk 'BEGIN { FS="[ \t/]+" } \
+ /^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { sub(/[ \t]*#.*$$/, "");\
+	   printf ":%s/%s ", $$1, $$3; print; \
+	   printf ":%s/ ", $$1; print; \
+	   printf "=%s/%s ", $$2, $$3; print; \
+	   printf "=%s/ ", $$2; print; \
+	   for (i = 4; i <= NF && !($$i ~ /^#/); ++i) \
+	     { printf ":%s/%s ", $$i, $$3; print; \
+	       printf ":%s/ ", $$i; print } }' /etc/services | \
+makedb --quiet -o $target -
+echo "done."
+fi
+
+# shadow.db
+if [ -e /etc/shadow ]; then
+target=$VAR_DB/shadow.db
+echo -n "shadow... "
+awk 'BEGIN { FS=":"; OFS=":" } \
+ /^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print }' /etc/shadow | \
+(umask 077 && makedb --quiet -o $target -)
+echo "done."
+if chgrp shadow $target 2>/dev/null; then
+	chmod g+r $target
+else
+	chown 0 $target; chgrp 0 $target; chmod 600 $target;
+	echo
+	echo "Warning: The shadow password database $target"
+	echo "has been set to be readable only by root.  You may want"
+	echo "to make it readable by the \`shadow' group depending"
+	echo "on your configuration."
+	echo
+fi
+fi
+
+# gshadow.db
+if [ -e /etc/gshadow ]; then
+target=$VAR_DB/gshadow.db
+echo -n "gshadow... "
+awk 'BEGIN { FS=":"; OFS=":" } \
+ /^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { printf ".%s ", $$1; print }' /etc/gshadow | \
+(umask 077 && makedb --quiet -o $target -)
+echo "done."
+if chgrp shadow $target 2>/dev/null; then
+	chmod g+r $target
+else
+	chown 0 $target; chgrp 0 $target; chmod 600 $target
+	echo
+	echo "Warning: The shadow group database $target"
+	echo "has been set to be readable only by root.  You may want"
+	echo "to make it readable by the \`shadow' group depending"
+	echo "on your configuration."
+	echo
+fi
+fi
+
+# netgroup.db
+if [ -e /etc/netgroup ]; then
+target=$VAR_DB/netgroup.db
+echo -n "netgroup... "
+awk 'BEGIN { ini=1 } \
+ /^[ \t]*$$/ { next } \
+ /^[ \t]*#/ { next } \
+ /^[^#]/ { if (sub(/[ \t]*\\$$/, " ") == 0) end="\n"; \
+	   else end=""; \
+	   gsub(/[ \t]+/, " "); \
+	   sub(/^[ \t]*/, ""); \
+	   if (ini == 0) printf "%s%s", $$0, end; \
+	   else printf ".%s %s%s", $$1, $$0, end; \
+	   ini=end == "" ? 0 : 1; } \
+ END { if (ini==0) printf "\n" }' /etc/netgroup | \
+makedb --quiet -o $target
+echo "done."
+fi

+ 131 - 0
recipes-core/glibc/glibc_2.35.bb

@@ -0,0 +1,131 @@
+require glibc.inc
+require glibc-version.inc
+
+CVE_CHECK_WHITELIST += "CVE-2020-10029 CVE-2021-27645"
+
+# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010022
+# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010023
+# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010024
+# Upstream glibc maintainers dispute there is any issue and have no plans to address it further.
+# "this is being treated as a non-security bug and no real threat."
+CVE_CHECK_WHITELIST += "CVE-2019-1010022 CVE-2019-1010023 CVE-2019-1010024"
+
+# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010025
+# Allows for ASLR bypass so can bypass some hardening, not an exploit in itself, may allow
+# easier access for another. "ASLR bypass itself is not a vulnerability."
+# Potential patch at https://sourceware.org/bugzilla/show_bug.cgi?id=22853
+CVE_CHECK_WHITELIST += "CVE-2019-1010025"
+
+DEPENDS += "gperf-native bison-native make-native"
+
+NATIVESDKFIXES ?= ""
+NATIVESDKFIXES_class-nativesdk = "\
+           file://0003-nativesdk-glibc-Look-for-host-system-ld.so.cache-as-.patch \
+           file://0004-nativesdk-glibc-Fix-buffer-overrun-with-a-relocated-.patch \
+           file://0005-nativesdk-glibc-Raise-the-size-of-arrays-containing-.patch \
+           file://0006-nativesdk-glibc-Allow-64-bit-atomics-for-x86.patch \
+           file://0007-nativesdk-glibc-Make-relocatable-install-for-locales.patch \
+           file://0008-nativesdk-glibc-Fall-back-to-faccessat-on-faccess2-r.patch \
+"
+
+SRC_URI =  "${GLIBC_GIT_URI};branch=${SRCBRANCH};name=glibc \
+           file://etc/ld.so.conf \
+           file://generate-supported.mk \
+           file://makedbs.sh \
+           \
+           ${NATIVESDKFIXES} \
+           file://0009-fsl-e500-e5500-e6500-603e-fsqrt-implementation.patch \
+           file://0010-ppc-sqrt-Fix-undefined-reference-to-__sqrt_finite.patch \
+           file://0011-__ieee754_sqrt-f-are-now-inline-functions-and-call-o.patch \
+           file://0012-Quote-from-bug-1443-which-explains-what-the-patch-do.patch \
+           file://0013-eglibc-run-libm-err-tab.pl-with-specific-dirs-in-S.patch \
+           file://0014-__ieee754_sqrt-f-are-now-inline-functions-and-call-o.patch \
+           file://0015-sysdeps-gnu-configure.ac-handle-correctly-libc_cv_ro.patch \
+           file://0016-yes-within-the-path-sets-wrong-config-variables.patch \
+           file://0017-timezone-re-written-tzselect-as-posix-sh.patch \
+           file://0018-Remove-bash-dependency-for-nscd-init-script.patch \
+           file://0019-eglibc-Cross-building-and-testing-instructions.patch \
+           file://0020-eglibc-Help-bootstrap-cross-toolchain.patch \
+           file://0021-eglibc-Resolve-__fpscr_values-on-SH4.patch \
+           file://0022-eglibc-Forward-port-cross-locale-generation-support.patch \
+           file://0024-localedef-add-to-archive-uses-a-hard-coded-locale-pa.patch \
+           file://0025-elf-dl-deps.c-Make-_dl_build_local_scope-breadth-fir.patch \
+           file://0026-intl-Emit-no-lines-in-bison-generated-files.patch \
+           file://0027-locale-prevent-maybe-uninitialized-errors-with-Os-BZ.patch \
+           file://0028-readlib-Add-OECORE_KNOWN_INTERPRETER_NAMES-to-known-.patch \
+           file://0029-wordsize.h-Unify-the-header-between-arm-and-aarch64.patch \
+           file://0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch \
+           file://0001-fix-create-thread-failed-in-unprivileged-process-BZ-.patch \
+           "
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build-${TARGET_SYS}"
+
+PACKAGES_DYNAMIC = ""
+
+# the -isystem in bitbake.conf screws up glibc do_stage
+BUILD_CPPFLAGS = "-I${STAGING_INCDIR_NATIVE}"
+TARGET_CPPFLAGS = "-I${STAGING_DIR_TARGET}${includedir}"
+
+GLIBC_BROKEN_LOCALES = ""
+
+GLIBCPIE ??= ""
+
+EXTRA_OECONF = "--enable-kernel=${OLDEST_KERNEL} \
+                --disable-profile \
+                --disable-debug --without-gd \
+                --enable-clocale=gnu \
+                --with-headers=${STAGING_INCDIR} \
+                --without-selinux \
+                --enable-tunables \
+                --enable-bind-now \
+                --enable-stack-protector=strong \
+                --disable-crypt \
+                --with-default-link \
+                ${@bb.utils.contains_any('SELECTED_OPTIMIZATION', '-O0 -Og', '--disable-werror', '', d)} \
+                ${GLIBCPIE} \
+                ${GLIBC_EXTRA_OECONF}"
+
+EXTRA_OECONF += "${@get_libc_fpu_setting(bb, d)}"
+
+EXTRA_OECONF_append_x86 = " --enable-cet"
+EXTRA_OECONF_append_x86-64 = " --enable-cet"
+
+PACKAGECONFIG ??= "nscd memory-tagging"
+PACKAGECONFIG[nscd] = "--enable-nscd,--disable-nscd"
+PACKAGECONFIG[memory-tagging] = "--enable-memory-tagging,--disable-memory-tagging"
+
+do_patch_append() {
+    bb.build.exec_func('do_fix_readlib_c', d)
+}
+
+do_fix_readlib_c () {
+	sed -i -e 's#OECORE_KNOWN_INTERPRETER_NAMES#${EGLIBC_KNOWN_INTERPRETER_NAMES}#' ${S}/elf/readlib.c
+}
+
+do_configure () {
+# override this function to avoid the autoconf/automake/aclocal/autoheader
+# calls for now
+# don't pass CPPFLAGS into configure, since it upsets the kernel-headers
+# version check and doesn't really help with anything
+        (cd ${S} && gnu-configize) || die "failure in running gnu-configize"
+        find ${S} -name "configure" | xargs touch
+        CPPFLAGS="" oe_runconf
+}
+
+LDFLAGS += "-fuse-ld=bfd"
+do_compile () {
+	base_do_compile
+	echo "Adjust ldd script"
+	if [ -n "${RTLDLIST}" ]
+	then
+		prevrtld=`cat ${B}/elf/ldd | grep "^RTLDLIST=" | sed 's#^RTLDLIST="\?\([^"]*\)"\?$#\1#'`
+		# remove duplicate entries
+		newrtld=`echo $(printf '%s\n' ${prevrtld} ${RTLDLIST} | LC_ALL=C sort -u)`
+		echo "ldd \"${prevrtld} ${RTLDLIST}\" -> \"${newrtld}\""
+		sed -i ${B}/elf/ldd -e "s#^RTLDLIST=.*\$#RTLDLIST=\"${newrtld}\"#"
+	fi
+}
+
+require glibc-package.inc
+
+BBCLASSEXTEND = "nativesdk"

+ 331 - 0
recipes-core/glibc/ldconfig-native-2.12.1/32and64bit.patch

@@ -0,0 +1,331 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+We run the ldconfig in the cross fashion. make the code bitsize aware so that 
+we can cross build ldconfig cache for various architectures.
+
+Richard Purdie <richard.purdie@linuxfoundation.org> 2009/05/19
+Nitin A Kamble <nitin.a.kamble@intel.com> 2009/03/29
+
+Index: ldconfig-native-2.12.1/readelflib.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/readelflib.c
++++ ldconfig-native-2.12.1/readelflib.c
+@@ -40,39 +40,212 @@ do								\
+ 
+ /* Returns 0 if everything is ok, != 0 in case of error.  */
+ int
+-process_elf_file (const char *file_name, const char *lib, int *flag,
++process_elf_file32 (const char *file_name, const char *lib, int *flag,
+ 		  unsigned int *osversion, char **soname, void *file_contents,
+ 		  size_t file_length)
+ {
+   int i;
+   unsigned int j;
+-  ElfW(Addr) loadaddr;
++  Elf32_Addr loadaddr;
+   unsigned int dynamic_addr;
+   size_t dynamic_size;
+   char *program_interpreter;
+ 
+-  ElfW(Ehdr) *elf_header;
+-  ElfW(Phdr) *elf_pheader, *segment;
+-  ElfW(Dyn) *dynamic_segment, *dyn_entry;
++  Elf32_Ehdr *elf_header;
++  Elf32_Phdr *elf_pheader, *segment;
++  Elf32_Dyn *dynamic_segment, *dyn_entry;
+   char *dynamic_strings;
+ 
+-  elf_header = (ElfW(Ehdr) *) file_contents;
++  elf_header = (Elf32_Ehdr *) file_contents;
+   *osversion = 0;
+ 
+-  if (elf_header->e_ident [EI_CLASS] != ElfW (CLASS))
++  if (elf_header->e_type != ET_DYN)
+     {
+-      if (opt_verbose)
++      error (0, 0, _("%s is not a shared object file (Type: %d).\n"), file_name,
++	     elf_header->e_type);
++      return 1;
++    }
++
++  /* Get information from elf program header.  */
++  elf_pheader = (Elf32_Phdr *) (elf_header->e_phoff + file_contents);
++  check_ptr (elf_pheader);
++
++  /* The library is an elf library, now search for soname and
++     libc5/libc6.  */
++  *flag = FLAG_ELF;
++
++  loadaddr = -1;
++  dynamic_addr = 0;
++  dynamic_size = 0;
++  program_interpreter = NULL;
++  for (i = 0, segment = elf_pheader;
++       i < elf_header->e_phnum; i++, segment++)
++    {
++      check_ptr (segment);
++
++      switch (segment->p_type)
+ 	{
+-	  if (elf_header->e_ident [EI_CLASS] == ELFCLASS32)
+-	    error (0, 0, _("%s is a 32 bit ELF file.\n"), file_name);
+-	  else if (elf_header->e_ident [EI_CLASS] == ELFCLASS64)
+-	    error (0, 0, _("%s is a 64 bit ELF file.\n"), file_name);
+-	  else
+-	    error (0, 0, _("Unknown ELFCLASS in file %s.\n"), file_name);
++	case PT_LOAD:
++	  if (loadaddr == (Elf32_Addr) -1)
++	    loadaddr = segment->p_vaddr - segment->p_offset;
++	  break;
++
++	case PT_DYNAMIC:
++	  if (dynamic_addr)
++	    error (0, 0, _("more than one dynamic segment\n"));
++
++	  dynamic_addr = segment->p_offset;
++	  dynamic_size = segment->p_filesz;
++	  break;
++
++	case PT_INTERP:
++	  program_interpreter = (char *) (file_contents + segment->p_offset);
++	  check_ptr (program_interpreter);
++
++	  /* Check if this is enough to classify the binary.  */
++	  for (j = 0; j < sizeof (interpreters) / sizeof (interpreters [0]);
++	       ++j)
++	    if (strcmp (program_interpreter, interpreters[j].soname) == 0)
++	      {
++		*flag = interpreters[j].flag;
++		break;
++	      }
++	  break;
++
++	case PT_NOTE:
++	  if (!*osversion && segment->p_filesz >= 32 && segment->p_align >= 4)
++	    {
++	      Elf32_Word *abi_note = (Elf32_Word *) (file_contents
++						     + segment->p_offset);
++	      Elf32_Addr size = segment->p_filesz;
++
++	      while (abi_note [0] != 4 || abi_note [1] != 16
++		     || abi_note [2] != 1
++		     || memcmp (abi_note + 3, "GNU", 4) != 0)
++		{
++#define ROUND(len) (((len) + sizeof (Elf32_Word)) - 1) & -sizeof (Elf32_Word)))
++		  Elf32_Addr) note_size = 3 * sizeof (Elf32_Word))
++					 + ROUND (abi_note[0])
++					 + ROUND (abi_note[1]);
++
++		  if (size - 32 < note_size || note_size == 0)
++		    {
++		      size = 0;
++		      break;
++		    }
++		  size -= note_size;
++		  abi_note = (void *) abi_note + note_size;
++		}
++
++	      if (size == 0)
++		break;
++
++	      *osversion = (abi_note [4] << 24) |
++			   ((abi_note [5] & 0xff) << 16) |
++			   ((abi_note [6] & 0xff) << 8) |
++			   (abi_note [7] & 0xff);
++	    }
++	  break;
++
++	default:
++	  break;
++	}
++
++    }
++  if (loadaddr == (Elf32_Addr) -1)
++    {
++      /* Very strange. */
++      loadaddr = 0;
++    }
++
++  /* Now we can read the dynamic sections.  */
++  if (dynamic_size == 0)
++    return 1;
++
++  dynamic_segment = (Elf32_Dyn *) (file_contents + dynamic_addr);
++  check_ptr (dynamic_segment);
++
++  /* Find the string table.  */
++  dynamic_strings = NULL;
++  for (dyn_entry = dynamic_segment; dyn_entry->d_tag != DT_NULL;
++       ++dyn_entry)
++    {
++      check_ptr (dyn_entry);
++      if (dyn_entry->d_tag == DT_STRTAB)
++	{
++	  dynamic_strings = (char *) (file_contents + dyn_entry->d_un.d_val - loadaddr);
++	  check_ptr (dynamic_strings);
++	  break;
+ 	}
+-      return 1;
+     }
+ 
++  if (dynamic_strings == NULL)
++    return 1;
++
++  /* Now read the DT_NEEDED and DT_SONAME entries.  */
++  for (dyn_entry = dynamic_segment; dyn_entry->d_tag != DT_NULL;
++       ++dyn_entry)
++    {
++      if (dyn_entry->d_tag == DT_NEEDED || dyn_entry->d_tag == DT_SONAME)
++	{
++	  char *name = dynamic_strings + dyn_entry->d_un.d_val;
++	  check_ptr (name);
++
++	  if (dyn_entry->d_tag == DT_NEEDED)
++	    {
++
++	      if (*flag == FLAG_ELF)
++		{
++		  /* Check if this is enough to classify the binary.  */
++		  for (j = 0;
++		       j < sizeof (known_libs) / sizeof (known_libs [0]);
++		       ++j)
++		    if (strcmp (name, known_libs [j].soname) == 0)
++		      {
++			*flag = known_libs [j].flag;
++			break;
++		      }
++		}
++	    }
++
++	  else if (dyn_entry->d_tag == DT_SONAME)
++	    *soname = xstrdup (name);
++
++	  /* Do we have everything we need?  */
++	  if (*soname && *flag != FLAG_ELF)
++	    return 0;
++	}
++    }
++
++  /* We reach this point only if the file doesn't contain a DT_SONAME
++     or if we can't classify the library.  If it doesn't have a
++     soname, return the name of the library.  */
++  if (*soname == NULL)
++    *soname = xstrdup (lib);
++
++  return 0;
++}
++
++int
++process_elf_file64 (const char *file_name, const char *lib, int *flag,
++		  unsigned int *osversion, char **soname, void *file_contents,
++		  size_t file_length)
++{
++  int i;
++  unsigned int j;
++  Elf64_Addr loadaddr;
++  unsigned int dynamic_addr;
++  size_t dynamic_size;
++  char *program_interpreter;
++
++  Elf64_Ehdr *elf_header;
++  Elf64_Phdr *elf_pheader, *segment;
++  Elf64_Dyn *dynamic_segment, *dyn_entry;
++  char *dynamic_strings;
++
++  elf_header = (Elf64_Ehdr *) file_contents;
++  *osversion = 0;
++
+   if (elf_header->e_type != ET_DYN)
+     {
+       error (0, 0, _("%s is not a shared object file (Type: %d).\n"), file_name,
+@@ -81,7 +254,7 @@ process_elf_file (const char *file_name,
+     }
+ 
+   /* Get information from elf program header.  */
+-  elf_pheader = (ElfW(Phdr) *) (elf_header->e_phoff + file_contents);
++  elf_pheader = (Elf64_Phdr *) (elf_header->e_phoff + file_contents);
+   check_ptr (elf_pheader);
+ 
+   /* The library is an elf library, now search for soname and
+@@ -100,7 +273,7 @@ process_elf_file (const char *file_name,
+       switch (segment->p_type)
+ 	{
+ 	case PT_LOAD:
+-	  if (loadaddr == (ElfW(Addr)) -1)
++	  if (loadaddr == (Elf64_Addr) -1)
+ 	    loadaddr = segment->p_vaddr - segment->p_offset;
+ 	  break;
+ 
+@@ -129,16 +302,16 @@ process_elf_file (const char *file_name,
+ 	case PT_NOTE:
+ 	  if (!*osversion && segment->p_filesz >= 32 && segment->p_align >= 4)
+ 	    {
+-	      ElfW(Word) *abi_note = (ElfW(Word) *) (file_contents
++	      Elf64_Word *abi_note = (Elf64_Word *) (file_contents
+ 						     + segment->p_offset);
+-	      ElfW(Addr) size = segment->p_filesz;
++	      Elf64_Addr size = segment->p_filesz;
+ 
+ 	      while (abi_note [0] != 4 || abi_note [1] != 16
+ 		     || abi_note [2] != 1
+ 		     || memcmp (abi_note + 3, "GNU", 4) != 0)
+ 		{
+-#define ROUND(len) (((len) + sizeof (ElfW(Word)) - 1) & -sizeof (ElfW(Word)))
+-		  ElfW(Addr) note_size = 3 * sizeof (ElfW(Word))
++#define ROUND(len) (((len) + sizeof (Elf64_Word) - 1) & -sizeof (Elf64_Word))
++		  Elf64_Addr note_size = 3 * sizeof (Elf64_Word)
+ 					 + ROUND (abi_note[0])
+ 					 + ROUND (abi_note[1]);
+ 
+@@ -166,7 +339,7 @@ process_elf_file (const char *file_name,
+ 	}
+ 
+     }
+-  if (loadaddr == (ElfW(Addr)) -1)
++  if (loadaddr == (Elf64_Addr) -1)
+     {
+       /* Very strange. */
+       loadaddr = 0;
+@@ -176,7 +349,7 @@ process_elf_file (const char *file_name,
+   if (dynamic_size == 0)
+     return 1;
+ 
+-  dynamic_segment = (ElfW(Dyn) *) (file_contents + dynamic_addr);
++  dynamic_segment = (Elf64_Dyn *) (file_contents + dynamic_addr);
+   check_ptr (dynamic_segment);
+ 
+   /* Find the string table.  */
+@@ -233,3 +406,33 @@ process_elf_file (const char *file_name,
+ 
+   return 0;
+ }
++/* Returns 0 if everything is ok, != 0 in case of error.  */
++int
++process_elf_file (const char *file_name, const char *lib, int *flag,
++		  unsigned int *osversion, char **soname, void *file_contents,
++		  size_t file_length)
++{
++  int i;
++  unsigned int j;
++  ElfW(Addr) loadaddr;
++  unsigned int dynamic_addr;
++  size_t dynamic_size;
++  char *program_interpreter;
++
++  ElfW(Ehdr) *elf_header;
++  ElfW(Phdr) *elf_pheader, *segment;
++  ElfW(Dyn) *dynamic_segment, *dyn_entry;
++  char *dynamic_strings;
++
++  elf_header = (ElfW(Ehdr) *) file_contents;
++  *osversion = 0;
++
++  if (elf_header->e_ident [EI_CLASS] == ELFCLASS32)
++    return process_elf_file32(file_name, lib,flag, osversion, soname, file_contents, file_length);
++  else if (elf_header->e_ident [EI_CLASS] == ELFCLASS64)
++    return process_elf_file64(file_name, lib,flag, osversion, soname, file_contents, file_length);
++  error (0, 0, _("Unknown ELFCLASS in file %s.\n"), file_name);
++  return 1;
++}
++
++

+ 8 - 0
recipes-core/glibc/ldconfig-native-2.12.1/README

@@ -0,0 +1,8 @@
+The files are pulled verbatim from glibc 2.5 and then patched to allow
+standalone compilation of ldconfig.
+
+Richard Purdie
+OpenedHand Ltd.
+
+Upgraded the ldconfig recipe to eglibc 2.12.1
+Nitin A Kamble <nitin.a.kamble@intel.com> 2011/03/29

+ 116 - 0
recipes-core/glibc/ldconfig-native-2.12.1/add-64-bit-flag-for-ELF64-entries.patch

@@ -0,0 +1,116 @@
+From 9d62544090b08849218cd1fc52a36cdd5d90363e Mon Sep 17 00:00:00 2001
+From: Yuanjie Huang <yuanjie.huang@windriver.com>
+Date: Fri, 24 Apr 2015 03:29:31 +0000
+Subject: [PATCH] Add 64-bit flag for ELF64 entries.
+
+ldconfig-native was grepped from an old version of glibc, and its output
+lacks neccessary 64bit flag in entries.
+Due to this defect, ctypes.util.find_library() python function fails to
+detect any library due to the old file format that ldconfig-native
+creates. This fix sets architecture-dependent 64bit flags for 64-bit ELF.
+
+Upstream-Status: Inappropriate [embedded specific]
+
+Signed-off-by: Yuanjie Huang <yuanjie.huang@windriver.com>
+---
+ cache.c      |  4 ++++
+ ldconfig.h   |  4 ++++
+ readelflib.c | 34 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 42 insertions(+)
+
+diff --git a/cache.c b/cache.c
+index a904d44..c4f5411 100644
+--- a/cache.c
++++ b/cache.c
+@@ -121,6 +121,10 @@ print_entry (const char *lib, int flag, unsigned int osversion,
+       break;
+     case FLAG_MIPS64_LIBN64:
+       fputs (",64bit", stdout);
++      break;
++    case FLAG_AARCH64_LIB64:
++      fputs (",AArch64", stdout);
++      break;
+     case 0:
+       break;
+     default:
+diff --git a/ldconfig.h b/ldconfig.h
+index fadd5ec..6a8a750 100644
+--- a/ldconfig.h
++++ b/ldconfig.h
+@@ -34,6 +34,10 @@
+ #define FLAG_POWERPC_LIB64	0x0500
+ #define FLAG_MIPS64_LIBN32	0x0600
+ #define FLAG_MIPS64_LIBN64	0x0700
++#define FLAG_X8664_LIBX32		0x0800
++#define FLAG_ARM_LIBHF			0x0900
++#define FLAG_AARCH64_LIB64		0x0a00
++#define FLAG_ARM_LIBSF			0x0b00
+ 
+ /* Name of auxiliary cache.  */
+ #define _PATH_LDCONFIG_AUX_CACHE "/var/cache/ldconfig/aux-cache"
+diff --git a/readelflib.c b/readelflib.c
+index 0bf0de3..6e87afc 100644
+--- a/readelflib.c
++++ b/readelflib.c
+@@ -28,6 +28,11 @@
+ 
+ #include "endian_extra.h"
+ 
++/* Work-around for old host that does not have AArch64 defined in elf.h. */
++#ifndef EM_AARCH64
++#define EM_AARCH64	183		/* ARM AARCH64 */
++#endif
++
+ #undef check_ptr
+ #define check_ptr(ptr)						\
+ do								\
+@@ -290,6 +295,48 @@ process_elf_file64 (const char *file_name, const char *lib, int *flag,
+      libc5/libc6.  */
+   *flag = FLAG_ELF;
+ 
++  /* Set flags according to information in ELF header to align with target
++     ldconfig */
++  switch (elf_header->e_machine)
++    {
++    case EM_IA_64:
++      /* Intel 64bit libraries are always libc.so.6+. */
++      /* see sysdeps/unix/sysv/linux/ia64/readelflib.c */
++      *flag |= FLAG_IA64_LIB64|FLAG_ELF_LIBC6;
++      break;
++    case EM_X86_64:
++      /* X86-64 64bit libraries are always libc.so.6+. */
++      /* see sysdeps/unix/sysv/linux/i386/readelflib.c */
++      *flag |= FLAG_X8664_LIB64|FLAG_ELF_LIBC6;
++      break;
++    case EM_S390:
++      /* S/390 64bit libraries are always libc.so.6+. */
++      /* see sysdeps/unix/sysv/linux/s390/readelflib.c */
++      *flag |= FLAG_S390_LIB64|FLAG_ELF_LIBC6;
++      break;
++    case EM_PPC64:
++      /* PowerPC 64bit libraries are always libc.so.6+. */
++      /* see sysdeps/unix/sysv/linux/powerpc/readelflib.c */
++      *flag |= FLAG_POWERPC_LIB64|FLAG_ELF_LIBC6;
++      break;
++    case EM_MIPS:
++    case EM_MIPS_RS3_LE:
++      /* n64 libraries are always libc.so.6+. */
++      /* NOTE: This does not correctly distinguish NAN2008 binaries and is possibly broken */
++      /* see sysdeps/unix/sysv/linux/mips/readelflib.c */
++      *flag |= FLAG_MIPS64_LIBN64|FLAG_ELF_LIBC6;
++      break;
++    case EM_AARCH64:
++      /* AArch64 libraries are always libc.so.6+. */
++      /* see sysdeps/unix/sysv/linux/arm/readelflib.c */
++      *flag |= FLAG_AARCH64_LIB64|FLAG_ELF_LIBC6;
++      break;
++    default:
++      error(0, 0, "%s is a 64-bit ELF for unknown machine %lx\n",
++            file_name, (long)elf_header->e_machine);
++      break;
++    }
++
+   loadaddr = -1;
+   dynamic_addr = 0;
+   dynamic_size = 0;
+-- 

+ 79 - 0
recipes-core/glibc/ldconfig-native-2.12.1/add-riscv-support.patch

@@ -0,0 +1,79 @@
+From fd50228cc213d2d87f5e3cf1f123acb3fda9b04e Mon Sep 17 00:00:00 2001
+From: Christoph Muellner <cmuellner@linux.com>
+Date: Mon, 28 Jun 2021 00:34:12 +0200
+Subject: [PATCH] ldconfig: Add RISC-V support
+
+ldconfig-native does not support RISC-V at the moment.
+Let's pull the reqired constants from upstream and add
+the required parsing code.
+
+Upstream-Status: Backport
+
+Signed-off-by: Christoph Muellner <cmuellner@linux.com>
+---
+ cache.c      |  6 ++++++
+ ldconfig.h   |  2 ++
+ readelflib.c | 10 ++++++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/cache.c b/cache.c
+index c4f5411..a3b9e70 100644
+--- a/cache.c
++++ b/cache.c
+@@ -125,6 +125,12 @@ print_entry (const char *lib, int flag, unsigned int osversion,
+     case FLAG_AARCH64_LIB64:
+       fputs (",AArch64", stdout);
+       break;
++    case FLAG_RISCV_FLOAT_ABI_SOFT:
++      fputs (",soft-float", stdout);
++      break;
++    case FLAG_RISCV_FLOAT_ABI_DOUBLE:
++      fputs (",double-float", stdout);
++      break;
+     case 0:
+       break;
+     default:
+diff --git a/ldconfig.h b/ldconfig.h
+index 6a8a750..2e5e379 100644
+--- a/ldconfig.h
++++ b/ldconfig.h
+@@ -38,6 +38,8 @@
+ #define FLAG_ARM_LIBHF			0x0900
+ #define FLAG_AARCH64_LIB64		0x0a00
+ #define FLAG_ARM_LIBSF			0x0b00
++#define FLAG_RISCV_FLOAT_ABI_SOFT	0x0f00
++#define FLAG_RISCV_FLOAT_ABI_DOUBLE	0x1000
+ 
+ /* Name of auxiliary cache.  */
+ #define _PATH_LDCONFIG_AUX_CACHE "/var/cache/ldconfig/aux-cache"
+diff --git a/readelflib.c b/readelflib.c
+index 9ec0a54..a01e1ce 100644
+--- a/readelflib.c
++++ b/readelflib.c
+@@ -33,6 +33,10 @@
+ #define EM_AARCH64	183		/* ARM AARCH64 */
+ #endif
+ 
++#ifndef EM_RISCV
++#define EM_RISCV	243		/* RISC-V */
++#endif
++
+ #undef check_ptr
+ #define check_ptr(ptr)						\
+ do								\
+@@ -331,6 +335,12 @@ process_elf_file64 (const char *file_name, const char *lib, int *flag,
+       /* see sysdeps/unix/sysv/linux/arm/readelflib.c */
+       *flag |= FLAG_AARCH64_LIB64|FLAG_ELF_LIBC6;
+       break;
++    case EM_RISCV:
++      /* RISC-V libraries are always libc.so.6+. */
++      /* NOTE: This does not correctly handle soft-float binaries */
++      /* see sysdeps/unix/sysv/linux/riscv/readelflib.c */
++      *flag |= FLAG_RISCV_FLOAT_ABI_DOUBLE|FLAG_ELF_LIBC6;
++      break;
+     default:
+       error(0, 0, "%s is a 64-bit ELF for unknown machine %lx\n",
+             file_name, (long)elf_header->e_machine);
+-- 
+2.25.1
+

+ 454 - 0
recipes-core/glibc/ldconfig-native-2.12.1/endian-ness_handling.patch

@@ -0,0 +1,454 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+Do data input/output handling according to endien-ness of the library file. That 
+enables use of ldconfig in the cross fashion for any architecture.
+
+2011/04/04
+Richard Purdie <richard.purdie@linuxfoundation.org>
+Nitin Kamble <nitin.a.kamble@intel.com>
+
+Index: ldconfig-native-2.12.1/readelflib.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/readelflib.c
++++ ldconfig-native-2.12.1/readelflib.c
+@@ -38,6 +38,28 @@ do								\
+   }								\
+  while (0);
+ 
++int be;
++static uint16_t read16(uint16_t x, int be)
++{
++  if (be)
++        return be16toh(x);
++  return le16toh(x);
++}
++
++static uint32_t read32(uint32_t x, int be)
++{
++  if (be)
++        return be32toh(x);
++  return le32toh(x);
++}
++
++static uint64_t read64(uint64_t x, int be)
++{
++  if (be)
++        return be64toh(x);
++  return le64toh(x);
++}
++
+ /* Returns 0 if everything is ok, != 0 in case of error.  */
+ int
+ process_elf_file32 (const char *file_name, const char *lib, int *flag,
+@@ -59,15 +81,17 @@ process_elf_file32 (const char *file_nam
+   elf_header = (Elf32_Ehdr *) file_contents;
+   *osversion = 0;
+ 
+-  if (elf_header->e_type != ET_DYN)
++  be = (elf_header->e_ident[EI_DATA] == ELFDATA2MSB);
++
++  if (read16(elf_header->e_type, be) != ET_DYN)
+     {
+       error (0, 0, _("%s is not a shared object file (Type: %d).\n"), file_name,
+-	     elf_header->e_type);
++	     read16(elf_header->e_type, be));
+       return 1;
+     }
+ 
+   /* Get information from elf program header.  */
+-  elf_pheader = (Elf32_Phdr *) (elf_header->e_phoff + file_contents);
++  elf_pheader = (Elf32_Phdr *) (read32(elf_header->e_phoff, be) + file_contents);
+   check_ptr (elf_pheader);
+ 
+   /* The library is an elf library, now search for soname and
+@@ -79,27 +103,27 @@ process_elf_file32 (const char *file_nam
+   dynamic_size = 0;
+   program_interpreter = NULL;
+   for (i = 0, segment = elf_pheader;
+-       i < elf_header->e_phnum; i++, segment++)
++       i < read16(elf_header->e_phnum, be); i++, segment++)
+     {
+       check_ptr (segment);
+ 
+-      switch (segment->p_type)
++      switch (read32(segment->p_type, be))
+ 	{
+ 	case PT_LOAD:
+ 	  if (loadaddr == (Elf32_Addr) -1)
+-	    loadaddr = segment->p_vaddr - segment->p_offset;
++	    loadaddr = read32(segment->p_vaddr, be) - read32(segment->p_offset, be);
+ 	  break;
+ 
+ 	case PT_DYNAMIC:
+ 	  if (dynamic_addr)
+ 	    error (0, 0, _("more than one dynamic segment\n"));
+ 
+-	  dynamic_addr = segment->p_offset;
+-	  dynamic_size = segment->p_filesz;
++	  dynamic_addr = read32(segment->p_offset, be);
++	  dynamic_size = read32(segment->p_filesz, be);
+ 	  break;
+ 
+ 	case PT_INTERP:
+-	  program_interpreter = (char *) (file_contents + segment->p_offset);
++	  program_interpreter = (char *) (file_contents + read32(segment->p_offset, be));
+ 	  check_ptr (program_interpreter);
+ 
+ 	  /* Check if this is enough to classify the binary.  */
+@@ -113,20 +137,20 @@ process_elf_file32 (const char *file_nam
+ 	  break;
+ 
+ 	case PT_NOTE:
+-	  if (!*osversion && segment->p_filesz >= 32 && segment->p_align >= 4)
++	  if (!*osversion && read32(segment->p_filesz, be) >= 32 && segment->p_align >= 4)
+ 	    {
+ 	      Elf32_Word *abi_note = (Elf32_Word *) (file_contents
+-						     + segment->p_offset);
+-	      Elf32_Addr size = segment->p_filesz;
++						     + read32(segment->p_offset, be));
++	      Elf32_Addr size = read32(segment->p_filesz, be);
+ 
+-	      while (abi_note [0] != 4 || abi_note [1] != 16
+-		     || abi_note [2] != 1
++	      while (read32(abi_note [0], be) != 4 || read32(abi_note [1], be) != 16
++		     || read32(abi_note [2], be) != 1
+ 		     || memcmp (abi_note + 3, "GNU", 4) != 0)
+ 		{
+-#define ROUND(len) (((len) + sizeof (Elf32_Word)) - 1) & -sizeof (Elf32_Word)))
+-		  Elf32_Addr) note_size = 3 * sizeof (Elf32_Word))
+-					 + ROUND (abi_note[0])
+-					 + ROUND (abi_note[1]);
++#define ROUND(len) (((len) + sizeof (Elf32_Word) - 1) & -sizeof (Elf32_Word))
++		  Elf32_Addr note_size = 3 * sizeof (Elf32_Word)
++					 + ROUND (read32(abi_note[0], be))
++					 + ROUND (read32(abi_note[1], be));
+ 
+ 		  if (size - 32 < note_size || note_size == 0)
+ 		    {
+@@ -140,10 +164,10 @@ process_elf_file32 (const char *file_nam
+ 	      if (size == 0)
+ 		break;
+ 
+-	      *osversion = (abi_note [4] << 24) |
+-			   ((abi_note [5] & 0xff) << 16) |
+-			   ((abi_note [6] & 0xff) << 8) |
+-			   (abi_note [7] & 0xff);
++	      *osversion = (read32(abi_note [4], be) << 24) |
++			   ((read32(abi_note [5], be) & 0xff) << 16) |
++			   ((read32(abi_note [6], be) & 0xff) << 8) |
++			   (read32(abi_note [7], be) & 0xff);
+ 	    }
+ 	  break;
+ 
+@@ -167,13 +191,13 @@ process_elf_file32 (const char *file_nam
+ 
+   /* Find the string table.  */
+   dynamic_strings = NULL;
+-  for (dyn_entry = dynamic_segment; dyn_entry->d_tag != DT_NULL;
++  for (dyn_entry = dynamic_segment; read32(dyn_entry->d_tag, be) != DT_NULL;
+        ++dyn_entry)
+     {
+       check_ptr (dyn_entry);
+-      if (dyn_entry->d_tag == DT_STRTAB)
++      if (read32(dyn_entry->d_tag, be) == DT_STRTAB)
+ 	{
+-	  dynamic_strings = (char *) (file_contents + dyn_entry->d_un.d_val - loadaddr);
++	  dynamic_strings = (char *) (file_contents + read32(dyn_entry->d_un.d_val, be) - loadaddr);
+ 	  check_ptr (dynamic_strings);
+ 	  break;
+ 	}
+@@ -183,15 +207,15 @@ process_elf_file32 (const char *file_nam
+     return 1;
+ 
+   /* Now read the DT_NEEDED and DT_SONAME entries.  */
+-  for (dyn_entry = dynamic_segment; dyn_entry->d_tag != DT_NULL;
++  for (dyn_entry = dynamic_segment; read32(dyn_entry->d_tag, be) != DT_NULL;
+        ++dyn_entry)
+     {
+-      if (dyn_entry->d_tag == DT_NEEDED || dyn_entry->d_tag == DT_SONAME)
++      if (read32(dyn_entry->d_tag, be) == DT_NEEDED || read32(dyn_entry->d_tag, be) == DT_SONAME)
+ 	{
+-	  char *name = dynamic_strings + dyn_entry->d_un.d_val;
++	  char *name = dynamic_strings + read32(dyn_entry->d_un.d_val, be);
+ 	  check_ptr (name);
+ 
+-	  if (dyn_entry->d_tag == DT_NEEDED)
++	  if (read32(dyn_entry->d_tag, be) == DT_NEEDED)
+ 	    {
+ 
+ 	      if (*flag == FLAG_ELF)
+@@ -208,7 +232,7 @@ process_elf_file32 (const char *file_nam
+ 		}
+ 	    }
+ 
+-	  else if (dyn_entry->d_tag == DT_SONAME)
++	  else if (read32(dyn_entry->d_tag, be) == DT_SONAME)
+ 	    *soname = xstrdup (name);
+ 
+ 	  /* Do we have everything we need?  */
+@@ -246,15 +270,17 @@ process_elf_file64 (const char *file_nam
+   elf_header = (Elf64_Ehdr *) file_contents;
+   *osversion = 0;
+ 
+-  if (elf_header->e_type != ET_DYN)
++  be = (elf_header->e_ident[EI_DATA] == ELFDATA2MSB);
++
++  if (read16(elf_header->e_type, be) != ET_DYN)
+     {
+       error (0, 0, _("%s is not a shared object file (Type: %d).\n"), file_name,
+-	     elf_header->e_type);
++	     read16(elf_header->e_type, be));
+       return 1;
+     }
+ 
+   /* Get information from elf program header.  */
+-  elf_pheader = (Elf64_Phdr *) (elf_header->e_phoff + file_contents);
++  elf_pheader = (Elf64_Phdr *) (read64(elf_header->e_phoff, be) + file_contents);
+   check_ptr (elf_pheader);
+ 
+   /* The library is an elf library, now search for soname and
+@@ -266,27 +292,27 @@ process_elf_file64 (const char *file_nam
+   dynamic_size = 0;
+   program_interpreter = NULL;
+   for (i = 0, segment = elf_pheader;
+-       i < elf_header->e_phnum; i++, segment++)
++       i < read16(elf_header->e_phnum, be); i++, segment++)
+     {
+       check_ptr (segment);
+ 
+-      switch (segment->p_type)
++      switch (read32(segment->p_type, be))
+ 	{
+ 	case PT_LOAD:
+ 	  if (loadaddr == (Elf64_Addr) -1)
+-	    loadaddr = segment->p_vaddr - segment->p_offset;
++	    loadaddr = read64(segment->p_vaddr, be) - read64(segment->p_offset, be);
+ 	  break;
+ 
+ 	case PT_DYNAMIC:
+ 	  if (dynamic_addr)
+ 	    error (0, 0, _("more than one dynamic segment\n"));
+ 
+-	  dynamic_addr = segment->p_offset;
+-	  dynamic_size = segment->p_filesz;
++	  dynamic_addr = read64(segment->p_offset, be);
++	  dynamic_size = read32(segment->p_filesz, be);
+ 	  break;
+ 
+ 	case PT_INTERP:
+-	  program_interpreter = (char *) (file_contents + segment->p_offset);
++	  program_interpreter = (char *) (file_contents + read64(segment->p_offset, be));
+ 	  check_ptr (program_interpreter);
+ 
+ 	  /* Check if this is enough to classify the binary.  */
+@@ -300,20 +326,21 @@ process_elf_file64 (const char *file_nam
+ 	  break;
+ 
+ 	case PT_NOTE:
+-	  if (!*osversion && segment->p_filesz >= 32 && segment->p_align >= 4)
++	  if (!*osversion && read32(segment->p_filesz, be) >= 32 && read32(segment->p_align, be) >= 4)
+ 	    {
+ 	      Elf64_Word *abi_note = (Elf64_Word *) (file_contents
+-						     + segment->p_offset);
+-	      Elf64_Addr size = segment->p_filesz;
++						     + read64(segment->p_offset, be));
++	      Elf64_Addr size = read32(segment->p_filesz, be);
+ 
+-	      while (abi_note [0] != 4 || abi_note [1] != 16
+-		     || abi_note [2] != 1
++	      while (read32(abi_note [0], be) != 4 || read32(abi_note [1], be) != 16
++		     || read32(abi_note [2], be) != 1
+ 		     || memcmp (abi_note + 3, "GNU", 4) != 0)
+ 		{
++#undef ROUND
+ #define ROUND(len) (((len) + sizeof (Elf64_Word) - 1) & -sizeof (Elf64_Word))
+ 		  Elf64_Addr note_size = 3 * sizeof (Elf64_Word)
+-					 + ROUND (abi_note[0])
+-					 + ROUND (abi_note[1]);
++					 + ROUND (read32(abi_note[0], be))
++					 + ROUND (read32(abi_note[1], be));
+ 
+ 		  if (size - 32 < note_size || note_size == 0)
+ 		    {
+@@ -327,10 +354,10 @@ process_elf_file64 (const char *file_nam
+ 	      if (size == 0)
+ 		break;
+ 
+-	      *osversion = (abi_note [4] << 24) |
+-			   ((abi_note [5] & 0xff) << 16) |
+-			   ((abi_note [6] & 0xff) << 8) |
+-			   (abi_note [7] & 0xff);
++	      *osversion = (read32(abi_note [4], be) << 24) |
++			   ((read32(abi_note [5], be) & 0xff) << 16) |
++			   ((read32(abi_note [6], be) & 0xff) << 8) |
++			   (read32(abi_note [7], be) & 0xff);
+ 	    }
+ 	  break;
+ 
+@@ -354,13 +381,13 @@ process_elf_file64 (const char *file_nam
+ 
+   /* Find the string table.  */
+   dynamic_strings = NULL;
+-  for (dyn_entry = dynamic_segment; dyn_entry->d_tag != DT_NULL;
++  for (dyn_entry = dynamic_segment; read64(dyn_entry->d_tag, be) != DT_NULL;
+        ++dyn_entry)
+     {
+       check_ptr (dyn_entry);
+-      if (dyn_entry->d_tag == DT_STRTAB)
++      if (read64(dyn_entry->d_tag, be) == DT_STRTAB)
+ 	{
+-	  dynamic_strings = (char *) (file_contents + dyn_entry->d_un.d_val - loadaddr);
++	  dynamic_strings = (char *) (file_contents + read64(dyn_entry->d_un.d_val, be) - loadaddr);
+ 	  check_ptr (dynamic_strings);
+ 	  break;
+ 	}
+@@ -370,15 +397,15 @@ process_elf_file64 (const char *file_nam
+     return 1;
+ 
+   /* Now read the DT_NEEDED and DT_SONAME entries.  */
+-  for (dyn_entry = dynamic_segment; dyn_entry->d_tag != DT_NULL;
++  for (dyn_entry = dynamic_segment; read64(dyn_entry->d_tag, be) != DT_NULL;
+        ++dyn_entry)
+     {
+-      if (dyn_entry->d_tag == DT_NEEDED || dyn_entry->d_tag == DT_SONAME)
++      if (read64(dyn_entry->d_tag, be) == DT_NEEDED || read64(dyn_entry->d_tag, be) == DT_SONAME)
+ 	{
+-	  char *name = dynamic_strings + dyn_entry->d_un.d_val;
++	  char *name = dynamic_strings + read64(dyn_entry->d_un.d_val, be);
+ 	  check_ptr (name);
+ 
+-	  if (dyn_entry->d_tag == DT_NEEDED)
++	  if (read64(dyn_entry->d_tag, be) == DT_NEEDED)
+ 	    {
+ 
+ 	      if (*flag == FLAG_ELF)
+@@ -395,7 +422,7 @@ process_elf_file64 (const char *file_nam
+ 		}
+ 	    }
+ 
+-	  else if (dyn_entry->d_tag == DT_SONAME)
++	  else if (read64(dyn_entry->d_tag, be) == DT_SONAME)
+ 	    *soname = xstrdup (name);
+ 
+ 	  /* Do we have everything we need?  */
+Index: ldconfig-native-2.12.1/readlib.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/readlib.c
++++ ldconfig-native-2.12.1/readlib.c
+@@ -169,7 +169,8 @@ process_file (const char *real_file_name
+       ret = 1;
+     }
+   /* Libraries have to be shared object files.  */
+-  else if (elf_header->e_type != ET_DYN)
++  else if ((elf_header->e_ident[EI_DATA] == ELFDATA2MSB && be16toh(elf_header->e_type) != ET_DYN) ||
++      (elf_header->e_ident[EI_DATA] == ELFDATA2LSB && le16toh(elf_header->e_type) != ET_DYN))
+     ret = 1;
+   else if (process_elf_file (file_name, lib, flag, osversion, soname,
+ 			     file_contents, statbuf.st_size))
+Index: ldconfig-native-2.12.1/cache.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/cache.c
++++ ldconfig-native-2.12.1/cache.c
+@@ -39,6 +39,29 @@
+ # define N_(msgid)  msgid
+ #define _(msg) msg
+ 
++extern int be;
++
++static uint16_t write16(uint16_t x, int be)
++{
++  if (be)
++        return htobe16(x);
++  return htole16(x);
++}
++
++static uint32_t write32(uint32_t x, int be)
++{
++  if (be)
++        return htobe32(x);
++  return htole32(x);
++}
++
++static uint64_t write64(uint64_t x, int be)
++{
++  if (be)
++        return htobe64(x);
++  return htole64(x);
++}
++
+ struct cache_entry
+ {
+   char *lib;			/* Library name.  */
+@@ -279,7 +302,12 @@ save_cache (const char *cache_name)
+   /* Number of normal cache entries.  */
+   int cache_entry_old_count = 0;
+ 
+-  for (entry = entries; entry != NULL; entry = entry->next)
++    if (be)
++      printf("saving cache in big endian encoding\n");
++    else
++      printf("saving cache in little endian encoding\n");
++
++    for (entry = entries; entry != NULL; entry = entry->next)
+     {
+       /* Account the final NULs.  */
+       total_strlen += strlen (entry->lib) + strlen (entry->path) + 2;
+@@ -310,7 +338,7 @@ save_cache (const char *cache_name)
+       memset (file_entries, '\0', sizeof (struct cache_file));
+       memcpy (file_entries->magic, CACHEMAGIC, sizeof CACHEMAGIC - 1);
+ 
+-      file_entries->nlibs = cache_entry_old_count;
++      file_entries->nlibs = write32(cache_entry_old_count, be);
+     }
+ 
+   struct cache_file_new *file_entries_new = NULL;
+@@ -330,8 +358,8 @@ save_cache (const char *cache_name)
+       memcpy (file_entries_new->version, CACHE_VERSION,
+ 	      sizeof CACHE_VERSION - 1);
+ 
+-      file_entries_new->nlibs = cache_entry_count;
+-      file_entries_new->len_strings = total_strlen;
++      file_entries_new->nlibs = write32(cache_entry_count, be);
++      file_entries_new->len_strings = write32(total_strlen, be);
+     }
+ 
+   /* Pad for alignment of cache_file_new.  */
+@@ -358,9 +386,9 @@ save_cache (const char *cache_name)
+       /* First the library.  */
+       if (opt_format != 2 && entry->hwcap == 0)
+ 	{
+-	  file_entries->libs[idx_old].flags = entry->flags;
++	  file_entries->libs[idx_old].flags = write32(entry->flags, be);
+ 	  /* XXX: Actually we can optimize here and remove duplicates.  */
+-	  file_entries->libs[idx_old].key = str_offset + pad;
++	  file_entries->libs[idx_old].key = write32(str_offset + pad, be);
+ 	}
+       if (opt_format != 0)
+ 	{
+@@ -368,10 +396,10 @@ save_cache (const char *cache_name)
+ 	     not doing so makes the code easier, the string table
+ 	     always begins at the beginning of the the new cache
+ 	     struct.  */
+-	  file_entries_new->libs[idx_new].flags = entry->flags;
+-	  file_entries_new->libs[idx_new].osversion = entry->osversion;
+-	  file_entries_new->libs[idx_new].hwcap = entry->hwcap;
+-	  file_entries_new->libs[idx_new].key = str_offset;
++	  file_entries_new->libs[idx_new].flags = write32(entry->flags, be);
++	  file_entries_new->libs[idx_new].osversion = write32(entry->osversion, be);
++	  file_entries_new->libs[idx_new].hwcap = write64(entry->hwcap, be);
++	  file_entries_new->libs[idx_new].key = write32(str_offset, be);
+ 	}
+ 
+       size_t len = strlen (entry->lib) + 1;
+@@ -379,9 +407,9 @@ save_cache (const char *cache_name)
+       str_offset += len;
+       /* Then the path.  */
+       if (opt_format != 2 && entry->hwcap == 0)
+-	file_entries->libs[idx_old].value = str_offset + pad;
++	file_entries->libs[idx_old].value = write32(str_offset + pad, be);
+       if (opt_format != 0)
+-	file_entries_new->libs[idx_new].value = str_offset;
++	file_entries_new->libs[idx_new].value = write32(str_offset, be);
+       len = strlen (entry->path) + 1;
+       str = mempcpy (str, entry->path, len);
+       str_offset += len;

+ 47 - 0
recipes-core/glibc/ldconfig-native-2.12.1/endian-ness_handling_fix.patch

@@ -0,0 +1,47 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+Fix problem during parsing of ELF headers for 64bit on big-endian.
+Some header fields were read with wrong size.
+
+2014/10/24
+Par Olsson <Par.Olsson@windriver.com>
+Shan Hai <shan.hai@windriver.com>
+
+diff --git a/readelflib.c b/readelflib.c
+index 3f5b25b..0bf0de3 100644
+--- a/readelflib.c
++++ b/readelflib.c
+@@ -261,8 +261,8 @@ process_elf_file64 (const char *file_name, const char *lib, int *flag,
+   int i;
+   unsigned int j;
+   Elf64_Addr loadaddr;
+-  unsigned int dynamic_addr;
+-  size_t dynamic_size;
++  Elf64_Addr dynamic_addr;
++  Elf64_Xword dynamic_size;
+   char *program_interpreter;
+ 
+   Elf64_Ehdr *elf_header;
+@@ -311,7 +311,7 @@ process_elf_file64 (const char *file_name, const char *lib, int *flag,
+ 	    error (0, 0, _("more than one dynamic segment\n"));
+ 
+ 	  dynamic_addr = read64(segment->p_offset, be);
+-	  dynamic_size = read32(segment->p_filesz, be);
++	  dynamic_size = read64(segment->p_filesz, be);
+ 	  break;
+ 
+ 	case PT_INTERP:
+@@ -329,11 +329,11 @@ process_elf_file64 (const char *file_name, const char *lib, int *flag,
+ 	  break;
+ 
+ 	case PT_NOTE:
+-	  if (!*osversion && read32(segment->p_filesz, be) >= 32 && read32(segment->p_align, be) >= 4)
++	  if (!*osversion && read64(segment->p_filesz, be) >= 32 && read64(segment->p_align, be) >= 4)
+ 	    {
+ 	      Elf64_Word *abi_note = (Elf64_Word *) (file_contents
+ 						     + read64(segment->p_offset, be));
+-	      Elf64_Addr size = read32(segment->p_filesz, be);
++	      Elf64_Xword size = read64(segment->p_filesz, be);
+ 
+ 	      while (read32(abi_note [0], be) != 4 || read32(abi_note [1], be) != 16
+ 		     || read32(abi_note [2], be) != 1

+ 113 - 0
recipes-core/glibc/ldconfig-native-2.12.1/endianess-header.patch

@@ -0,0 +1,113 @@
+Upstream-Status: Inappropriate [fix poky patch]
+
+This patch fixes build issues with a previous endian-ness_handling.patch on
+distros that don't have macros referenced
+
+7/20/2011
+Matthew McClintock <msm@freescale.com>
+
+diff -purN ldconfig-native-2.12.1.orig/endian_extra.h ldconfig-native-2.12.1/endian_extra.h
+--- ldconfig-native-2.12.1.orig/endian_extra.h	1969-12-31 18:00:00.000000000 -0600
++++ ldconfig-native-2.12.1/endian_extra.h	2011-07-19 18:09:14.323048417 -0500
+@@ -0,0 +1,64 @@
++/* Copyright (C) 1992, 1996, 1997, 2000, 2008 Free Software Foundation, Inc.
++   This file is part of the GNU C Library.
++
++   The GNU C Library is free software; you can redistribute it and/or
++   modify it under the terms of the GNU Lesser General Public
++   License as published by the Free Software Foundation; either
++   version 2.1 of the License, or (at your option) any later version.
++
++   The GNU C Library is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++   Lesser General Public License for more details.
++
++   You should have received a copy of the GNU Lesser General Public
++   License along with the GNU C Library; if not, write to the Free
++   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
++   02111-1307 USA.  */
++
++#include <endian.h>
++
++#ifndef	_ENDIAN_EXTRA_H
++#define	_ENDIAN_EXTRA_H	1
++
++/* Don't redefine these macros if they already exist */
++#ifndef htobe16
++#ifdef __USE_BSD
++/* Conversion interfaces.  */
++# include <byteswap.h>
++
++# if __BYTE_ORDER == __LITTLE_ENDIAN
++#  define htobe16(x) __bswap_16 (x)
++#  define htole16(x) (x)
++#  define be16toh(x) __bswap_16 (x)
++#  define le16toh(x) (x)
++
++#  define htobe32(x) __bswap_32 (x)
++#  define htole32(x) (x)
++#  define be32toh(x) __bswap_32 (x)
++#  define le32toh(x) (x)
++
++#  define htobe64(x) __bswap_64 (x)
++#  define htole64(x) (x)
++#  define be64toh(x) __bswap_64 (x)
++#  define le64toh(x) (x)
++# else
++#  define htobe16(x) (x)
++#  define htole16(x) __bswap_16 (x)
++#  define be16toh(x) (x)
++#  define le16toh(x) __bswap_16 (x)
++
++#  define htobe32(x) (x)
++#  define htole32(x) __bswap_32 (x)
++#  define be32toh(x) (x)
++#  define le32toh(x) __bswap_32 (x)
++
++#  define htobe64(x) (x)
++#  define htole64(x) __bswap_64 (x)
++#  define be64toh(x) (x)
++#  define le64toh(x) __bswap_64 (x)
++# endif
++#endif
++#endif
++
++#endif	/* endian_extra.h */
+diff -purN ldconfig-native-2.12.1.orig/cache.c ldconfig-native-2.12.1/cache.c
+--- ldconfig-native-2.12.1.orig/cache.c	2011-07-19 18:21:28.347041301 -0500
++++ ldconfig-native-2.12.1/cache.c	2011-07-19 18:22:54.118048064 -0500
+@@ -39,6 +39,8 @@
+ # define N_(msgid)  msgid
+ #define _(msg) msg
+ 
++#include "endian_extra.h"
++
+ extern int be;
+ 
+ static uint16_t write16(uint16_t x, int be)
+diff -purN ldconfig-native-2.12.1.orig/readelflib.c ldconfig-native-2.12.1/readelflib.c
+--- ldconfig-native-2.12.1.orig/readelflib.c	2011-07-19 18:21:28.346041593 -0500
++++ ldconfig-native-2.12.1/readelflib.c	2011-07-19 18:23:05.324059875 -0500
+@@ -25,6 +25,9 @@
+ 
+ /* check_ptr checks that a pointer is in the mmaped file and doesn't
+    point outside it.  */
++
++#include "endian_extra.h"
++
+ #undef check_ptr
+ #define check_ptr(ptr)						\
+ do								\
+diff -purN ldconfig-native-2.12.1.orig/readlib.c ldconfig-native-2.12.1/readlib.c
+--- ldconfig-native-2.12.1.orig/readlib.c	2011-07-19 18:21:28.346041593 -0500
++++ ldconfig-native-2.12.1/readlib.c	2011-07-19 18:23:23.877046210 -0500
+@@ -40,6 +40,8 @@
+ 
+ #include "ldconfig.h"
+ 
++#include "endian_extra.h"
++
+ #define _(msg) msg
+ 
+ #define Elf32_CLASS ELFCLASS32

+ 24 - 0
recipes-core/glibc/ldconfig-native-2.12.1/flag_fix.patch

@@ -0,0 +1,24 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+The native version of ldconfig was using native definition of LD_SO (i.e. 
+ld-linux-x86-64.so.2 ) which is not correct for doing the cross ldconfig.
+This was causing libc.so on the target marked as ELF lib rather than 
+FLAG_ELF_LIBC6 in the ld.so.cache.
+
+Nitin A Kamble <nitin.a.kamble@intel.com> 2011/04/4
+
+Index: ldconfig-native-2.12.1/readlib.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/readlib.c
++++ ldconfig-native-2.12.1/readlib.c
+@@ -51,6 +51,10 @@ struct known_names
+   int flag;
+ };
+ 
++/* don't use host's definition of LD_SO */
++#undef LD_SO 
++#define LD_SO "ld.so.1"
++
+ static struct known_names interpreters[] =
+ {
+   { "/lib/" LD_SO, FLAG_ELF_LIBC6 },

+ 37 - 0
recipes-core/glibc/ldconfig-native-2.12.1/ldconfig-default-to-all-multilib-dirs.patch

@@ -0,0 +1,37 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+make ldconfig default to both /lib+/usr/lib, /lib32+/usr/lib32 and
+/lib64+/usr/lib64 on bi-ABI architectures.
+
+---
+ ldconfig.c |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff -urpN a/ldconfig.c b/ldconfig.c
+--- a/ldconfig.c
++++ b/ldconfig.c
+@@ -52,7 +52,11 @@
+ 
+ #define SYSCONFDIR "/etc"
+ #define LIBDIR "/usr/lib"
++#define LIBDIR32 "/usr/lib32"
++#define LIBDIR64 "/usr/lib64"
+ #define SLIBDIR "/lib"
++#define SLIBDIR32 "/lib32"
++#define SLIBDIR64 "/lib64"
+ # define N_(msgid)  msgid
+ #define _(msg) msg
+ 
+@@ -1373,6 +1377,12 @@ main (int argc, char **argv)
+       add_system_dir (SLIBDIR);
+       if (strcmp (SLIBDIR, LIBDIR))
+ 	add_system_dir (LIBDIR);
++      add_system_dir (SLIBDIR32);
++      if (strcmp (SLIBDIR32, LIBDIR32))
++	add_system_dir (LIBDIR32);
++      add_system_dir (SLIBDIR64);
++      if (strcmp (SLIBDIR64, LIBDIR64))
++	add_system_dir (LIBDIR64);
+     }
+ 
+   const char *aux_cache_file = _PATH_LDCONFIG_AUX_CACHE;

BIN
recipes-core/glibc/ldconfig-native-2.12.1/ldconfig-native-2.12.1.tar.bz2


+ 471 - 0
recipes-core/glibc/ldconfig-native-2.12.1/ldconfig.patch

@@ -0,0 +1,471 @@
+Upstream-Status: Inappropriate [embedded specific]
+
+enable standalone building of ldconfig
+
+---
+ cache.c        |   11 +-
+ chroot_canon.c |    7 +
+ dl-cache.c     |  235 ---------------------------------------------------------
+ dl-cache.h     |    3 
+ ldconfig.c     |   27 ++++--
+ readlib.c      |    7 +
+ xstrdup.c      |   11 --
+ 7 files changed, 45 insertions(+), 256 deletions(-)
+
+Index: ldconfig-native-2.12.1/cache.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/cache.c
++++ ldconfig-native-2.12.1/cache.c
+@@ -16,6 +16,9 @@
+    along with this program; if not, write to the Free Software Foundation,
+    Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
++#define _LARGEFILE64_SOURCE
++#define _GNU_SOURCE
++
+ #include <errno.h>
+ #include <error.h>
+ #include <dirent.h>
+@@ -31,8 +34,10 @@
+ #include <sys/stat.h>
+ #include <sys/types.h>
+ 
+-#include <ldconfig.h>
+-#include <dl-cache.h>
++#include "ldconfig.h"
++#include "dl-cache.h"
++# define N_(msgid)  msgid
++#define _(msg) msg
+ 
+ struct cache_entry
+ {
+Index: ldconfig-native-2.12.1/chroot_canon.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/chroot_canon.c
++++ ldconfig-native-2.12.1/chroot_canon.c
+@@ -17,6 +17,9 @@
+    along with this program; if not, write to the Free Software Foundation,
+    Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
++#define _LARGEFILE64_SOURCE
++#define _GNU_SOURCE
++
+ #include <stdlib.h>
+ #include <string.h>
+ #include <unistd.h>
+@@ -27,7 +30,9 @@
+ #include <stddef.h>
+ #include <stdint.h>
+ 
+-#include <ldconfig.h>
++#include "ldconfig.h"
++
++#define __set_errno(Val) errno = (Val)
+ 
+ #ifndef PATH_MAX
+ #define PATH_MAX 1024
+Index: ldconfig-native-2.12.1/dl-cache.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/dl-cache.c
++++ ldconfig-native-2.12.1/dl-cache.c
+@@ -20,12 +20,12 @@
+ 
+ #include <assert.h>
+ #include <unistd.h>
+-#include <ldsodefs.h>
++//#include "ldsodefs.h"
+ #include <sys/mman.h>
+ #include <dl-cache.h>
+ #include <dl-procinfo.h>
+ 
+-#include <stdio-common/_itoa.h>
++//#include "_itoa.h"
+ 
+ #ifndef _DL_PLATFORMS_COUNT
+ # define _DL_PLATFORMS_COUNT 0
+@@ -39,103 +39,7 @@ static size_t cachesize;
+ /* 1 if cache_data + PTR points into the cache.  */
+ #define _dl_cache_verify_ptr(ptr) (ptr < cache_data_size)
+ 
+-#define SEARCH_CACHE(cache) \
+-/* We use binary search since the table is sorted in the cache file.	      \
+-   The first matching entry in the table is returned.			      \
+-   It is important to use the same algorithm as used while generating	      \
+-   the cache file.  */							      \
+-do									      \
+-  {									      \
+-    left = 0;								      \
+-    right = cache->nlibs - 1;						      \
+-									      \
+-    while (left <= right)						      \
+-      {									      \
+-	__typeof__ (cache->libs[0].key) key;				      \
+-									      \
+-	middle = (left + right) / 2;					      \
+-									      \
+-	key = cache->libs[middle].key;					      \
+-									      \
+-	/* Make sure string table indices are not bogus before using	      \
+-	   them.  */							      \
+-	if (! _dl_cache_verify_ptr (key))				      \
+-	  {								      \
+-	    cmpres = 1;							      \
+-	    break;							      \
+-	  }								      \
+-									      \
+-	/* Actually compare the entry with the key.  */			      \
+-	cmpres = _dl_cache_libcmp (name, cache_data + key);		      \
+-	if (__builtin_expect (cmpres == 0, 0))				      \
+-	  {								      \
+-	    /* Found it.  LEFT now marks the last entry for which we	      \
+-	       know the name is correct.  */				      \
+-	    left = middle;						      \
+-									      \
+-	    /* There might be entries with this name before the one we	      \
+-	       found.  So we have to find the beginning.  */		      \
+-	    while (middle > 0)						      \
+-	      {								      \
+-		__typeof__ (cache->libs[0].key) key;			      \
+-									      \
+-		key = cache->libs[middle - 1].key;			      \
+-		/* Make sure string table indices are not bogus before	      \
+-		   using them.  */					      \
+-		if (! _dl_cache_verify_ptr (key)			      \
+-		    /* Actually compare the entry.  */			      \
+-		    || _dl_cache_libcmp (name, cache_data + key) != 0)	      \
+-		  break;						      \
+-		--middle;						      \
+-	      }								      \
+-									      \
+-	    do								      \
+-	      {								      \
+-		int flags;						      \
+-		__typeof__ (cache->libs[0]) *lib = &cache->libs[middle];      \
+-									      \
+-		/* Only perform the name test if necessary.  */		      \
+-		if (middle > left					      \
+-		    /* We haven't seen this string so far.  Test whether the  \
+-		       index is ok and whether the name matches.  Otherwise   \
+-		       we are done.  */					      \
+-		    && (! _dl_cache_verify_ptr (lib->key)		      \
+-			|| (_dl_cache_libcmp (name, cache_data + lib->key)    \
+-			    != 0)))					      \
+-		  break;						      \
+-									      \
+-		flags = lib->flags;					      \
+-		if (_dl_cache_check_flags (flags)			      \
+-		    && _dl_cache_verify_ptr (lib->value))		      \
+-		  {							      \
+-		    if (best == NULL || flags == GLRO(dl_correct_cache_id))   \
+-		      {							      \
+-			HWCAP_CHECK;					      \
+-			best = cache_data + lib->value;			      \
+-									      \
+-			if (flags == GLRO(dl_correct_cache_id))		      \
+-			  /* We've found an exact match for the shared	      \
+-			     object and no general `ELF' release.  Stop	      \
+-			     searching.  */				      \
+-			  break;					      \
+-		      }							      \
+-		  }							      \
+-	      }								      \
+-	    while (++middle <= right);					      \
+-	    break;							      \
+-	}								      \
+-									      \
+-	if (cmpres < 0)							      \
+-	  left = middle + 1;						      \
+-	else								      \
+-	  right = middle - 1;						      \
+-      }									      \
+-  }									      \
+-while (0)
+-
+-
+ int
+-internal_function
+ _dl_cache_libcmp (const char *p1, const char *p2)
+ {
+   while (*p1 != '\0')
+@@ -172,139 +76,3 @@ _dl_cache_libcmp (const char *p1, const 
+     }
+   return *p1 - *p2;
+ }
+-
+-
+-/* Look up NAME in ld.so.cache and return the file name stored there,
+-   or null if none is found.  */
+-
+-const char *
+-internal_function
+-_dl_load_cache_lookup (const char *name)
+-{
+-  int left, right, middle;
+-  int cmpres;
+-  const char *cache_data;
+-  uint32_t cache_data_size;
+-  const char *best;
+-
+-  /* Print a message if the loading of libs is traced.  */
+-  if (__builtin_expect (GLRO_dl_debug_mask & DL_DEBUG_LIBS, 0))
+-    _dl_debug_printf (" search cache=%s\n", LD_SO_CACHE);
+-
+-  if (cache == NULL)
+-    {
+-      /* Read the contents of the file.  */
+-      void *file = _dl_sysdep_read_whole_file (LD_SO_CACHE, &cachesize,
+-					       PROT_READ);
+-
+-      /* We can handle three different cache file formats here:
+-	 - the old libc5/glibc2.0/2.1 format
+-	 - the old format with the new format in it
+-	 - only the new format
+-	 The following checks if the cache contains any of these formats.  */
+-      if (file != MAP_FAILED && cachesize > sizeof *cache
+-	  && memcmp (file, CACHEMAGIC, sizeof CACHEMAGIC - 1) == 0)
+-	{
+-	  size_t offset;
+-	  /* Looks ok.  */
+-	  cache = file;
+-
+-	  /* Check for new version.  */
+-	  offset = ALIGN_CACHE (sizeof (struct cache_file)
+-				+ cache->nlibs * sizeof (struct file_entry));
+-
+-	  cache_new = (struct cache_file_new *) ((void *) cache + offset);
+-	  if (cachesize < (offset + sizeof (struct cache_file_new))
+-	      || memcmp (cache_new->magic, CACHEMAGIC_VERSION_NEW,
+-			 sizeof CACHEMAGIC_VERSION_NEW - 1) != 0)
+-	    cache_new = (void *) -1;
+-	}
+-      else if (file != MAP_FAILED && cachesize > sizeof *cache_new
+-	       && memcmp (file, CACHEMAGIC_VERSION_NEW,
+-			  sizeof CACHEMAGIC_VERSION_NEW - 1) == 0)
+-	{
+-	  cache_new = file;
+-	  cache = file;
+-	}
+-      else
+-	{
+-	  if (file != MAP_FAILED)
+-	    __munmap (file, cachesize);
+-	  cache = (void *) -1;
+-	}
+-
+-      assert (cache != NULL);
+-    }
+-
+-  if (cache == (void *) -1)
+-    /* Previously looked for the cache file and didn't find it.  */
+-    return NULL;
+-
+-  best = NULL;
+-
+-  if (cache_new != (void *) -1)
+-    {
+-      uint64_t platform;
+-
+-      /* This is where the strings start.  */
+-      cache_data = (const char *) cache_new;
+-
+-      /* Now we can compute how large the string table is.  */
+-      cache_data_size = (const char *) cache + cachesize - cache_data;
+-
+-      platform = _dl_string_platform (GLRO(dl_platform));
+-      if (platform != (uint64_t) -1)
+-	platform = 1ULL << platform;
+-
+-#define _DL_HWCAP_TLS_MASK (1LL << 63)
+-      uint64_t hwcap_exclude = ~((GLRO(dl_hwcap) & GLRO(dl_hwcap_mask))
+-				 | _DL_HWCAP_PLATFORM | _DL_HWCAP_TLS_MASK);
+-
+-      /* Only accept hwcap if it's for the right platform.  */
+-#define HWCAP_CHECK \
+-      if (lib->hwcap & hwcap_exclude)					      \
+-	continue;							      \
+-      if (GLRO(dl_osversion) && lib->osversion > GLRO(dl_osversion))	      \
+-	continue;							      \
+-      if (_DL_PLATFORMS_COUNT						      \
+-	  && (lib->hwcap & _DL_HWCAP_PLATFORM) != 0			      \
+-	  && (lib->hwcap & _DL_HWCAP_PLATFORM) != platform)		      \
+-	continue
+-      SEARCH_CACHE (cache_new);
+-    }
+-  else
+-    {
+-      /* This is where the strings start.  */
+-      cache_data = (const char *) &cache->libs[cache->nlibs];
+-
+-      /* Now we can compute how large the string table is.  */
+-      cache_data_size = (const char *) cache + cachesize - cache_data;
+-
+-#undef HWCAP_CHECK
+-#define HWCAP_CHECK do {} while (0)
+-      SEARCH_CACHE (cache);
+-    }
+-
+-  /* Print our result if wanted.  */
+-  if (__builtin_expect (GLRO_dl_debug_mask & DL_DEBUG_LIBS, 0)
+-      && best != NULL)
+-    _dl_debug_printf ("  trying file=%s\n", best);
+-
+-  return best;
+-}
+-
+-#ifndef MAP_COPY
+-/* If the system does not support MAP_COPY we cannot leave the file open
+-   all the time since this would create problems when the file is replaced.
+-   Therefore we provide this function to close the file and open it again
+-   once needed.  */
+-void
+-_dl_unload_cache (void)
+-{
+-  if (cache != NULL && cache != (struct cache_file *) -1)
+-    {
+-      __munmap (cache, cachesize);
+-      cache = NULL;
+-    }
+-}
+-#endif
+Index: ldconfig-native-2.12.1/dl-cache.h
+===================================================================
+--- ldconfig-native-2.12.1.orig/dl-cache.h
++++ ldconfig-native-2.12.1/dl-cache.h
+@@ -101,5 +101,4 @@ struct cache_file_new
+ (((addr) + __alignof__ (struct cache_file_new) -1)	\
+  & (~(__alignof__ (struct cache_file_new) - 1)))
+ 
+-extern int _dl_cache_libcmp (const char *p1, const char *p2)
+-     internal_function;
++extern int _dl_cache_libcmp (const char *p1, const char *p2);
+Index: ldconfig-native-2.12.1/ldconfig.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/ldconfig.c
++++ ldconfig-native-2.12.1/ldconfig.c
+@@ -16,6 +16,9 @@
+    along with this program; if not, write to the Free Software Foundation,
+    Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
++#define _LARGEFILE64_SOURCE
++#define _GNU_SOURCE
++
+ #define PROCINFO_CLASS static
+ #include <alloca.h>
+ #include <argp.h>
+@@ -39,10 +42,20 @@
+ #include <glob.h>
+ #include <libgen.h>
+ 
+-#include <ldconfig.h>
+-#include <dl-cache.h>
++#include "ldconfig.h"
++#include "dl-cache.h"
++
++#include "dl-procinfo.h"
++
++#include "argp.h"
++
++
++#define SYSCONFDIR "/etc"
++#define LIBDIR "/usr/lib"
++#define SLIBDIR "/lib"
++# define N_(msgid)  msgid
++#define _(msg) msg
+ 
+-#include <dl-procinfo.h>
+ 
+ #ifdef _DL_FIRST_PLATFORM
+ # define _DL_FIRST_EXTRA (_DL_FIRST_PLATFORM + _DL_PLATFORMS_COUNT)
+@@ -55,7 +68,7 @@
+ #endif
+ 
+ /* Get libc version number.  */
+-#include <version.h>
++#include "version.h"
+ 
+ #define PACKAGE _libc_intl_domainname
+ 
+@@ -152,8 +165,8 @@ static const struct argp_option options[
+   { NULL, 0, NULL, 0, NULL, 0 }
+ };
+ 
+-#define PROCINFO_CLASS static
+-#include <dl-procinfo.c>
++//#define PROCINFO_CLASS static
++//#include <dl-procinfo.c>
+ 
+ /* Short description of program.  */
+ static const char doc[] = N_("Configure Dynamic Linker Run Time Bindings.");
+@@ -291,6 +304,7 @@ parse_opt (int key, char *arg, struct ar
+   return 0;
+ }
+ 
++#define REPORT_BUGS_TO "mailing list : poky@lists.yoctoproject.org"
+ /* Print bug-reporting information in the help message.  */
+ static char *
+ more_help (int key, const char *text, void *input)
+@@ -315,7 +329,7 @@ For bug reporting instructions, please s
+ static void
+ print_version (FILE *stream, struct argp_state *state)
+ {
+-  fprintf (stream, "ldconfig %s%s\n", PKGVERSION, VERSION);
++  fprintf (stream, "ldconfig (Hacked Poky Version)\n");
+   fprintf (stream, gettext ("\
+ Copyright (C) %s Free Software Foundation, Inc.\n\
+ This is free software; see the source for copying conditions.  There is NO\n\
+@@ -1233,6 +1247,7 @@ set_hwcap (void)
+     hwcap_mask = strtoul (mask, NULL, 0);
+ }
+ 
++const char _libc_intl_domainname[] = "libc";
+ 
+ int
+ main (int argc, char **argv)
+Index: ldconfig-native-2.12.1/readlib.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/readlib.c
++++ ldconfig-native-2.12.1/readlib.c
+@@ -22,6 +22,9 @@
+    development version.  Besides the simplification, it has also been
+    modified to read some other file formats.  */
+ 
++#define _LARGEFILE64_SOURCE
++#define _GNU_SOURCE
++
+ #include <a.out.h>
+ #include <elf.h>
+ #include <error.h>
+@@ -35,7 +38,9 @@
+ #include <sys/stat.h>
+ #include <gnu/lib-names.h>
+ 
+-#include <ldconfig.h>
++#include "ldconfig.h"
++
++#define _(msg) msg
+ 
+ #define Elf32_CLASS ELFCLASS32
+ #define Elf64_CLASS ELFCLASS64
+Index: ldconfig-native-2.12.1/xstrdup.c
+===================================================================
+--- ldconfig-native-2.12.1.orig/xstrdup.c
++++ ldconfig-native-2.12.1/xstrdup.c
+@@ -16,15 +16,10 @@
+    along with this program; if not, write to the Free Software Foundation,
+    Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+ 
+-#ifdef HAVE_CONFIG_H
+-# include <config.h>
+-#endif
++#define _GNU_SOURCE
++
++#include <string.h>
+ 
+-#if defined STDC_HEADERS || defined HAVE_STRING_H || _LIBC
+-# include <string.h>
+-#else
+-# include <strings.h>
+-#endif
+ void *xmalloc (size_t n) __THROW;
+ char *xstrdup (char *string) __THROW;
+ 

+ 36 - 0
recipes-core/glibc/ldconfig-native-2.12.1/ldconfig_aux-cache_path_fix.patch

@@ -0,0 +1,36 @@
+Upstream-Status: Pending
+
+Coming from this bug: http://sourceware.org/bugzilla/show_bug.cgi?id=11149
+
+Nitin A Kamble <nitin.a.kamble@intel.com>2011/03/29
+
+--- ldconfig-native-2.12.1.orig/ldconfig.c	
++++ ldconfig-native-2.12.1/ldconfig.c	
+@@ -1359,14 +1359,9 @@ main (int argc, char **argv)
+ 
+   const char *aux_cache_file = _PATH_LDCONFIG_AUX_CACHE;
+   if (opt_chroot)
+-    {
+-      aux_cache_file = chroot_canon (opt_chroot, aux_cache_file);
+-      if (aux_cache_file == NULL)
+-	error (EXIT_FAILURE, errno, _("Can't open cache file %s\n"),
+-	       _PATH_LDCONFIG_AUX_CACHE);
+-    }
++    aux_cache_file = chroot_canon (opt_chroot, aux_cache_file);
+ 
+-  if (! opt_ignore_aux_cache)
++  if (! opt_ignore_aux_cache && aux_cache_file)
+     load_aux_cache (aux_cache_file);
+   else
+     init_aux_cache ();
+@@ -1376,7 +1371,8 @@ main (int argc, char **argv)
+   if (opt_build_cache)
+     {
+       save_cache (cache_file);
+-      save_aux_cache (aux_cache_file);
++      if (aux_cache_file)
++        save_aux_cache (aux_cache_file);
+     }
+ 
+   return 0;
+

+ 19 - 0
recipes-core/glibc/ldconfig-native-2.12.1/no-aux-cache.patch

@@ -0,0 +1,19 @@
+The ldconfig auxiliary cache is a dictionary where the keys include inode, so
+there is no point in writing these files on the build host. 
+
+Upstream-Status: Inappropriate
+Signed-off-by: Ross Burton <ross.burton@arm.com>
+
+diff --git a/ldconfig.c b/ldconfig.c
+index 2c4eb57..2d6dc92 100644
+--- a/ldconfig.c
++++ b/ldconfig.c
+@@ -1399,8 +1399,6 @@ main (int argc, char **argv)
+   if (opt_build_cache)
+     {
+       save_cache (cache_file);
+-      if (aux_cache_file)
+-        save_aux_cache (aux_cache_file);
+     }
+ 
+   return 0;

+ 36 - 0
recipes-core/glibc/ldconfig-native_2.12.1.bb

@@ -0,0 +1,36 @@
+SUMMARY = "A standalone native ldconfig build"
+
+LICENSE = "GPLv2+"
+
+LIC_FILES_CHKSUM = "file://${S}/ldconfig.c;endline=17;md5=1d15f20937c055cb5de2329a4c054399"
+
+SRC_URI = "file://ldconfig-native-2.12.1.tar.bz2 \
+           file://ldconfig.patch \
+           file://ldconfig_aux-cache_path_fix.patch \
+           file://32and64bit.patch \
+           file://endian-ness_handling.patch \
+           file://flag_fix.patch \
+           file://endianess-header.patch \
+           file://ldconfig-default-to-all-multilib-dirs.patch \
+           file://endian-ness_handling_fix.patch \
+           file://add-64-bit-flag-for-ELF64-entries.patch \
+           file://no-aux-cache.patch \
+           file://add-riscv-support.patch \
+"
+
+PR = "r2"
+
+FILESEXTRAPATHS =. "${FILE_DIRNAME}/${P}:"
+
+inherit native
+
+S = "${WORKDIR}/${PN}-${PV}"
+
+do_compile () {
+	$CC ldconfig.c -std=gnu99 chroot_canon.c xmalloc.c xstrdup.c cache.c readlib.c  -I. dl-cache.c -o ldconfig
+}
+
+do_install () {
+	install -d ${D}/${bindir}/
+	install ldconfig ${D}/${bindir}/
+}

+ 50 - 0
recipes-devtools/binutils/binutils-2.37.inc

@@ -0,0 +1,50 @@
+LIC_FILES_CHKSUM="\
+    file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552\
+    file://COPYING.LIB;md5=9f604d8a4f8e74f4f5140845a21b6674\
+    file://COPYING3;md5=d32239bcb673463ab874e80d47fae504\
+    file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6\
+    file://gas/COPYING;md5=d32239bcb673463ab874e80d47fae504\
+    file://include/COPYING;md5=59530bdf33659b29e73d4adb9f9f6552\
+    file://include/COPYING3;md5=d32239bcb673463ab874e80d47fae504\
+    file://libiberty/COPYING.LIB;md5=a916467b91076e631dd8edb7424769c7\
+    file://bfd/COPYING;md5=d32239bcb673463ab874e80d47fae504\
+    "
+
+# When upgrading to 2.37, please make sure there is no trailing .0, so
+# that upstream version check can work correctly.
+PV = "2.37"
+CVE_VERSION = "2.37"
+SRCBRANCH ?= "binutils-2_37-branch"
+
+UPSTREAM_CHECK_GITTAGREGEX = "binutils-(?P<pver>\d+_(\d_?)*)"
+
+SRCREV ?= "116a737f438d03a1bd6aa706b6ea0b4022f3b7e2"
+BINUTILS_GIT_URI ?= "git://sourceware.org/git/binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
+SRC_URI = "\
+     ${BINUTILS_GIT_URI} \
+     file://0004-configure-widen-the-regexp-for-SH-architectures.patch \
+     file://0005-Point-scripts-location-to-libdir.patch \
+     file://0006-Only-generate-an-RPATH-entry-if-LD_RUN_PATH-is-not-e.patch \
+     file://0007-don-t-let-the-distro-compiler-point-to-the-wrong-ins.patch \
+     file://0008-warn-for-uses-of-system-directories-when-cross-linki.patch \
+     file://0009-Change-default-emulation-for-mips64-linux.patch \
+     file://0010-Add-support-for-Netlogic-XLP.patch \
+     file://0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch \
+     file://0012-Detect-64-bit-MIPS-targets.patch \
+     file://0013-Use-libtool-2.4.patch \
+     file://0014-Fix-rpath-in-libtool-when-sysroot-is-enabled.patch \
+     file://0015-sync-with-OE-libtool-changes.patch \
+     file://0016-Check-for-clang-before-checking-gcc-version.patch \
+     file://0001-merge-from-dubhe-pr-06-30-to-support-b0.94.patch \
+     file://0002-merge-from-dubhe-pr-06-30-to-support-vector1.0.patch \
+     file://0003-fix-unrecoginized-b-ext-issue.patch \
+     file://0004-set-v-ext-version-to-1.0-draft.patch \
+     file://0005-fix-incorrect-RCLASS_MAX.patch \
+     file://0006-Merge-B-instruction-from-0p94-to-1.0.patch \
+     file://0007-merge-Add-four-new-instruction-of-custom-CSRs.patch \
+     file://0008-add-cache-prefetch-instruction.patch \
+     file://0009-Delete-redundant-b0.94-instructions.patch \
+     file://0010-change-vle1.v-vse1.v-to-vlm.v-vsm.v-according-rvv-1..patch \
+     file://0011-enable-l2-cache-prefetch.patch \
+"
+S  = "${WORKDIR}/git"

+ 32 - 0
recipes-devtools/binutils/binutils-cross-canadian.inc

@@ -0,0 +1,32 @@
+inherit cross-canadian
+
+SUMMARY = "GNU binary utilities (cross-canadian for ${TARGET_ARCH} target)"
+PN = "binutils-cross-canadian-${TRANSLATED_TARGET_ARCH}"
+BPN = "binutils"
+
+DEPENDS = "flex-native bison-native virtual/${HOST_PREFIX}gcc-crosssdk virtual/nativesdk-libc nativesdk-zlib nativesdk-gettext nativesdk-flex"
+EXTRA_OECONF += "--with-sysroot=${SDKPATH}/sysroots/${TUNE_PKGARCH}${TARGET_VENDOR}-${TARGET_OS} \
+                --enable-poison-system-directories \
+                "
+
+# We have to point binutils at a sysroot but we don't need to rebuild if this changes
+# e.g. we switch between different machines with different tunes.
+EXTRA_OECONF[vardepsexclude] = "TUNE_PKGARCH"
+
+LDGOLD_sdkmingw32 = ""
+
+do_install () {
+	autotools_do_install
+
+	# We're not interested in the libs or headers, these would come from the 
+	# nativesdk or target version of the binutils recipe
+	rm -rf ${D}${prefix}/${TARGET_SYS}
+	rm -f ${D}${libdir}/libbfd*
+	rm -f ${D}${libdir}/libiberty*
+	rm -f ${D}${libdir}/libopcodes*
+	rm -f ${D}${includedir}/*.h
+	
+	cross_canadian_bindirlinks
+}
+
+BBCLASSEXTEND = ""

+ 0 - 38
recipes-devtools/binutils/binutils-cross-canadian_2.36.bbappend

@@ -1,38 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
-SRCBRANCH = "riscv-binutils-2.36.1"
-
-SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
-
-BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
-
-SRC_URI = "\
-      ${BINUTILS_GIT_URI} \
-      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
-      file://0002-Add-support-for-B-extension.patch \
-      file://0003-merge-rvv1.0-branch.patch \
-      file://0005-support-Dubhe-V-extension.patch \
-      file://0005-Point-scripts-location-to-libdir.patch \ 
-      file://0006-Add-pseudo-instructions-for-B-extension.patch \
-      file://0007-Rename-bdep-to-bdecompress.patch \
-      file://0008-RISCV-Add-support-for-bcompress.patch \
-      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
-      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
-      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
-      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
-      file://0013-Fix-gas-test-cases.patch \
-      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
-      file://0015-Remove-MASK_SHAMT2.patch \
-      file://0016-Fix-internal-error-undefined-modifier-r.patch \
-      file://0017-Fix-coding-for-Bcompressw.patch \
-      file://0018-Fix-zip2.b-testcase.patch \
-      file://0019-Fix-orc2.n-testcase.patch \
-      file://0020-Fix-rev2.n-test-case.patch \
-      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
-      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
-      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
-      file://0024-add-vid-instruction-support.patch \
-      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
-      file://0026-Apply-same-fix-on-b-ext.d.patch \
-      file://0027-remove-redundant-symbol.patch \
-      file://0028-solved-vector-insns-test-failed-n.patch \
-"

+ 3 - 0
recipes-devtools/binutils/binutils-cross-canadian_2.37.bb

@@ -0,0 +1,3 @@
+require binutils.inc
+require binutils-${PV}.inc
+require binutils-cross-canadian.inc

+ 81 - 0
recipes-devtools/binutils/binutils-cross-testsuite_2.37.bb

@@ -0,0 +1,81 @@
+require binutils.inc
+require binutils-${PV}.inc
+
+BPN = "binutils"
+
+DEPENDS += "dejagnu-native expect-native"
+DEPENDS += "binutils-native"
+
+deltask do_compile
+deltask do_install
+
+inherit nopackages
+
+do_configure[dirs] += "${B}/ld ${B}/bfd"
+do_configure() {
+    # create config.h, oe enables initfini-array by default
+    echo "#define HAVE_INITFINI_ARRAY" > ${B}/ld/config.h
+}
+
+# target depends
+DEPENDS += "virtual/${MLPREFIX}${TARGET_PREFIX}binutils"
+DEPENDS += "virtual/${MLPREFIX}${TARGET_PREFIX}gcc"
+DEPENDS += "virtual/${MLPREFIX}${TARGET_PREFIX}compilerlibs"
+DEPENDS += "virtual/${MLPREFIX}libc"
+
+python check_prepare() {
+    def suffix_sys(sys):
+        if sys.endswith("-linux"):
+            return sys + "-gnu"
+        return sys
+
+    def generate_site_exp(d, suite):
+        content = []
+        content.append('set srcdir "{0}/{1}"'.format(d.getVar("S"), suite))
+        content.append('set objdir "{0}/{1}"'.format(d.getVar("B"), suite))
+        content.append('set build_alias "{0}"'.format(d.getVar("BUILD_SYS")))
+        content.append('set build_triplet {0}'.format(d.getVar("BUILD_SYS")))
+        # use BUILD here since HOST=TARGET
+        content.append('set host_alias "{0}"'.format(d.getVar("BUILD_SYS")))
+        content.append('set host_triplet {0}'.format(d.getVar("BUILD_SYS")))
+        content.append('set target_alias "{0}"'.format(d.getVar("TARGET_SYS")))
+        content.append('set target_triplet {0}'.format(suffix_sys(d.getVar("TARGET_SYS"))))
+        content.append("set development true")
+        content.append("set experimental false")
+
+        content.append(d.expand('set CXXFILT "${TARGET_PREFIX}c++filt"'))
+        content.append(d.expand('set CC "${TARGET_PREFIX}gcc --sysroot=${STAGING_DIR_TARGET} ${TUNE_CCARGS}"'))
+        content.append(d.expand('set CXX "${TARGET_PREFIX}g++ --sysroot=${STAGING_DIR_TARGET} ${TUNE_CCARGS}"'))
+        content.append(d.expand('set CFLAGS_FOR_TARGET "--sysroot=${STAGING_DIR_TARGET} ${TUNE_CCARGS}"'))
+
+        if suite == "ld" and d.getVar("TUNE_ARCH") == "mips64":
+            # oe patches binutils to have the default mips64 abi as 64bit, but
+            # skips gas causing issues with the ld test suite (which uses gas)
+            content.append('set ASFLAGS "-64"')
+
+        return "\n".join(content)
+
+    for i in ["binutils", "gas", "ld"]:
+        builddir = os.path.join(d.getVar("B"), i)
+        if not os.path.isdir(builddir):
+            os.makedirs(builddir)
+        with open(os.path.join(builddir, "site.exp"), "w") as f:
+            f.write(generate_site_exp(d, i))
+}
+
+CHECK_TARGETS ??= "binutils gas ld"
+
+do_check[dirs] = "${B} ${B}/binutils ${B}/gas ${B}/ld"
+do_check[prefuncs] += "check_prepare"
+do_check[nostamp] = "1"
+do_check() {
+    export LC_ALL=C
+    for i in ${CHECK_TARGETS}; do
+        (cd ${B}/$i; runtest \
+            --tool $i \
+            --srcdir ${S}/$i/testsuite \
+            --ignore 'plugin.exp' \
+            || true)
+    done
+}
+addtask check after do_configure

+ 38 - 0
recipes-devtools/binutils/binutils-cross.inc

@@ -0,0 +1,38 @@
+inherit cross
+PROVIDES = "virtual/${TARGET_PREFIX}binutils"
+
+PN = "binutils-cross-${TARGET_ARCH}"
+BPN = "binutils"
+
+# Ignore how TARGET_ARCH is computed.
+TARGET_ARCH[vardepvalue] = "${TARGET_ARCH}"
+
+INHIBIT_DEFAULT_DEPS = "1"
+INHIBIT_AUTOTOOLS_DEPS = "1"
+
+SRC_URI += "file://0002-binutils-cross-Do-not-generate-linker-script-directo.patch"
+
+# Specify lib-path else we use a load of search dirs which we don't use
+# and mean the linker scripts have to be relocated.
+EXTRA_OECONF += "--with-sysroot=${STAGING_DIR_TARGET} \
+                --disable-install-libbfd \
+                --enable-poison-system-directories \
+                --with-lib-path==${target_base_libdir}:=${target_libdir} \
+                "
+do_install () {
+	oe_runmake 'DESTDIR=${D}' install
+
+	# We don't really need these, so we'll remove them...
+	rm -rf ${D}${STAGING_DIR_NATIVE}${libdir_native}/libiberty.a
+	rm -rf ${D}${STAGING_DIR_NATIVE}${prefix_native}/${TARGET_SYS}
+	rm -rf ${D}${STAGING_DIR_NATIVE}${prefix_native}/lib/ldscripts
+	rm -rf ${D}${STAGING_DIR_NATIVE}${prefix_native}/share/info
+	rm -rf ${D}${STAGING_DIR_NATIVE}${prefix_native}/share/locale
+	rm -rf ${D}${STAGING_DIR_NATIVE}${prefix_native}/share/man
+	rmdir ${D}${STAGING_DIR_NATIVE}${prefix_native}/share || :
+	rmdir ${D}${STAGING_DIR_NATIVE}${prefix_native}/${libdir}/gcc-lib || :
+	rmdir ${D}${STAGING_DIR_NATIVE}${prefix_native}/${libdir}64/gcc-lib || :
+	rmdir ${D}${STAGING_DIR_NATIVE}${prefix_native}/${libdir} || :
+	rmdir ${D}${STAGING_DIR_NATIVE}${prefix_native}/${libdir}64 || :
+	rmdir ${D}${STAGING_DIR_NATIVE}${prefix_native}/${prefix} || :
+}

+ 0 - 38
recipes-devtools/binutils/binutils-cross_2.36.bbappend

@@ -1,38 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
-SRCBRANCH = "riscv-binutils-2.36.1"
-
-SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
-
-BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
-
-SRC_URI = "\
-      ${BINUTILS_GIT_URI} \
-      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
-      file://0002-Add-support-for-B-extension.patch \
-      file://0003-merge-rvv1.0-branch.patch \
-      file://0005-support-Dubhe-V-extension.patch \
-      file://0005-Point-scripts-location-to-libdir.patch \ 
-      file://0006-Add-pseudo-instructions-for-B-extension.patch \
-      file://0007-Rename-bdep-to-bdecompress.patch \
-      file://0008-RISCV-Add-support-for-bcompress.patch \
-      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
-      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
-      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
-      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
-      file://0013-Fix-gas-test-cases.patch \
-      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
-      file://0015-Remove-MASK_SHAMT2.patch \
-      file://0016-Fix-internal-error-undefined-modifier-r.patch \
-      file://0017-Fix-coding-for-Bcompressw.patch \
-      file://0018-Fix-zip2.b-testcase.patch \
-      file://0019-Fix-orc2.n-testcase.patch \
-      file://0020-Fix-rev2.n-test-case.patch \
-      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
-      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
-      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
-      file://0024-add-vid-instruction-support.patch \
-      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
-      file://0026-Apply-same-fix-on-b-ext.d.patch \
-      file://0027-remove-redundant-symbol.patch \
-      file://0028-solved-vector-insns-test-failed-n.patch \
-"

+ 3 - 0
recipes-devtools/binutils/binutils-cross_2.37.bb

@@ -0,0 +1,3 @@
+require binutils.inc
+require binutils-${PV}.inc
+require binutils-cross.inc

+ 0 - 38
recipes-devtools/binutils/binutils-crosssdk_2.36.bbappend

@@ -1,38 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/binutils:"
-SRCBRANCH = "riscv-binutils-2.36.1"
-
-SRCREV = "f35674005e609660f5f45005a9e095541ca4c5fe"
-
-BINUTILS_GIT_URI = "git://github.com/riscv/riscv-binutils-gdb.git;branch=${SRCBRANCH};protocol=git"
-
-SRC_URI = "\
-      ${BINUTILS_GIT_URI} \
-      file://0001-resolve-bug-1-unsupported-zvmo-extension.patch \
-      file://0002-Add-support-for-B-extension.patch \
-      file://0003-merge-rvv1.0-branch.patch \
-      file://0005-support-Dubhe-V-extension.patch \
-      file://0005-Point-scripts-location-to-libdir.patch \ 
-      file://0006-Add-pseudo-instructions-for-B-extension.patch \
-      file://0007-Rename-bdep-to-bdecompress.patch \
-      file://0008-RISCV-Add-support-for-bcompress.patch \
-      file://0009-RISCV-Coding-bug-Fix-for-FSRW.patch \
-      file://0010-RISCV-Coding-bug-Fix-for-FSRIW.patch \
-      file://0011-RISCV-Fix-coding-for-un-zip-2-4-8-16-n-b-h-w.patch \
-      file://0012-update-bitmap-version-number-from-0.93-to-0.94.patch \
-      file://0013-Fix-gas-test-cases.patch \
-      file://0014-resolve-crash-issue-when-objdump-encounter-unrecogni.patch \
-      file://0015-Remove-MASK_SHAMT2.patch \
-      file://0016-Fix-internal-error-undefined-modifier-r.patch \
-      file://0017-Fix-coding-for-Bcompressw.patch \
-      file://0018-Fix-zip2.b-testcase.patch \
-      file://0019-Fix-orc2.n-testcase.patch \
-      file://0020-Fix-rev2.n-test-case.patch \
-      file://0021-Fix-testcase-for-zip2.b-and-rev2.n.patch \
-      file://0022-Fix-r-operands-type-from-fpr-to-gpr.patch \
-      file://0023-support-vid-vmv1r-vl1r-vs1r-instruction.patch \
-      file://0024-add-vid-instruction-support.patch \
-      file://0025-Fix-all-issues-in-b-ext-64.d.patch \
-      file://0026-Apply-same-fix-on-b-ext.d.patch \
-      file://0027-remove-redundant-symbol.patch \
-      file://0028-solved-vector-insns-test-failed-n.patch \
-"

+ 13 - 0
recipes-devtools/binutils/binutils-crosssdk_2.37.bb

@@ -0,0 +1,13 @@
+require binutils-cross_${PV}.bb
+
+inherit crosssdk
+
+PN = "binutils-crosssdk-${SDK_SYS}"
+
+PROVIDES = "virtual/${TARGET_PREFIX}binutils-crosssdk"
+
+SRC_URI += "file://0001-binutils-crosssdk-Generate-relocatable-SDKs.patch"
+
+do_configure_prepend () {
+	sed -i 's#/usr/local/lib /lib /usr/lib#${SDKPATHNATIVE}/lib ${SDKPATHNATIVE}/usr/lib /usr/local/lib /lib /usr/lib#' ${S}/ld/configure.tgt
+}

+ 184 - 0
recipes-devtools/binutils/binutils.inc

@@ -0,0 +1,184 @@
+SUMMARY = "GNU binary utilities"
+DESCRIPTION = "The GNU Binutils are a collection of binary tools. \
+The main ones are ld (GNU Linker), and as (GNU Assembler). This \
+package also includes addition tools such as addr2line (Converts \
+addresses into filenames and line numbers), ar (utility for creating, \
+modifying and extracting archives), nm (list symbols in object \
+files), objcopy (copy and translate object files), objdump (Display \
+object information), and other tools and related libraries."
+HOMEPAGE = "http://www.gnu.org/software/binutils/"
+BUGTRACKER = "http://sourceware.org/bugzilla/"
+SECTION = "devel"
+LICENSE = "GPLv3"
+
+DEPENDS = "flex-native bison-native zlib-native gnu-config-native autoconf-native"
+
+inherit autotools gettext multilib_header texinfo
+
+FILES_${PN} = " \
+	${bindir}/${TARGET_PREFIX}* \
+	${libdir}/lib*.so.* \
+	${libdir}/bfd-plugins/lib*.so \
+	${libdir}/lib*-${PV}*.so \
+	${prefix}/${TARGET_SYS}/bin/* \
+        ${bindir}/embedspu"
+
+RPROVIDES_${PN} += "${PN}-symlinks"
+
+FILES_${PN}-dev = " \
+	${includedir} \
+	${libdir}/*.la \
+	${libdir}/libbfd.so \
+	${libdir}/libctf.so \
+	${libdir}/libctf-nobfd.so \
+	${libdir}/libopcodes.so"
+
+# Rather than duplicating multiple entries for these, make one
+# list and reuse it.
+
+LDGOLD_ALTS ?= "ld.gold dwp"
+LDGOLD_ALTS_riscv64 = ""
+LDGOLD_ALTS_riscv32 = ""
+LDGOLD_ALTS_libc-glibc_mipsarch = ""
+
+USE_ALTERNATIVES_FOR = " \
+	addr2line \
+	ar \
+	as \
+	c++filt \
+	elfedit \
+	gprof \
+	ld \
+	ld.bfd \
+	${LDGOLD_ALTS} \
+	nm \
+	objcopy \
+	objdump \
+	ranlib \
+	readelf \
+	size \
+	strings \
+	strip \
+"
+
+python do_package_prepend() {
+    make_alts = d.getVar("USE_ALTERNATIVES_FOR") or ""
+    prefix = d.getVar("TARGET_PREFIX")
+    bindir = d.getVar("bindir")
+    for alt in make_alts.split():
+        d.setVarFlag('ALTERNATIVE_TARGET', alt, bindir + "/" + prefix + alt)
+        d.setVarFlag('ALTERNATIVE_LINK_NAME', alt, bindir + "/" + alt)
+}
+
+B = "${S}/build.${HOST_SYS}.${TARGET_SYS}"
+
+EXTRA_OECONF = "--program-prefix=${TARGET_PREFIX} \
+                --disable-werror \
+                --enable-deterministic-archives \
+                --enable-plugins \
+                --disable-gdb \
+                --disable-gdbserver \
+                --disable-libdecnumber \
+                --disable-readline \
+                --disable-sim \
+                ${LDGOLD} \
+                ${EXTRA_TARGETS} \
+                ${@bb.utils.contains('DISTRO_FEATURES', 'multiarch', '--enable-64-bit-bfd', '', d)}"
+
+EXTRA_TARGETS = ""
+EXTRA_TARGETS_x86-64 = " --enable-targets=x86_64-pe,x86_64-pep "
+EXTRA_TARGETS_class-native = ""
+
+LDGOLD_class-native = ""
+LDGOLD_class-crosssdk = ""
+LDGOLD_libc-glibc_mipsarch = ""
+LDGOLD ?= "${@bb.utils.contains('DISTRO_FEATURES', 'ld-is-gold', '--enable-gold=default --enable-threads', '--enable-gold --enable-ld=default --enable-threads', d)}"
+
+
+# This is necessary due to a bug in the binutils Makefiles
+# EXTRA_OEMAKE = "configure-build-libiberty all"
+
+export AR = "${HOST_PREFIX}ar"
+export AS = "${HOST_PREFIX}as"
+export LD = "${HOST_PREFIX}ld"
+export NM = "${HOST_PREFIX}nm"
+export RANLIB = "${HOST_PREFIX}ranlib"
+export OBJCOPY = "${HOST_PREFIX}objcopy"
+export OBJDUMP = "${HOST_PREFIX}objdump"
+
+export AR_FOR_TARGET = "${TARGET_PREFIX}ar"
+export AS_FOR_TARGET = "${TARGET_PREFIX}as"
+export LD_FOR_TARGET = "${TARGET_PREFIX}ld"
+export NM_FOR_TARGET = "${TARGET_PREFIX}nm"
+export RANLIB_FOR_TARGET = "${TARGET_PREFIX}ranlib"
+
+export CC_FOR_HOST = "${CCACHE}${HOST_PREFIX}gcc ${HOST_CC_ARCH}"
+export CXX_FOR_HOST = "${CCACHE}${HOST_PREFIX}gcc ${HOST_CC_ARCH}"
+
+# autotools.bbclass sets the _FOR_BUILD variables, but for some reason we need
+# to unset LD_LIBRARY_PATH.
+export CC_FOR_BUILD = "LD_LIBRARY_PATH= ${BUILD_CC}"
+
+MULTIARCH := "${@bb.utils.contains("DISTRO_FEATURES", "multiarch", "yes", "no", d)}"
+do_configure[vardeps] += "MULTIARCH"
+do_configure () {
+	(cd ${S} && gnu-configize)
+
+	oe_runconf
+#
+# must prime config.cache to ensure the build of libiberty
+#
+	mkdir -p ${B}/build-${BUILD_SYS}
+	for i in ${CONFIG_SITE}; do
+		cat $i >> ${B}/build-${BUILD_SYS}/config.cache || true
+	done
+}
+
+do_install () {
+	autotools_do_install
+
+	# We don't really need these, so we'll remove them...
+	rm -rf ${D}${libdir}/ldscripts
+
+	bindir_rel=${@os.path.relpath('${bindir}', '${prefix}/${TARGET_SYS}/bin')}
+
+	# Fix the /usr/${TARGET_SYS}/bin/* links
+	for l in ${D}${prefix}/${TARGET_SYS}/bin/*; do
+		rm -f $l
+		ln -sf $bindir_rel/${TARGET_PREFIX}`basename $l` $l
+	done
+
+	# Install the libiberty header
+	install -d ${D}${includedir}
+	install -m 644 ${S}/include/ansidecl.h ${D}${includedir}
+	install -m 644 ${S}/include/libiberty.h ${D}${includedir}
+
+	# insall pic version of libiberty if available
+        if [ -e ${B}/libiberty/pic/libiberty.a ]; then
+		install -Dm 0644 ${B}/libiberty/pic/libiberty.a ${D}${libdir}/libiberty.a
+	fi
+
+	cd ${D}${bindir}
+
+	# Symlinks for ease of running these on the native target
+	for p in ${TARGET_PREFIX}* ; do
+		ln -sf $p `echo $p | sed -e s,${TARGET_PREFIX},,`
+	done
+
+	for alt in ${USE_ALTERNATIVES_FOR}; do
+		rm -f ${D}${bindir}/$alt
+	done
+
+	oe_multilib_header bfd.h
+}
+
+inherit update-alternatives
+
+ALTERNATIVE_PRIORITY = "100"
+
+ALTERNATIVE_${PN}_class-target = "${USE_ALTERNATIVES_FOR}"
+
+python () {
+    if bb.utils.contains('DISTRO_FEATURES', 'ld-is-gold', True, False, d) and bb.utils.contains_any('TARGET_ARCH', 'riscv32 riscv64', True, False, d):
+        bb.fatal("Gold linker does not _yet_ support RISC-V architecture please remove ld-is-gold from DISTRO_FEATURES")
+}

+ 75 - 0
recipes-devtools/binutils/binutils/0001-binutils-crosssdk-Generate-relocatable-SDKs.patch

@@ -0,0 +1,75 @@
+From 257ad1ce148417e1cefe2332d8acc5c8216c2522 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Mon, 2 Mar 2015 01:58:54 +0000
+Subject: [PATCH] binutils-crosssdk: Generate relocatable SDKs
+
+This patch will modify the ELF linker scripts so that the crosssdk
+linker will generate binaries with a 4096 bytes PT_INTERP section. When the binaries
+will be relocated, at SDK install time, the interpreter path can be easily
+changed by the relocating script.
+
+generate larger .interp section for gold linker as well
+
+Upstream-Status: Inappropriate [SDK specific]
+
+Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ gold/layout.cc        | 2 +-
+ ld/genscripts.sh      | 3 +++
+ ld/scripttempl/elf.sc | 4 ++--
+ 3 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/gold/layout.cc b/gold/layout.cc
+index a27cb071c75..32b52890b39 100644
+--- a/gold/layout.cc
++++ b/gold/layout.cc
+@@ -5032,7 +5032,7 @@ Layout::create_interp(const Target* target)
+       gold_assert(interp != NULL);
+     }
+ 
+-  size_t len = strlen(interp) + 1;
++  size_t len = 4096;
+ 
+   Output_section_data* odata = new Output_data_const(interp, len, 1);
+ 
+diff --git a/ld/genscripts.sh b/ld/genscripts.sh
+index 088417ef2d5..46a2db7005c 100755
+--- a/ld/genscripts.sh
++++ b/ld/genscripts.sh
+@@ -304,6 +304,7 @@ DATA_ALIGNMENT_u="${DATA_ALIGNMENT_u-${DATA_ALIGNMENT_r}}"
+ LD_FLAG=r
+ DATA_ALIGNMENT=${DATA_ALIGNMENT_r}
+ DEFAULT_DATA_ALIGNMENT="ALIGN(${SEGMENT_SIZE})"
++PARTIAL_LINKING=" "
+ ( echo "/* Script for -r */"
+   source_sh ${CUSTOMIZER_SCRIPT}
+   source_sh ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
+@@ -312,10 +313,12 @@ DEFAULT_DATA_ALIGNMENT="ALIGN(${SEGMENT_SIZE})"
+ LD_FLAG=u
+ DATA_ALIGNMENT=${DATA_ALIGNMENT_u}
+ CONSTRUCTING=" "
++PARTIAL_LINKING=" "
+ ( echo "/* Script for -Ur */"
+   source_sh ${CUSTOMIZER_SCRIPT}
+   source_sh ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
+ ) | sed -e '/^ *$/d;s/[	 ]*$//' > ldscripts/${EMULATION_NAME}.xu
++unset PARTIAL_LINKING
+ 
+ DATA_ALIGNMENT=${DATA_ALIGNMENT_}
+ RELOCATING=" "
+diff --git a/ld/scripttempl/elf.sc b/ld/scripttempl/elf.sc
+index 29a8f0781d5..75e46f4adaf 100644
+--- a/ld/scripttempl/elf.sc
++++ b/ld/scripttempl/elf.sc
+@@ -147,8 +147,8 @@ if test -z "$DATA_SEGMENT_ALIGN"; then
+     DATA_SEGMENT_RELRO_END=". = DATA_SEGMENT_RELRO_END (${SEPARATE_GOTPLT-0}, .);"
+   fi
+ fi
+-if test -z "${INITIAL_READONLY_SECTIONS}${CREATE_SHLIB}"; then
+-  INITIAL_READONLY_SECTIONS=".interp       ${RELOCATING-0} : { *(.interp) }"
++if test -z "${INITIAL_READONLY_SECTIONS}${CREATE_SHLIB}${PARTIAL_LINKING}"; then
++  INITIAL_READONLY_SECTIONS=".interp       ${RELOCATING-0} : { *(.interp); . = 0x1000; }"
+ fi
+ if test -z "$PLT"; then
+   IPLT=".iplt         ${RELOCATING-0} : { *(.iplt) }"

+ 927 - 0
recipes-devtools/binutils/binutils/0001-merge-from-dubhe-pr-06-30-to-support-b0.94.patch

@@ -0,0 +1,927 @@
+From cc2d8c8bed31f441206b53009d5d681132c6e332 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Wed, 29 Sep 2021 02:42:26 -0700
+Subject: [PATCH 01/11] merge from dubhe-pr-06-30 to support b0.94
+
+---
+ gas/config/tc-riscv.c              |  24 +++
+ gas/testsuite/gas/riscv/b-ext-64.d |  69 +++++++
+ gas/testsuite/gas/riscv/b-ext-64.s |  69 +++++++
+ gas/testsuite/gas/riscv/b-ext.d    |  39 ++++
+ gas/testsuite/gas/riscv/b-ext.s    |  39 ++++
+ include/opcode/riscv-opc.h         | 206 +++++++++++++++++++
+ include/opcode/riscv.h             |  12 ++
+ opcodes/riscv-opc.c                | 316 +++++++++++++++++++++++++++++
+ 8 files changed, 774 insertions(+)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 70cbc8190f..e5d8070b75 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -343,6 +343,30 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+     case INSN_CLASS_ZBC:
+       return riscv_subset_supports ("zbc");
+ 
++    case INSN_CLASS_ZBE:
++      return riscv_subset_supports ("zbe");
++    case INSN_CLASS_ZBF:
++      return riscv_subset_supports ("zbf");
++    case INSN_CLASS_ZBM:
++      return riscv_subset_supports ("zbm");
++    case INSN_CLASS_ZBP:
++      return riscv_subset_supports ("zbp");
++    case INSN_CLASS_ZBR:
++      return riscv_subset_supports ("zbr");
++    case INSN_CLASS_ZBS:
++      return riscv_subset_supports ("zbs");
++    case INSN_CLASS_ZBT:
++      return riscv_subset_supports ("zbt");
++    case INSN_CLASS_ZBB_OR_ZBP:
++      return (riscv_subset_supports ("zbb") || riscv_subset_supports ("zbp"));
++    case INSN_CLASS_ZBS_OR_ZBE:
++      return (riscv_subset_supports ("zbs") || riscv_subset_supports ("zbe"));
++    case INSN_CLASS_ZBP_OR_ZBM:
++      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbm"));
++    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF:
++      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
++    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
++      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
+     default:
+       as_fatal ("internal: unreachable");
+       return false;
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
+index f4a7abf02d..d1b512b9e9 100644
+--- a/gas/testsuite/gas/riscv/b-ext-64.d
++++ b/gas/testsuite/gas/riscv/b-ext-64.d
+@@ -46,3 +46,72 @@ Disassembly of section .text:
+ [ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
+ [ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
+ [ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
++[ 	]+98:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
++[ 	]+9c:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
++[ 	]+a0:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
++[ 	]+a4:[ 	]+0825c53b[ 	]+packw[ 	]+a0,a1,0x2
++[ 	]+a8:[ 	]+4825c53b[ 	]+packuw[ 	]+a0,a1,0x2
++[ 	]+ac:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
++[ 	]+b0:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
++[ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
++[ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
++[ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
++[ 	]+c0:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
++[ 	]+c4:[ 	]+2825d53b[ 	]+gorcw[ 	]+a0,a1,0x2
++[ 	]+c8:[ 	]+2825d51b[ 	]+gorciw[ 	]+a0,a1,0x2
++[ 	]+cc:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
++[ 	]+d0:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
++[ 	]+d4:[ 	]+0825953b[ 	]+shflw[ 	]+a0,a1,0x2
++[ 	]+d8:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
++[ 	]+dc:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
++[ 	]+e0:[ 	]+0825d53b[ 	]+unshflw[ 	]+a0,a1,0x2
++[ 	]+e4:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
++[ 	]+e8:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
++[ 	]+ec:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
++[ 	]+f0:[ 	]+28258533[ 	]+xperm.w[ 	]+a0,a1,0x2
++[ 	]+f4:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
++[ 	]+f8:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
++[ 	]+fc:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
++[ 	]+100:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
++[ 	]+104:[ 	]+48c5e533[ 	]+bdecompress[ 	]+a0,a1,a2
++[ 	]+108:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
++[ 	]+10c:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
++[ 	]+110:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
++[ 	]+114:[ 	]+4825d513[ 	]+bexti[ 	]+a0,a1,0x2
++[ 	]+118:[ 	]+28c5953b[ 	]+bsetw[ 	]+a0,a1,a2
++[ 	]+11c:[ 	]+48c5953b[ 	]+bclrw[ 	]+a0,a1,a2
++[ 	]+120:[ 	]+68c5953b[ 	]+binvw[ 	]+a0,a1,a2
++[ 	]+124:[ 	]+48c5d53b[ 	]+bextw[ 	]+a0,a1,a2
++[ 	]+128:[ 	]+4825e53b[ 	]+bdecompressw[ 	]+a0,a1,0x2
++[ 	]+12c:[ 	]+2825951b[ 	]+bsetiw[ 	]+a0,a1,0x2
++[ 	]+130:[ 	]+4825951b[ 	]+bclriw[ 	]+a0,a1,0x2
++[ 	]+134:[ 	]+6825951b[ 	]+binviw[ 	]+a0,a1,0x2
++[ 	]+138:[ 	]+20c59533[ 	]+slo[ 	]+a0,a1,a2
++[ 	]+13c:[ 	]+20c5d533[ 	]+sro[ 	]+a0,a1,a2
++[ 	]+140:[ 	]+20259513[ 	]+sloi[ 	]+a0,a1,0x2
++[ 	]+144:[ 	]+2025d513[ 	]+sroi[ 	]+a0,a1,0x2
++[ 	]+148:[ 	]+2025953b[ 	]+slow[ 	]+a0,a1,0x2
++[ 	]+14c:[ 	]+2025d53b[ 	]+srow[ 	]+a0,a1,0x2
++[ 	]+150:[ 	]+2025951b[ 	]+sloiw[ 	]+a0,a1,0x2
++[ 	]+154:[ 	]+2025d51b[ 	]+sroiw[ 	]+a0,a1,0x2
++[ 	]+158:[ 	]+48c5f533[ 	]+bfp[ 	]+a0,a1,a2
++[ 	]+15c:[ 	]+4825f53b[ 	]+bfpw[ 	]+a0,a1,0x2
++[ 	]+160:[ 	]+08c5b533[ 	]+bmator[ 	]+a0,a1,a2
++[ 	]+164:[ 	]+48c5b533[ 	]+bmatxor[ 	]+a0,a1,a2
++[ 	]+168:[ 	]+60351513[ 	]+bmatflip[ 	]+a0,a0
++[ 	]+16c:[ 	]+61051513[ 	]+crc32.b[ 	]+a0,a0
++[ 	]+170:[ 	]+61151513[ 	]+crc32.h[ 	]+a0,a0
++[ 	]+174:[ 	]+61251513[ 	]+crc32.w[ 	]+a0,a0
++[ 	]+178:[ 	]+61851513[ 	]+crc32c.b[ 	]+a0,a0
++[ 	]+17c:[ 	]+61951513[ 	]+crc32c.h[ 	]+a0,a0
++[ 	]+180:[ 	]+61a51513[ 	]+crc32c.w[ 	]+a0,a0
++[ 	]+184:[ 	]+61351513[ 	]+crc32.d[ 	]+a0,a0
++[ 	]+188:[ 	]+61b51513[ 	]+crc32c.d[ 	]+a0,a0
++[ 	]+18c:[ 	]+6ec59533[ 	]+cmix[ 	]+a0,a1,a2,a3
++[ 	]+190:[ 	]+6ec5d533[ 	]+cmov[ 	]+a0,a1,a2,a3
++[ 	]+194:[ 	]+6cc59533[ 	]+fsl[ 	]+a0,a1,a2,a3
++[ 	]+198:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
++[ 	]+19c:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
++[ 	]+1a0:[ 	]+6c25953b[ 	]+fslw[ 	]+a0,a1,0x2,a3
++[ 	]+1a4:[ 	]+6c25d53b[ 	]+fsrw[ 	]+a0,a1,0x2,a3
++[ 	]+1a8:[ 	]+6c25d51b[ 	]+fsriw[ 	]+a0,a1,0x2,a3
+\ No newline at end of file
+diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
+index c3ac377f4b..23b1cbe473 100644
+--- a/gas/testsuite/gas/riscv/b-ext-64.s
++++ b/gas/testsuite/gas/riscv/b-ext-64.s
+@@ -37,3 +37,72 @@ target:
+ 	add.uw	a0, a1, a2
+ 	zext.w	a0, a1
+ 	slli.uw	a0, a1, 2
++	pack	a0, a1, a2
++	packu	a0, a1, a2
++	packh	a0, a1, a2
++	packw	a0, a1, 2
++	packuw	a0, a1, 2
++	grev	a0, a1, a2
++	grevi	a0, a1, 2
++	grevw	a0, a1, 2
++	greviw	a0, a1, 2
++	gorc	a0, a1, a2
++	gorci	a0, a1, 2
++	gorcw	a0, a1, 2
++	gorciw	a0, a1, 2
++	shfl	a0, a1, a2
++	shfli	a0, a1, 2
++	shflw	a0, a1, 2
++	unshfl	a0, a1, a2
++	unshfli	a0, a1, 2
++	unshflw	a0, a1, 2
++	xperm.n	a0, a1, a2
++	xperm.b	a0, a1, a2
++	xperm.h	a0, a1, a2
++	xperm.w	a0, a1, 2
++	bset	a0, a1, a2
++	bclr	a0, a1, a2
++	binv	a0, a1, a2
++	bext	a0, a1, a2
++	bdecompress	a0, a1, a2
++	bseti	a0, a1, 2
++	bclri	a0, a1, 2
++	binvi	a0, a1, 2
++	bexti	a0, a1, 2
++	bsetw	a0, a1, a2
++	bclrw	a0, a1, a2
++	binvw	a0, a1, a2
++	bextw	a0, a1, a2
++	bdecompressw	a0, a1, 2
++	bsetiw	a0, a1, 2
++	bclriw	a0, a1, 2
++	binviw	a0, a1, 2
++	slo	a0, a1, a2
++	sro	a0, a1, a2
++	sloi	a0, a1, 2
++	sroi	a0, a1, 2
++	slow	a0, a1, 2
++	srow	a0, a1, 2
++	sloiw	a0, a1, 2
++	sroiw	a0, a1, 2
++	bfp	a0, a1, a2
++	bfpw	a0, a1, 2
++	bmator	a0, a1, a2
++	bmatxor	a0, a1, a2
++	bmatflip	a0, a0
++	crc32.b	a0, a0
++	crc32.h	a0, a0
++	crc32.w	a0, a0
++	crc32c.b	a0, a0
++	crc32c.h	a0, a0
++	crc32c.w	a0, a0
++	crc32.d	a0, a0
++	crc32c.d	a0, a0
++	cmix	a0, a1, a2, a3
++	cmov	a0, a1, a2, a3
++	fsl	a0, a1, a2, a3
++	fsr	a0, a1, a2, a3
++	fsri	a0, a1,  2, a3
++	fslw	a0, a1,  2, a3
++	fsrw	a0, a1,  2, a3
++	fsriw	a0, a1,  2, a3
+\ No newline at end of file
+diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
+index 7410796a3b..059a8fa146 100644
+--- a/gas/testsuite/gas/riscv/b-ext.d
++++ b/gas/testsuite/gas/riscv/b-ext.d
+@@ -33,3 +33,42 @@ Disassembly of section .text:
+ [ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
+ [ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
+ [ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
++[ 	]+64:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
++[ 	]+68:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
++[ 	]+6c:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
++[ 	]+70:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
++[ 	]+74:[ 	]+6825d513[ 	]+rev2.n[ 	]+a0,a1
++[ 	]+78:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
++[ 	]+7c:[ 	]+2825d513[ 	]+orc2.n[ 	]+a0,a1
++[ 	]+80:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
++[ 	]+84:[ 	]+08259513[ 	]+zip2.b[ 	]+a0,a1
++[ 	]+88:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
++[ 	]+8c:[ 	]+0825d513[ 	]+unzip2.b[ 	]+a0,a1
++[ 	]+90:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
++[ 	]+94:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
++[ 	]+98:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
++[ 	]+9c:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
++[ 	]+a0:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
++[ 	]+a4:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
++[ 	]+a8:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
++[ 	]+ac:[ 	]+48c5e533[ 	]+bdecompress[ 	]+a0,a1,a2
++[ 	]+b0:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
++[ 	]+b4:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
++[ 	]+b8:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
++[ 	]+bc:[ 	]+4825d513[ 	]+bexti[ 	]+a0,a1,0x2
++[ 	]+c0:[ 	]+20c59533[ 	]+slo[ 	]+a0,a1,a2
++[ 	]+c4:[ 	]+20c5d533[ 	]+sro[ 	]+a0,a1,a2
++[ 	]+c8:[ 	]+20259513[ 	]+sloi[ 	]+a0,a1,0x2
++[ 	]+cc:[ 	]+2025d513[ 	]+sroi[ 	]+a0,a1,0x2
++[ 	]+d0:[ 	]+48c5f533[ 	]+bfp[ 	]+a0,a1,a2
++[ 	]+d4:[ 	]+61051513[ 	]+crc32.b[ 	]+a0,a0
++[ 	]+d8:[ 	]+61151513[ 	]+crc32.h[ 	]+a0,a0
++[ 	]+dc:[ 	]+61251513[ 	]+crc32.w[ 	]+a0,a0
++[ 	]+e0:[ 	]+61851513[ 	]+crc32c.b[ 	]+a0,a0
++[ 	]+e4:[ 	]+61951513[ 	]+crc32c.h[ 	]+a0,a0
++[ 	]+e8:[ 	]+61a51513[ 	]+crc32c.w[ 	]+a0,a0
++[ 	]+ec:[ 	]+6ec59533[ 	]+cmix[ 	]+a0,a1,a2,a3
++[ 	]+f0:[ 	]+6ec5d533[ 	]+cmov[ 	]+a0,a1,a2,a3
++[ 	]+f4:[ 	]+6cc59533[ 	]+fsl[ 	]+a0,a1,a2,a3
++[ 	]+f8:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
++[ 	]+fc:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
+\ No newline at end of file
+diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
+index 051dafd171..041af79bbd 100644
+--- a/gas/testsuite/gas/riscv/b-ext.s
++++ b/gas/testsuite/gas/riscv/b-ext.s
+@@ -24,3 +24,42 @@ target:
+ 	clmul	a0, a1, a2
+ 	clmulh	a0, a1, a2
+ 	clmulr	a0, a1, a2
++	pack	 a0, a1, a2
++	packu	 a0, a1, a2
++	packh	 a0, a1, a2
++	grev	 a0, a1, a2
++	grevi	 a0, a1, 2
++	gorc	 a0, a1, a2
++	gorci	 a0, a1, 2
++	shfl	 a0, a1, a2
++	shfli	 a0, a1, 2
++	unshfl	 a0, a1, a2
++	unshfli	 a0, a1, 2
++	xperm.n	 a0, a1, a2
++	xperm.b	 a0, a1, a2
++	xperm.h	 a0, a1, a2
++	bset	 a0, a1, a2
++	bclr	 a0, a1, a2
++	binv	 a0, a1, a2
++	bext	 a0, a1, a2
++	bdecompress	 a0, a1, a2
++	bseti	 a0, a1, 2
++	bclri	 a0, a1, 2
++	binvi	 a0, a1, 2
++	bexti	 a0, a1, 2
++	slo	 a0, a1, a2
++	sro	 a0, a1, a2
++	sloi	 a0, a1, 2
++	sroi	 a0, a1, 2
++	bfp	 a0, a1, a2
++	crc32.b	 a0, a0
++	crc32.h	 a0, a0
++	crc32.w	 a0, a0
++	crc32c.b	 a0, a0
++	crc32c.h	 a0, a0
++	crc32c.w	 a0, a0
++	cmix	 a0, a1, a2, a3
++	cmov	 a0, a1, a2, a3
++	fsl	 a0, a1, a2, a3
++	fsr	 a0, a1, a2, a3
++	fsri	 a0, a1, 2, a3
+\ No newline at end of file
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 9999da6241..1a80dbf87d 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -113,6 +113,18 @@
+ #define MASK_SRL  0xfe00707f
+ #define MATCH_SRA 0x40005033
+ #define MASK_SRA  0xfe00707f
++#define MATCH_SLO 0x20001033
++#define MASK_SLO  0xfe00707f
++#define MATCH_SLOI 0x20001013
++#define MASK_SLOI  0xfc00707f
++#define MATCH_SLOW 0x2000103b
++#define MASK_SLOW  0xfe00707f
++#define MATCH_SRO 0x20005033
++#define MASK_SRO  0xfe00707f
++#define MATCH_SROI 0x20005013
++#define MASK_SROI  0xfc00707f
++#define MATCH_SROW 0x2000503b
++#define MASK_SROW  0xfe00707f
+ #define MATCH_OR 0x6033
+ #define MASK_OR  0xfe00707f
+ #define MATCH_AND 0x7033
+@@ -429,6 +441,24 @@
+ #define MASK_CTZ  0xfff0707f
+ #define MATCH_CPOP 0x60201013
+ #define MASK_CPOP  0xfff0707f
++#define MATCH_BMATFLIP 0x60301013
++#define MASK_BMATFLIP  0xfff0707f
++#define MATCH_CRC32_B 0x61001013
++#define MASK_CRC32_B  0xfff0707f
++#define MATCH_CRC32_H 0x61101013
++#define MASK_CRC32_H  0xfff0707f
++#define MATCH_CRC32_W 0x61201013
++#define MASK_CRC32_W  0xfff0707f
++#define MATCH_CRC32_D 0x61301013
++#define MASK_CRC32_D  0xfff0707f
++#define MATCH_CRC32C_B 0x61801013
++#define MASK_CRC32C_B  0xfff0707f
++#define MATCH_CRC32C_H 0x61901013
++#define MASK_CRC32C_H  0xfff0707f
++#define MATCH_CRC32C_W 0x61A01013
++#define MASK_CRC32C_W  0xfff0707f
++#define MATCH_CRC32C_D 0x61B01013
++#define MASK_CRC32C_D  0xfff0707f
+ #define MATCH_MIN 0xa004033
+ #define MASK_MIN  0xfe00707f
+ #define MATCH_MINU 0xa005033
+@@ -437,14 +467,38 @@
+ #define MASK_MAX  0xfe00707f
+ #define MATCH_MAXU 0xa007033
+ #define MASK_MAXU  0xfe00707f
++#define MATCH_SHFL 0x8001033
++#define MASK_SHFL  0xfe00707f
++#define MATCH_SHFLI 0x8001013
++#define MASK_SHFLI  0xfc00707f
++#define MATCH_UNSHFL 0x8005033
++#define MASK_UNSHFL  0xfe00707f
++#define MATCH_UNSHFLI 0x8005013
++#define MASK_UNSHFLI  0xfc00707f
++#define MATCH_BCOMPRESS 0x8006033
++#define MASK_BCOMPRESS  0xfe00707f
++#define MATCH_BDECOMPRESS 0x48006033
++#define MASK_BDECOMPRESS  0xfe00707f
+ #define MATCH_SEXT_B 0x60401013
+ #define MASK_SEXT_B  0xfff0707f
+ #define MATCH_SEXT_H 0x60501013
+ #define MASK_SEXT_H  0xfff0707f
+ #define MATCH_PACK 0x8004033
+ #define MASK_PACK  0xfe00707f
++#define MATCH_PACKU 0x48004033
++#define MASK_PACKU  0xfe00707f
++#define MATCH_BMATOR 0x8003033
++#define MASK_BMATOR  0xfe00707f
++#define MATCH_BMATXOR 0x48003033
++#define MASK_BMATXOR  0xfe00707f
++#define MATCH_PACKH 0x8007033
++#define MASK_PACKH  0xfe00707f
++#define MATCH_BFP 0x48007033
++#define MASK_BFP  0xfe00707f
+ #define MATCH_PACKW 0x800403b
+ #define MASK_PACKW  0xfe00707f
++#define MATCH_PACKUW 0x4800403b
++#define MASK_PACKUW  0xfe00707f
+ #define MATCH_ANDN 0x40007033
+ #define MASK_ANDN  0xfe00707f
+ #define MATCH_ORN 0x40006033
+@@ -457,10 +511,40 @@
+ #define MASK_ROR  0xfe00707f
+ #define MATCH_RORI 0x60005013
+ #define MASK_RORI  0xfc00707f
++#define MATCH_BCLR 0x48001033
++#define MASK_BCLR  0xfe00707f
++#define MATCH_BCLRI 0x48001013
++#define MASK_BCLRI  0xfc00707f
++#define MATCH_BSET 0x28001033
++#define MASK_BSET  0xfe00707f
++#define MATCH_BSETI 0x28001013
++#define MASK_BSETI  0xfc00707f
++#define MATCH_BINV 0x68001033
++#define MASK_BINV  0xfe00707f
++#define MATCH_BINVI 0x68001013
++#define MASK_BINVI  0xfc00707f
++#define MATCH_BEXT 0x48005033
++#define MASK_BEXT  0xfe00707f
++#define MATCH_BEXTI 0x48005013
++#define MASK_BEXTI  0xfc00707f
++#define MATCH_GREV 0x68005033
++#define MASK_GREV  0xfe00707f
+ #define MATCH_GREVI 0x68005013
+ #define MASK_GREVI  0xfc00707f
++#define MATCH_GORC 0x28005033
++#define MASK_GORC  0xfe00707f
+ #define MATCH_GORCI 0x28005013
+ #define MASK_GORCI  0xfc00707f
++#define MATCH_CMIX 0x6001033
++#define MASK_CMIX  0x600707f
++#define MATCH_CMOV 0x6005033
++#define MASK_CMOV  0x600707f
++#define MATCH_FSL 0x4001033
++#define MASK_FSL  0x600707f
++#define MATCH_FSR 0x4005033
++#define MASK_FSR  0x600707f
++#define MATCH_FSRI 0x4005013
++#define MASK_FSRI  0x400707f
+ #define MATCH_CLZW 0x6000101b
+ #define MASK_CLZW  0xfff0707f
+ #define MATCH_CTZW 0x6010101b
+@@ -485,6 +569,56 @@
+ #define MASK_SH2ADD_UW  0xfe00707f
+ #define MATCH_SH3ADD_UW 0x2000603b
+ #define MASK_SH3ADD_UW  0xfe00707f
++#define MATCH_BCLRW 0x4800103b
++#define MASK_BCLRW  0xfe00707f
++#define MATCH_BSETW 0x2800103b
++#define MASK_BSETW  0xfe00707f
++#define MATCH_BINVW 0x6800103b
++#define MASK_BINVW  0xfe00707f
++#define MATCH_BEXTW 0x4800503b
++#define MASK_BEXTW  0xfe00707f
++#define MATCH_GORCW 0x2800503b
++#define MASK_GORCW  0xfe00707f
++#define MATCH_GREVW 0x6800503b
++#define MASK_GREVW  0xfe00707f
++#define MATCH_SLOIW 0x2000101b
++#define MASK_SLOIW  0xfe00707f
++#define MATCH_SROIW 0x2000501b
++#define MASK_SROIW  0xfe00707f
++#define MATCH_BCLRIW 0x4800101b
++#define MASK_BCLRIW  0xfe00707f
++#define MATCH_BSETIW 0x2800101b
++#define MASK_BSETIW  0xfe00707f
++#define MATCH_BINVIW 0x6800101b
++#define MASK_BINVIW  0xfe00707f
++#define MATCH_GORCIW 0x2800501b
++#define MASK_GORCIW  0xfe00707f
++#define MATCH_GREVIW 0x6800501b
++#define MASK_GREVIW  0xfe00707f
++#define MATCH_FSLW 0x400103b
++#define MASK_FSLW  0x600707f
++#define MATCH_FSRW 0x400503B
++#define MASK_FSRW  0x600707f
++#define MATCH_FSRIW 0x400501B
++#define MASK_FSRIW  0x600707f
++#define MATCH_SHFLW 0x800103b
++#define MASK_SHFLW  0xfe00707f
++#define MATCH_UNSHFLW 0x800503b
++#define MASK_UNSHFLW  0xfe00707f
++#define MATCH_BCOMPRESSW 0x800603B
++#define MASK_BCOMPRESSW  0xfe00707f
++#define MATCH_BDECOMPRESSW 0x4800603b
++#define MASK_BDECOMPRESSW  0xfe00707f
++#define MATCH_BFPW 0x4800703b
++#define MASK_BFPW  0xfe00707f
++#define MATCH_XPERM_N 0x28002033
++#define MASK_XPERM_N  0xfe00707f
++#define MATCH_XPERM_B 0x28004033
++#define MASK_XPERM_B  0xfe00707f
++#define MATCH_XPERM_H 0x28006033
++#define MASK_XPERM_H  0xfe00707f
++#define MATCH_XPERM_W 0x28000033
++#define MASK_XPERM_W  0xfe00707f
+ #define MATCH_ADD_UW 0x800003b
+ #define MASK_ADD_UW  0xfe00707f
+ #define MATCH_SLLI_UW 0x800101b
+@@ -1102,6 +1236,78 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
+ DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+ DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
+ DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
++DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
++DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
++DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
++DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
++DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
++DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
++DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
++DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
++DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
++DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
++DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
++DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
++DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
++DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
++DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
++DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
++DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
++DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
++DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
++DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
++DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
++DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
++DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
++DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
++DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
++DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
++DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
++DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS)
++DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
++DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
++DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
++DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
++DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
++DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
++DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
++DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
++DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
++DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW)
++DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
++DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
++DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
++DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
++DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
++DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
++DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
++DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
++DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
++DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
++DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
++DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
++DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
++DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
++DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
++DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
++DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
++DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
++DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
++DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
++DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
++DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
++DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
++DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
++DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
++DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
++DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
++DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
++DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
++DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
++DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
++DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
++DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
++DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
+ DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+ DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+ DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index fdf3df4f5c..ae8c6bd33f 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -319,6 +319,18 @@ enum riscv_insn_class
+   INSN_CLASS_ZBA,
+   INSN_CLASS_ZBB,
+   INSN_CLASS_ZBC,
++  INSN_CLASS_ZBP,
++  INSN_CLASS_ZBB_OR_ZBP,
++  INSN_CLASS_ZBS,
++  INSN_CLASS_ZBE,
++  INSN_CLASS_ZBS_OR_ZBE,
++  INSN_CLASS_ZBF,
++  INSN_CLASS_ZBM,
++  INSN_CLASS_ZBP_OR_ZBM,
++  INSN_CLASS_ZBR,
++  INSN_CLASS_ZBT,
++  INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
++  INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
+ };
+ 
+ /* This structure holds information for a particular instruction.  */
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index f55a01b071..3d9240262c 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -24,6 +24,130 @@
+ #include "opcode/riscv.h"
+ #include <stdio.h>
+ 
++#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_32     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_64     (0b111111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_P_32   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_P_64   (0b000001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_N_32   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_N_64   (0b000011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_B_32   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_B_64   (0b000111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_H_32   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_H_64   (0b001111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV_W_64   (0b011111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_32    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_64    (0b111110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_N_32  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_N_64  (0b000010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_B_32  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_B_64  (0b000110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_H_32  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_H_64  (0b001110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV2_W_64  (0b011110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_32    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_64    (0b111100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_B_32  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_B_64  (0b000100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_H_32  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_H_64  (0b001100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV4_W_64  (0b011100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_32    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_64    (0b111000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_H_32  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_H_64  (0b001000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV8_W_64  (0b011000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV16_32   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV16_64   (0b110000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV16_W_64 (0b010000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_REV32_64   (0b100000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_32     (0b1111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_64     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_N_32   (0b0001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_N_64   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_B_32   (0b0011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_B_64   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_H_32   (0b0111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_H_64   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP_W_64   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_32    (0b1110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_64    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_B_32  (0b0010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_B_64  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_H_32  (0b0110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_H_64  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP2_W_64  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_32    (0b1100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_64    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_H_32  (0b0100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_H_64  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP4_W_64  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_32    (0b1000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_64    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP8_W_64  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ZIP16_64   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_32     (0b1111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_64     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_N_32   (0b0001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_N_64   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_B_32   (0b0011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_B_64   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_H_32   (0b0111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_H_64   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP_W_64   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_32    (0b1110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_64    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_B_32  (0b0010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_B_64  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_H_32  (0b0110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_H_64  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP2_W_64  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_32    (0b1100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_64    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_H_32  (0b0100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_H_64  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP4_W_64  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_32    (0b1000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_64    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP8_W_64  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_UNZIP16_64   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_32     (0b11111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_64     (0b111111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_P_32   (0b00001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_P_64   (0b000001 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_N_32   (0b00011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_N_64   (0b000011 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_B_32   (0b00111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_B_64   (0b000111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_H_32   (0b01111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_H_64   (0b001111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC_W_64   (0b011111 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_32    (0b11110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_64    (0b111110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_N_32  (0b00010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_N_64  (0b000010 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_B_32  (0b00110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_B_64  (0b000110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_H_32  (0b01110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_H_64  (0b001110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC2_W_64  (0b011110 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_32    (0b11100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_64    (0b111100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_B_32  (0b00100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_B_64  (0b000100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_H_32  (0b01100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_H_64  (0b001100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC4_W_64  (0b011100 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_32    (0b11000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_64    (0b111000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_H_32  (0b01000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_H_64  (0b001000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC8_W_64  (0b011000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC16_32   (0b10000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC16_64   (0b110000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC16_W_64 (0b010000 << OP_SH_SHAMT)
++#define MATCH_SHAMT_ORC32_64   (0b100000 << OP_SH_SHAMT)
++
+ /* Register names used by gas and objdump.  */
+ 
+ const char * const riscv_gpr_names_numeric[NGPR] =
+@@ -827,6 +951,198 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"clmulh",     0, INSN_CLASS_ZBC,  "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+ {"clmulr",     0, INSN_CLASS_ZBC,  "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+ 
++/* ZBS instructions */
++{"bclr",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
++{"bclri",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
++{"bext",       0, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"bexti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
++{"binv",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINV, MASK_BINV, match_opcode, 0 },
++{"binvi",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
++{"bset",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSET, MASK_BSET, match_opcode, 0 },
++{"bseti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
++
++/* B instructions excluded from spec1.0 */
++{"rev",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"rev32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV32_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
++{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
++{"orc",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"orc32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC32_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
++{"pack",       0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
++{"packu",      0, INSN_CLASS_ZBP_OR_ZBM,  "d,s,t",    MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
++{"packh",      0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
++{"packw",     64, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,<",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
++{"packuw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
++{"grev",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GREV, MASK_GREV, match_opcode, 0 },
++{"grevi",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
++{"grevw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
++{"greviw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
++{"gorc",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GORC, MASK_GORC, match_opcode, 0 },
++{"gorci",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
++{"gorcw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
++{"gorciw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
++{"shfl",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
++{"shfli",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
++{"shflw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
++{"unshfl",     0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
++{"unshfli",    0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
++{"unshflw",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
++{"xperm.n",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
++{"xperm.b",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
++{"xperm.h",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
++{"xperm.w",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
++{"bcompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BCOMPRESS, MASK_BCOMPRESS, match_opcode, 0 },
++{"bdecompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 },
++{"bsetw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
++{"bclrw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
++{"binvw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
++{"bextw",     64, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
++{"bcompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BCOMPRESSW, MASK_BCOMPRESSW, match_opcode, 0 },
++{"bdecompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 },
++{"bsetiw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
++{"bclriw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
++{"binviw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
++{"slo",        0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_SLO, MASK_SLO, match_opcode, 0 },
++{"sro",        0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_SRO, MASK_SRO, match_opcode, 0 },
++{"sloi",       0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
++{"sroi",       0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_SROI, MASK_SROI, match_opcode, 0 },
++{"slow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
++{"srow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROW, MASK_SROW, match_opcode, 0 },
++{"sloiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
++{"sroiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
++{"bfp",        0, INSN_CLASS_ZBF,  "d,s,t",    MATCH_BFP, MASK_BFP, match_opcode, 0 },
++{"bfpw",      64, INSN_CLASS_ZBF,  "d,s,<",    MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
++{"bmator",    64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
++{"bmatxor",   64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
++{"bmatflip",  64, INSN_CLASS_ZBM,  "d,s",      MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
++{"crc32.b",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
++{"crc32.h",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
++{"crc32.w",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
++{"crc32c.b",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
++{"crc32c.h",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
++{"crc32c.w",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
++{"crc32.d",   64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
++{"crc32c.d",  64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
++{"cmix",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
++{"cmov",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
++{"fsl",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
++{"fsr",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
++{"fsri",       0, INSN_CLASS_ZBT,  "d,s,>,r",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
++{"fslw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
++{"fsrw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
++{"fsriw",     64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+ 
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+-- 
+2.33.1
+

+ 0 - 25
recipes-devtools/binutils/binutils/0001-resolve-bug-1-unsupported-zvmo-extension.patch

@@ -1,25 +0,0 @@
-From 7578dbdb2be0b6183b36303d115521ebae28f2f6 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Tue, 18 May 2021 18:05:37 -0700
-Subject: [PATCH 01/28] resolve bug#1: unsupported zvmo extension
-
----
- bfd/elfxx-riscv.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
-index 97ad51f865..0d5bec4762 100644
---- a/bfd/elfxx-riscv.c
-+++ b/bfd/elfxx-riscv.c
-@@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
- 
- static const char * const riscv_std_z_ext_strtab[] =
- {
--  "zicsr", "zifencei", "zihintpause", NULL
-+  "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg", NULL
- };
- 
- static const char * const riscv_std_s_ext_strtab[] =
--- 
-2.33.0
-

+ 0 - 1001
recipes-devtools/binutils/binutils/0002-Add-support-for-B-extension.patch

@@ -1,1001 +0,0 @@
-From 4bbe6648eb8c452a9dcd77895caf2c3f0d8771f7 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Wed, 19 May 2021 02:19:34 -0700
-Subject: [PATCH 02/28] Add support for B extension
-
----
- bfd/elfxx-riscv.c                  |   2 +-
- gas/config/tc-riscv.c              |  31 +++
- gas/testsuite/gas/riscv/b-ext-64.d | 117 +++++++++++
- gas/testsuite/gas/riscv/b-ext-64.s | 108 ++++++++++
- gas/testsuite/gas/riscv/b-ext.d    |  74 +++++++
- gas/testsuite/gas/riscv/b-ext.s    |  65 +++++++
- include/opcode/riscv-opc.h         | 303 +++++++++++++++++++++++++++++
- include/opcode/riscv.h             |  15 ++
- opcodes/riscv-dis.c                |   4 +
- opcodes/riscv-opc.c                | 139 +++++++++++++
- 10 files changed, 857 insertions(+), 1 deletion(-)
- create mode 100755 gas/testsuite/gas/riscv/b-ext-64.d
- create mode 100755 gas/testsuite/gas/riscv/b-ext-64.s
- create mode 100755 gas/testsuite/gas/riscv/b-ext.d
- create mode 100755 gas/testsuite/gas/riscv/b-ext.s
-
-diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
-index 0d5bec4762..8c8af2386b 100644
---- a/bfd/elfxx-riscv.c
-+++ b/bfd/elfxx-riscv.c
-@@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
- 
- static const char * const riscv_std_z_ext_strtab[] =
- {
--  "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg", NULL
-+  "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt", "zvamo", "zvlsseg",NULL
- };
- 
- static const char * const riscv_std_s_ext_strtab[] =
-diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
-index 3322f17ccb..3e76e538c4 100644
---- a/gas/config/tc-riscv.c
-+++ b/gas/config/tc-riscv.c
-@@ -253,6 +253,37 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
-     case INSN_CLASS_ZIHINTPAUSE:
-       return riscv_subset_supports ("zihintpause");
- 
-+    case INSN_CLASS_ZBB:
-+      return riscv_subset_supports ("zbb");
-+    case INSN_CLASS_ZBA:
-+      return riscv_subset_supports ("zba");
-+    case INSN_CLASS_ZBC:
-+      return riscv_subset_supports ("zbc");
-+    case INSN_CLASS_ZBE:
-+      return riscv_subset_supports ("zbe");
-+    case INSN_CLASS_ZBF:
-+      return riscv_subset_supports ("zbf");
-+    case INSN_CLASS_ZBM:
-+      return riscv_subset_supports ("zbm");
-+    case INSN_CLASS_ZBP:
-+      return riscv_subset_supports ("zbp");
-+    case INSN_CLASS_ZBR:
-+      return riscv_subset_supports ("zbr");
-+    case INSN_CLASS_ZBS:
-+      return riscv_subset_supports ("zbs");
-+    case INSN_CLASS_ZBT:
-+      return riscv_subset_supports ("zbt");
-+    case INSN_CLASS_ZBB_OR_ZBP:
-+      return (riscv_subset_supports ("zbb") || riscv_subset_supports ("zbp"));
-+    case INSN_CLASS_ZBS_OR_ZBE:
-+      return (riscv_subset_supports ("zbs") || riscv_subset_supports ("zbe"));
-+    case INSN_CLASS_ZBP_OR_ZBM:
-+      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbm"));
-+    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF:
-+      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
-+    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
-+      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
-+
-     default:
-       as_fatal ("Unreachable");
-       return FALSE;
-diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
-new file mode 100755
-index 0000000000..23da2e0d58
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/b-ext-64.d
-@@ -0,0 +1,117 @@
-+#as: -march=rv64i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
-+#source: b-ext-64.s
-+#objdump: -d
-+
-+.*:[ 	]+file format .*
-+
-+
-+Disassembly of section .text:
-+
-+0+000 <target>:
-+[ 	]+0:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
-+[ 	]+4:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
-+[ 	]+8:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
-+[ 	]+c:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
-+[ 	]+10:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
-+[ 	]+14:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
-+[ 	]+18:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
-+[ 	]+1c:[ 	]+60451513[ 	]+sext.b[ 	]+a0,a0
-+[ 	]+20:[ 	]+60551513[ 	]+sext.h[ 	]+a0,a0
-+[ 	]+24:[ 	]+0805453b[ 	]+zext.h[ 	]+a0,a0
-+[ 	]+28:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
-+[ 	]+2c:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
-+[ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
-+[ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
-+[ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
-+[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
-+[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
-+[ 	]+44:[ 	]+6b855513[ 	]+rev8[ 	]+a0,a0
-+[ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
-+[ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
-+[ 	]+50:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
-+[ 	]+54:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
-+[ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
-+[ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
-+[ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
-+[ 	]+64:[ 	]+6005151b[ 	]+clzw[ 	]+a0,a0
-+[ 	]+68:[ 	]+6015151b[ 	]+ctzw[ 	]+a0,a0
-+[ 	]+6c:[ 	]+6025151b[ 	]+cpopw[ 	]+a0,a0
-+[ 	]+70:[ 	]+60c5953b[ 	]+rolw[ 	]+a0,a1,a2
-+[ 	]+74:[ 	]+60c5d53b[ 	]+rorw[ 	]+a0,a1,a2
-+[ 	]+78:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
-+[ 	]+7c:[ 	]+6025d51b[ 	]+roriw[ 	]+a0,a1,0x2
-+[ 	]+80:[ 	]+20c5a53b[ 	]+sh1add.uw[ 	]+a0,a1,a2
-+[ 	]+84:[ 	]+20c5c53b[ 	]+sh2add.uw[ 	]+a0,a1,a2
-+[ 	]+88:[ 	]+20c5e53b[ 	]+sh3add.uw[ 	]+a0,a1,a2
-+[ 	]+8c:[ 	]+08c5853b[ 	]+add.uw[ 	]+a0,a1,a2
-+[ 	]+90:[ 	]+0805853b[ 	]+zext.w[ 	]+a0,a1
-+[ 	]+94:[ 	]+0825951b[ 	]+slli.uw[ 	]+a0,a1,0x2
-+[ 	]+98:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
-+[ 	]+9c:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
-+[ 	]+a0:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
-+[ 	]+a4:[ 	]+0825c53b[ 	]+packw[ 	]+a0,a1,0x2
-+[ 	]+a8:[ 	]+4825c53b[ 	]+packuw[ 	]+a0,a1,0x2
-+[ 	]+ac:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
-+[ 	]+b0:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
-+[ 	]+b4:[ 	]+6825d53b[ 	]+grevw[ 	]+a0,a1,0x2
-+[ 	]+b8:[ 	]+6825d51b[ 	]+greviw[ 	]+a0,a1,0x2
-+[ 	]+bc:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
-+[ 	]+c0:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
-+[ 	]+c4:[ 	]+2825d53b[ 	]+gorcw[ 	]+a0,a1,0x2
-+[ 	]+c8:[ 	]+2825d51b[ 	]+gorciw[ 	]+a0,a1,0x2
-+[ 	]+cc:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
-+[ 	]+d0:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
-+[ 	]+d4:[ 	]+0825953b[ 	]+shflw[ 	]+a0,a1,0x2
-+[ 	]+d8:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
-+[ 	]+dc:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
-+[ 	]+e0:[ 	]+0825d53b[ 	]+unshflw[ 	]+a0,a1,0x2
-+[ 	]+e4:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
-+[ 	]+e8:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
-+[ 	]+ec:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
-+[ 	]+f0:[ 	]+28258533[ 	]+xperm.w[ 	]+a0,a1,0x2
-+[ 	]+f4:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
-+[ 	]+f8:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
-+[ 	]+fc:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
-+[ 	]+100:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
-+[ 	]+104:[ 	]+48c5e533[ 	]+bdep[ 	]+a0,a1,a2
-+[ 	]+108:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
-+[ 	]+10c:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
-+[ 	]+110:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
-+[ 	]+114:[ 	]+4825d513[ 	]+bexti[ 	]+a0,a1,0x2
-+[ 	]+118:[ 	]+28c5953b[ 	]+bsetw[ 	]+a0,a1,a2
-+[ 	]+11c:[ 	]+48c5953b[ 	]+bclrw[ 	]+a0,a1,a2
-+[ 	]+120:[ 	]+68c5953b[ 	]+binvw[ 	]+a0,a1,a2
-+[ 	]+124:[ 	]+48c5d53b[ 	]+bextw[ 	]+a0,a1,a2
-+[ 	]+128:[ 	]+4825e53b[ 	]+bdepw[ 	]+a0,a1,0x2
-+[ 	]+12c:[ 	]+2825951b[ 	]+bsetiw[ 	]+a0,a1,0x2
-+[ 	]+130:[ 	]+4825951b[ 	]+bclriw[ 	]+a0,a1,0x2
-+[ 	]+134:[ 	]+6825951b[ 	]+binviw[ 	]+a0,a1,0x2
-+[ 	]+138:[ 	]+20c59533[ 	]+slo[ 	]+a0,a1,a2
-+[ 	]+13c:[ 	]+20c5d533[ 	]+sro[ 	]+a0,a1,a2
-+[ 	]+140:[ 	]+20259513[ 	]+sloi[ 	]+a0,a1,0x2
-+[ 	]+144:[ 	]+2025d513[ 	]+sroi[ 	]+a0,a1,0x2
-+[ 	]+148:[ 	]+2025953b[ 	]+slow[ 	]+a0,a1,0x2
-+[ 	]+14c:[ 	]+2025d53b[ 	]+srow[ 	]+a0,a1,0x2
-+[ 	]+150:[ 	]+2025951b[ 	]+sloiw[ 	]+a0,a1,0x2
-+[ 	]+154:[ 	]+2025d51b[ 	]+sroiw[ 	]+a0,a1,0x2
-+[ 	]+158:[ 	]+48c5f533[ 	]+bfp[ 	]+a0,a1,a2
-+[ 	]+15c:[ 	]+4825f53b[ 	]+bfpw[ 	]+a0,a1,0x2
-+[ 	]+160:[ 	]+08c5b533[ 	]+bmator[ 	]+a0,a1,a2
-+[ 	]+164:[ 	]+48c5b533[ 	]+bmatxor[ 	]+a0,a1,a2
-+[ 	]+168:[ 	]+60351513[ 	]+bmatflip[ 	]+a0,a0
-+[ 	]+16c:[ 	]+61051513[ 	]+crc32.b[ 	]+a0,a0
-+[ 	]+170:[ 	]+61151513[ 	]+crc32.h[ 	]+a0,a0
-+[ 	]+174:[ 	]+61251513[ 	]+crc32.w[ 	]+a0,a0
-+[ 	]+178:[ 	]+61851513[ 	]+crc32c.b[ 	]+a0,a0
-+[ 	]+17c:[ 	]+61951513[ 	]+crc32c.h[ 	]+a0,a0
-+[ 	]+180:[ 	]+61a51513[ 	]+crc32c.w[ 	]+a0,a0
-+[ 	]+184:[ 	]+61351513[ 	]+crc32.d[ 	]+a0,a0
-+[ 	]+188:[ 	]+61b51513[ 	]+crc32c.d[ 	]+a0,a0
-+[ 	]+18c:[ 	]+6ec59533[ 	]+cmix[ 	]+a0,a1,a2,a3
-+[ 	]+190:[ 	]+6ec5d533[ 	]+cmov[ 	]+a0,a1,a2,a3
-+[ 	]+194:[ 	]+6cc59533[ 	]+fsl[ 	]+a0,a1,a2,a3
-+[ 	]+198:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
-+[ 	]+19c:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
-+[ 	]+1a0:[ 	]+6c25953b[ 	]+fslw[ 	]+a0,a1,0x2,a3
-+[ 	]+1a4:[ 	]+6c25b53b[ 	]+fsrw[ 	]+a0,a1,0x2,a3
-+[ 	]+1a8:[ 	]+6c25b51b[ 	]+fsriw[ 	]+a0,a1,0x2,a3
-diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
-new file mode 100755
-index 0000000000..176d617be5
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/b-ext-64.s
-@@ -0,0 +1,108 @@
-+target:
-+	clz	a0, a0
-+	ctz	a0, a0
-+	cpop	a0, a0
-+	min	a0, a1, a2
-+	minu	a0, a1, a2
-+	max	a0, a1, a2
-+	maxu	a0, a1, a2
-+	sext.b	a0, a0
-+	sext.h	a0, a0
-+	zext.h	a0, a0
-+	andn	a0, a1, a2
-+	orn	a0, a1, a2
-+	xnor	a0, a1, a2
-+	rol	a0, a1, a2
-+	ror	a0, a1, a2
-+	ror	a0, a1, 2
-+	rori	a0, a1, 2
-+	rev8	a0, a0
-+	orc.b	a0, a0
-+	sh1add	a0, a1, a2
-+	sh2add	a0, a1, a2
-+	sh3add	a0, a1, a2
-+	clmul	a0, a1, a2
-+	clmulh	a0, a1, a2
-+	clmulr	a0, a1, a2
-+	clzw	a0, a0
-+	ctzw	a0, a0
-+	cpopw	a0, a0
-+	rolw	a0, a1, a2
-+	rorw	a0, a1, a2
-+	rorw	a0, a1, 2
-+	roriw	a0, a1, 2
-+	sh1add.uw	a0, a1, a2
-+	sh2add.uw	a0, a1, a2
-+	sh3add.uw	a0, a1, a2
-+	add.uw	a0, a1, a2
-+	zext.w	a0, a1
-+	slli.uw	a0, a1, 2
-+	pack	a0, a1, a2
-+	packu	a0, a1, a2
-+	packh	a0, a1, a2
-+	packw	a0, a1, 2
-+	packuw	a0, a1, 2
-+	grev	a0, a1, a2
-+	grevi	a0, a1, 2
-+	grevw	a0, a1, 2
-+	greviw	a0, a1, 2
-+	gorc	a0, a1, a2
-+	gorci	a0, a1, 2
-+	gorcw	a0, a1, 2
-+	gorciw	a0, a1, 2
-+	shfl	a0, a1, a2
-+	shfli	a0, a1, 2
-+	shflw	a0, a1, 2
-+	unshfl	a0, a1, a2
-+	unshfli	a0, a1, 2
-+	unshflw	a0, a1, 2
-+	xperm.n	a0, a1, a2
-+	xperm.b	a0, a1, a2
-+	xperm.h	a0, a1, a2
-+	xperm.w	a0, a1, 2
-+	bset	a0, a1, a2
-+	bclr	a0, a1, a2
-+	binv	a0, a1, a2
-+	bext	a0, a1, a2
-+	bdep	a0, a1, a2
-+	bseti	a0, a1, 2
-+	bclri	a0, a1, 2
-+	binvi	a0, a1, 2
-+	bexti	a0, a1, 2
-+	bsetw	a0, a1, a2
-+	bclrw	a0, a1, a2
-+	binvw	a0, a1, a2
-+	bextw	a0, a1, a2
-+	bdepw	a0, a1, 2
-+	bsetiw	a0, a1, 2
-+	bclriw	a0, a1, 2
-+	binviw	a0, a1, 2
-+	slo	a0, a1, a2
-+	sro	a0, a1, a2
-+	sloi	a0, a1, 2
-+	sroi	a0, a1, 2
-+	slow	a0, a1, 2
-+	srow	a0, a1, 2
-+	sloiw	a0, a1, 2
-+	sroiw	a0, a1, 2
-+	bfp	a0, a1, a2
-+	bfpw	a0, a1, 2
-+	bmator	a0, a1, a2
-+	bmatxor	a0, a1, a2
-+	bmatflip	a0, a0
-+	crc32.b	a0, a0
-+	crc32.h	a0, a0
-+	crc32.w	a0, a0
-+	crc32c.b	a0, a0
-+	crc32c.h	a0, a0
-+	crc32c.w	a0, a0
-+	crc32.d	a0, a0
-+	crc32c.d	a0, a0
-+	cmix	a0, a1, a2, a3
-+	cmov	a0, a1, a2, a3
-+	fsl	a0, a1, a2, a3
-+	fsr	a0, a1, a2, a3
-+	fsri	a0, a1,  2, a3
-+	fslw	a0, a1,  2, a3
-+	fsrw	a0, a1,  2, a3
-+	fsriw	a0, a1,  2, a3
-diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
-new file mode 100755
-index 0000000000..4df9e90693
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/b-ext.d
-@@ -0,0 +1,74 @@
-+#as: -march=rv32i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
-+#source: b-ext.s
-+#objdump: -d
-+
-+.*:[ 	]+file format .*
-+
-+
-+Disassembly of section .text:
-+
-+0+000 <target>:
-+[ 	]+0:[ 	]+60051513[ 	]+clz[ 	]+a0,a0
-+[ 	]+4:[ 	]+60151513[ 	]+ctz[ 	]+a0,a0
-+[ 	]+8:[ 	]+60251513[ 	]+cpop[ 	]+a0,a0
-+[ 	]+c:[ 	]+0ac5c533[ 	]+min[ 	]+a0,a1,a2
-+[ 	]+10:[ 	]+0ac5d533[ 	]+minu[ 	]+a0,a1,a2
-+[ 	]+14:[ 	]+0ac5e533[ 	]+max[ 	]+a0,a1,a2
-+[ 	]+18:[ 	]+0ac5f533[ 	]+maxu[ 	]+a0,a1,a2
-+[ 	]+1c:[ 	]+60451513[ 	]+sext.b[ 	]+a0,a0
-+[ 	]+20:[ 	]+60551513[ 	]+sext.h[ 	]+a0,a0
-+[ 	]+24:[ 	]+08054533[ 	]+zext.h[ 	]+a0,a0
-+[ 	]+28:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
-+[ 	]+2c:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
-+[ 	]+30:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
-+[ 	]+34:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
-+[ 	]+38:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
-+[ 	]+3c:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
-+[ 	]+40:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
-+[ 	]+44:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
-+[ 	]+48:[ 	]+28755513[ 	]+orc.b[ 	]+a0,a0
-+[ 	]+4c:[ 	]+20c5a533[ 	]+sh1add[ 	]+a0,a1,a2
-+[ 	]+50:[ 	]+20c5c533[ 	]+sh2add[ 	]+a0,a1,a2
-+[ 	]+54:[ 	]+20c5e533[ 	]+sh3add[ 	]+a0,a1,a2
-+[ 	]+58:[ 	]+0ac59533[ 	]+clmul[ 	]+a0,a1,a2
-+[ 	]+5c:[ 	]+0ac5b533[ 	]+clmulh[ 	]+a0,a1,a2
-+[ 	]+60:[ 	]+0ac5a533[ 	]+clmulr[ 	]+a0,a1,a2
-+[ 	]+64:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
-+[ 	]+68:[ 	]+48c5c533[ 	]+packu[ 	]+a0,a1,a2
-+[ 	]+6c:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
-+[ 	]+70:[ 	]+68c5d533[ 	]+grev[ 	]+a0,a1,a2
-+[ 	]+74:[ 	]+6825d513[ 	]+grevi[ 	]+a0,a1,0x2
-+[ 	]+78:[ 	]+28c5d533[ 	]+gorc[ 	]+a0,a1,a2
-+[ 	]+7c:[ 	]+2825d513[ 	]+gorci[ 	]+a0,a1,0x2
-+[ 	]+80:[ 	]+08c59533[ 	]+shfl[ 	]+a0,a1,a2
-+[ 	]+84:[ 	]+08259513[ 	]+shfli[ 	]+a0,a1,0x2
-+[ 	]+88:[ 	]+08c5d533[ 	]+unshfl[ 	]+a0,a1,a2
-+[ 	]+8c:[ 	]+0825d513[ 	]+unshfli[ 	]+a0,a1,0x2
-+[ 	]+90:[ 	]+28c5a533[ 	]+xperm.n[ 	]+a0,a1,a2
-+[ 	]+94:[ 	]+28c5c533[ 	]+xperm.b[ 	]+a0,a1,a2
-+[ 	]+98:[ 	]+28c5e533[ 	]+xperm.h[ 	]+a0,a1,a2
-+[ 	]+9c:[ 	]+28c59533[ 	]+bset[ 	]+a0,a1,a2
-+[ 	]+a0:[ 	]+48c59533[ 	]+bclr[ 	]+a0,a1,a2
-+[ 	]+a4:[ 	]+68c59533[ 	]+binv[ 	]+a0,a1,a2
-+[ 	]+a8:[ 	]+48c5d533[ 	]+bext[ 	]+a0,a1,a2
-+[ 	]+ac:[ 	]+48c5e533[ 	]+bdep[ 	]+a0,a1,a2
-+[ 	]+b0:[ 	]+28259513[ 	]+bseti[ 	]+a0,a1,0x2
-+[ 	]+b4:[ 	]+48259513[ 	]+bclri[ 	]+a0,a1,0x2
-+[ 	]+b8:[ 	]+68259513[ 	]+binvi[ 	]+a0,a1,0x2
-+[ 	]+bc:[ 	]+4825d513[ 	]+bexti[ 	]+a0,a1,0x2
-+[ 	]+c0:[ 	]+20c59533[ 	]+slo[ 	]+a0,a1,a2
-+[ 	]+c4:[ 	]+20c5d533[ 	]+sro[ 	]+a0,a1,a2
-+[ 	]+c8:[ 	]+20259513[ 	]+sloi[ 	]+a0,a1,0x2
-+[ 	]+cc:[ 	]+2025d513[ 	]+sroi[ 	]+a0,a1,0x2
-+[ 	]+d0:[ 	]+48c5f533[ 	]+bfp[ 	]+a0,a1,a2
-+[ 	]+d4:[ 	]+61051513[ 	]+crc32.b[ 	]+a0,a0
-+[ 	]+d8:[ 	]+61151513[ 	]+crc32.h[ 	]+a0,a0
-+[ 	]+dc:[ 	]+61251513[ 	]+crc32.w[ 	]+a0,a0
-+[ 	]+e0:[ 	]+61851513[ 	]+crc32c.b[ 	]+a0,a0
-+[ 	]+e4:[ 	]+61951513[ 	]+crc32c.h[ 	]+a0,a0
-+[ 	]+e8:[ 	]+61a51513[ 	]+crc32c.w[ 	]+a0,a0
-+[ 	]+ec:[ 	]+6ec59533[ 	]+cmix[ 	]+a0,a1,a2,a3
-+[ 	]+f0:[ 	]+6ec5d533[ 	]+cmov[ 	]+a0,a1,a2,a3
-+[ 	]+f4:[ 	]+6cc59533[ 	]+fsl[ 	]+a0,a1,a2,a3
-+[ 	]+f8:[ 	]+6cc5d533[ 	]+fsr[ 	]+a0,a1,a2,a3
-+[ 	]+fc:[ 	]+6c25d513[ 	]+fsri[ 	]+a0,a1,0x2,a3
-diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
-new file mode 100755
-index 0000000000..429c005849
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/b-ext.s
-@@ -0,0 +1,65 @@
-+target:
-+	clz	 a0, a0
-+	ctz	 a0, a0
-+	cpop	 a0, a0
-+	min	 a0, a1, a2
-+	minu	 a0, a1, a2
-+	max	 a0, a1, a2
-+	maxu	 a0, a1, a2
-+	sext.b	 a0, a0
-+	sext.h	 a0, a0
-+	zext.h	 a0, a0
-+	andn	 a0, a1, a2
-+	orn	 a0, a1, a2
-+	xnor	 a0, a1, a2
-+	rol	 a0, a1, a2
-+	ror	 a0, a1, a2
-+	ror	 a0, a1, 2
-+	rori	 a0, a1, 2
-+	rev8	 a0, a0
-+	orc.b	 a0, a0
-+	sh1add	 a0, a1, a2
-+	sh2add	 a0, a1, a2
-+	sh3add	 a0, a1, a2
-+	clmul	 a0, a1, a2
-+	clmulh	 a0, a1, a2
-+	clmulr	 a0, a1, a2
-+	pack	 a0, a1, a2
-+	packu	 a0, a1, a2
-+	packh	 a0, a1, a2
-+	grev	 a0, a1, a2
-+	grevi	 a0, a1, 2
-+	gorc	 a0, a1, a2
-+	gorci	 a0, a1, 2
-+	shfl	 a0, a1, a2
-+	shfli	 a0, a1, 2
-+	unshfl	 a0, a1, a2
-+	unshfli	 a0, a1, 2
-+	xperm.n	 a0, a1, a2
-+	xperm.b	 a0, a1, a2
-+	xperm.h	 a0, a1, a2
-+	bset	 a0, a1, a2
-+	bclr	 a0, a1, a2
-+	binv	 a0, a1, a2
-+	bext	 a0, a1, a2
-+	bdep	 a0, a1, a2
-+	bseti	 a0, a1, 2
-+	bclri	 a0, a1, 2
-+	binvi	 a0, a1, 2
-+	bexti	 a0, a1, 2
-+	slo	 a0, a1, a2
-+	sro	 a0, a1, a2
-+	sloi	 a0, a1, 2
-+	sroi	 a0, a1, 2
-+	bfp	 a0, a1, a2
-+	crc32.b	 a0, a0
-+	crc32.h	 a0, a0
-+	crc32.w	 a0, a0
-+	crc32c.b	 a0, a0
-+	crc32c.h	 a0, a0
-+	crc32c.w	 a0, a0
-+	cmix	 a0, a1, a2, a3
-+	cmov	 a0, a1, a2, a3
-+	fsl	 a0, a1, a2, a3
-+	fsr	 a0, a1, a2, a3
-+	fsri	 a0, a1, 2, a3
-diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
-index b0e549a0f2..1a9e313fc3 100644
---- a/include/opcode/riscv-opc.h
-+++ b/include/opcode/riscv-opc.h
-@@ -113,6 +113,18 @@
- #define MASK_SRL  0xfe00707f
- #define MATCH_SRA 0x40005033
- #define MASK_SRA  0xfe00707f
-+#define MATCH_SLO 0x20001033
-+#define MASK_SLO  0xfe00707f
-+#define MATCH_SLOI 0x20001013
-+#define MASK_SLOI  0xfc00707f
-+#define MATCH_SLOW 0x2000103b
-+#define MASK_SLOW  0xfe00707f
-+#define MATCH_SRO 0x20005033
-+#define MASK_SRO  0xfe00707f
-+#define MATCH_SROI 0x20005013
-+#define MASK_SROI  0xfc00707f
-+#define MATCH_SROW 0x2000503b
-+#define MASK_SROW  0xfe00707f
- #define MATCH_OR 0x6033
- #define MASK_OR  0xfe00707f
- #define MATCH_AND 0x7033
-@@ -423,6 +435,196 @@
- #define MASK_FCVT_Q_LU  0xfff0007f
- #define MATCH_FMV_Q_X 0xf6000053
- #define MASK_FMV_Q_X  0xfff0707f
-+#define MATCH_CLZ 0x60001013
-+#define MASK_CLZ  0xfff0707f
-+#define MATCH_CTZ 0x60101013
-+#define MASK_CTZ  0xfff0707f
-+#define MATCH_CPOP 0x60201013
-+#define MASK_CPOP  0xfff0707f
-+#define MATCH_BMATFLIP 0x60301013
-+#define MASK_BMATFLIP  0xfff0707f
-+#define MATCH_CRC32_B 0x61001013
-+#define MASK_CRC32_B  0xfff0707f
-+#define MATCH_CRC32_H 0x61101013
-+#define MASK_CRC32_H  0xfff0707f
-+#define MATCH_CRC32_W 0x61201013
-+#define MASK_CRC32_W  0xfff0707f
-+#define MATCH_CRC32_D 0x61301013
-+#define MASK_CRC32_D  0xfff0707f
-+#define MATCH_CRC32C_B 0x61801013
-+#define MASK_CRC32C_B  0xfff0707f
-+#define MATCH_CRC32C_H 0x61901013
-+#define MASK_CRC32C_H  0xfff0707f
-+#define MATCH_CRC32C_W 0x61A01013
-+#define MASK_CRC32C_W  0xfff0707f
-+#define MATCH_CRC32C_D 0x61B01013
-+#define MASK_CRC32C_D  0xfff0707f
-+#define MATCH_MIN 0xa004033
-+#define MASK_MIN  0xfe00707f
-+#define MATCH_MINU 0xa005033
-+#define MASK_MINU  0xfe00707f
-+#define MATCH_MAX 0xa006033
-+#define MASK_MAX  0xfe00707f
-+#define MATCH_MAXU 0xa007033
-+#define MASK_MAXU  0xfe00707f
-+#define MATCH_SHFL 0x8001033
-+#define MASK_SHFL  0xfe00707f
-+#define MATCH_SHFLI 0x8001013
-+#define MASK_SHFLI  0xfc00707f
-+#define MATCH_UNSHFL 0x8005033
-+#define MASK_UNSHFL  0xfe00707f
-+#define MATCH_UNSHFLI 0x8005013
-+#define MASK_UNSHFLI  0xfc00707f
-+#define MATCH_BDEP 0x48006033
-+#define MASK_BDEP  0xfe00707f
-+#define MATCH_SEXT_B 0x60401013
-+#define MASK_SEXT_B  0xfff0707f
-+#define MATCH_SEXT_H 0x60501013
-+#define MASK_SEXT_H  0xfff0707f
-+#define MATCH_PACK 0x8004033
-+#define MASK_PACK  0xfe00707f
-+#define MATCH_PACKU 0x48004033
-+#define MASK_PACKU  0xfe00707f
-+#define MATCH_BMATOR 0x8003033
-+#define MASK_BMATOR  0xfe00707f
-+#define MATCH_BMATXOR 0x48003033
-+#define MASK_BMATXOR  0xfe00707f
-+#define MATCH_PACKH 0x8007033
-+#define MASK_PACKH  0xfe00707f
-+#define MATCH_BFP 0x48007033
-+#define MASK_BFP  0xfe00707f
-+#define MATCH_PACKW 0x800403b
-+#define MASK_PACKW  0xfe00707f
-+#define MATCH_PACKUW 0x4800403b
-+#define MASK_PACKUW  0xfe00707f
-+#define MATCH_ANDN 0x40007033
-+#define MASK_ANDN  0xfe00707f
-+#define MATCH_ORN 0x40006033
-+#define MASK_ORN  0xfe00707f
-+#define MATCH_XNOR 0x40004033
-+#define MASK_XNOR  0xfe00707f
-+#define MATCH_ROL 0x60001033
-+#define MASK_ROL  0xfe00707f
-+#define MATCH_ROR 0x60005033
-+#define MASK_ROR  0xfe00707f
-+#define MATCH_RORI 0x60005013
-+#define MASK_RORI  0xfc00707f
-+#define MATCH_BCLR 0x48001033
-+#define MASK_BCLR  0xfe00707f
-+#define MATCH_BCLRI 0x48001013
-+#define MASK_BCLRI  0xfc00707f
-+#define MATCH_BSET 0x28001033
-+#define MASK_BSET  0xfe00707f
-+#define MATCH_BSETI 0x28001013
-+#define MASK_BSETI  0xfc00707f
-+#define MATCH_BINV 0x68001033
-+#define MASK_BINV  0xfe00707f
-+#define MATCH_BINVI 0x68001013
-+#define MASK_BINVI  0xfc00707f
-+#define MATCH_BEXT 0x48005033
-+#define MASK_BEXT  0xfe00707f
-+#define MATCH_BEXTI 0x48005013
-+#define MASK_BEXTI  0xfc00707f
-+#define MATCH_GREV 0x68005033
-+#define MASK_GREV  0xfe00707f
-+#define MATCH_GREVI 0x68005013
-+#define MASK_GREVI  0xfc00707f
-+#define MATCH_GORC 0x28005033
-+#define MASK_GORC  0xfe00707f
-+#define MATCH_GORCI 0x28005013
-+#define MASK_GORCI  0xfc00707f
-+#define MATCH_CMIX 0x6001033
-+#define MASK_CMIX  0x600707f
-+#define MATCH_CMOV 0x6005033
-+#define MASK_CMOV  0x600707f
-+#define MATCH_FSL 0x4001033
-+#define MASK_FSL  0x600707f
-+#define MATCH_FSR 0x4005033
-+#define MASK_FSR  0x600707f
-+#define MATCH_FSRI 0x4005013
-+#define MASK_FSRI  0x400707f
-+#define MATCH_CLZW 0x6000101b
-+#define MASK_CLZW  0xfff0707f
-+#define MATCH_CTZW 0x6010101b
-+#define MASK_CTZW  0xfff0707f
-+#define MATCH_CPOPW 0x6020101b
-+#define MASK_CPOPW  0xfff0707f
-+#define MATCH_ROLW 0x6000103b
-+#define MASK_ROLW  0xfe00707f
-+#define MATCH_RORW 0x6000503b
-+#define MASK_RORW  0xfe00707f
-+#define MATCH_RORIW 0x6000501b
-+#define MASK_RORIW  0xfe00707f
-+#define MATCH_SH1ADD 0x20002033
-+#define MASK_SH1ADD  0xfe00707f
-+#define MATCH_SH2ADD 0x20004033
-+#define MASK_SH2ADD  0xfe00707f
-+#define MATCH_SH3ADD 0x20006033
-+#define MASK_SH3ADD  0xfe00707f
-+#define MATCH_SH1ADD_UW 0x2000203b
-+#define MASK_SH1ADD_UW  0xfe00707f
-+#define MATCH_SH2ADD_UW 0x2000403b
-+#define MASK_SH2ADD_UW  0xfe00707f
-+#define MATCH_SH3ADD_UW 0x2000603b
-+#define MASK_SH3ADD_UW  0xfe00707f
-+#define MATCH_BCLRW 0x4800103b
-+#define MASK_BCLRW  0xfe00707f
-+#define MATCH_BSETW 0x2800103b
-+#define MASK_BSETW  0xfe00707f
-+#define MATCH_BINVW 0x6800103b
-+#define MASK_BINVW  0xfe00707f
-+#define MATCH_BEXTW 0x4800503b
-+#define MASK_BEXTW  0xfe00707f
-+#define MATCH_GORCW 0x2800503b
-+#define MASK_GORCW  0xfe00707f
-+#define MATCH_GREVW 0x6800503b
-+#define MASK_GREVW  0xfe00707f
-+#define MATCH_SLOIW 0x2000101b
-+#define MASK_SLOIW  0xfe00707f
-+#define MATCH_SROIW 0x2000501b
-+#define MASK_SROIW  0xfe00707f
-+#define MATCH_BCLRIW 0x4800101b
-+#define MASK_BCLRIW  0xfe00707f
-+#define MATCH_BSETIW 0x2800101b
-+#define MASK_BSETIW  0xfe00707f
-+#define MATCH_BINVIW 0x6800101b
-+#define MASK_BINVIW  0xfe00707f
-+#define MATCH_GORCIW 0x2800501b
-+#define MASK_GORCIW  0xfe00707f
-+#define MATCH_GREVIW 0x6800501b
-+#define MASK_GREVIW  0xfe00707f
-+#define MATCH_FSLW 0x400103b
-+#define MASK_FSLW  0x600707f
-+#define MATCH_FSRW 0x400303b
-+#define MASK_FSRW  0x600707f
-+#define MATCH_FSRIW 0x400301b
-+#define MASK_FSRIW  0x600707f
-+#define MATCH_SHFLW 0x800103b
-+#define MASK_SHFLW  0xfe00707f
-+#define MATCH_UNSHFLW 0x800503b
-+#define MASK_UNSHFLW  0xfe00707f
-+#define MATCH_BDEPW 0x4800603b
-+#define MASK_BDEPW  0xfe00707f
-+#define MATCH_BFPW 0x4800703b
-+#define MASK_BFPW  0xfe00707f
-+#define MATCH_XPERM_N 0x28002033
-+#define MASK_XPERM_N  0xfe00707f
-+#define MATCH_XPERM_B 0x28004033
-+#define MASK_XPERM_B  0xfe00707f
-+#define MATCH_XPERM_H 0x28006033
-+#define MASK_XPERM_H  0xfe00707f
-+#define MATCH_XPERM_W 0x28000033
-+#define MASK_XPERM_W  0xfe00707f
-+#define MATCH_ADD_UW 0x800003b
-+#define MASK_ADD_UW  0xfe00707f
-+#define MATCH_SLLI_UW 0x800101b
-+#define MASK_SLLI_UW  0xfc00707f
-+#define MATCH_CLMUL 0xa001033
-+#define MASK_CLMUL  0xfe00707f
-+#define MATCH_CLMULH 0xa003033
-+#define MASK_CLMULH  0xfe00707f
-+#define MATCH_CLMULR 0xa002033
-+#define MASK_CLMULR  0xfe00707f
- #define MATCH_FLW 0x2007
- #define MASK_FLW  0x707f
- #define MATCH_FLD 0x3007
-@@ -1046,6 +1248,107 @@ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
- DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
- DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
- DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
-+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
-+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
-+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
-+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
-+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
-+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
-+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
-+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
-+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
-+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
-+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
-+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
-+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
-+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
-+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
-+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
-+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
-+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
-+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
-+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
-+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
-+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
-+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
-+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
-+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
-+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
-+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
-+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
-+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
-+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
-+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
-+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
-+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
-+DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
-+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
-+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
-+DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
-+DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
-+DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
-+DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
-+DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
-+DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
-+DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
-+DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
-+DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
-+DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
-+DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
-+DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
-+DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
-+DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
-+DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
-+DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
-+DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
-+DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
-+DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
-+DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
-+DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
-+DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
-+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
-+DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
-+DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
-+DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
-+DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
-+DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
-+DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
-+DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
-+DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
-+DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
-+DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
-+DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
-+DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
-+DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
-+DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
-+DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
-+DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
-+DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
-+DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
-+DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
-+DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
-+DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
-+DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
-+DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
-+DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
-+DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
-+DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
-+DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
-+DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
-+DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
-+DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
-+DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
-+DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
-+DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
-+DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
-+DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
-+DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
-+DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
-+DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
-+DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
-+DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
-+DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
-+DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
- DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
- DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
- DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
-diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
-index caaaea5162..87d1aedb40 100644
---- a/include/opcode/riscv.h
-+++ b/include/opcode/riscv.h
-@@ -312,6 +312,21 @@ enum riscv_insn_class
-    INSN_CLASS_ZICSR,
-    INSN_CLASS_ZIFENCEI,
-    INSN_CLASS_ZIHINTPAUSE,
-+   INSN_CLASS_ZBA,
-+   INSN_CLASS_ZBB,
-+   INSN_CLASS_ZBC,
-+   INSN_CLASS_ZBP,
-+   INSN_CLASS_ZBB_OR_ZBP,
-+   INSN_CLASS_ZBS,
-+   INSN_CLASS_ZBE,
-+   INSN_CLASS_ZBS_OR_ZBE,
-+   INSN_CLASS_ZBF,
-+   INSN_CLASS_ZBM,
-+   INSN_CLASS_ZBP_OR_ZBM,
-+   INSN_CLASS_ZBR,
-+   INSN_CLASS_ZBT,
-+   INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
-+   INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
-   };
- 
- /* This structure holds information for a particular instruction.  */
-diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
-index c3d9bb8745..a169d013c4 100644
---- a/opcodes/riscv-dis.c
-+++ b/opcodes/riscv-dis.c
-@@ -238,6 +238,10 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
- 	      info->target = EXTRACT_RVC_J_IMM (l) + pc;
- 	      (*info->print_address_func) (info->target, info);
- 	      break;
-+	    case 'r':
-+	      print (info->stream, "%s",
-+                     riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
-+              break;
- 	    case 'u':
- 	      print (info->stream, "0x%x",
- 		     (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
-diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
-index a2ea66a723..d73c980acd 100644
---- a/opcodes/riscv-opc.c
-+++ b/opcodes/riscv-opc.c
-@@ -24,6 +24,11 @@
- #include "opcode/riscv.h"
- #include <stdio.h>
- 
-+#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
-+
- /* Register names used by gas and objdump.  */
- 
- const char * const riscv_gpr_names_numeric[NGPR] =
-@@ -786,6 +791,127 @@ const struct riscv_opcode riscv_opcodes[] =
- {"sfence.vma", 0, INSN_CLASS_I,   "s,t",  MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
- {"wfi",        0, INSN_CLASS_I,   "",     MATCH_WFI, MASK_WFI, match_opcode, 0 },
- 
-+
-+/* RVB instructions.  */
-+{"clz",        0, INSN_CLASS_ZBB,  "d,s",      MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
-+{"ctz",        0, INSN_CLASS_ZBB,  "d,s",      MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
-+{"cpop",       0, INSN_CLASS_ZBB,  "d,s",      MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
-+{"min",        0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MIN, MASK_MIN, match_opcode, 0 },
-+{"max",        0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MAX, MASK_MAX, match_opcode, 0 },
-+{"minu",       0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MINU, MASK_MINU, match_opcode, 0 },
-+{"maxu",       0, INSN_CLASS_ZBB,  "d,s,t",    MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
-+{"sext.b",     0, INSN_CLASS_ZBB,  "d,s",      MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
-+{"sext.b",     0, INSN_CLASS_I,    "d,s",      0, (int) M_SEXTB, match_never, INSN_MACRO },
-+{"sext.h",     0, INSN_CLASS_ZBB,  "d,s",      MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
-+{"sext.h",     0, INSN_CLASS_I,    "d,s",      0, (int) M_SEXTH, match_never, INSN_MACRO },
-+{"zext.h",    32, INSN_CLASS_ZBB,  "d,s",      MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
-+{"zext.h",    64, INSN_CLASS_ZBB,  "d,s",      MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
-+{"zext.h",     0, INSN_CLASS_I,    "d,s",      0, (int) M_ZEXTH, match_never, INSN_MACRO },
-+{"andn",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
-+{"orn",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ORN, MASK_ORN, match_opcode, 0 },
-+{"xnor",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
-+{"rol",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROL, MASK_ROL, match_opcode, 0 },
-+{"rori",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, 0 },
-+{"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROR, MASK_ROR, match_opcode, 0 },
-+{"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
-+{"rev8",      32, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev8",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.b",      0, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"clzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
-+{"ctzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
-+{"cpopw",     64, INSN_CLASS_ZBB,  "d,s",      MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
-+{"rolw",      64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
-+{"roriw",     64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,<",    MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
-+{"rorw",      64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_RORW, MASK_RORW, match_opcode, 0 },
-+{"rorw",      64, INSN_CLASS_ZBB_OR_ZBP,  "d,s,<",    MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
-+{"sh1add",     0, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
-+{"sh2add",     0, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
-+{"sh3add",     0, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
-+{"sh1add.uw", 64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
-+{"sh2add.uw", 64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
-+{"sh3add.uw", 64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
-+{"zext.w",    64, INSN_CLASS_ZBA,  "d,s",      MATCH_ADD_UW, MASK_ADD_UW|MASK_RS2, match_opcode, INSN_ALIAS },
-+{"zext.w",    64, INSN_CLASS_I,    "d,s",      0, (int) M_ZEXTW, match_never, INSN_MACRO },
-+{"add.uw",    64, INSN_CLASS_ZBA,  "d,s,t",    MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
-+{"slli.uw",   64, INSN_CLASS_ZBA,  "d,s,>",    MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
-+{"clmul",      0, INSN_CLASS_ZBC,  "d,s,t",    MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
-+{"clmulh",     0, INSN_CLASS_ZBC,  "d,s,t",    MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
-+{"clmulr",     0, INSN_CLASS_ZBC,  "d,s,t",    MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
-+
-+{"pack",       0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
-+{"packu",      0, INSN_CLASS_ZBP_OR_ZBM,  "d,s,t",    MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
-+{"packh",      0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
-+{"packw",     64, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,<",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
-+{"packuw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
-+{"grev",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GREV, MASK_GREV, match_opcode, 0 },
-+{"grevi",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
-+{"grevw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
-+{"greviw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
-+{"gorc",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GORC, MASK_GORC, match_opcode, 0 },
-+{"gorci",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
-+{"gorcw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
-+{"gorciw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
-+{"shfl",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
-+{"shfli",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
-+{"shflw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
-+{"unshfl",     0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
-+{"unshfli",    0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
-+{"unshflw",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
-+{"xperm.n",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
-+{"xperm.b",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
-+{"xperm.h",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
-+{"xperm.w",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
-+
-+{"bset",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSET, MASK_BSET, match_opcode, 0 },
-+{"bclr",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
-+{"binv",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINV, MASK_BINV, match_opcode, 0 },
-+{"bext",       0, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
-+{"bdep",       0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
-+{"bseti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
-+{"bclri",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
-+{"binvi",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
-+{"bexti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
-+{"bsetw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
-+{"bclrw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
-+{"binvw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
-+{"bextw",     64, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
-+{"bdepw",     64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
-+{"bsetiw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
-+{"bclriw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
-+{"binviw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
-+{"slo",        0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_SLO, MASK_SLO, match_opcode, 0 },
-+{"sro",        0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_SRO, MASK_SRO, match_opcode, 0 },
-+{"sloi",       0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
-+{"sroi",       0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_SROI, MASK_SROI, match_opcode, 0 },
-+{"slow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
-+{"srow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROW, MASK_SROW, match_opcode, 0 },
-+{"sloiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
-+{"sroiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
-+
-+{"bfp",        0, INSN_CLASS_ZBF,  "d,s,t",    MATCH_BFP, MASK_BFP, match_opcode, 0 },
-+{"bfpw",      64, INSN_CLASS_ZBF,  "d,s,<",    MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
-+
-+{"bmator",    64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
-+{"bmatxor",   64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
-+{"bmatflip",  64, INSN_CLASS_ZBM,  "d,s",      MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
-+
-+{"crc32.b",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
-+{"crc32.h",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
-+{"crc32.w",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
-+{"crc32c.b",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
-+{"crc32c.h",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
-+{"crc32c.w",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
-+{"crc32.d",   64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
-+{"crc32c.d",  64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
-+
-+{"cmix",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
-+{"cmov",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
-+{"fsl",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
-+{"fsr",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
-+{"fsri",       0, INSN_CLASS_ZBT,  "d,s,>,r",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
-+{"fslw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
-+{"fsrw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
-+{"fsriw",     64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
- /* Terminate the list.  */
- {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
- };
-@@ -935,6 +1061,19 @@ const struct riscv_ext_version riscv_ext_version_table[] =
- 
- {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
- 
-+{"b",     ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zba",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbe",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbf",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbm",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbp",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbr",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+{"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 93},
-+
-+
- /* Terminate the list.  */
- {NULL, 0, 0, 0}
- };
--- 
-2.33.0
-

+ 59 - 0
recipes-devtools/binutils/binutils/0002-binutils-cross-Do-not-generate-linker-script-directo.patch

@@ -0,0 +1,59 @@
+From 6e93d0328f499569db7ce6396f94f304ce340df8 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Mon, 6 Mar 2017 23:37:05 -0800
+Subject: [PATCH] binutils-cross: Do not generate linker script directories
+
+We don't place target libraries within ${exec_prefix}, we'd always place these
+within the target sysroot within the standard library directories. Worse, the
+append_to_lib_path code prefixes these paths with the sysroot which makes even
+less sense.
+
+These directories therefore don't make sense in our case and mean we have to
+relocate all the linker scripts if they're present. Dropping them
+gives a reasonable performance improvement/simplification.
+
+Upstream-Status: Inappropriate
+
+RP 2017/01/30
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ ld/genscripts.sh | 25 -------------------------
+ 1 file changed, 25 deletions(-)
+
+diff --git a/ld/genscripts.sh b/ld/genscripts.sh
+index 46a2db7005c..4bb7c33f560 100755
+--- a/ld/genscripts.sh
++++ b/ld/genscripts.sh
+@@ -235,31 +235,6 @@ append_to_lib_path()
+   fi
+ }
+ 
+-# Always search $(tooldir)/lib, aka /usr/local/TARGET/lib when native
+-# except when LIBPATH=":".
+-if [ "${LIB_PATH}" != ":" ] ; then
+-  libs=
+-  if [ "x${TOOL_LIB}" = "x" ] ; then
+-    if [ "x${NATIVE}" = "xyes" ] ; then
+-      libs="${exec_prefix}/${target_alias}/lib"
+-    fi
+-  else
+-    # For multilib'ed targets, ensure both ${target_alias}/lib${LIBPATH_SUFFIX}
+-    # and ${TOOL_LIB}/lib${LIBPATH_SUFFIX} are in the default search path,
+-    # because 64bit libraries may be in both places, depending on
+-    # cross-development setup method (e.g.: /usr/s390x-linux/lib64
+-    # vs. /usr/s390-linux/lib64)
+-    for libpath_suffix in ${LIBPATH_SUFFIX}; do
+-      case "${NATIVE}:${libpath_suffix}:${TOOL_LIB}" in
+-	:* | *::* | *:*:*${libpath_suffix}) ;;
+-	*) libs="${exec_prefix}/${target_alias}/lib${libpath_suffix}" ;;
+-      esac
+-    done
+-    libs="${exec_prefix}/${TOOL_LIB}/lib ${libs}"
+-  fi
+-  append_to_lib_path ${libs}
+-fi
+-
+ if [ "x${LIB_PATH}" = "x" ] && [ "x${USE_LIBPATH}" = xyes ] ; then
+   libs=${NATIVE_LIB_DIRS}
+   if [ "x${NATIVE}" = "xyes" ] ; then

+ 14220 - 0
recipes-devtools/binutils/binutils/0002-merge-from-dubhe-pr-06-30-to-support-vector1.0.patch

@@ -0,0 +1,14220 @@
+From 9c5cb77c2ba2d45a8f22fe9ac5e2819703f82f66 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Thu, 30 Sep 2021 00:18:49 -0700
+Subject: [PATCH 02/11] merge from dubhe-pr-06-30 to support vector1.0
+
+---
+ gas/config/tc-riscv.c                         |  405 ++-
+ gas/testsuite/gas/riscv/v-zero-imm.d          |   17 +
+ gas/testsuite/gas/riscv/v-zero-imm.s          |    8 +
+ .../gas/riscv/vector-insns-fail-arith-fixp.d  |    3 +
+ .../gas/riscv/vector-insns-fail-arith-fixp.l  |   27 +
+ .../gas/riscv/vector-insns-fail-arith-fixp.s  |   81 +
+ .../riscv/vector-insns-fail-arith-floatp.d    |    3 +
+ .../riscv/vector-insns-fail-arith-floatp.l    |   49 +
+ .../riscv/vector-insns-fail-arith-floatp.s    |  157 ++
+ .../gas/riscv/vector-insns-fail-arith-int.d   |    3 +
+ .../gas/riscv/vector-insns-fail-arith-int.l   |   71 +
+ .../gas/riscv/vector-insns-fail-arith-int.s   |  213 ++
+ .../riscv/vector-insns-fail-arith-narrow.d    |    3 +
+ .../riscv/vector-insns-fail-arith-narrow.l    |   85 +
+ .../riscv/vector-insns-fail-arith-narrow.s    |  100 +
+ .../gas/riscv/vector-insns-fail-arith-widen.d |    3 +
+ .../gas/riscv/vector-insns-fail-arith-widen.l |  253 ++
+ .../gas/riscv/vector-insns-fail-arith-widen.s |  297 +++
+ .../gas/riscv/vector-insns-fail-load-store.d  |    3 +
+ .../gas/riscv/vector-insns-fail-load-store.l  |  419 ++++
+ .../gas/riscv/vector-insns-fail-load-store.s  |  481 ++++
+ .../gas/riscv/vector-insns-fail-mask.d        |    3 +
+ .../gas/riscv/vector-insns-fail-mask.l        |   10 +
+ .../gas/riscv/vector-insns-fail-mask.s        |   23 +
+ .../gas/riscv/vector-insns-fail-permutation.d |    3 +
+ .../gas/riscv/vector-insns-fail-permutation.l |   31 +
+ .../gas/riscv/vector-insns-fail-permutation.s |   56 +
+ .../gas/riscv/vector-insns-fail-unsupport.d   |    3 +
+ .../gas/riscv/vector-insns-fail-unsupport.l   | 1454 +++++++++++
+ .../gas/riscv/vector-insns-fail-unsupport.s   | 1663 +++++++++++++
+ .../gas/riscv/vector-insns-fail-zvamo.d       |    3 +
+ .../gas/riscv/vector-insns-fail-zvamo.l       |  109 +
+ .../gas/riscv/vector-insns-fail-zvamo.s       |  217 ++
+ .../gas/riscv/vector-insns-vmsgtvx.d          |   29 +
+ .../gas/riscv/vector-insns-vmsgtvx.s          |    9 +
+ gas/testsuite/gas/riscv/vector-insns.d        | 1944 +++++++++++++++
+ gas/testsuite/gas/riscv/vector-insns.s        | 2185 +++++++++++++++++
+ include/opcode/riscv-opc.h                    | 1916 ++++++++++++++-
+ include/opcode/riscv.h                        |   82 +-
+ opcodes/riscv-dis.c                           |   90 +-
+ opcodes/riscv-opc.c                           | 1125 ++++++++-
+ 41 files changed, 13626 insertions(+), 10 deletions(-)
+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index e5d8070b75..898ee89f96 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -64,6 +64,7 @@ enum riscv_csr_class
+   CSR_CLASS_I,
+   CSR_CLASS_I_32, /* rv32 only */
+   CSR_CLASS_F, /* f-ext only */
++  CSR_CLASS_V,
+   CSR_CLASS_DEBUG /* debug CSR */
+ };
+ 
+@@ -367,6 +368,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+       return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
+     case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
+       return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
++    case INSN_CLASS_V: 
++      return riscv_subset_supports ("v");
++    case INSN_CLASS_V_AND_F:
++      return riscv_subset_supports ("v") && riscv_subset_supports ("f");
++    case INSN_CLASS_V_OR_ZVAMO:
++      return (riscv_subset_supports ("a")
++	      && (riscv_subset_supports ("v")
++		  || riscv_subset_supports ("zvamo")));
++    case INSN_CLASS_V_OR_ZVLSSEG:
++      return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
+     default:
+       as_fatal ("internal: unreachable");
+       return false;
+@@ -807,7 +818,8 @@ enum reg_class
+   RCLASS_GPR,
+   RCLASS_FPR,
+   RCLASS_MAX,
+-
++  RCLASS_VECR,
++  RCLASS_VECM,
+   RCLASS_CSR
+ };
+ 
+@@ -909,6 +921,12 @@ riscv_csr_address (const char *csr_name,
+       result = riscv_subset_supports ("f");
+       need_check_version = false;
+       break;
++    case CSR_CLASS_V:
++      result = (riscv_subset_supports ("v")
++		|| riscv_subset_supports ("zvamo")
++		|| riscv_subset_supports ("zvlsseg"));
++      need_check_version = false;    
++      break;  
+     case CSR_CLASS_DEBUG:
+       need_check_version = false;
+       break;
+@@ -1171,6 +1189,33 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
+ 	     return false;
+ 	  }
+ 	break;
++
++ case 'V': /* RVV */
++	switch (c = *p++)
++	  {
++	  case 'd':
++	  case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
++	  case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
++	  case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
++	  case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
++		    USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
++		    USE_BITS (OP_MASK_VS1, OP_SH_VS1);
++		    USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
++	  case '0': break;
++	  case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break;
++	  case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
++	  case 'i':
++	  case 'j':
++	  case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
++	  case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
++	  default:
++	    as_bad (_("internal: bad RISC-V opcode (unknown operand type `V%c'): %s %s"),
++		    c, opc->name, opc->args);
++	  }
++	break;
++
+       default:
+ 	as_bad (_("internal: bad RISC-V opcode "
+ 		  "(unknown operand type `%c'): %s %s"),
+@@ -1252,6 +1297,8 @@ md_begin (void)
+   hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
+   hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
+   hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
++  hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
++  hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);  
+   /* Add "fp" as an alias for "s0".  */
+   hash_reg_name (RCLASS_GPR, "fp", 8);
+ 
+@@ -1412,6 +1459,41 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
+ 	  break;
+ 	case ',':
+ 	  continue;
++
++	case 'V': /* RVV */
++	  {
++	    switch (*fmt++)
++	      {
++	      case 'd':
++		INSERT_OPERAND (VD, insn, va_arg (args, int));
++		continue;
++
++	      case 's':
++		INSERT_OPERAND (VS1, insn, va_arg (args, int));
++		continue;
++
++	      case 't':
++		INSERT_OPERAND (VS2, insn, va_arg (args, int));
++		continue;
++
++	      case 'm':
++		{
++		  int reg = va_arg (args, int);
++		  if (reg == -1)
++		    {
++		      INSERT_OPERAND (VMASK, insn, 1);
++		      continue;
++		    }
++		  else if (reg == 0)
++		    {
++		      INSERT_OPERAND (VMASK, insn, 0);
++		      continue;
++		    }
++		}
++		/* fallthru */
++	      }
++	  }
++
+ 	default:
+ 	  as_fatal (_("internal: invalid macro"));
+ 	}
+@@ -1584,6 +1666,96 @@ load_const (int reg, expressionS *ep)
+     }
+ }
+ 
++/* Expand RISC-V Vector macros into one of more instructions.  */
++
++static void
++vector_macro (struct riscv_cl_insn *ip)
++{
++  int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
++  int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
++  int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
++  int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
++  int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
++  int mask = ip->insn_mo->mask;
++
++  switch (mask)
++    {
++    case M_VMSGE:
++      if (vm)
++	{
++	  /* Unmasked.  */
++	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
++	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
++	  break;
++	}
++      if (vtemp != 0)
++	{
++	  /* Masked.  Have vtemp to avoid overlap constraints.  */
++	  if (vd == vm)
++	    {
++	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
++	    }
++	  else
++	    {
++	      /* Preserve the value of vd if not updating by vm.  */
++	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
++	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
++	    }
++	}
++      else if (vd != vm)
++	{
++	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
++	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
++	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
++	}
++      else
++	as_bad (_("must provide temp if destination overlaps mask"));
++      break;
++
++    case M_VMSGEU:
++      if (vm)
++	{
++	  /* Unmasked.  */
++	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
++	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
++	  break;
++	}
++      if (vtemp != 0)
++	{
++	  /* Masked.  Have vtemp to avoid overlap constraints.  */
++	  if (vd == vm)
++	    {
++	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
++	    }
++	  else
++	    {
++	      /* Preserve the value of vd if not updating by vm.  */
++	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
++	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
++	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
++	    }
++	}
++      else if (vd != vm)
++	{
++	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
++	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
++	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
++	}
++      else
++	as_bad (_("must provide temp if destination overlaps mask"));
++      break;
++
++    default:
++      as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
++      break;
++    }
++}
++
+ /* Zero extend and sign extend byte/half-word/word.  */
+ 
+ static void
+@@ -1739,6 +1911,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
+       riscv_ext (rd, rs1, xlen - 16, true);
+       break;
+ 
++    case M_VMSGE:
++    case M_VMSGEU:
++      vector_macro (ip);
++      break;
++
+     default:
+       as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
+       break;
+@@ -1892,6 +2069,66 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
+   return reloc_index;
+ }
+ 
++/* Parse string STR as a vsetvli operand.  Store the expression in *EP.
++   On exit, EXPR_END points to the first character after the expression.  */
++
++static void
++my_getVsetvliExpression (expressionS *ep, char *str)
++{
++  unsigned int vsew_value = 0, vlmul_value = 0;
++  unsigned int vta_value = 0, vma_value = 0;
++  bfd_boolean vsew_found = FALSE, vlmul_found = FALSE;
++  bfd_boolean vta_found = FALSE, vma_found = FALSE;
++
++  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vsew_found)
++	as_bad (_("multiple vsew constants"));
++      vsew_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vlmul_found)
++	as_bad (_("multiple vlmul constants"));
++      vlmul_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vta_found)
++	as_bad (_("multiple vta constants"));
++      vta_found = TRUE;
++    }
++  if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
++    {
++      if (*str == ',')
++	++str;
++      if (vma_found)
++	as_bad (_("multiple vma constants"));
++      vma_found = TRUE;
++    }
++
++  if (vsew_found || vlmul_found || vta_found || vma_found)
++    {
++      ep->X_op = O_constant;
++      ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
++			 | (vsew_value << OP_SH_VSEW)
++			 | (vta_value << OP_SH_VTA)
++			 | (vma_value << OP_SH_VMA);
++      expr_end = str;
++    }
++  else
++    {
++      my_getExpression (ep, str);
++      str = expr_end;
++    }
++}
++
+ /* Parse opcode name, could be an mnemonics or number.  */
+ 
+ static size_t
+@@ -2755,6 +2992,170 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
+ 	      imm_expr->X_op = O_absent;
+ 	      continue;
+ 
++	    case 'V': /* RVV */
++	      switch (*++args)
++		{
++		case 'd': /* VD */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VD, *ip, regno);
++		  continue;
++
++		case 'e': /* AMO VD */
++		  if (reg_lookup (&s, RCLASS_GPR, &regno) && regno == 0)
++		    INSERT_OPERAND (VWD, *ip, 0);
++		  else if (reg_lookup (&s, RCLASS_VECR, &regno))
++		    {
++		      INSERT_OPERAND (VWD, *ip, 1);
++		      INSERT_OPERAND (VD, *ip, regno);
++		    }
++		  else
++		    break;
++		  continue;
++
++		case 'f': /* AMO VS3 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
++		    INSERT_OPERAND (VD, *ip, regno);
++		  else
++		    {
++		      /* VS3 must match VD.  */
++		      if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
++			break;
++		    }
++		  continue;
++
++		case 's': /* VS1 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  continue;
++
++		case 't': /* VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case 'u': /* VS1 == VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		case 'v': /* VD == VS1 == VS2 */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno))
++		    break;
++		  INSERT_OPERAND (VD, *ip, regno);
++		  INSERT_OPERAND (VS1, *ip, regno);
++		  INSERT_OPERAND (VS2, *ip, regno);
++		  continue;
++
++		/* The `V0` is carry-in register for v[m]adc and v[m]sbc,
++		   and is used to choose vs1/rs1/frs1/imm or vs2 for
++		   v[f]merge.  It use the same encoding as the vector mask
++		   register.  */
++		case '0':
++		  if (reg_lookup (&s, RCLASS_VECR, &regno) && regno == 0)
++		    continue;
++		  break;
++
++		case 'b': /* vtypei for vsetivli */
++		  my_getVsetvliExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (!VALID_RVV_VB_IMM (imm_expr->X_add_number))
++		    as_bad (_("bad value for vsetivli immediate field, "
++			      "value must be 0..1023"));
++		  ip->insn_opcode
++		    |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'c': /* vtypei for vsetvli */
++		  my_getVsetvliExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
++		    as_bad (_("bad value for vsetvli immediate field, "
++			      "value must be 0..2047"));
++		  ip->insn_opcode
++		    |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'i': /* vector arith signed immediate */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number > 15
++		      || imm_expr->X_add_number < -16)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be -16...15"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'j': /* vector arith unsigned immediate */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number < 0
++		      || imm_expr->X_add_number >= 32)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be 0...31"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'k': /* vector arith signed immediate, minus 1 */
++		  my_getExpression (imm_expr, s);
++		  check_absolute_expr (ip, imm_expr, FALSE);
++		  if (imm_expr->X_add_number > 16
++		      || imm_expr->X_add_number < -15)
++		    as_bad (_("bad value for vector immediate field, "
++			      "value must be -15...16"));
++		  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
++		  imm_expr->X_op = O_absent;
++		  s = expr_end;
++		  continue;
++
++		case 'm': /* optional vector mask */
++		  if (*s == '\0')
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 1);
++		      continue;
++		    }
++		  else if (*s == ',' && s++
++			   && reg_lookup (&s, RCLASS_VECM, &regno)
++			   && regno == 0)
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 0);
++		      continue;
++		    }
++		  break;
++
++		  /* The following ones are only used in macros.  */
++		case 'M': /* required vector mask */
++		  if (reg_lookup (&s, RCLASS_VECM, &regno) && regno == 0)
++		    {
++		      INSERT_OPERAND (VMASK, *ip, 0);
++		      continue;
++		    }
++		  break;
++
++		case 'T': /* vector macro temporary register */
++		  if (!reg_lookup (&s, RCLASS_VECR, &regno) || regno == 0)
++		    break;
++		  /* Store it in the FUNCT6 field as we don't have anyplace
++		     else to store it.  */
++		  INSERT_OPERAND (VFUNCT6, *ip, regno);
++		  continue;
++		}
++	      break;
++
+ 	    default:
+ 	      as_fatal (_("internal: unknown argument type `%c'"), *args);
+ 	    }
+@@ -3940,4 +4341,4 @@ riscv_pop_insert (void)
+   extern void pop_insert (const pseudo_typeS *);
+ 
+   pop_insert (riscv_pseudo_table);
+-}
++}
+\ No newline at end of file
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
+new file mode 100644
+index 0000000000..b95c068a17
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/v-zero-imm.d
+@@ -0,0 +1,17 @@
++#as: -march=rv32ifv0p10
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+768fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1
++[ 	]+[0-9a-f]+:[ 	]+748fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66840257[ 	]+vmsne.vv[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+64840257[ 	]+vmsne.vv[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+7e8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1
++[ 	]+[0-9a-f]+:[ 	]+7c8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62840257[ 	]+vmseq.vv[ 	]+v4,v8,v8
++[ 	]+[0-9a-f]+:[ 	]+60840257[ 	]+vmseq.vv[ 	]+v4,v8,v8,v0.t
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
+new file mode 100644
+index 0000000000..98b7063880
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/v-zero-imm.s
+@@ -0,0 +1,8 @@
++	vmslt.vi v4, v8, 0
++	vmslt.vi v4, v8, 0, v0.t
++	vmsltu.vi v4, v8, 0
++	vmsltu.vi v4, v8, 0, v0.t
++	vmsge.vi v4, v8, 0
++	vmsge.vi v4, v8, 0, v0.t
++	vmsgeu.vi v4, v8, 0
++	vmsgeu.vi v4, v8, 0, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
+new file mode 100644
+index 0000000000..55cfd83301
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10 
++#source: vector-insns-fail-arith-fixp.s
++#error_output: vector-insns-fail-arith-fixp.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+new file mode 100644
+index 0000000000..a3c126d8ec
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
+@@ -0,0 +1,27 @@
++.*: Assembler messages:
++.*Error: illegal operands `vsaddu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsaddu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsaddu.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vssubu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssubu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vaaddu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vaaddu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vaadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vaadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vasubu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vasubu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vasub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vasub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssrl.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssrl.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssrl.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vssra.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vssra.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vssra.vi v0,v4,31,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
+new file mode 100644
+index 0000000000..1fbcb601ea
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
+@@ -0,0 +1,81 @@
++# Vector Single-Width Saturating Add and Subtract
++
++	vsaddu.vv v4, v4, v8		# OK
++	vsaddu.vv v8, v4, v8		# OK
++	vsaddu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsaddu.vx v4, v4, a1		# OK
++	vsaddu.vx v0, v4, a1, v0.t	# vd overlap vm
++	vsaddu.vi v4, v4, 15		# OK
++	vsaddu.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vsadd.vv v4, v4, v8
++	vsadd.vv v8, v4, v8
++	vsadd.vv v0, v4, v8, v0.t
++	vsadd.vx v4, v4, a1
++	vsadd.vx v0, v4, a1, v0.t
++	vsadd.vi v4, v4, 15
++	vsadd.vi v0, v4, 15, v0.t
++
++	vssubu.vv v4, v4, v8		# OK
++	vssubu.vv v8, v4, v8		# OK
++	vssubu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vssubu.vx v4, v4, a1		# OK
++	vssubu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vssub.vv v4, v4, v8
++	vssub.vv v8, v4, v8
++	vssub.vv v0, v4, v8, v0.t
++	vssub.vx v4, v4, a1
++	vssub.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Averaging Add and Subtract
++
++	vaaddu.vv v4, v4, v8		# OK
++	vaaddu.vv v8, v4, v8		# OK
++	vaaddu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vaaddu.vx v4, v4, a1		# OK
++	vaaddu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vaadd.vv v4, v4, v8
++	vaadd.vv v8, v4, v8
++	vaadd.vv v0, v4, v8, v0.t
++	vaadd.vx v4, v4, a1
++	vaadd.vx v0, v4, a1, v0.t
++
++	vasubu.vv v4, v4, v8
++	vasubu.vv v8, v4, v8
++	vasubu.vv v0, v4, v8, v0.t
++	vasubu.vx v4, v4, a1
++	vasubu.vx v0, v4, a1, v0.t
++
++	vasub.vv v4, v4, v8
++	vasub.vv v8, v4, v8
++	vasub.vv v0, v4, v8, v0.t
++	vasub.vx v4, v4, a1
++	vasub.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Fractional Multiply with Rounding and Saturation
++
++	vsmul.vv v4, v4, v8		# OK
++	vsmul.vv v8, v4, v8		# OK
++	vsmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsmul.vx v4, v4, a1		# OK
++	vsmul.vx v0, v4, a1, v0.t	# vd overlap vm
++
++# Vector Single-Width Scaling Shift Instructions
++
++	vssrl.vv v4, v4, v8		# OK
++	vssrl.vv v8, v4, v8		# OK
++	vssrl.vv v0, v4, v8, v0.t	# vd overlap vm
++	vssrl.vx v4, v4, a1		# OK
++	vssrl.vx v0, v4, a1, v0.t	# vd overlap vm
++	vssrl.vi v4, v4, 31		# OK
++	vssrl.vi v0, v4, 31, v0.t	# vd overlap vm
++
++	vssra.vv v4, v4, v8
++	vssra.vv v8, v4, v8
++	vssra.vv v0, v4, v8, v0.t
++	vssra.vx v4, v4, a1
++	vssra.vx v0, v4, a1, v0.t
++	vssra.vi v4, v4, 31
++	vssra.vi v0, v4, 31, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+new file mode 100644
+index 0000000000..d192761c06
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv0p10
++#source: vector-insns-fail-arith-floatp.s
++#error_output: vector-insns-fail-arith-floatp.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+new file mode 100644
+index 0000000000..e4d365cfa5
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
+@@ -0,0 +1,49 @@
++.*: Assembler messages:
++.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
++.*Error: illegal operands `vfsqrt.v v0,v4,v0.t'
++.*Error: illegal operands `vfrece7.v v0,v4,v0.t'
++.*Error: illegal operands `vfrsqrte7.v v0,v4,v0.t'
++.*Error: illegal operands `vfclass.v v0,v4,v0.t'
++.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfneg.v v0,v4,v0.t'
++.*Error: illegal operands `vfabs.v v0,v4,v0.t'
++.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vfcvt.xu.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.x.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.rtz.xu.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.rtz.x.f.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.f.xu.v v0,v4,v0.t'
++.*Error: illegal operands `vfcvt.f.x.v v0,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+new file mode 100644
+index 0000000000..19ed26a95a
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
+@@ -0,0 +1,157 @@
++# Vector Single-Width Floating-Point Add/Subtract Instructions
++
++	vfadd.vv v4, v4, v8		# OK
++	vfadd.vv v8, v4, v8		# OK
++	vfadd.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfadd.vf v4, v4, fa1		# OK
++	vfadd.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfsub.vv v4, v4, v8
++	vfsub.vv v8, v4, v8
++	vfsub.vv v0, v4, v8, v0.t
++	vfsub.vf v4, v4, fa1
++	vfsub.vf v0, v4, fa1, v0.t
++
++	vfrsub.vf v4, v4, fa1		# OK
++	vfrsub.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Single-Width Floating-Point Multiply/Divide Instructions
++
++	vfmul.vv v4, v4, v8		# OK
++	vfmul.vv v8, v4, v8		# OK
++	vfmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmul.vf v4, v4, fa1		# OK
++	vfmul.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfdiv.vv v4, v4, v8
++	vfdiv.vv v8, v4, v8
++	vfdiv.vv v0, v4, v8, v0.t
++	vfdiv.vf v4, v4, fa1
++	vfdiv.vf v0, v4, fa1, v0.t
++
++	vfrdiv.vf v4, v4, fa1		# OK
++	vfrdiv.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
++
++	vfmacc.vv v4, v4, v8		# OK
++	vfmacc.vv v8, v4, v8		# OK
++	vfmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmacc.vf v4, fa1, v4		# OK
++	vfmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
++
++	vfnmacc.vv v4, v4, v8
++	vfnmacc.vv v8, v4, v8
++	vfnmacc.vv v0, v4, v8, v0.t
++	vfnmacc.vf v4, fa1, v4
++	vfnmacc.vf v0, fa1, v4, v0.t
++
++	vfmsac.vv v4, v4, v8
++	vfmsac.vv v8, v4, v8
++	vfmsac.vv v0, v4, v8, v0.t
++	vfmsac.vf v4, fa1, v4
++	vfmsac.vf v0, fa1, v4, v0.t
++
++	vfnmsac.vv v4, v4, v8
++	vfnmsac.vv v8, v4, v8
++	vfnmsac.vv v0, v4, v8, v0.t
++	vfnmsac.vf v4, fa1, v4
++	vfnmsac.vf v0, fa1, v4, v0.t
++
++	vfmadd.vv v4, v4, v8
++	vfmadd.vv v8, v4, v8
++	vfmadd.vv v0, v4, v8, v0.t
++	vfmadd.vf v4, fa1, v4
++	vfmadd.vf v0, fa1, v4, v0.t
++
++	vfnmadd.vv v4, v4, v8
++	vfnmadd.vv v8, v4, v8
++	vfnmadd.vv v0, v4, v8, v0.t
++	vfnmadd.vf v4, fa1, v4
++	vfnmadd.vf v0, fa1, v4, v0.t
++
++	vfmsub.vv v4, v4, v8
++	vfmsub.vv v8, v4, v8
++	vfmsub.vv v0, v4, v8, v0.t
++	vfmsub.vf v4, fa1, v4
++	vfmsub.vf v0, fa1, v4, v0.t
++
++	vfnmsub.vv v4, v4, v8
++	vfnmsub.vv v8, v4, v8
++	vfnmsub.vv v0, v4, v8, v0.t
++	vfnmsub.vf v4, fa1, v4
++	vfnmsub.vf v0, fa1, v4, v0.t
++
++# Vector Floating-Point Square-Root Instruction
++
++	vfsqrt.v v4, v4			# OK
++	vfsqrt.v v0, v4, v0.t		# vd overlap vm
++
++# Vector Floating-Point Reciprocal Estimate Instruction
++
++	vfrece7.v v4, v4		# OK
++	vfrece7.v v0, v4, v0.t		# vd overlap vm
++
++# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
++
++	vfrsqrte7.v v4, v4		# OK
++	vfrsqrte7.v v0, v4, v0.t	# vd overlap vm
++
++# Vector Floating-Point Classify Instruction
++
++	vfclass.v v4, v4		# OK
++	vfclass.v v0, v4, v0.t		# vd overlap vm
++
++# Vector Floating-Point MIN/MAX Instructions
++
++	vfmin.vv v4, v4, v8		# OK
++	vfmin.vv v8, v4, v8		# OK
++	vfmin.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfmin.vf v4, v4, fa1		# OK
++	vfmin.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfmax.vv v4, v4, v8
++	vfmax.vv v8, v4, v8
++	vfmax.vv v0, v4, v8, v0.t
++	vfmax.vf v4, v4, fa1
++	vfmax.vf v0, v4, fa1, v0.t
++
++# Vector Floating-Point Sign-Injection Instructions
++
++	vfneg.v v4, v4			# OK
++	vfneg.v v0, v4, v0.t		# vd overlap vm
++	vfabs.v v4, v4			# OK
++	vfabs.v v0, v4, v0.t		# vd overlap vm
++
++	vfsgnj.vv v4, v4, v8		# OK
++	vfsgnj.vv v8, v4, v8		# OK
++	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
++	vfsgnj.vf v4, v4, fa1		# OK
++	vfsgnj.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++	vfsgnjn.vv v4, v4, v8
++	vfsgnjn.vv v8, v4, v8
++	vfsgnjn.vv v0, v4, v8, v0.t
++	vfsgnjn.vf v4, v4, fa1
++	vfsgnjn.vf v0, v4, fa1, v0.t
++
++	vfsgnjx.vv v4, v4, v8
++	vfsgnjx.vv v8, v4, v8
++	vfsgnjx.vv v0, v4, v8, v0.t
++	vfsgnjx.vf v4, v4, fa1
++	vfsgnjx.vf v0, v4, fa1, v0.t
++
++# Single-Width Floating-Point/Integer Type-Convert Instructions
++
++	vfcvt.xu.f.v v4, v4		# OK
++	vfcvt.xu.f.v v0, v4, v0.t	# vd overlap vm
++	vfcvt.x.f.v v4, v4
++	vfcvt.x.f.v v0, v4, v0.t
++	vfcvt.rtz.xu.f.v v4, v4
++	vfcvt.rtz.xu.f.v v0, v4, v0.t
++	vfcvt.rtz.x.f.v v4, v4
++	vfcvt.rtz.x.f.v v0, v4, v0.t
++	vfcvt.f.xu.v v4, v4
++	vfcvt.f.xu.v v0, v4, v0.t
++	vfcvt.f.x.v v4, v4
++	vfcvt.f.x.v v0, v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+new file mode 100644
+index 0000000000..e26778a4e6
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10 
++#source: vector-insns-fail-arith-int.s
++#error_output: vector-insns-fail-arith-int.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+new file mode 100644
+index 0000000000..e42096c1c4
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
+@@ -0,0 +1,71 @@
++.*: Assembler messages:
++.*Error: illegal operands `vneg.v v0,v4,v0.t'
++.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
++.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
++.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
++.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
++.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
++.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
++.*Error: illegal operands `vadc.vim v0,v4,15,v0'
++.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
++.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
++.*Error: illegal operands `vnot.v v0,v4,v0.t'
++.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
++.*Error: illegal operands `vsll.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsll.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsll.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vsrl.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsrl.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsrl.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vsra.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vsra.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vsra.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
++.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+new file mode 100644
+index 0000000000..6ce4e420c7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
+@@ -0,0 +1,213 @@
++# Vector Single-Width Integer Add and Subtract
++
++	vneg.v v4, v4			# OK
++	vneg.v v0, v4, v0.t		# vd overlap vm
++
++	vadd.vv v4, v4, v8		# OK
++	vadd.vv v8, v4, v8		# OK
++	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
++	vadd.vx v4, v4, a1		# OK
++	vadd.vx v0, v4, a1, v0.t	# vd overlap vm
++	vadd.vi v4, v4, 15		# OK
++	vadd.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vsub.vv v4, v4, v8		# OK
++	vsub.vv v8, v4, v8		# OK
++	vsub.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsub.vx v4, v4, a1		# OK
++	vsub.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vrsub.vx v4, v4, a1		# OK
++	vrsub.vx v0, v4, a1, v0.t	# vd overlap vm
++	vrsub.vi v4, v4, 15		# OK
++	vrsub.vi v0, v4, 15, v0.t	# vd overlap vm
++
++# Vector Integer Extension
++
++	vzext.vf2 v4, v4		# OK
++	vzext.vf2 v0, v4, v0.t		# vd overlap vm
++	vsext.vf2 v4, v4
++	vsext.vf2 v0, v4, v0.t
++	vzext.vf4 v4, v4
++	vzext.vf4 v0, v4, v0.t
++	vsext.vf4 v4, v4
++	vsext.vf4 v0, v4, v0.t
++	vzext.vf8 v4, v4
++	vzext.vf8 v0, v4, v0.t
++	vsext.vf8 v4, v4
++	vsext.vf8 v0, v4, v0.t
++
++# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
++
++	vadc.vvm v4, v4, v8, v0		# OK
++	vadc.vvm v8, v4, v8, v0		# OK
++	vadc.vvm v0, v4, v8, v0		# vd overlap vm
++	vadc.vxm v4, v4, a1, v0		# OK
++	vadc.vxm v0, v4, a1, v0		# vd overlap vm
++	vadc.vim v4, v4, 15, v0		# OK
++	vadc.vim v0, v4, 15, v0		# vd overlap vm
++
++	vsbc.vvm v4, v4, v8, v0		# OK
++	vsbc.vvm v8, v4, v8, v0		# OK
++	vsbc.vvm v0, v4, v8, v0		# vd overlap vm
++	vsbc.vxm v4, v4, a1, v0		# OK
++	vsbc.vxm v0, v4, a1, v0		# vd overlap vm
++
++# Vector Bitwise Logical Instructions
++
++	vnot.v v4, v4			# OK
++	vnot.v v0, v4, v0.t		# vd overlap vm
++
++	vand.vv	v4, v4, v8		# OK
++	vand.vv v8, v4, v8		# OK
++	vand.vv v0, v4, v8, v0.t	# vd overlap vm
++	vand.vx v4, v4, a1		# OK
++	vand.vx v0, v4, a1, v0.t	# vd overlap vm
++	vand.vi v4, v4, 15		# OK
++	vand.vi v0, v4, 15, v0.t	# vd overlap vm
++
++	vor.vv	v4, v4, v8
++	vor.vv v8, v4, v8
++	vor.vv v0, v4, v8, v0.t
++	vor.vx v4, v4, a1
++	vor.vx v0, v4, a1, v0.t
++	vor.vi v4, v4, 15
++	vor.vi v0, v4, 15, v0.t
++
++	vxor.vv	v4, v4, v8
++	vxor.vv v8, v4, v8
++	vxor.vv v0, v4, v8, v0.t
++	vxor.vx v4, v4, a1
++	vxor.vx v0, v4, a1, v0.t
++	vxor.vi v4, v4, 15
++	vxor.vi v0, v4, 15, v0.t
++
++# Vector Single-Width Bit Shift Instructions
++
++	vsll.vv v4, v4, v8		# OK
++	vsll.vv v8, v4, v8		# OK
++	vsll.vv v0, v4, v8, v0.t	# vd overlap vm
++	vsll.vx v4, v4, a1		# OK
++	vsll.vx v0, v4, a1, v0.t	# vd overlap vm
++	vsll.vi v4, v4, 31		# OK
++	vsll.vi v0, v4, 31, v0.t	# vd overlap vm
++
++	vsrl.vv v4, v4, v8
++	vsrl.vv v8, v4, v8
++	vsrl.vv v0, v4, v8, v0.t
++	vsrl.vx v4, v4, a1
++	vsrl.vx v0, v4, a1, v0.t
++	vsrl.vi v4, v4, 31
++	vsrl.vi v0, v4, 31, v0.t
++
++	vsra.vv v4, v4, v8
++	vsra.vv v8, v4, v8
++	vsra.vv v0, v4, v8, v0.t
++	vsra.vx v4, v4, a1
++	vsra.vx v0, v4, a1, v0.t
++	vsra.vi v4, v4, 31
++	vsra.vi v0, v4, 31, v0.t
++
++# Vector Integer Min/Max Instructions
++
++	vminu.vv v4, v4, v8		# OK
++	vminu.vv v8, v4, v8		# OK
++	vminu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vminu.vx v4, v4, a1		# OK
++	vminu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vmin.vv v4, v4, v8
++	vmin.vv v8, v4, v8
++	vmin.vv v0, v4, v8, v0.t
++	vmin.vx v4, v4, a1
++	vmin.vx v0, v4, a1, v0.t
++
++	vmaxu.vv v4, v4, v8
++	vmaxu.vv v8, v4, v8
++	vmaxu.vv v0, v4, v8, v0.t
++	vmaxu.vx v4, v4, a1
++	vmaxu.vx v0, v4, a1, v0.t
++
++	vmax.vv v4, v4, v8
++	vmax.vv v8, v4, v8
++	vmax.vv v0, v4, v8, v0.t
++	vmax.vx v4, v4, a1
++	vmax.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Integer Multiply Instructions
++
++	vmul.vv v4, v4, v8		# OK
++	vmul.vv v8, v4, v8		# OK
++	vmul.vv v0, v4, v8, v0.t	# vd overlap vm
++	vmul.vx v4, v4, a1		# OK
++	vmul.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vmulh.vv v4, v4, v8
++	vmulh.vv v8, v4, v8
++	vmulh.vv v0, v4, v8, v0.t
++	vmulh.vx v4, v4, a1
++	vmulh.vx v0, v4, a1, v0.t
++
++	vmulhu.vv v4, v4, v8
++	vmulhu.vv v8, v4, v8
++	vmulhu.vv v0, v4, v8, v0.t
++	vmulhu.vx v4, v4, a1
++	vmulhu.vx v0, v4, a1, v0.t
++
++	vmulhsu.vv v4, v4, v8
++	vmulhsu.vv v8, v4, v8
++	vmulhsu.vv v0, v4, v8, v0.t
++	vmulhsu.vx v4, v4, a1
++	vmulhsu.vx v0, v4, a1, v0.t
++
++# Vector Integer Divide Instructions
++
++	vdivu.vv v4, v4, v8		# OK
++	vdivu.vv v8, v4, v8		# OK
++	vdivu.vv v0, v4, v8, v0.t	# vd overlap vm
++	vdivu.vx v4, v4, a1		# OK
++	vdivu.vx v0, v4, a1, v0.t	# vd overlap vm
++
++	vdiv.vv v4, v4, v8
++	vdiv.vv v8, v4, v8
++	vdiv.vv v0, v4, v8, v0.t
++	vdiv.vx v4, v4, a1
++	vdiv.vx v0, v4, a1, v0.t
++
++	vremu.vv v4, v4, v8
++	vremu.vv v8, v4, v8
++	vremu.vv v0, v4, v8, v0.t
++	vremu.vx v4, v4, a1
++	vremu.vx v0, v4, a1, v0.t
++
++	vrem.vv v4, v4, v8
++	vrem.vv v8, v4, v8
++	vrem.vv v0, v4, v8, v0.t
++	vrem.vx v4, v4, a1
++	vrem.vx v0, v4, a1, v0.t
++
++# Vector Single-Width Integer Multiply-Add Instructions
++
++	vmacc.vv v4, v4, v8		# OK
++	vmacc.vv v8, v4, v8		# OK
++	vmacc.vv v0, v4, v8, v0.t	# vd overlap vm
++	vmacc.vx v4, a1, v4		# OK
++	vmacc.vx v0, a1, v4, v0.t	# vd overlap vm
++
++	vnmsac.vv v4, v4, v8
++	vnmsac.vv v8, v4, v8
++	vnmsac.vv v0, v4, v8, v0.t
++	vnmsac.vx v4, a1, v4
++	vnmsac.vx v0, a1, v4, v0.t
++
++	vmadd.vv v4, v4, v8
++	vmadd.vv v8, v4, v8
++	vmadd.vv v0, v4, v8, v0.t
++	vmadd.vx v4, a1, v4
++	vmadd.vx v0, a1, v4, v0.t
++
++	vnmsub.vv v4, v4, v8
++	vnmsub.vv v8, v4, v8
++	vnmsub.vv v0, v4, v8, v0.t
++	vnmsub.vx v4, a1, v4
++	vnmsub.vx v0, a1, v4, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
+new file mode 100644
+index 0000000000..5d38168a0b
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv0p10 
++#source: vector-insns-fail-arith-narrow.s
++#error_output: vector-insns-fail-arith-narrow.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+new file mode 100644
+index 0000000000..4bba63a6cd
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
+@@ -0,0 +1,85 @@
++.*: Assembler messages:
++.*Error: illegal operands `vncvt.x.x.w v2,v2'
++.*Error: illegal operands `vncvt.x.x.w v2,v3'
++.*Error: illegal operands `vncvt.x.x.w v3,v2'
++.*Error: illegal operands `vncvt.x.x.w v0,v2,v0.t'
++.*Error: illegal operands `vnsrl.wv v2,v2,v4'
++.*Error: illegal operands `vnsrl.wv v2,v3,v4'
++.*Error: illegal operands `vnsrl.wv v3,v2,v4'
++.*Error: illegal operands `vnsrl.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vnsrl.wx v2,v2,a1'
++.*Error: illegal operands `vnsrl.wx v2,v3,a1'
++.*Error: illegal operands `vnsrl.wx v3,v2,a1'
++.*Error: illegal operands `vnsrl.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnsrl.wi v2,v2,31'
++.*Error: illegal operands `vnsrl.wi v2,v3,31'
++.*Error: illegal operands `vnsrl.wi v3,v2,31'
++.*Error: illegal operands `vnsrl.wi v0,v2,31,v0.t'
++.*Error: illegal operands `vnsra.wv v2,v2,v4'
++.*Error: illegal operands `vnsra.wv v2,v3,v4'
++.*Error: illegal operands `vnsra.wv v3,v2,v4'
++.*Error: illegal operands `vnsra.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vnsra.wx v2,v2,a1'
++.*Error: illegal operands `vnsra.wx v2,v3,a1'
++.*Error: illegal operands `vnsra.wx v3,v2,a1'
++.*Error: illegal operands `vnsra.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnsra.wi v2,v2,31'
++.*Error: illegal operands `vnsra.wi v2,v3,31'
++.*Error: illegal operands `vnsra.wi v3,v2,31'
++.*Error: illegal operands `vnsra.wi v0,v2,31,v0.t'
++.*Error: illegal operands `vnclipu.wv v2,v2,v4'
++.*Error: illegal operands `vnclipu.wv v2,v3,v4'
++.*Error: illegal operands `vnclipu.wv v3,v2,v4'
++.*Error: illegal operands `vnclipu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vnclipu.wx v2,v2,a1'
++.*Error: illegal operands `vnclipu.wx v2,v3,a1'
++.*Error: illegal operands `vnclipu.wx v3,v2,a1'
++.*Error: illegal operands `vnclipu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnclipu.wi v2,v2,31'
++.*Error: illegal operands `vnclipu.wi v2,v3,31'
++.*Error: illegal operands `vnclipu.wi v3,v2,31'
++.*Error: illegal operands `vnclipu.wi v0,v2,31,v0.t'
++.*Error: illegal operands `vnclip.wv v2,v2,v4'
++.*Error: illegal operands `vnclip.wv v2,v3,v4'
++.*Error: illegal operands `vnclip.wv v3,v2,v4'
++.*Error: illegal operands `vnclip.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vnclip.wx v2,v2,a1'
++.*Error: illegal operands `vnclip.wx v2,v3,a1'
++.*Error: illegal operands `vnclip.wx v3,v2,a1'
++.*Error: illegal operands `vnclip.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vnclip.wi v2,v2,31'
++.*Error: illegal operands `vnclip.wi v2,v3,31'
++.*Error: illegal operands `vnclip.wi v3,v2,31'
++.*Error: illegal operands `vnclip.wi v0,v2,31,v0.t'
++.*Error: illegal operands `vfncvt.xu.f.w v2,v2'
++.*Error: illegal operands `vfncvt.xu.f.w v2,v3'
++.*Error: illegal operands `vfncvt.xu.f.w v3,v2'
++.*Error: illegal operands `vfncvt.xu.f.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.x.f.w v2,v2'
++.*Error: illegal operands `vfncvt.x.f.w v2,v3'
++.*Error: illegal operands `vfncvt.x.f.w v3,v2'
++.*Error: illegal operands `vfncvt.x.f.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rtz.x.f.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.f.xu.w v2,v2'
++.*Error: illegal operands `vfncvt.f.xu.w v2,v3'
++.*Error: illegal operands `vfncvt.f.xu.w v3,v2'
++.*Error: illegal operands `vfncvt.f.xu.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.f.x.w v2,v2'
++.*Error: illegal operands `vfncvt.f.x.w v2,v3'
++.*Error: illegal operands `vfncvt.f.x.w v3,v2'
++.*Error: illegal operands `vfncvt.f.x.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.f.f.w v2,v2'
++.*Error: illegal operands `vfncvt.f.f.w v2,v3'
++.*Error: illegal operands `vfncvt.f.f.w v3,v2'
++.*Error: illegal operands `vfncvt.f.f.w v0,v2,v0.t'
++.*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
++.*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
++.*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
++.*Error: illegal operands `vfncvt.rod.f.f.w v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+new file mode 100644
+index 0000000000..73b96ef800
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
+@@ -0,0 +1,100 @@
++# Vector Narrowing Integer Right Shift Instructions
++
++	# vncvt.x.x.w vd,vs,vm = vnsrl.wx vd,vs,x0,vm
++	vncvt.x.x.w v2, v2		# vd overlap vs2
++	vncvt.x.x.w v2, v3		# vs2 should be multiple of 2
++	vncvt.x.x.w v3, v2		# vd overlap vs2
++	vncvt.x.x.w v0, v2, v0.t	# vd overlap vm
++
++	vnsrl.wv v2, v2, v4		# vd overlap vs2
++	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnsrl.wv v3, v2, v4		# vd overlap vs2
++	vnsrl.wv v4, v2, v4		# OK
++	vnsrl.wv v0, v2, v4, v0.t	# vd overlap vm
++	vnsrl.wx v2, v2, a1		# vd overlap vs2
++	vnsrl.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnsrl.wx v3, v2, a1		# vd overlap vs2
++	vnsrl.wx v0, v2, a1, v0.t	# vd overlap vm
++	vnsrl.wi v2, v2, 31		# vd overlap vs2
++	vnsrl.wi v2, v3, 31		# vs2 should be multiple of 2
++	vnsrl.wi v3, v2, 31		# vd overlap vs2
++	vnsrl.wi v0, v2, 31, v0.t	# vd overlap vm
++
++	vnsra.wv v2, v2, v4
++	vnsra.wv v2, v3, v4
++	vnsra.wv v3, v2, v4
++	vnsra.wv v4, v2, v4
++	vnsra.wv v0, v2, v4, v0.t
++	vnsra.wx v2, v2, a1
++	vnsra.wx v2, v3, a1
++	vnsra.wx v3, v2, a1
++	vnsra.wx v0, v2, a1, v0.t
++	vnsra.wi v2, v2, 31
++	vnsra.wi v2, v3, 31
++	vnsra.wi v3, v2, 31
++	vnsra.wi v0, v2, 31, v0.t
++
++# Vector Narrowing Fixed-Point Clip Instructions
++
++	vnclipu.wv v2, v2, v4		# vd overlap vs2
++	vnclipu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vnclipu.wv v3, v2, v4		# vd overlap vs2
++	vnclipu.wv v4, v2, v4		# OK
++	vnclipu.wv v0, v2, v4, v0.t	# vd overlap vm
++	vnclipu.wx v2, v2, a1		# vd overlap vs2
++	vnclipu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vnclipu.wx v3, v2, a1		# vd overlap vs2
++	vnclipu.wx v0, v2, a1, v0.t	# vd overlap vm
++	vnclipu.wi v2, v2, 31		# vd overlap vs2
++	vnclipu.wi v2, v3, 31		# vs2 should be multiple of 2
++	vnclipu.wi v3, v2, 31		# vd overlap vs2
++	vnclipu.wi v0, v2, 31, v0.t	# vd overlap vm
++
++	vnclip.wv v2, v2, v4
++	vnclip.wv v2, v3, v4
++	vnclip.wv v3, v2, v4
++	vnclip.wv v4, v2, v4
++	vnclip.wv v0, v2, v4, v0.t
++	vnclip.wx v2, v2, a1
++	vnclip.wx v2, v3, a1
++	vnclip.wx v3, v2, a1
++	vnclip.wx v0, v2, a1, v0.t
++	vnclip.wi v2, v2, 31
++	vnclip.wi v2, v3, 31
++	vnclip.wi v3, v2, 31
++	vnclip.wi v0, v2, 31, v0.t
++
++# Narrowing Floating-Point/Integer Type-Convert Instructions
++
++	vfncvt.xu.f.w v2, v2		# vd overlap vs2
++	vfncvt.xu.f.w v2, v3		# vs2 should be multiple of 2
++	vfncvt.xu.f.w v3, v2		# vd overlap vs2
++	vfncvt.xu.f.w v0, v2, v0.t	# vd overlap vm
++	vfncvt.x.f.w v2, v2
++	vfncvt.x.f.w v2, v3
++	vfncvt.x.f.w v3, v2
++	vfncvt.x.f.w v0, v2, v0.t
++	vfncvt.rtz.xu.f.w v2, v2
++	vfncvt.rtz.xu.f.w v2, v3
++	vfncvt.rtz.xu.f.w v3, v2
++	vfncvt.rtz.xu.f.w v0, v2, v0.t
++	vfncvt.rtz.x.f.w v2, v2
++	vfncvt.rtz.x.f.w v2, v3
++	vfncvt.rtz.x.f.w v3, v2
++	vfncvt.rtz.x.f.w v0, v2, v0.t
++	vfncvt.f.xu.w v2, v2
++	vfncvt.f.xu.w v2, v3
++	vfncvt.f.xu.w v3, v2
++	vfncvt.f.xu.w v0, v2, v0.t
++	vfncvt.f.x.w v2, v2
++	vfncvt.f.x.w v2, v3
++	vfncvt.f.x.w v3, v2
++	vfncvt.f.x.w v0, v2, v0.t
++	vfncvt.f.f.w v2, v2
++	vfncvt.f.f.w v2, v3
++	vfncvt.f.f.w v3, v2
++	vfncvt.f.f.w v0, v2, v0.t
++	vfncvt.rod.f.f.w v2, v2
++	vfncvt.rod.f.f.w v2, v3
++	vfncvt.rod.f.f.w v3, v2
++	vfncvt.rod.f.f.w v0, v2, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
+new file mode 100644
+index 0000000000..b3a61bbbb3
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv0p10
++#source: vector-insns-fail-arith-widen.s
++#error_output: vector-insns-fail-arith-widen.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+new file mode 100644
+index 0000000000..5684601697
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
+@@ -0,0 +1,253 @@
++.*: Assembler messages:
++.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
++.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
++.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
++.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
++.*Error: illegal operands `vwcvt.x.x.v v1,v2'
++.*Error: illegal operands `vwcvt.x.x.v v2,v2'
++.*Error: illegal operands `vwcvt.x.x.v v2,v3'
++.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
++.*Error: illegal operands `vwaddu.vv v1,v2,v4'
++.*Error: illegal operands `vwaddu.vv v2,v2,v4'
++.*Error: illegal operands `vwaddu.vv v2,v3,v4'
++.*Error: illegal operands `vwaddu.vv v4,v2,v4'
++.*Error: illegal operands `vwaddu.vv v4,v2,v5'
++.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwaddu.vx v1,v2,a1'
++.*Error: illegal operands `vwaddu.vx v2,v2,a1'
++.*Error: illegal operands `vwaddu.vx v2,v3,a1'
++.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwaddu.wv v1,v2,v4'
++.*Error: illegal operands `vwaddu.wv v2,v3,v4'
++.*Error: illegal operands `vwaddu.wv v4,v2,v4'
++.*Error: illegal operands `vwaddu.wv v4,v2,v5'
++.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwaddu.wx v1,v2,a1'
++.*Error: illegal operands `vwaddu.wx v2,v3,a1'
++.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsubu.vv v1,v2,v4'
++.*Error: illegal operands `vwsubu.vv v2,v2,v4'
++.*Error: illegal operands `vwsubu.vv v2,v3,v4'
++.*Error: illegal operands `vwsubu.vv v4,v2,v4'
++.*Error: illegal operands `vwsubu.vv v4,v2,v5'
++.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsubu.vx v1,v2,a1'
++.*Error: illegal operands `vwsubu.vx v2,v2,a1'
++.*Error: illegal operands `vwsubu.vx v2,v3,a1'
++.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsubu.wv v1,v2,v4'
++.*Error: illegal operands `vwsubu.wv v2,v3,v4'
++.*Error: illegal operands `vwsubu.wv v4,v2,v4'
++.*Error: illegal operands `vwsubu.wv v4,v2,v5'
++.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsubu.wx v1,v2,a1'
++.*Error: illegal operands `vwsubu.wx v2,v3,a1'
++.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwadd.vv v1,v2,v4'
++.*Error: illegal operands `vwadd.vv v2,v2,v4'
++.*Error: illegal operands `vwadd.vv v2,v3,v4'
++.*Error: illegal operands `vwadd.vv v4,v2,v4'
++.*Error: illegal operands `vwadd.vv v4,v2,v5'
++.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwadd.vx v1,v2,a1'
++.*Error: illegal operands `vwadd.vx v2,v2,a1'
++.*Error: illegal operands `vwadd.vx v2,v3,a1'
++.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwadd.wv v1,v2,v4'
++.*Error: illegal operands `vwadd.wv v2,v3,v4'
++.*Error: illegal operands `vwadd.wv v4,v2,v4'
++.*Error: illegal operands `vwadd.wv v4,v2,v5'
++.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwadd.wx v1,v2,a1'
++.*Error: illegal operands `vwadd.wx v2,v3,a1'
++.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsub.vv v1,v2,v4'
++.*Error: illegal operands `vwsub.vv v2,v2,v4'
++.*Error: illegal operands `vwsub.vv v2,v3,v4'
++.*Error: illegal operands `vwsub.vv v4,v2,v4'
++.*Error: illegal operands `vwsub.vv v4,v2,v5'
++.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsub.vx v1,v2,a1'
++.*Error: illegal operands `vwsub.vx v2,v2,a1'
++.*Error: illegal operands `vwsub.vx v2,v3,a1'
++.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwsub.wv v1,v2,v4'
++.*Error: illegal operands `vwsub.wv v2,v3,v4'
++.*Error: illegal operands `vwsub.wv v4,v2,v4'
++.*Error: illegal operands `vwsub.wv v4,v2,v5'
++.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwsub.wx v1,v2,a1'
++.*Error: illegal operands `vwsub.wx v2,v3,a1'
++.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmul.vv v1,v2,v4'
++.*Error: illegal operands `vwmul.vv v2,v2,v4'
++.*Error: illegal operands `vwmul.vv v2,v3,v4'
++.*Error: illegal operands `vwmul.vv v4,v2,v4'
++.*Error: illegal operands `vwmul.vv v4,v2,v5'
++.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmul.vx v1,v2,a1'
++.*Error: illegal operands `vwmul.vx v2,v2,a1'
++.*Error: illegal operands `vwmul.vx v2,v3,a1'
++.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmulu.vv v1,v2,v4'
++.*Error: illegal operands `vwmulu.vv v2,v2,v4'
++.*Error: illegal operands `vwmulu.vv v2,v3,v4'
++.*Error: illegal operands `vwmulu.vv v4,v2,v4'
++.*Error: illegal operands `vwmulu.vv v4,v2,v5'
++.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmulu.vx v1,v2,a1'
++.*Error: illegal operands `vwmulu.vx v2,v2,a1'
++.*Error: illegal operands `vwmulu.vx v2,v3,a1'
++.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
++.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
++.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
++.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
++.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
++.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
++.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
++.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
++.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
++.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
++.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmaccu.vx v1,a1,v2'
++.*Error: illegal operands `vwmaccu.vx v2,a1,v2'
++.*Error: illegal operands `vwmaccu.vx v2,a1,v3'
++.*Error: illegal operands `vwmaccu.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vwmacc.vv v1,v2,v4'
++.*Error: illegal operands `vwmacc.vv v2,v2,v4'
++.*Error: illegal operands `vwmacc.vv v2,v3,v4'
++.*Error: illegal operands `vwmacc.vv v4,v2,v4'
++.*Error: illegal operands `vwmacc.vv v4,v2,v5'
++.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmacc.vx v1,a1,v2'
++.*Error: illegal operands `vwmacc.vx v2,a1,v2'
++.*Error: illegal operands `vwmacc.vx v2,a1,v3'
++.*Error: illegal operands `vwmacc.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
++.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vwmaccsu.vx v1,a1,v2'
++.*Error: illegal operands `vwmaccsu.vx v2,a1,v2'
++.*Error: illegal operands `vwmaccsu.vx v2,a1,v3'
++.*Error: illegal operands `vwmaccsu.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vwmaccus.vx v1,a1,v2'
++.*Error: illegal operands `vwmaccus.vx v2,a1,v2'
++.*Error: illegal operands `vwmaccus.vx v2,a1,v3'
++.*Error: illegal operands `vwmaccus.vx v0,a1,v2,v0.t'
++.*Error: illegal operands `vfwadd.vv v1,v2,v4'
++.*Error: illegal operands `vfwadd.vv v2,v2,v4'
++.*Error: illegal operands `vfwadd.vv v2,v3,v4'
++.*Error: illegal operands `vfwadd.vv v4,v2,v4'
++.*Error: illegal operands `vfwadd.vv v4,v2,v5'
++.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
++.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
++.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
++.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwadd.wv v1,v2,v4'
++.*Error: illegal operands `vfwadd.wv v2,v3,v4'
++.*Error: illegal operands `vfwadd.wv v4,v2,v4'
++.*Error: illegal operands `vfwadd.wv v4,v2,v5'
++.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vv v1,v2,v4'
++.*Error: illegal operands `vfwsub.vv v2,v2,v4'
++.*Error: illegal operands `vfwsub.vv v2,v3,v4'
++.*Error: illegal operands `vfwsub.vv v4,v2,v4'
++.*Error: illegal operands `vfwsub.vv v4,v2,v5'
++.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwsub.wv v1,v2,v4'
++.*Error: illegal operands `vfwsub.wv v2,v3,v4'
++.*Error: illegal operands `vfwsub.wv v4,v2,v4'
++.*Error: illegal operands `vfwsub.wv v4,v2,v5'
++.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmul.vv v1,v2,v4'
++.*Error: illegal operands `vfwmul.vv v2,v2,v4'
++.*Error: illegal operands `vfwmul.vv v2,v3,v4'
++.*Error: illegal operands `vfwmul.vv v4,v2,v4'
++.*Error: illegal operands `vfwmul.vv v4,v2,v5'
++.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
++.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
++.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
++.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
++.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmacc.vf v1,fa1,v2'
++.*Error: illegal operands `vfwmacc.vf v2,fa1,v2'
++.*Error: illegal operands `vfwmacc.vf v2,fa1,v3'
++.*Error: illegal operands `vfwmacc.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
++.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwnmacc.vf v1,fa1,v2'
++.*Error: illegal operands `vfwnmacc.vf v2,fa1,v2'
++.*Error: illegal operands `vfwnmacc.vf v2,fa1,v3'
++.*Error: illegal operands `vfwnmacc.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
++.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
++.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
++.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwmsac.vf v1,fa1,v2'
++.*Error: illegal operands `vfwmsac.vf v2,fa1,v2'
++.*Error: illegal operands `vfwmsac.vf v2,fa1,v3'
++.*Error: illegal operands `vfwmsac.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
++.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
++.*Error: illegal operands `vfwnmsac.vf v1,fa1,v2'
++.*Error: illegal operands `vfwnmsac.vf v2,fa1,v2'
++.*Error: illegal operands `vfwnmsac.vf v2,fa1,v3'
++.*Error: illegal operands `vfwnmsac.vf v0,fa1,v2,v0.t'
++.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
++.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
++.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
++.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
++.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
+new file mode 100644
+index 0000000000..addedd4dc2
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
+@@ -0,0 +1,297 @@
++# Vector Widening Integer Add/Subtract
++
++	# vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
++	vwcvtu.x.x.v v1, v2		# vd should be multiple of 2
++	vwcvtu.x.x.v v2, v2		# vd overlap vs2
++	vwcvtu.x.x.v v2, v3		# vd overlap vs2
++	vwcvtu.x.x.v v0, v2, v0.t	# vd overlap vm
++
++	# vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
++	vwcvt.x.x.v v1, v2
++	vwcvt.x.x.v v2, v2
++	vwcvt.x.x.v v2, v3
++	vwcvt.x.x.v v0, v2, v0.t
++
++	vwaddu.vv v1, v2, v4		# vd should be multiple of 2
++	vwaddu.vv v2, v2, v4		# vd overlap vs2
++	vwaddu.vv v2, v3, v4		# vd overlap vs2
++	vwaddu.vv v4, v2, v4		# vd overlap vs1
++	vwaddu.vv v4, v2, v5		# vd overlap vs1
++	vwaddu.vv v0, v2, v4, v0.t	# vd overlap vm
++	vwaddu.vx v1, v2, a1		# vd should be multiple of 2
++	vwaddu.vx v2, v2, a1		# vd overlap vs2
++	vwaddu.vx v2, v3, a1		# vd overlap vs2
++	vwaddu.vx v0, v2, a1, v0.t	# vd overlap vm
++	vwaddu.wv v1, v2, v4		# vd should be multiple of 2
++	vwaddu.wv v2, v2, v4		# OK
++	vwaddu.wv v2, v3, v4		# vs2 should be multiple of 2
++	vwaddu.wv v4, v2, v4		# vd overlap vs1
++	vwaddu.wv v4, v2, v5		# vd overlap vs1
++	vwaddu.wv v0, v2, v4, v0.t	# vd overlap vm
++	vwaddu.wx v1, v2, a1		# vd should be multiple of 2
++	vwaddu.wx v2, v2, a1		# OK
++	vwaddu.wx v2, v3, a1		# vs2 should be multiple of 2
++	vwaddu.wx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwsubu.vv v1, v2, v4
++	vwsubu.vv v2, v2, v4
++	vwsubu.vv v2, v3, v4
++	vwsubu.vv v4, v2, v4
++	vwsubu.vv v4, v2, v5
++	vwsubu.vv v0, v2, v4, v0.t
++	vwsubu.vx v1, v2, a1
++	vwsubu.vx v2, v2, a1
++	vwsubu.vx v2, v3, a1
++	vwsubu.vx v0, v2, a1, v0.t
++	vwsubu.wv v1, v2, v4
++	vwsubu.wv v2, v2, v4
++	vwsubu.wv v2, v3, v4
++	vwsubu.wv v4, v2, v4
++	vwsubu.wv v4, v2, v5
++	vwsubu.wv v0, v2, v4, v0.t
++	vwsubu.wx v1, v2, a1
++	vwsubu.wx v2, v2, a1
++	vwsubu.wx v2, v3, a1
++	vwsubu.wx v0, v2, a1, v0.t
++
++	vwadd.vv v1, v2, v4
++	vwadd.vv v2, v2, v4
++	vwadd.vv v2, v3, v4
++	vwadd.vv v4, v2, v4
++	vwadd.vv v4, v2, v5
++	vwadd.vv v0, v2, v4, v0.t
++	vwadd.vx v1, v2, a1
++	vwadd.vx v2, v2, a1
++	vwadd.vx v2, v3, a1
++	vwadd.vx v0, v2, a1, v0.t
++	vwadd.wv v1, v2, v4
++	vwadd.wv v2, v2, v4
++	vwadd.wv v2, v3, v4
++	vwadd.wv v4, v2, v4
++	vwadd.wv v4, v2, v5
++	vwadd.wv v0, v2, v4, v0.t
++	vwadd.wx v1, v2, a1
++	vwadd.wx v2, v2, a1
++	vwadd.wx v2, v3, a1
++	vwadd.wx v0, v2, a1, v0.t
++
++	vwsub.vv v1, v2, v4
++	vwsub.vv v2, v2, v4
++	vwsub.vv v2, v3, v4
++	vwsub.vv v4, v2, v4
++	vwsub.vv v4, v2, v5
++	vwsub.vv v0, v2, v4, v0.t
++	vwsub.vx v1, v2, a1
++	vwsub.vx v2, v2, a1
++	vwsub.vx v2, v3, a1
++	vwsub.vx v0, v2, a1, v0.t
++	vwsub.wv v1, v2, v4
++	vwsub.wv v2, v2, v4
++	vwsub.wv v2, v3, v4
++	vwsub.wv v4, v2, v4
++	vwsub.wv v4, v2, v5
++	vwsub.wv v0, v2, v4, v0.t
++	vwsub.wx v1, v2, a1
++	vwsub.wx v2, v2, a1
++	vwsub.wx v2, v3, a1
++	vwsub.wx v0, v2, a1, v0.t
++
++# Vector Widening Integer Multiply Instructions
++
++	vwmul.vv v1, v2, v4		# vd should be multiple of 2
++	vwmul.vv v2, v2, v4		# vd overlap vs2
++	vwmul.vv v2, v3, v4		# vd overlap vs2
++	vwmul.vv v4, v2, v4		# vd overlap vs1
++	vwmul.vv v4, v2, v5		# vd overlap vs1
++	vwmul.vv v0, v2, v4, v0.t	# vd overlap vm
++	vwmul.vx v1, v2, a1		# vd should be multiple of 2
++	vwmul.vx v2, v2, a1		# vd overlap vs2
++	vwmul.vx v2, v3, a1		# vd overlap vs2
++	vwmul.vx v0, v2, a1, v0.t	# vd overlap vm
++
++	vwmulu.vv v1, v2, v4
++	vwmulu.vv v2, v2, v4
++	vwmulu.vv v2, v3, v4
++	vwmulu.vv v4, v2, v4
++	vwmulu.vv v4, v2, v5
++	vwmulu.vv v0, v2, v4, v0.t
++	vwmulu.vx v1, v2, a1
++	vwmulu.vx v2, v2, a1
++	vwmulu.vx v2, v3, a1
++	vwmulu.vx v0, v2, a1, v0.t
++
++	vwmulsu.vv v1, v2, v4
++	vwmulsu.vv v2, v2, v4
++	vwmulsu.vv v2, v3, v4
++	vwmulsu.vv v4, v2, v4
++	vwmulsu.vv v4, v2, v5
++	vwmulsu.vv v0, v2, v4, v0.t
++	vwmulsu.vx v1, v2, a1
++	vwmulsu.vx v2, v2, a1
++	vwmulsu.vx v2, v3, a1
++	vwmulsu.vx v0, v2, a1, v0.t
++
++# Vector Widening Integer Multiply-Add Instructions
++
++	vwmaccu.vv v1, v2, v4		# vd should be multiple of 2
++	vwmaccu.vv v2, v2, v4		# vd overlap vs1
++	vwmaccu.vv v2, v3, v4		# vd overlap vs1
++	vwmaccu.vv v4, v2, v4		# vd overlap vs2
++	vwmaccu.vv v4, v2, v5		# vd overlap vs2
++	vwmaccu.vv v0, v2, v4, v0.t	# vd overlap vm
++	vwmaccu.vx v1, a1, v2		# vd should be multiple of 2
++	vwmaccu.vx v2, a1, v2		# vd overlap vs2
++	vwmaccu.vx v2, a1, v3		# vd overlap vs2
++	vwmaccu.vx v0, a1, v2, v0.t	# vd overlap vm
++
++	vwmacc.vv v1, v2, v4
++	vwmacc.vv v2, v2, v4
++	vwmacc.vv v2, v3, v4
++	vwmacc.vv v4, v2, v4
++	vwmacc.vv v4, v2, v5
++	vwmacc.vv v0, v2, v4, v0.t
++	vwmacc.vx v1, a1, v2
++	vwmacc.vx v2, a1, v2
++	vwmacc.vx v2, a1, v3
++	vwmacc.vx v0, a1, v2, v0.t
++
++	vwmaccsu.vv v1, v2, v4
++	vwmaccsu.vv v2, v2, v4
++	vwmaccsu.vv v2, v3, v4
++	vwmaccsu.vv v4, v2, v4
++	vwmaccsu.vv v4, v2, v5
++	vwmaccsu.vv v0, v2, v4, v0.t
++	vwmaccsu.vx v1, a1, v2
++	vwmaccsu.vx v2, a1, v2
++	vwmaccsu.vx v2, a1, v3
++	vwmaccsu.vx v0, a1, v2, v0.t
++
++	vwmaccus.vx v1, a1, v2		# vd should be multiple of 2
++	vwmaccus.vx v2, a1, v2		# vd overlap vs2
++	vwmaccus.vx v2, a1, v3		# vd overlap vs2
++	vwmaccus.vx v0, a1, v2, v0.t	# vd overlap vm
++
++# Vector Widening Floating-Point Add/Subtract Instructions
++
++	vfwadd.vv v1, v2, v4		# vd should be multiple of 2
++	vfwadd.vv v2, v2, v4		# vd overlap vs2
++	vfwadd.vv v2, v3, v4		# vd overlap vs2
++	vfwadd.vv v4, v2, v4		# vd overlap vs1
++	vfwadd.vv v4, v2, v5		# vd overlap vs1
++	vfwadd.vv v0, v2, v4, v0.t	# vd overlap vm
++	vfwadd.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwadd.vf v2, v2, fa1		# vd overlap vs2
++	vfwadd.vf v2, v3, fa1		# vd overlap vs2
++	vfwadd.vf v0, v2, fa1, v0.t	# vd overlap vm
++	vfwadd.wv v1, v2, v4		# vd should be multiple of 2
++	vfwadd.wv v2, v2, v4		# OK
++	vfwadd.wv v2, v3, v4		# vs2 should be multiple of 2
++	vfwadd.wv v4, v2, v4		# vd overlap vs1
++	vfwadd.wv v4, v2, v5		# vd overlap vs1
++	vfwadd.wv v0, v2, v4, v0.t	# vd overlap vm
++
++	vfwsub.vv v1, v2, v4
++	vfwsub.vv v2, v2, v4
++	vfwsub.vv v2, v3, v4
++	vfwsub.vv v4, v2, v4
++	vfwsub.vv v4, v2, v5
++	vfwsub.vv v0, v2, v4, v0.t
++	vfwsub.vf v1, v2, fa1
++	vfwsub.vf v2, v2, fa1
++	vfwsub.vf v2, v3, fa1
++	vfwsub.vf v0, v2, fa1, v0.t
++	vfwsub.wv v1, v2, v4
++	vfwsub.wv v2, v2, v4
++	vfwsub.wv v2, v3, v4
++	vfwsub.wv v4, v2, v4
++	vfwsub.wv v4, v2, v5
++	vfwsub.wv v0, v2, v4, v0.t
++
++# Vector Widening Floating-Point Multiply
++
++	vfwmul.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmul.vv v2, v2, v4		# vd overlap vs2
++	vfwmul.vv v2, v3, v4		# vd overlap vs2
++	vfwmul.vv v4, v2, v4		# vd overlap vs1
++	vfwmul.vv v4, v2, v5		# vd overlap vs1
++	vfwmul.vv v0, v2, v4, v0.t	# vd overlap vm
++	vfwsub.vf v1, v2, fa1		# vd should be multiple of 2
++	vfwsub.vf v2, v2, fa1		# vd overlap vs2
++	vfwsub.vf v2, v3, fa1		# vd overlap vs2
++	vfwsub.vf v0, v2, fa1, v0.t	# vd overlap vm
++
++# Vector Widening Floating-Point Fused Multiply-Add Instructions
++	vfwmacc.vv v1, v2, v4		# vd should be multiple of 2
++	vfwmacc.vv v2, v2, v4		# vd overlap vs1
++	vfwmacc.vv v2, v3, v4		# vd overlap vs1
++	vfwmacc.vv v4, v2, v4		# vd overlap vs2
++	vfwmacc.vv v4, v2, v5		# vd overlap vs2
++	vfwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
++	vfwmacc.vf v1, fa1, v2		# vd should be multiple of 2
++	vfwmacc.vf v2, fa1, v2		# vd overlap vs2
++	vfwmacc.vf v2, fa1, v3		# vd overlap vs2
++	vfwmacc.vf v0, fa1, v2, v0.t	# vd overlap vm
++
++	vfwnmacc.vv v1, v2, v4
++	vfwnmacc.vv v2, v2, v4
++	vfwnmacc.vv v2, v3, v4
++	vfwnmacc.vv v4, v2, v4
++	vfwnmacc.vv v4, v2, v5
++	vfwnmacc.vv v0, v2, v4, v0.t
++	vfwnmacc.vf v1, fa1, v2
++	vfwnmacc.vf v2, fa1, v2
++	vfwnmacc.vf v2, fa1, v3
++	vfwnmacc.vf v0, fa1, v2, v0.t
++
++	vfwmsac.vv v1, v2, v4
++	vfwmsac.vv v2, v2, v4
++	vfwmsac.vv v2, v3, v4
++	vfwmsac.vv v4, v2, v4
++	vfwmsac.vv v4, v2, v5
++	vfwmsac.vv v0, v2, v4, v0.t
++	vfwmsac.vf v1, fa1, v2
++	vfwmsac.vf v2, fa1, v2
++	vfwmsac.vf v2, fa1, v3
++	vfwmsac.vf v0, fa1, v2, v0.t
++
++	vfwnmsac.vv v1, v2, v4
++	vfwnmsac.vv v2, v2, v4
++	vfwnmsac.vv v2, v3, v4
++	vfwnmsac.vv v4, v2, v4
++	vfwnmsac.vv v4, v2, v5
++	vfwnmsac.vv v0, v2, v4, v0.t
++	vfwnmsac.vf v1, fa1, v2
++	vfwnmsac.vf v2, fa1, v2
++	vfwnmsac.vf v2, fa1, v3
++	vfwnmsac.vf v0, fa1, v2, v0.t
++
++# Widening Floating-Point/Integer Type-Convert Instructions
++
++	vfwcvt.xu.f.v v1, v2		# vd should be multiple of 2
++	vfwcvt.xu.f.v v2, v2		# vd overlap vs2
++	vfwcvt.xu.f.v v2, v3		# vd overlap vs2
++	vfwcvt.xu.f.v v0, v2, v0.t	# vd overlap vm
++	vfwcvt.x.f.v v1, v2
++	vfwcvt.x.f.v v2, v2
++	vfwcvt.x.f.v v2, v3
++	vfwcvt.x.f.v v0, v2, v0.t
++	vfwcvt.rtz.xu.f.v v1, v2
++	vfwcvt.rtz.xu.f.v v2, v2
++	vfwcvt.rtz.xu.f.v v2, v3
++	vfwcvt.rtz.xu.f.v v0, v2, v0.t
++	vfwcvt.rtz.x.f.v v1, v2
++	vfwcvt.rtz.x.f.v v2, v2
++	vfwcvt.rtz.x.f.v v2, v3
++	vfwcvt.rtz.x.f.v v0, v2, v0.t
++	vfwcvt.f.xu.v v1, v2
++	vfwcvt.f.xu.v v2, v2
++	vfwcvt.f.xu.v v2, v3
++	vfwcvt.f.xu.v v0, v2, v0.t
++	vfwcvt.f.x.v v1, v2
++	vfwcvt.f.x.v v2, v2
++	vfwcvt.f.x.v v2, v3
++	vfwcvt.f.x.v v0, v2, v0.t
++	vfwcvt.f.f.v v1, v2
++	vfwcvt.f.f.v v2, v2
++	vfwcvt.f.f.v v2, v3
++	vfwcvt.f.f.v v0, v2, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+new file mode 100644
+index 0000000000..1e4ac10260
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10 
++#source: vector-insns-fail-load-store.s
++#error_output: vector-insns-fail-load-store.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+new file mode 100644
+index 0000000000..f2e682214c
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
+@@ -0,0 +1,419 @@
++.*: Assembler messages:
++.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vle64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vloxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e8.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e16.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e32.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg2e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg3e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg4e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg5e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg6e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg7e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vsseg8e64.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
++.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e8.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e16.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e32.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg2e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg3e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg4e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg5e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg6e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg7e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vssseg8e64.v v0,\(a0\),a1,v0.t'
++.*Error: illegal operands `vloxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vloxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vloxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsoxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsoxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg2ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg2ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg3ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg3ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg4ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg4ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg5ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg5ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg6ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg6ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg7ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg7ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg8ei8.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg8ei8.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg2ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg2ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg3ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg3ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg4ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg4ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg5ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg5ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg6ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg6ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg7ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg7ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg8ei16.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg8ei16.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg2ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg2ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg3ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg3ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg4ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg4ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg5ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg5ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg6ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg6ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg7ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg7ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg8ei32.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg8ei32.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg2ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg2ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg3ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg3ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg4ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg4ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg5ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg5ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg6ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg6ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg7ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg7ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vluxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vluxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vsuxseg8ei64.v v4,\(a0\),v4'
++.*Error: illegal operands `vsuxseg8ei64.v v0,\(a0\),v4,v0.t'
++.*Error: illegal operands `vl2r.v v31,\(a0\)'
++.*Error: illegal operands `vl2re8.v v31,\(a0\)'
++.*Error: illegal operands `vl2re16.v v31,\(a0\)'
++.*Error: illegal operands `vl2re32.v v31,\(a0\)'
++.*Error: illegal operands `vl2re64.v v31,\(a0\)'
++.*Error: illegal operands `vl4r.v v30,\(a0\)'
++.*Error: illegal operands `vl4re8.v v30,\(a0\)'
++.*Error: illegal operands `vl4re16.v v30,\(a0\)'
++.*Error: illegal operands `vl4re32.v v30,\(a0\)'
++.*Error: illegal operands `vl4re64.v v30,\(a0\)'
++.*Error: illegal operands `vl8r.v v26,\(a0\)'
++.*Error: illegal operands `vl8re8.v v26,\(a0\)'
++.*Error: illegal operands `vl8re16.v v26,\(a0\)'
++.*Error: illegal operands `vl8re32.v v26,\(a0\)'
++.*Error: illegal operands `vl8re64.v v26,\(a0\)'
++.*Error: illegal operands `vs2r.v v31,\(a0\)'
++.*Error: illegal operands `vs4r.v v30,\(a0\)'
++.*Error: illegal operands `vs8r.v v26,\(a0\)'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+new file mode 100644
+index 0000000000..274d0b4226
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
+@@ -0,0 +1,481 @@
++# Vector Unit-Stride Loads and Stores
++
++	vle8.v v0, (a0), v0.t		# vd overlap vm
++	vle8ff.v v0, (a0), v0.t		# vd overlap vm
++	vle16.v v0, (a0), v0.t
++	vle16ff.v v0, (a0), v0.t
++	vle32.v v0, (a0), v0.t
++	vle32ff.v v0, (a0), v0.t
++	vle64.v v0, (a0), v0.t
++	vle64ff.v v0, (a0), v0.t
++
++	vse8.v v0, (a0), v0.t		# vd overlap vm
++	vse16.v v0, (a0), v0.t
++	vse32.v v0, (a0), v0.t
++	vse64.v v0, (a0), v0.t
++
++# Vector Strided Loads and Stores
++
++	vlse8.v v0, (a0), a1, v0.t	# vd overlap vm
++	vlse16.v v0, (a0), a1, v0.t
++	vlse32.v v0, (a0), a1, v0.t
++	vlse64.v v0, (a0), a1, v0.t
++
++	vsse8.v v0, (a0), a1, v0.t
++	vsse16.v v0, (a0), a1, v0.t
++	vsse32.v v0, (a0), a1, v0.t
++	vsse64.v v0, (a0), a1, v0.t
++
++# Vector Ordered Indexed Loads and Stores
++
++	vloxei8.v v4, (a0), v4		# OK
++	vloxei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vloxei16.v v4, (a0), v4
++	vloxei16.v v0, (a0), v4, v0.t
++	vloxei32.v v4, (a0), v4
++	vloxei32.v v0, (a0), v4, v0.t
++	vloxei64.v v4, (a0), v4
++	vloxei64.v v0, (a0), v4, v0.t
++
++	vsoxei8.v v4, (a0), v4
++	vsoxei8.v v0, (a0), v4, v0.t
++	vsoxei16.v v4, (a0), v4
++	vsoxei16.v v0, (a0), v4, v0.t
++	vsoxei32.v v4, (a0), v4
++	vsoxei32.v v0, (a0), v4, v0.t
++	vsoxei64.v v4, (a0), v4
++	vsoxei64.v v0, (a0), v4, v0.t
++
++# Vector Unordered Indexed Loads and Stores
++
++	vluxei8.v v4, (a0), v4		# OK
++	vluxei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vluxei16.v v4, (a0), v4
++	vluxei16.v v0, (a0), v4, v0.t
++	vluxei32.v v4, (a0), v4
++	vluxei32.v v0, (a0), v4, v0.t
++	vluxei64.v v4, (a0), v4
++	vluxei64.v v0, (a0), v4, v0.t
++
++	vsuxei8.v v4, (a0), v4
++	vsuxei8.v v0, (a0), v4, v0.t
++	vsuxei16.v v4, (a0), v4
++	vsuxei16.v v0, (a0), v4, v0.t
++	vsuxei32.v v4, (a0), v4
++	vsuxei32.v v0, (a0), v4, v0.t
++	vsuxei64.v v4, (a0), v4
++	vsuxei64.v v0, (a0), v4, v0.t
++
++# Vector Unit-Stride Segment Loads and Stores
++
++	vlseg2e8.v v0, (a0), v0.t	# vd overlap vm
++	vsseg2e8.v v0, (a0), v0.t	# vd overlap vm
++	vlseg2e8ff.v v0, (a0), v0.t	# vd overlap vm
++	vlseg3e8.v v0, (a0), v0.t
++	vsseg3e8.v v0, (a0), v0.t
++	vlseg3e8ff.v v0, (a0), v0.t
++	vlseg4e8.v v0, (a0), v0.t
++	vsseg4e8.v v0, (a0), v0.t
++	vlseg4e8ff.v v0, (a0), v0.t
++	vlseg5e8.v v0, (a0), v0.t
++	vsseg5e8.v v0, (a0), v0.t
++	vlseg5e8ff.v v0, (a0), v0.t
++	vlseg6e8.v v0, (a0), v0.t
++	vsseg6e8.v v0, (a0), v0.t
++	vlseg6e8ff.v v0, (a0), v0.t
++	vlseg7e8.v v0, (a0), v0.t
++	vsseg7e8.v v0, (a0), v0.t
++	vlseg7e8ff.v v0, (a0), v0.t
++	vlseg8e8.v v0, (a0), v0.t
++	vsseg8e8.v v0, (a0), v0.t
++	vlseg8e8ff.v v0, (a0), v0.t
++
++	vlseg2e16.v v0, (a0), v0.t
++	vsseg2e16.v v0, (a0), v0.t
++	vlseg2e16ff.v v0, (a0), v0.t
++	vlseg3e16.v v0, (a0), v0.t
++	vsseg3e16.v v0, (a0), v0.t
++	vlseg3e16ff.v v0, (a0), v0.t
++	vlseg4e16.v v0, (a0), v0.t
++	vsseg4e16.v v0, (a0), v0.t
++	vlseg4e16ff.v v0, (a0), v0.t
++	vlseg5e16.v v0, (a0), v0.t
++	vsseg5e16.v v0, (a0), v0.t
++	vlseg5e16ff.v v0, (a0), v0.t
++	vlseg6e16.v v0, (a0), v0.t
++	vsseg6e16.v v0, (a0), v0.t
++	vlseg6e16ff.v v0, (a0), v0.t
++	vlseg7e16.v v0, (a0), v0.t
++	vsseg7e16.v v0, (a0), v0.t
++	vlseg7e16ff.v v0, (a0), v0.t
++	vlseg8e16.v v0, (a0), v0.t
++	vsseg8e16.v v0, (a0), v0.t
++	vlseg8e16ff.v v0, (a0), v0.t
++
++	vlseg2e32.v v0, (a0), v0.t
++	vsseg2e32.v v0, (a0), v0.t
++	vlseg2e32ff.v v0, (a0), v0.t
++	vlseg3e32.v v0, (a0), v0.t
++	vsseg3e32.v v0, (a0), v0.t
++	vlseg3e32ff.v v0, (a0), v0.t
++	vlseg4e32.v v0, (a0), v0.t
++	vsseg4e32.v v0, (a0), v0.t
++	vlseg4e32ff.v v0, (a0), v0.t
++	vlseg5e32.v v0, (a0), v0.t
++	vsseg5e32.v v0, (a0), v0.t
++	vlseg5e32ff.v v0, (a0), v0.t
++	vlseg6e32.v v0, (a0), v0.t
++	vsseg6e32.v v0, (a0), v0.t
++	vlseg6e32ff.v v0, (a0), v0.t
++	vlseg7e32.v v0, (a0), v0.t
++	vsseg7e32.v v0, (a0), v0.t
++	vlseg7e32ff.v v0, (a0), v0.t
++	vlseg8e32.v v0, (a0), v0.t
++	vsseg8e32.v v0, (a0), v0.t
++	vlseg8e32ff.v v0, (a0), v0.t
++
++	vlseg2e64.v v0, (a0), v0.t
++	vsseg2e64.v v0, (a0), v0.t
++	vlseg2e64ff.v v0, (a0), v0.t
++	vlseg3e64.v v0, (a0), v0.t
++	vsseg3e64.v v0, (a0), v0.t
++	vlseg3e64ff.v v0, (a0), v0.t
++	vlseg4e64.v v0, (a0), v0.t
++	vsseg4e64.v v0, (a0), v0.t
++	vlseg4e64ff.v v0, (a0), v0.t
++	vlseg5e64.v v0, (a0), v0.t
++	vsseg5e64.v v0, (a0), v0.t
++	vlseg5e64ff.v v0, (a0), v0.t
++	vlseg6e64.v v0, (a0), v0.t
++	vsseg6e64.v v0, (a0), v0.t
++	vlseg6e64ff.v v0, (a0), v0.t
++	vlseg7e64.v v0, (a0), v0.t
++	vsseg7e64.v v0, (a0), v0.t
++	vlseg7e64ff.v v0, (a0), v0.t
++	vlseg8e64.v v0, (a0), v0.t
++	vsseg8e64.v v0, (a0), v0.t
++	vlseg8e64ff.v v0, (a0), v0.t
++
++# Vector Strided Segment Loads and Stores
++
++	vlsseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
++	vssseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
++	vlsseg3e8.v v0, (a0), a1, v0.t
++	vssseg3e8.v v0, (a0), a1, v0.t
++	vlsseg4e8.v v0, (a0), a1, v0.t
++	vssseg4e8.v v0, (a0), a1, v0.t
++	vlsseg5e8.v v0, (a0), a1, v0.t
++	vssseg5e8.v v0, (a0), a1, v0.t
++	vlsseg6e8.v v0, (a0), a1, v0.t
++	vssseg6e8.v v0, (a0), a1, v0.t
++	vlsseg7e8.v v0, (a0), a1, v0.t
++	vssseg7e8.v v0, (a0), a1, v0.t
++	vlsseg8e8.v v0, (a0), a1, v0.t
++	vssseg8e8.v v0, (a0), a1, v0.t
++
++	vlsseg2e16.v v0, (a0), a1, v0.t
++	vssseg2e16.v v0, (a0), a1, v0.t
++	vlsseg3e16.v v0, (a0), a1, v0.t
++	vssseg3e16.v v0, (a0), a1, v0.t
++	vlsseg4e16.v v0, (a0), a1, v0.t
++	vssseg4e16.v v0, (a0), a1, v0.t
++	vlsseg5e16.v v0, (a0), a1, v0.t
++	vssseg5e16.v v0, (a0), a1, v0.t
++	vlsseg6e16.v v0, (a0), a1, v0.t
++	vssseg6e16.v v0, (a0), a1, v0.t
++	vlsseg7e16.v v0, (a0), a1, v0.t
++	vssseg7e16.v v0, (a0), a1, v0.t
++	vlsseg8e16.v v0, (a0), a1, v0.t
++	vssseg8e16.v v0, (a0), a1, v0.t
++
++	vlsseg2e32.v v0, (a0), a1, v0.t
++	vssseg2e32.v v0, (a0), a1, v0.t
++	vlsseg3e32.v v0, (a0), a1, v0.t
++	vssseg3e32.v v0, (a0), a1, v0.t
++	vlsseg4e32.v v0, (a0), a1, v0.t
++	vssseg4e32.v v0, (a0), a1, v0.t
++	vlsseg5e32.v v0, (a0), a1, v0.t
++	vssseg5e32.v v0, (a0), a1, v0.t
++	vlsseg6e32.v v0, (a0), a1, v0.t
++	vssseg6e32.v v0, (a0), a1, v0.t
++	vlsseg7e32.v v0, (a0), a1, v0.t
++	vssseg7e32.v v0, (a0), a1, v0.t
++	vlsseg8e32.v v0, (a0), a1, v0.t
++	vssseg8e32.v v0, (a0), a1, v0.t
++
++	vlsseg2e64.v v0, (a0), a1, v0.t
++	vssseg2e64.v v0, (a0), a1, v0.t
++	vlsseg3e64.v v0, (a0), a1, v0.t
++	vssseg3e64.v v0, (a0), a1, v0.t
++	vlsseg4e64.v v0, (a0), a1, v0.t
++	vssseg4e64.v v0, (a0), a1, v0.t
++	vlsseg5e64.v v0, (a0), a1, v0.t
++	vssseg5e64.v v0, (a0), a1, v0.t
++	vlsseg6e64.v v0, (a0), a1, v0.t
++	vssseg6e64.v v0, (a0), a1, v0.t
++	vlsseg7e64.v v0, (a0), a1, v0.t
++	vssseg7e64.v v0, (a0), a1, v0.t
++	vlsseg8e64.v v0, (a0), a1, v0.t
++	vssseg8e64.v v0, (a0), a1, v0.t
++
++# Vector Ordered Indexed Segment Loads and Stores
++
++	vloxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vloxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vsoxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vsoxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vloxseg3ei8.v v4, (a0), v4
++	vloxseg3ei8.v v0, (a0), v4, v0.t
++	vsoxseg3ei8.v v4, (a0), v4
++	vsoxseg3ei8.v v0, (a0), v4, v0.t
++	vloxseg4ei8.v v4, (a0), v4
++	vloxseg4ei8.v v0, (a0), v4, v0.t
++	vsoxseg4ei8.v v4, (a0), v4
++	vsoxseg4ei8.v v0, (a0), v4, v0.t
++	vloxseg5ei8.v v4, (a0), v4
++	vloxseg5ei8.v v0, (a0), v4, v0.t
++	vsoxseg5ei8.v v4, (a0), v4
++	vsoxseg5ei8.v v0, (a0), v4, v0.t
++	vloxseg6ei8.v v4, (a0), v4
++	vloxseg6ei8.v v0, (a0), v4, v0.t
++	vsoxseg6ei8.v v4, (a0), v4
++	vsoxseg6ei8.v v0, (a0), v4, v0.t
++	vloxseg7ei8.v v4, (a0), v4
++	vloxseg7ei8.v v0, (a0), v4, v0.t
++	vsoxseg7ei8.v v4, (a0), v4
++	vsoxseg7ei8.v v0, (a0), v4, v0.t
++	vloxseg8ei8.v v4, (a0), v4
++	vloxseg8ei8.v v0, (a0), v4, v0.t
++	vsoxseg8ei8.v v4, (a0), v4
++	vsoxseg8ei8.v v0, (a0), v4, v0.t
++
++	vloxseg2ei16.v v4, (a0), v4
++	vloxseg2ei16.v v0, (a0), v4, v0.t
++	vsoxseg2ei16.v v4, (a0), v4
++	vsoxseg2ei16.v v0, (a0), v4, v0.t
++	vloxseg3ei16.v v4, (a0), v4
++	vloxseg3ei16.v v0, (a0), v4, v0.t
++	vsoxseg3ei16.v v4, (a0), v4
++	vsoxseg3ei16.v v0, (a0), v4, v0.t
++	vloxseg4ei16.v v4, (a0), v4
++	vloxseg4ei16.v v0, (a0), v4, v0.t
++	vsoxseg4ei16.v v4, (a0), v4
++	vsoxseg4ei16.v v0, (a0), v4, v0.t
++	vloxseg5ei16.v v4, (a0), v4
++	vloxseg5ei16.v v0, (a0), v4, v0.t
++	vsoxseg5ei16.v v4, (a0), v4
++	vsoxseg5ei16.v v0, (a0), v4, v0.t
++	vloxseg6ei16.v v4, (a0), v4
++	vloxseg6ei16.v v0, (a0), v4, v0.t
++	vsoxseg6ei16.v v4, (a0), v4
++	vsoxseg6ei16.v v0, (a0), v4, v0.t
++	vloxseg7ei16.v v4, (a0), v4
++	vloxseg7ei16.v v0, (a0), v4, v0.t
++	vsoxseg7ei16.v v4, (a0), v4
++	vsoxseg7ei16.v v0, (a0), v4, v0.t
++	vloxseg8ei16.v v4, (a0), v4
++	vloxseg8ei16.v v0, (a0), v4, v0.t
++	vsoxseg8ei16.v v4, (a0), v4
++	vsoxseg8ei16.v v0, (a0), v4, v0.t
++
++	vloxseg2ei32.v v4, (a0), v4
++	vloxseg2ei32.v v0, (a0), v4, v0.t
++	vsoxseg2ei32.v v4, (a0), v4
++	vsoxseg2ei32.v v0, (a0), v4, v0.t
++	vloxseg3ei32.v v4, (a0), v4
++	vloxseg3ei32.v v0, (a0), v4, v0.t
++	vsoxseg3ei32.v v4, (a0), v4
++	vsoxseg3ei32.v v0, (a0), v4, v0.t
++	vloxseg4ei32.v v4, (a0), v4
++	vloxseg4ei32.v v0, (a0), v4, v0.t
++	vsoxseg4ei32.v v4, (a0), v4
++	vsoxseg4ei32.v v0, (a0), v4, v0.t
++	vloxseg5ei32.v v4, (a0), v4
++	vloxseg5ei32.v v0, (a0), v4, v0.t
++	vsoxseg5ei32.v v4, (a0), v4
++	vsoxseg5ei32.v v0, (a0), v4, v0.t
++	vloxseg6ei32.v v4, (a0), v4
++	vloxseg6ei32.v v0, (a0), v4, v0.t
++	vsoxseg6ei32.v v4, (a0), v4
++	vsoxseg6ei32.v v0, (a0), v4, v0.t
++	vloxseg7ei32.v v4, (a0), v4
++	vloxseg7ei32.v v0, (a0), v4, v0.t
++	vsoxseg7ei32.v v4, (a0), v4
++	vsoxseg7ei32.v v0, (a0), v4, v0.t
++	vloxseg8ei32.v v4, (a0), v4
++	vloxseg8ei32.v v0, (a0), v4, v0.t
++	vsoxseg8ei32.v v4, (a0), v4
++	vsoxseg8ei32.v v0, (a0), v4, v0.t
++
++	vloxseg2ei64.v v4, (a0), v4
++	vloxseg2ei64.v v0, (a0), v4, v0.t
++	vsoxseg2ei64.v v4, (a0), v4
++	vsoxseg2ei64.v v0, (a0), v4, v0.t
++	vloxseg3ei64.v v4, (a0), v4
++	vloxseg3ei64.v v0, (a0), v4, v0.t
++	vsoxseg3ei64.v v4, (a0), v4
++	vsoxseg3ei64.v v0, (a0), v4, v0.t
++	vloxseg4ei64.v v4, (a0), v4
++	vloxseg4ei64.v v0, (a0), v4, v0.t
++	vsoxseg4ei64.v v4, (a0), v4
++	vsoxseg4ei64.v v0, (a0), v4, v0.t
++	vloxseg5ei64.v v4, (a0), v4
++	vloxseg5ei64.v v0, (a0), v4, v0.t
++	vsoxseg5ei64.v v4, (a0), v4
++	vsoxseg5ei64.v v0, (a0), v4, v0.t
++	vloxseg6ei64.v v4, (a0), v4
++	vloxseg6ei64.v v0, (a0), v4, v0.t
++	vsoxseg6ei64.v v4, (a0), v4
++	vsoxseg6ei64.v v0, (a0), v4, v0.t
++	vloxseg7ei64.v v4, (a0), v4
++	vloxseg7ei64.v v0, (a0), v4, v0.t
++	vsoxseg7ei64.v v4, (a0), v4
++	vsoxseg7ei64.v v0, (a0), v4, v0.t
++	vloxseg8ei64.v v4, (a0), v4
++	vloxseg8ei64.v v0, (a0), v4, v0.t
++	vsoxseg8ei64.v v4, (a0), v4
++	vsoxseg8ei64.v v0, (a0), v4, v0.t
++
++# Vector Unordered Indexed Segment Loads and Stores
++
++	vluxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vluxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vsuxseg2ei8.v v4, (a0), v4		# vd overlap vs2
++	vsuxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
++	vluxseg3ei8.v v4, (a0), v4
++	vluxseg3ei8.v v0, (a0), v4, v0.t
++	vsuxseg3ei8.v v4, (a0), v4
++	vsuxseg3ei8.v v0, (a0), v4, v0.t
++	vluxseg4ei8.v v4, (a0), v4
++	vluxseg4ei8.v v0, (a0), v4, v0.t
++	vsuxseg4ei8.v v4, (a0), v4
++	vsuxseg4ei8.v v0, (a0), v4, v0.t
++	vluxseg5ei8.v v4, (a0), v4
++	vluxseg5ei8.v v0, (a0), v4, v0.t
++	vsuxseg5ei8.v v4, (a0), v4
++	vsuxseg5ei8.v v0, (a0), v4, v0.t
++	vluxseg6ei8.v v4, (a0), v4
++	vluxseg6ei8.v v0, (a0), v4, v0.t
++	vsuxseg6ei8.v v4, (a0), v4
++	vsuxseg6ei8.v v0, (a0), v4, v0.t
++	vluxseg7ei8.v v4, (a0), v4
++	vluxseg7ei8.v v0, (a0), v4, v0.t
++	vsuxseg7ei8.v v4, (a0), v4
++	vsuxseg7ei8.v v0, (a0), v4, v0.t
++	vluxseg8ei8.v v4, (a0), v4
++	vluxseg8ei8.v v0, (a0), v4, v0.t
++	vsuxseg8ei8.v v4, (a0), v4
++	vsuxseg8ei8.v v0, (a0), v4, v0.t
++
++	vluxseg2ei16.v v4, (a0), v4
++	vluxseg2ei16.v v0, (a0), v4, v0.t
++	vsuxseg2ei16.v v4, (a0), v4
++	vsuxseg2ei16.v v0, (a0), v4, v0.t
++	vluxseg3ei16.v v4, (a0), v4
++	vluxseg3ei16.v v0, (a0), v4, v0.t
++	vsuxseg3ei16.v v4, (a0), v4
++	vsuxseg3ei16.v v0, (a0), v4, v0.t
++	vluxseg4ei16.v v4, (a0), v4
++	vluxseg4ei16.v v0, (a0), v4, v0.t
++	vsuxseg4ei16.v v4, (a0), v4
++	vsuxseg4ei16.v v0, (a0), v4, v0.t
++	vluxseg5ei16.v v4, (a0), v4
++	vluxseg5ei16.v v0, (a0), v4, v0.t
++	vsuxseg5ei16.v v4, (a0), v4
++	vsuxseg5ei16.v v0, (a0), v4, v0.t
++	vluxseg6ei16.v v4, (a0), v4
++	vluxseg6ei16.v v0, (a0), v4, v0.t
++	vsuxseg6ei16.v v4, (a0), v4
++	vsuxseg6ei16.v v0, (a0), v4, v0.t
++	vluxseg7ei16.v v4, (a0), v4
++	vluxseg7ei16.v v0, (a0), v4, v0.t
++	vsuxseg7ei16.v v4, (a0), v4
++	vsuxseg7ei16.v v0, (a0), v4, v0.t
++	vluxseg8ei16.v v4, (a0), v4
++	vluxseg8ei16.v v0, (a0), v4, v0.t
++	vsuxseg8ei16.v v4, (a0), v4
++	vsuxseg8ei16.v v0, (a0), v4, v0.t
++
++	vluxseg2ei32.v v4, (a0), v4
++	vluxseg2ei32.v v0, (a0), v4, v0.t
++	vsuxseg2ei32.v v4, (a0), v4
++	vsuxseg2ei32.v v0, (a0), v4, v0.t
++	vluxseg3ei32.v v4, (a0), v4
++	vluxseg3ei32.v v0, (a0), v4, v0.t
++	vsuxseg3ei32.v v4, (a0), v4
++	vsuxseg3ei32.v v0, (a0), v4, v0.t
++	vluxseg4ei32.v v4, (a0), v4
++	vluxseg4ei32.v v0, (a0), v4, v0.t
++	vsuxseg4ei32.v v4, (a0), v4
++	vsuxseg4ei32.v v0, (a0), v4, v0.t
++	vluxseg5ei32.v v4, (a0), v4
++	vluxseg5ei32.v v0, (a0), v4, v0.t
++	vsuxseg5ei32.v v4, (a0), v4
++	vsuxseg5ei32.v v0, (a0), v4, v0.t
++	vluxseg6ei32.v v4, (a0), v4
++	vluxseg6ei32.v v0, (a0), v4, v0.t
++	vsuxseg6ei32.v v4, (a0), v4
++	vsuxseg6ei32.v v0, (a0), v4, v0.t
++	vluxseg7ei32.v v4, (a0), v4
++	vluxseg7ei32.v v0, (a0), v4, v0.t
++	vsuxseg7ei32.v v4, (a0), v4
++	vsuxseg7ei32.v v0, (a0), v4, v0.t
++	vluxseg8ei32.v v4, (a0), v4
++	vluxseg8ei32.v v0, (a0), v4, v0.t
++	vsuxseg8ei32.v v4, (a0), v4
++	vsuxseg8ei32.v v0, (a0), v4, v0.t
++
++	vluxseg2ei64.v v4, (a0), v4
++	vluxseg2ei64.v v0, (a0), v4, v0.t
++	vsuxseg2ei64.v v4, (a0), v4
++	vsuxseg2ei64.v v0, (a0), v4, v0.t
++	vluxseg3ei64.v v4, (a0), v4
++	vluxseg3ei64.v v0, (a0), v4, v0.t
++	vsuxseg3ei64.v v4, (a0), v4
++	vsuxseg3ei64.v v0, (a0), v4, v0.t
++	vluxseg4ei64.v v4, (a0), v4
++	vluxseg4ei64.v v0, (a0), v4, v0.t
++	vsuxseg4ei64.v v4, (a0), v4
++	vsuxseg4ei64.v v0, (a0), v4, v0.t
++	vluxseg5ei64.v v4, (a0), v4
++	vluxseg5ei64.v v0, (a0), v4, v0.t
++	vsuxseg5ei64.v v4, (a0), v4
++	vsuxseg5ei64.v v0, (a0), v4, v0.t
++	vluxseg6ei64.v v4, (a0), v4
++	vluxseg6ei64.v v0, (a0), v4, v0.t
++	vsuxseg6ei64.v v4, (a0), v4
++	vsuxseg6ei64.v v0, (a0), v4, v0.t
++	vluxseg7ei64.v v4, (a0), v4
++	vluxseg7ei64.v v0, (a0), v4, v0.t
++	vsuxseg7ei64.v v4, (a0), v4
++	vsuxseg7ei64.v v0, (a0), v4, v0.t
++	vluxseg8ei64.v v4, (a0), v4
++	vluxseg8ei64.v v0, (a0), v4, v0.t
++	vsuxseg8ei64.v v4, (a0), v4
++	vsuxseg8ei64.v v0, (a0), v4, v0.t
++
++# Vector Load/Store Whole Register Instructions
++
++	vl1r.v v31, (a0)		# OK
++
++	vl2r.v v31, (a0)		# vd must be aligned to 2
++	vl2re8.v v31, (a0)
++	vl2re16.v v31, (a0)
++	vl2re32.v v31, (a0)
++	vl2re64.v v31, (a0)
++
++	vl4r.v v30, (a0)		# vd must be aligned to 4
++	vl4re8.v v30, (a0)
++	vl4re16.v v30, (a0)
++	vl4re32.v v30, (a0)
++	vl4re64.v v30, (a0)
++
++	vl8r.v v26, (a0)		# vd must be aligned to 8
++	vl8re8.v v26, (a0)
++	vl8re16.v v26, (a0)
++	vl8re32.v v26, (a0)
++	vl8re64.v v26, (a0)
++
++	vs2r.v v31, (a0)		# vs3 must be aligned to 2
++	vs4r.v v30, (a0)		# vs3 must be aligned to 4
++	vs8r.v v26, (a0)		# vs3 must be aligned to 8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.d b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
+new file mode 100644
+index 0000000000..1d3aa8d7d3
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10
++#source: vector-insns-fail-mask.s
++#error_output: vector-insns-fail-mask.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+new file mode 100644
+index 0000000000..3b23becc16
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
+@@ -0,0 +1,10 @@
++.*: Assembler messages:
++.*Error: illegal operands `vmsbf.m v4,v4'
++.*Error: illegal operands `vmsbf.m v0,v4,v0.t'
++.*Error: illegal operands `vmsif.m v4,v4'
++.*Error: illegal operands `vmsif.m v0,v4,v0.t'
++.*Error: illegal operands `vmsof.m v4,v4'
++.*Error: illegal operands `vmsof.m v0,v4,v0.t'
++.*Error: illegal operands `viota.m v4,v4'
++.*Error: illegal operands `viota.m v0,v4,v0.t'
++.*Error: illegal operands `vid.v v0,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+new file mode 100644
+index 0000000000..99b19f6bdd
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
+@@ -0,0 +1,23 @@
++# Vector Set-before-first Mask Bit
++
++	vmsbf.m v4, v4		# vd overlap vs2
++	vmsbf.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Set-including-first Mask Bit
++
++	vmsif.m v4, v4		# vd overlap vs2
++	vmsif.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Set-only-first Mask Bit
++
++	vmsof.m v4, v4		# vd overlap vs2
++	vmsof.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Iota Instruction
++
++	viota.m v4, v4		# vd overlap vs2
++	viota.m v0, v4, v0.t	# vd overlap vm
++
++# Vector Element Index Instruction
++
++	vid.v v0, v0.t		# vd overlap vm
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+new file mode 100644
+index 0000000000..ebdd2b1051
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32ifv0p10
++#source: vector-insns-fail-permutation.s
++#error_output: vector-insns-fail-permutation.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+new file mode 100644
+index 0000000000..c208f5710f
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
+@@ -0,0 +1,31 @@
++.*: Assembler messages:
++.*Error: illegal operands `vslideup.vx v4,v4,a1'
++.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vslideup.vi v4,v4,31'
++.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vslide1up.vx v4,v4,a1'
++.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
++.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
++.*Error: illegal operands `vrgather.vv v4,v4,v8'
++.*Error: illegal operands `vrgather.vv v8,v4,v8'
++.*Error: illegal operands `vrgather.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vrgather.vx v4,v4,a1'
++.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
++.*Error: illegal operands `vrgather.vi v4,v4,31'
++.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
++.*Error: illegal operands `vrgatherei16.vv v4,v4,v8'
++.*Error: illegal operands `vrgatherei16.vv v8,v4,v8'
++.*Error: illegal operands `vrgatherei16.vv v0,v4,v8,v0.t'
++.*Error: illegal operands `vcompress.vm v4,v4,v8'
++.*Error: illegal operands `vcompress.vm v8,v4,v8'
++.*Error: illegal operands `vmv2r.v v30,v31'
++.*Error: illegal operands `vmv2r.v v31,v30'
++.*Error: illegal operands `vmv4r.v v28,v30'
++.*Error: illegal operands `vmv4r.v v30,v28'
++.*Error: illegal operands `vmv8r.v v24,v26'
++.*Error: illegal operands `vmv8r.v v26,v24'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+new file mode 100644
+index 0000000000..85116457ff
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
+@@ -0,0 +1,56 @@
++# Vector Slideup Instructions
++
++	vslideup.vx v4, v4, a1			# vd overlap vs2
++	vslideup.vx v0, v4, a1, v0.t		# vd overlap vm
++	vslideup.vi v4, v4, 31			# vd overlap vs2
++	vslideup.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vslidedown.vx v4, v4, a1		# OK
++	vslidedown.vx v0, v4, a1, v0.t		# vd overlap vm
++	vslidedown.vi v4, v4, 31		# OK
++	vslidedown.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vslide1up.vx v4, v4, a1			# vd overlap vs2
++	vslide1up.vx v0, v4, a1, v0.t		# vd overlap vm
++	vfslide1up.vf v4, v4, fa1		# vd overlap vs2
++	vfslide1up.vf v0, v4, fa1, v0.t		# vd overlap vm
++
++	vslide1down.vx v4, v4, a1		# OK
++	vslide1down.vx v0, v4, a1, v0.t		# vd overlap vm
++	vfslide1down.vf v4, v4, fa1		# OK
++	vfslide1down.vf v0, v4, fa1, v0.t	# vd overlap vm
++
++# Vector Register Gather Instructions
++
++	vrgather.vv v4, v4, v8			# vd overlap vs2
++	vrgather.vv v8, v4, v8			# vd overlap vs1
++	vrgather.vv v0, v4, v8, v0.t		# vd overlap vm
++	vrgather.vx v4, v4, a1			# vd overlap vs2
++	vrgather.vx v0, v4, a1, v0.t		# vd overlap vm
++	vrgather.vi v4, v4, 31			# vd overlap vs2
++	vrgather.vi v0, v4, 31, v0.t		# vd overlap vm
++
++	vrgatherei16.vv v4, v4, v8		# vd overlap vs2
++	vrgatherei16.vv v8, v4, v8		# vd overlap vs1
++	vrgatherei16.vv v0, v4, v8, v0.t	# vd overlap vm
++
++# Vector Compress Instruction
++
++	vcompress.vm v4, v4, v8			# vd overlap vs2
++	vcompress.vm v8, v4, v8			# vd overlap vs1
++
++# Whole Vector Register Move
++
++	vmv1r.v v31, v31			# OK, HINT
++
++	vmv2r.v v30, v30			# OK, HINT
++	vmv2r.v v30, v31			# vs2 must be aligned to 2
++	vmv2r.v v31, v30			# vd must be aligned to 2
++
++	vmv4r.v v28, v28			# OK, HINT
++	vmv4r.v v28, v30			# vs2 must be aligned to 4
++	vmv4r.v v30, v28			# vd must be aligned to 4
++
++	vmv8r.v v24, v24			# OK, HINT
++	vmv8r.v v24, v26			# vs2 must be aligned to 8
++	vmv8r.v v26, v24			# vd must be aligned to 8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
+new file mode 100644
+index 0000000000..cca6928e7d
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iv0p10 
++#source: vector-insns-fail-unsupport.s
++#error_output: vector-insns-fail-unsupport.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+new file mode 100644
+index 0000000000..2b726b0268
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
+@@ -0,0 +1,1454 @@
++.*: Assembler messages:
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0x3ff'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e16,m2'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,m8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m1'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,mf2'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,mf4'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,mf8'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ma'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,mu'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,ma'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,ma'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,mu'
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,mu'
++.*: Error: unrecognized opcode `vle1.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle1.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vse1.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vse1.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vle64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e8.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e16.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e32.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1'
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12'
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t'
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
++.*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re8.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re16.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re16.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re32.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re32.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl2re64.v v2,\(a0\)'
++.*: Error: unrecognized opcode `vl2re64.v v2,0\(a0\)'
++.*: Error: unrecognized opcode `vl4r.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4r.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re8.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re8.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re16.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re16.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re32.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re32.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl4re64.v v4,\(a0\)'
++.*: Error: unrecognized opcode `vl4re64.v v4,0\(a0\)'
++.*: Error: unrecognized opcode `vl8r.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8r.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re8.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re8.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re16.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re16.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re32.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
++.*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
++.*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
++.*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
++.*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
++.*: Error: unrecognized opcode `vs4r.v v4,0\(a1\)'
++.*: Error: unrecognized opcode `vs8r.v v8,\(a1\)'
++.*: Error: unrecognized opcode `vs8r.v v8,0\(a1\)'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4'
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4,v0.t'
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8'
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8'
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31'
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31'
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31'
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8'
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8'
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16'
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15,v0.t'
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16,v0.t'
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16'
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15,v0.t'
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16,v0.t'
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31'
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31'
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31'
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1,v0.t'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1,v0.t'
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31,v0.t'
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2'
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2,v0.t'
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8'
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8'
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8,v0.t'
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8,v0.t'
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8'
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8'
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8'
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrece7.v v4,v8'
++.*: Error: unrecognized opcode `vfrece7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfrec7.v v4,v8'
++.*: Error: unrecognized opcode `vfrec7.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfclass.v v4,v8'
++.*: Error: unrecognized opcode `vfclass.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8'
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8'
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8'
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8,v0.t'
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8'
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8,v0.t'
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12'
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vmsbf.m v4,v8'
++.*: Error: unrecognized opcode `vmsif.m v4,v8'
++.*: Error: unrecognized opcode `vmsof.m v4,v8'
++.*: Error: unrecognized opcode `viota.m v4,v8'
++.*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
++.*: Error: unrecognized opcode `vmv2r.v v2,v4'
++.*: Error: unrecognized opcode `vmv4r.v v4,v8'
++.*: Error: unrecognized opcode `vmv8r.v v0,v8'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+new file mode 100644
+index 0000000000..0112d0bce7
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
+@@ -0,0 +1,1663 @@
++	
++	vsetivli a0, 0xb, 0
++	vsetivli a0, 0xb, 0x3ff
++	vsetivli a0, 0xb, e16, m2
++	vsetivli a0, 0xb, e256, m8
++	vsetivli a0, 0xb, e512, m8
++	vsetivli a0, 0xb, e1024, m8
++	vsetivli a0, 0xb, e1024, m1
++	vsetivli a0, 0xb, e1024, mf2
++	vsetivli a0, 0xb, e512, mf4
++	vsetivli a0, 0xb, e256, mf8
++	vsetivli a0, 0xb, e256, m2, ta
++	vsetivli a0, 0xb, e256, m2, ma
++	vsetivli a0, 0xb, e256, m2, tu
++	vsetivli a0, 0xb, e256, m2, mu
++	vsetivli a0, 0xb, e256, m2, ta, ma
++	vsetivli a0, 0xb, e256, m2, tu, ma
++	vsetivli a0, 0xb, e256, m2, ta, mu
++	vsetivli a0, 0xb, e256, m2, tu, mu
++
++	vle1.v v4, (a0)
++	vle1.v v4, 0(a0)
++	vse1.v v4, (a0)
++	vse1.v v4, 0(a0)
++
++	
++	vluxei8.v v4, (a0), v12
++	vluxei8.v v4, 0(a0), v12
++	vluxei8.v v4, (a0), v12, v0.t
++	vsuxei8.v v4, (a0), v12
++	vsuxei8.v v4, 0(a0), v12
++	vsuxei8.v v4, (a0), v12, v0.t
++
++	
++	vluxei16.v v4, (a0), v12
++	vluxei16.v v4, 0(a0), v12
++	vluxei16.v v4, (a0), v12, v0.t
++	vsuxei16.v v4, (a0), v12
++	vsuxei16.v v4, 0(a0), v12
++	vsuxei16.v v4, (a0), v12, v0.t
++
++	
++	vluxei32.v v4, (a0), v12
++	vluxei32.v v4, 0(a0), v12
++	vluxei32.v v4, (a0), v12, v0.t
++	vsuxei32.v v4, (a0), v12
++	vsuxei32.v v4, 0(a0), v12
++	vsuxei32.v v4, (a0), v12, v0.t
++
++	
++	vluxei64.v v4, (a0), v12
++	vluxei64.v v4, 0(a0), v12
++	vluxei64.v v4, (a0), v12, v0.t
++	vsuxei64.v v4, (a0), v12
++	vsuxei64.v v4, 0(a0), v12
++	vsuxei64.v v4, (a0), v12, v0.t
++
++	vle8ff.v v4, (a0)
++	vle8ff.v v4, 0(a0)
++	vle8ff.v v4, (a0), v0.t
++
++	vle16ff.v v4, (a0)
++	vle16ff.v v4, 0(a0)
++	vle16ff.v v4, (a0), v0.t
++
++	vle32ff.v v4, (a0)
++	vle32ff.v v4, 0(a0)
++	vle32ff.v v4, (a0), v0.t
++
++	vle64ff.v v4, (a0)
++	vle64ff.v v4, 0(a0)
++	vle64ff.v v4, (a0), v0.t
++
++	vlseg2e8.v v4, (a0)
++	vlseg2e8.v v4, 0(a0)
++	vlseg2e8.v v4, (a0), v0.t
++	vsseg2e8.v v4, (a0)
++	vsseg2e8.v v4, 0(a0)
++	vsseg2e8.v v4, (a0), v0.t
++
++	vlseg3e8.v v4, (a0)
++	vlseg3e8.v v4, 0(a0)
++	vlseg3e8.v v4, (a0), v0.t
++	vsseg3e8.v v4, (a0)
++	vsseg3e8.v v4, 0(a0)
++	vsseg3e8.v v4, (a0), v0.t
++
++	vlseg4e8.v v4, (a0)
++	vlseg4e8.v v4, 0(a0)
++	vlseg4e8.v v4, (a0), v0.t
++	vsseg4e8.v v4, (a0)
++	vsseg4e8.v v4, 0(a0)
++	vsseg4e8.v v4, (a0), v0.t
++
++	vlseg5e8.v v4, (a0)
++	vlseg5e8.v v4, 0(a0)
++	vlseg5e8.v v4, (a0), v0.t
++	vsseg5e8.v v4, (a0)
++	vsseg5e8.v v4, 0(a0)
++	vsseg5e8.v v4, (a0), v0.t
++
++	vlseg6e8.v v4, (a0)
++	vlseg6e8.v v4, 0(a0)
++	vlseg6e8.v v4, (a0), v0.t
++	vsseg6e8.v v4, (a0)
++	vsseg6e8.v v4, 0(a0)
++	vsseg6e8.v v4, (a0), v0.t
++
++	vlseg7e8.v v4, (a0)
++	vlseg7e8.v v4, 0(a0)
++	vlseg7e8.v v4, (a0), v0.t
++	vsseg7e8.v v4, (a0)
++	vsseg7e8.v v4, 0(a0)
++	vsseg7e8.v v4, (a0), v0.t
++
++	vlseg8e8.v v4, (a0)
++	vlseg8e8.v v4, 0(a0)
++	vlseg8e8.v v4, (a0), v0.t
++	vsseg8e8.v v4, (a0)
++	vsseg8e8.v v4, 0(a0)
++	vsseg8e8.v v4, (a0), v0.t
++
++	vlseg2e16.v v4, (a0)
++	vlseg2e16.v v4, 0(a0)
++	vlseg2e16.v v4, (a0), v0.t
++	vsseg2e16.v v4, (a0)
++	vsseg2e16.v v4, 0(a0)
++	vsseg2e16.v v4, (a0), v0.t
++
++	vlseg3e16.v v4, (a0)
++	vlseg3e16.v v4, 0(a0)
++	vlseg3e16.v v4, (a0), v0.t
++	vsseg3e16.v v4, (a0)
++	vsseg3e16.v v4, 0(a0)
++	vsseg3e16.v v4, (a0), v0.t
++
++	vlseg4e16.v v4, (a0)
++	vlseg4e16.v v4, 0(a0)
++	vlseg4e16.v v4, (a0), v0.t
++	vsseg4e16.v v4, (a0)
++	vsseg4e16.v v4, 0(a0)
++	vsseg4e16.v v4, (a0), v0.t
++
++	vlseg5e16.v v4, (a0)
++	vlseg5e16.v v4, 0(a0)
++	vlseg5e16.v v4, (a0), v0.t
++	vsseg5e16.v v4, (a0)
++	vsseg5e16.v v4, 0(a0)
++	vsseg5e16.v v4, (a0), v0.t
++
++	vlseg6e16.v v4, (a0)
++	vlseg6e16.v v4, 0(a0)
++	vlseg6e16.v v4, (a0), v0.t
++	vsseg6e16.v v4, (a0)
++	vsseg6e16.v v4, 0(a0)
++	vsseg6e16.v v4, (a0), v0.t
++
++	vlseg7e16.v v4, (a0)
++	vlseg7e16.v v4, 0(a0)
++	vlseg7e16.v v4, (a0), v0.t
++	vsseg7e16.v v4, (a0)
++	vsseg7e16.v v4, 0(a0)
++	vsseg7e16.v v4, (a0), v0.t
++
++	vlseg8e16.v v4, (a0)
++	vlseg8e16.v v4, 0(a0)
++	vlseg8e16.v v4, (a0), v0.t
++	vsseg8e16.v v4, (a0)
++	vsseg8e16.v v4, 0(a0)
++	vsseg8e16.v v4, (a0), v0.t
++
++	vlseg2e32.v v4, (a0)
++	vlseg2e32.v v4, 0(a0)
++	vlseg2e32.v v4, (a0), v0.t
++	vsseg2e32.v v4, (a0)
++	vsseg2e32.v v4, 0(a0)
++	vsseg2e32.v v4, (a0), v0.t
++
++	vlseg3e32.v v4, (a0)
++	vlseg3e32.v v4, 0(a0)
++	vlseg3e32.v v4, (a0), v0.t
++	vsseg3e32.v v4, (a0)
++	vsseg3e32.v v4, 0(a0)
++	vsseg3e32.v v4, (a0), v0.t
++
++	vlseg4e32.v v4, (a0)
++	vlseg4e32.v v4, 0(a0)
++	vlseg4e32.v v4, (a0), v0.t
++	vsseg4e32.v v4, (a0)
++	vsseg4e32.v v4, 0(a0)
++	vsseg4e32.v v4, (a0), v0.t
++
++	vlseg5e32.v v4, (a0)
++	vlseg5e32.v v4, 0(a0)
++	vlseg5e32.v v4, (a0), v0.t
++	vsseg5e32.v v4, (a0)
++	vsseg5e32.v v4, 0(a0)
++	vsseg5e32.v v4, (a0), v0.t
++
++	vlseg6e32.v v4, (a0)
++	vlseg6e32.v v4, 0(a0)
++	vlseg6e32.v v4, (a0), v0.t
++	vsseg6e32.v v4, (a0)
++	vsseg6e32.v v4, 0(a0)
++	vsseg6e32.v v4, (a0), v0.t
++
++	vlseg7e32.v v4, (a0)
++	vlseg7e32.v v4, 0(a0)
++	vlseg7e32.v v4, (a0), v0.t
++	vsseg7e32.v v4, (a0)
++	vsseg7e32.v v4, 0(a0)
++	vsseg7e32.v v4, (a0), v0.t
++
++	vlseg8e32.v v4, (a0)
++	vlseg8e32.v v4, 0(a0)
++	vlseg8e32.v v4, (a0), v0.t
++	vsseg8e32.v v4, (a0)
++	vsseg8e32.v v4, 0(a0)
++	vsseg8e32.v v4, (a0), v0.t
++
++	vlseg2e64.v v4, (a0)
++	vlseg2e64.v v4, 0(a0)
++	vlseg2e64.v v4, (a0), v0.t
++	vsseg2e64.v v4, (a0)
++	vsseg2e64.v v4, 0(a0)
++	vsseg2e64.v v4, (a0), v0.t
++
++	vlseg3e64.v v4, (a0)
++	vlseg3e64.v v4, 0(a0)
++	vlseg3e64.v v4, (a0), v0.t
++	vsseg3e64.v v4, (a0)
++	vsseg3e64.v v4, 0(a0)
++	vsseg3e64.v v4, (a0), v0.t
++
++	vlseg4e64.v v4, (a0)
++	vlseg4e64.v v4, 0(a0)
++	vlseg4e64.v v4, (a0), v0.t
++	vsseg4e64.v v4, (a0)
++	vsseg4e64.v v4, 0(a0)
++	vsseg4e64.v v4, (a0), v0.t
++
++	vlseg5e64.v v4, (a0)
++	vlseg5e64.v v4, 0(a0)
++	vlseg5e64.v v4, (a0), v0.t
++	vsseg5e64.v v4, (a0)
++	vsseg5e64.v v4, 0(a0)
++	vsseg5e64.v v4, (a0), v0.t
++
++	vlseg6e64.v v4, (a0)
++	vlseg6e64.v v4, 0(a0)
++	vlseg6e64.v v4, (a0), v0.t
++	vsseg6e64.v v4, (a0)
++	vsseg6e64.v v4, 0(a0)
++	vsseg6e64.v v4, (a0), v0.t
++
++	vlseg7e64.v v4, (a0)
++	vlseg7e64.v v4, 0(a0)
++	vlseg7e64.v v4, (a0), v0.t
++	vsseg7e64.v v4, (a0)
++	vsseg7e64.v v4, 0(a0)
++	vsseg7e64.v v4, (a0), v0.t
++
++	vlseg8e64.v v4, (a0)
++	vlseg8e64.v v4, 0(a0)
++	vlseg8e64.v v4, (a0), v0.t
++	vsseg8e64.v v4, (a0)
++	vsseg8e64.v v4, 0(a0)
++	vsseg8e64.v v4, (a0), v0.t
++
++	vlsseg2e8.v v4, (a0), a1
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++	vluxseg3ei8.v v4, (a0), v12
++	vluxseg3ei8.v v4, 0(a0), v12
++	vluxseg3ei8.v v4, (a0), v12, v0.t
++	vsuxseg3ei8.v v4, (a0), v12
++	vsuxseg3ei8.v v4, 0(a0), v12
++	vsuxseg3ei8.v v4, (a0), v12, v0.t
++
++	vluxseg4ei8.v v4, (a0), v12
++	vluxseg4ei8.v v4, 0(a0), v12
++	vluxseg4ei8.v v4, (a0), v12, v0.t
++	vsuxseg4ei8.v v4, (a0), v12
++	vsuxseg4ei8.v v4, 0(a0), v12
++	vsuxseg4ei8.v v4, (a0), v12, v0.t
++
++	vluxseg5ei8.v v4, (a0), v12
++	vluxseg5ei8.v v4, 0(a0), v12
++	vluxseg5ei8.v v4, (a0), v12, v0.t
++	vsuxseg5ei8.v v4, (a0), v12
++	vsuxseg5ei8.v v4, 0(a0), v12
++	vsuxseg5ei8.v v4, (a0), v12, v0.t
++
++	vluxseg6ei8.v v4, (a0), v12
++	vluxseg6ei8.v v4, 0(a0), v12
++	vluxseg6ei8.v v4, (a0), v12, v0.t
++	vsuxseg6ei8.v v4, (a0), v12
++	vsuxseg6ei8.v v4, 0(a0), v12
++	vsuxseg6ei8.v v4, (a0), v12, v0.t
++
++	vluxseg7ei8.v v4, (a0), v12
++	vluxseg7ei8.v v4, 0(a0), v12
++	vluxseg7ei8.v v4, (a0), v12, v0.t
++	vsuxseg7ei8.v v4, (a0), v12
++	vsuxseg7ei8.v v4, 0(a0), v12
++	vsuxseg7ei8.v v4, (a0), v12, v0.t
++
++	vluxseg8ei8.v v4, (a0), v12
++	vluxseg8ei8.v v4, 0(a0), v12
++	vluxseg8ei8.v v4, (a0), v12, v0.t
++	vsuxseg8ei8.v v4, (a0), v12
++	vsuxseg8ei8.v v4, 0(a0), v12
++	vsuxseg8ei8.v v4, (a0), v12, v0.t
++
++	vluxseg2ei16.v v4, (a0), v12
++	vluxseg2ei16.v v4, 0(a0), v12
++	vluxseg2ei16.v v4, (a0), v12, v0.t
++	vsuxseg2ei16.v v4, (a0), v12
++	vsuxseg2ei16.v v4, 0(a0), v12
++	vsuxseg2ei16.v v4, (a0), v12, v0.t
++
++	vluxseg3ei16.v v4, (a0), v12
++	vluxseg3ei16.v v4, 0(a0), v12
++	vluxseg3ei16.v v4, (a0), v12, v0.t
++	vsuxseg3ei16.v v4, (a0), v12
++	vsuxseg3ei16.v v4, 0(a0), v12
++	vsuxseg3ei16.v v4, (a0), v12, v0.t
++
++	vluxseg4ei16.v v4, (a0), v12
++	vluxseg4ei16.v v4, 0(a0), v12
++	vluxseg4ei16.v v4, (a0), v12, v0.t
++	vsuxseg4ei16.v v4, (a0), v12
++	vsuxseg4ei16.v v4, 0(a0), v12
++	vsuxseg4ei16.v v4, (a0), v12, v0.t
++
++	vluxseg5ei16.v v4, (a0), v12
++	vluxseg5ei16.v v4, 0(a0), v12
++	vluxseg5ei16.v v4, (a0), v12, v0.t
++	vsuxseg5ei16.v v4, (a0), v12
++	vsuxseg5ei16.v v4, 0(a0), v12
++	vsuxseg5ei16.v v4, (a0), v12, v0.t
++
++	vluxseg6ei16.v v4, (a0), v12
++	vluxseg6ei16.v v4, 0(a0), v12
++	vluxseg6ei16.v v4, (a0), v12, v0.t
++	vsuxseg6ei16.v v4, (a0), v12
++	vsuxseg6ei16.v v4, 0(a0), v12
++	vsuxseg6ei16.v v4, (a0), v12, v0.t
++
++	vluxseg7ei16.v v4, (a0), v12
++	vluxseg7ei16.v v4, 0(a0), v12
++	vluxseg7ei16.v v4, (a0), v12, v0.t
++	vsuxseg7ei16.v v4, (a0), v12
++	vsuxseg7ei16.v v4, 0(a0), v12
++	vsuxseg7ei16.v v4, (a0), v12, v0.t
++
++	vluxseg8ei16.v v4, (a0), v12
++	vluxseg8ei16.v v4, 0(a0), v12
++	vluxseg8ei16.v v4, (a0), v12, v0.t
++	vsuxseg8ei16.v v4, (a0), v12
++	vsuxseg8ei16.v v4, 0(a0), v12
++	vsuxseg8ei16.v v4, (a0), v12, v0.t
++
++	vluxseg2ei32.v v4, (a0), v12
++	vluxseg2ei32.v v4, 0(a0), v12
++	vluxseg2ei32.v v4, (a0), v12, v0.t
++	vsuxseg2ei32.v v4, (a0), v12
++	vsuxseg2ei32.v v4, 0(a0), v12
++	vsuxseg2ei32.v v4, (a0), v12, v0.t
++
++	vluxseg3ei32.v v4, (a0), v12
++	vluxseg3ei32.v v4, 0(a0), v12
++	vluxseg3ei32.v v4, (a0), v12, v0.t
++	vsuxseg3ei32.v v4, (a0), v12
++	vsuxseg3ei32.v v4, 0(a0), v12
++	vsuxseg3ei32.v v4, (a0), v12, v0.t
++
++	vluxseg4ei32.v v4, (a0), v12
++	vluxseg4ei32.v v4, 0(a0), v12
++	vluxseg4ei32.v v4, (a0), v12, v0.t
++	vsuxseg4ei32.v v4, (a0), v12
++	vsuxseg4ei32.v v4, 0(a0), v12
++	vsuxseg4ei32.v v4, (a0), v12, v0.t
++
++	vluxseg5ei32.v v4, (a0), v12
++	vluxseg5ei32.v v4, 0(a0), v12
++	vluxseg5ei32.v v4, (a0), v12, v0.t
++	vsuxseg5ei32.v v4, (a0), v12
++	vsuxseg5ei32.v v4, 0(a0), v12
++	vsuxseg5ei32.v v4, (a0), v12, v0.t
++
++	vluxseg6ei32.v v4, (a0), v12
++	vluxseg6ei32.v v4, 0(a0), v12
++	vluxseg6ei32.v v4, (a0), v12, v0.t
++	vsuxseg6ei32.v v4, (a0), v12
++	vsuxseg6ei32.v v4, 0(a0), v12
++	vsuxseg6ei32.v v4, (a0), v12, v0.t
++
++	vluxseg7ei32.v v4, (a0), v12
++	vluxseg7ei32.v v4, 0(a0), v12
++	vluxseg7ei32.v v4, (a0), v12, v0.t
++	vsuxseg7ei32.v v4, (a0), v12
++	vsuxseg7ei32.v v4, 0(a0), v12
++	vsuxseg7ei32.v v4, (a0), v12, v0.t
++
++	vluxseg8ei32.v v4, (a0), v12
++	vluxseg8ei32.v v4, 0(a0), v12
++	vluxseg8ei32.v v4, (a0), v12, v0.t
++	vsuxseg8ei32.v v4, (a0), v12
++	vsuxseg8ei32.v v4, 0(a0), v12
++	vsuxseg8ei32.v v4, (a0), v12, v0.t
++
++	vluxseg2ei64.v v4, (a0), v12
++	vluxseg2ei64.v v4, 0(a0), v12
++	vluxseg2ei64.v v4, (a0), v12, v0.t
++	vsuxseg2ei64.v v4, (a0), v12
++	vsuxseg2ei64.v v4, 0(a0), v12
++	vsuxseg2ei64.v v4, (a0), v12, v0.t
++
++	vluxseg3ei64.v v4, (a0), v12
++	vluxseg3ei64.v v4, 0(a0), v12
++	vluxseg3ei64.v v4, (a0), v12, v0.t
++	vsuxseg3ei64.v v4, (a0), v12
++	vsuxseg3ei64.v v4, 0(a0), v12
++	vsuxseg3ei64.v v4, (a0), v12, v0.t
++
++	vluxseg4ei64.v v4, (a0), v12
++	vluxseg4ei64.v v4, 0(a0), v12
++	vluxseg4ei64.v v4, (a0), v12, v0.t
++	vsuxseg4ei64.v v4, (a0), v12
++	vsuxseg4ei64.v v4, 0(a0), v12
++	vsuxseg4ei64.v v4, (a0), v12, v0.t
++
++	vluxseg5ei64.v v4, (a0), v12
++	vluxseg5ei64.v v4, 0(a0), v12
++	vluxseg5ei64.v v4, (a0), v12, v0.t
++	vsuxseg5ei64.v v4, (a0), v12
++	vsuxseg5ei64.v v4, 0(a0), v12
++	vsuxseg5ei64.v v4, (a0), v12, v0.t
++
++	vluxseg6ei64.v v4, (a0), v12
++	vluxseg6ei64.v v4, 0(a0), v12
++	vluxseg6ei64.v v4, (a0), v12, v0.t
++	vsuxseg6ei64.v v4, (a0), v12
++	vsuxseg6ei64.v v4, 0(a0), v12
++	vsuxseg6ei64.v v4, (a0), v12, v0.t
++
++	vluxseg7ei64.v v4, (a0), v12
++	vluxseg7ei64.v v4, 0(a0), v12
++	vluxseg7ei64.v v4, (a0), v12, v0.t
++	vsuxseg7ei64.v v4, (a0), v12
++	vsuxseg7ei64.v v4, 0(a0), v12
++	vsuxseg7ei64.v v4, (a0), v12, v0.t
++
++	vluxseg8ei64.v v4, (a0), v12
++	vluxseg8ei64.v v4, 0(a0), v12
++	vluxseg8ei64.v v4, (a0), v12, v0.t
++	vsuxseg8ei64.v v4, (a0), v12
++	vsuxseg8ei64.v v4, 0(a0), v12
++	vsuxseg8ei64.v v4, (a0), v12, v0.t
++
++	vlseg2e8ff.v v4, (a0)
++	vlseg2e8ff.v v4, 0(a0)
++	vlseg2e8ff.v v4, (a0), v0.t
++
++	vlseg3e8ff.v v4, (a0)
++	vlseg3e8ff.v v4, 0(a0)
++	vlseg3e8ff.v v4, (a0), v0.t
++
++	vlseg4e8ff.v v4, (a0)
++	vlseg4e8ff.v v4, 0(a0)
++	vlseg4e8ff.v v4, (a0), v0.t
++
++	vlseg5e8ff.v v4, (a0)
++	vlseg5e8ff.v v4, 0(a0)
++	vlseg5e8ff.v v4, (a0), v0.t
++
++	vlseg6e8ff.v v4, (a0)
++	vlseg6e8ff.v v4, 0(a0)
++	vlseg6e8ff.v v4, (a0), v0.t
++
++	vlseg7e8ff.v v4, (a0)
++	vlseg7e8ff.v v4, 0(a0)
++	vlseg7e8ff.v v4, (a0), v0.t
++
++	vlseg8e8ff.v v4, (a0)
++	vlseg8e8ff.v v4, 0(a0)
++	vlseg8e8ff.v v4, (a0), v0.t
++
++	vlseg2e16ff.v v4, (a0)
++	vlseg2e16ff.v v4, 0(a0)
++	vlseg2e16ff.v v4, (a0), v0.t
++
++	vlseg3e16ff.v v4, (a0)
++	vlseg3e16ff.v v4, 0(a0)
++	vlseg3e16ff.v v4, (a0), v0.t
++
++	vlseg4e16ff.v v4, (a0)
++	vlseg4e16ff.v v4, 0(a0)
++	vlseg4e16ff.v v4, (a0), v0.t
++
++	vlseg5e16ff.v v4, (a0)
++	vlseg5e16ff.v v4, 0(a0)
++	vlseg5e16ff.v v4, (a0), v0.t
++
++	vlseg6e16ff.v v4, (a0)
++	vlseg6e16ff.v v4, 0(a0)
++	vlseg6e16ff.v v4, (a0), v0.t
++
++	vlseg7e16ff.v v4, (a0)
++	vlseg7e16ff.v v4, 0(a0)
++	vlseg7e16ff.v v4, (a0), v0.t
++
++	vlseg8e16ff.v v4, (a0)
++	vlseg8e16ff.v v4, 0(a0)
++	vlseg8e16ff.v v4, (a0), v0.t
++
++	vlseg2e32ff.v v4, (a0)
++	vlseg2e32ff.v v4, 0(a0)
++	vlseg2e32ff.v v4, (a0), v0.t
++
++	vlseg3e32ff.v v4, (a0)
++	vlseg3e32ff.v v4, 0(a0)
++	vlseg3e32ff.v v4, (a0), v0.t
++
++	vlseg4e32ff.v v4, (a0)
++	vlseg4e32ff.v v4, 0(a0)
++	vlseg4e32ff.v v4, (a0), v0.t
++
++	vlseg5e32ff.v v4, (a0)
++	vlseg5e32ff.v v4, 0(a0)
++	vlseg5e32ff.v v4, (a0), v0.t
++
++	vlseg6e32ff.v v4, (a0)
++	vlseg6e32ff.v v4, 0(a0)
++	vlseg6e32ff.v v4, (a0), v0.t
++
++	vlseg7e32ff.v v4, (a0)
++	vlseg7e32ff.v v4, 0(a0)
++	vlseg7e32ff.v v4, (a0), v0.t
++
++	vlseg8e32ff.v v4, (a0)
++	vlseg8e32ff.v v4, 0(a0)
++	vlseg8e32ff.v v4, (a0), v0.t
++
++	vlseg2e64ff.v v4, (a0)
++	vlseg2e64ff.v v4, 0(a0)
++	vlseg2e64ff.v v4, (a0), v0.t
++
++	vlseg3e64ff.v v4, (a0)
++	vlseg3e64ff.v v4, 0(a0)
++	vlseg3e64ff.v v4, (a0), v0.t
++
++	vlseg4e64ff.v v4, (a0)
++	vlseg4e64ff.v v4, 0(a0)
++	vlseg4e64ff.v v4, (a0), v0.t
++
++	vlseg5e64ff.v v4, (a0)
++	vlseg5e64ff.v v4, 0(a0)
++	vlseg5e64ff.v v4, (a0), v0.t
++
++	vlseg6e64ff.v v4, (a0)
++	vlseg6e64ff.v v4, 0(a0)
++	vlseg6e64ff.v v4, (a0), v0.t
++
++	vlseg7e64ff.v v4, (a0)
++	vlseg7e64ff.v v4, 0(a0)
++	vlseg7e64ff.v v4, (a0), v0.t
++
++	vlseg8e64ff.v v4, (a0)
++	vlseg8e64ff.v v4, 0(a0)
++	vlseg8e64ff.v v4, (a0), v0.t
++
++	vl2r.v v2, (a0)
++	vl2r.v v2, 0(a0)
++	vl2re8.v v2, (a0)
++	vl2re8.v v2, 0(a0)
++	vl2re16.v v2, (a0)
++	vl2re16.v v2, 0(a0)
++	vl2re32.v v2, (a0)
++	vl2re32.v v2, 0(a0)
++	vl2re64.v v2, (a0)
++	vl2re64.v v2, 0(a0)
++
++	vl4r.v v4, (a0)
++	vl4r.v v4, 0(a0)
++	vl4re8.v v4, (a0)
++	vl4re8.v v4, 0(a0)
++	vl4re16.v v4, (a0)
++	vl4re16.v v4, 0(a0)
++	vl4re32.v v4, (a0)
++	vl4re32.v v4, 0(a0)
++	vl4re64.v v4, (a0)
++	vl4re64.v v4, 0(a0)
++
++	vl8r.v v8, (a0)
++	vl8r.v v8, 0(a0)
++	vl8re8.v v8, (a0)
++	vl8re8.v v8, 0(a0)
++	vl8re16.v v8, (a0)
++	vl8re16.v v8, 0(a0)
++	vl8re32.v v8, (a0)
++	vl8re32.v v8, 0(a0)
++	vl8re64.v v8, (a0)
++	vl8re64.v v8, 0(a0)
++
++	vs2r.v v2, (a1)
++	vs2r.v v2, 0(a1)
++	vs4r.v v4, (a1)
++	vs4r.v v4, 0(a1)
++	vs8r.v v8, (a1)
++	vs8r.v v8, 0(a1)
++
++	vamoaddei8.v v4, (a1), v8, v4
++	vamoaddei8.v x0, (a1), v8, v4
++	vamoaddei8.v v4, (a1), v8, v4, v0.t
++	vamoaddei8.v x0, (a1), v8, v4, v0.t
++	vamoswapei8.v v4, (a1), v8, v4
++	vamoswapei8.v x0, (a1), v8, v4
++	vamoswapei8.v v4, (a1), v8, v4, v0.t
++	vamoswapei8.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, (a1), v8, v4
++	vamoxorei8.v x0, (a1), v8, v4
++	vamoxorei8.v v4, (a1), v8, v4, v0.t
++	vamoxorei8.v x0, (a1), v8, v4, v0.t
++	vamoandei8.v v4, (a1), v8, v4
++	vamoandei8.v x0, (a1), v8, v4
++	vamoandei8.v v4, (a1), v8, v4, v0.t
++	vamoandei8.v x0, (a1), v8, v4, v0.t
++	vamoorei8.v v4, (a1), v8, v4
++	vamoorei8.v x0, (a1), v8, v4
++	vamoorei8.v v4, (a1), v8, v4, v0.t
++	vamoorei8.v x0, (a1), v8, v4, v0.t
++
++	vamominei8.v v4, (a1), v8, v4
++	vamominei8.v x0, (a1), v8, v4
++	vamominei8.v v4, (a1), v8, v4, v0.t
++	vamominei8.v x0, (a1), v8, v4, v0.t
++	vamomaxei8.v v4, (a1), v8, v4
++	vamomaxei8.v x0, (a1), v8, v4
++	vamomaxei8.v v4, (a1), v8, v4, v0.t
++	vamomaxei8.v x0, (a1), v8, v4, v0.t
++	vamominuei8.v v4, (a1), v8, v4
++	vamominuei8.v x0, (a1), v8, v4
++	vamominuei8.v v4, (a1), v8, v4, v0.t
++	vamominuei8.v x0, (a1), v8, v4, v0.t
++	vamomaxuei8.v v4, (a1), v8, v4
++	vamomaxuei8.v x0, (a1), v8, v4
++	vamomaxuei8.v v4, (a1), v8, v4, v0.t
++	vamomaxuei8.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei8.v v4, 0(a1), v8, v4
++	vamoaddei8.v x0, 0(a1), v8, v4
++	vamoaddei8.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei8.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei8.v v4, 0(a1), v8, v4
++	vamoswapei8.v x0, 0(a1), v8, v4
++	vamoswapei8.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, 0(a1), v8, v4
++	vamoxorei8.v x0, 0(a1), v8, v4
++	vamoxorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei8.v x0, 0(a1), v8, v4, v0.t
++	vamoandei8.v v4, 0(a1), v8, v4
++	vamoandei8.v x0, 0(a1), v8, v4
++	vamoandei8.v v4, 0(a1), v8, v4, v0.t
++	vamoandei8.v x0, 0(a1), v8, v4, v0.t
++	vamoorei8.v v4, 0(a1), v8, v4
++	vamoorei8.v x0, 0(a1), v8, v4
++	vamoorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoorei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei8.v v4, 0(a1), v8, v4
++	vamominei8.v x0, 0(a1), v8, v4
++	vamominei8.v v4, 0(a1), v8, v4, v0.t
++	vamominei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei8.v v4, 0(a1), v8, v4
++	vamomaxei8.v x0, 0(a1), v8, v4
++	vamomaxei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei8.v x0, 0(a1), v8, v4, v0.t
++	vamominuei8.v v4, 0(a1), v8, v4
++	vamominuei8.v x0, 0(a1), v8, v4
++	vamominuei8.v v4, 0(a1), v8, v4, v0.t
++	vamominuei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v v4, 0(a1), v8, v4
++	vamomaxuei8.v x0, 0(a1), v8, v4
++	vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, (a1), v8, v4
++	vamoaddei16.v x0, (a1), v8, v4
++	vamoaddei16.v v4, (a1), v8, v4, v0.t
++	vamoaddei16.v x0, (a1), v8, v4, v0.t
++	vamoswapei16.v v4, (a1), v8, v4
++	vamoswapei16.v x0, (a1), v8, v4
++	vamoswapei16.v v4, (a1), v8, v4, v0.t
++	vamoswapei16.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, (a1), v8, v4
++	vamoxorei16.v x0, (a1), v8, v4
++	vamoxorei16.v v4, (a1), v8, v4, v0.t
++	vamoxorei16.v x0, (a1), v8, v4, v0.t
++	vamoandei16.v v4, (a1), v8, v4
++	vamoandei16.v x0, (a1), v8, v4
++	vamoandei16.v v4, (a1), v8, v4, v0.t
++	vamoandei16.v x0, (a1), v8, v4, v0.t
++	vamoorei16.v v4, (a1), v8, v4
++	vamoorei16.v x0, (a1), v8, v4
++	vamoorei16.v v4, (a1), v8, v4, v0.t
++	vamoorei16.v x0, (a1), v8, v4, v0.t
++
++	vamominei16.v v4, (a1), v8, v4
++	vamominei16.v x0, (a1), v8, v4
++	vamominei16.v v4, (a1), v8, v4, v0.t
++	vamominei16.v x0, (a1), v8, v4, v0.t
++	vamomaxei16.v v4, (a1), v8, v4
++	vamomaxei16.v x0, (a1), v8, v4
++	vamomaxei16.v v4, (a1), v8, v4, v0.t
++	vamomaxei16.v x0, (a1), v8, v4, v0.t
++	vamominuei16.v v4, (a1), v8, v4
++	vamominuei16.v x0, (a1), v8, v4
++	vamominuei16.v v4, (a1), v8, v4, v0.t
++	vamominuei16.v x0, (a1), v8, v4, v0.t
++	vamomaxuei16.v v4, (a1), v8, v4
++	vamomaxuei16.v x0, (a1), v8, v4
++	vamomaxuei16.v v4, (a1), v8, v4, v0.t
++	vamomaxuei16.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, 0(a1), v8, v4
++	vamoaddei16.v x0, 0(a1), v8, v4
++	vamoaddei16.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei16.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei16.v v4, 0(a1), v8, v4
++	vamoswapei16.v x0, 0(a1), v8, v4
++	vamoswapei16.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, 0(a1), v8, v4
++	vamoxorei16.v x0, 0(a1), v8, v4
++	vamoxorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei16.v x0, 0(a1), v8, v4, v0.t
++	vamoandei16.v v4, 0(a1), v8, v4
++	vamoandei16.v x0, 0(a1), v8, v4
++	vamoandei16.v v4, 0(a1), v8, v4, v0.t
++	vamoandei16.v x0, 0(a1), v8, v4, v0.t
++	vamoorei16.v v4, 0(a1), v8, v4
++	vamoorei16.v x0, 0(a1), v8, v4
++	vamoorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoorei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei16.v v4, 0(a1), v8, v4
++	vamominei16.v x0, 0(a1), v8, v4
++	vamominei16.v v4, 0(a1), v8, v4, v0.t
++	vamominei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei16.v v4, 0(a1), v8, v4
++	vamomaxei16.v x0, 0(a1), v8, v4
++	vamomaxei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei16.v x0, 0(a1), v8, v4, v0.t
++	vamominuei16.v v4, 0(a1), v8, v4
++	vamominuei16.v x0, 0(a1), v8, v4
++	vamominuei16.v v4, 0(a1), v8, v4, v0.t
++	vamominuei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v v4, 0(a1), v8, v4
++	vamomaxuei16.v x0, 0(a1), v8, v4
++	vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, (a1), v8, v4
++	vamoaddei32.v x0, (a1), v8, v4
++	vamoaddei32.v v4, (a1), v8, v4, v0.t
++	vamoaddei32.v x0, (a1), v8, v4, v0.t
++	vamoswapei32.v v4, (a1), v8, v4
++	vamoswapei32.v x0, (a1), v8, v4
++	vamoswapei32.v v4, (a1), v8, v4, v0.t
++	vamoswapei32.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, (a1), v8, v4
++	vamoxorei32.v x0, (a1), v8, v4
++	vamoxorei32.v v4, (a1), v8, v4, v0.t
++	vamoxorei32.v x0, (a1), v8, v4, v0.t
++	vamoandei32.v v4, (a1), v8, v4
++	vamoandei32.v x0, (a1), v8, v4
++	vamoandei32.v v4, (a1), v8, v4, v0.t
++	vamoandei32.v x0, (a1), v8, v4, v0.t
++	vamoorei32.v v4, (a1), v8, v4
++	vamoorei32.v x0, (a1), v8, v4
++	vamoorei32.v v4, (a1), v8, v4, v0.t
++	vamoorei32.v x0, (a1), v8, v4, v0.t
++
++	vamominei32.v v4, (a1), v8, v4
++	vamominei32.v x0, (a1), v8, v4
++	vamominei32.v v4, (a1), v8, v4, v0.t
++	vamominei32.v x0, (a1), v8, v4, v0.t
++	vamomaxei32.v v4, (a1), v8, v4
++	vamomaxei32.v x0, (a1), v8, v4
++	vamomaxei32.v v4, (a1), v8, v4, v0.t
++	vamomaxei32.v x0, (a1), v8, v4, v0.t
++	vamominuei32.v v4, (a1), v8, v4
++	vamominuei32.v x0, (a1), v8, v4
++	vamominuei32.v v4, (a1), v8, v4, v0.t
++	vamominuei32.v x0, (a1), v8, v4, v0.t
++	vamomaxuei32.v v4, (a1), v8, v4
++	vamomaxuei32.v x0, (a1), v8, v4
++	vamomaxuei32.v v4, (a1), v8, v4, v0.t
++	vamomaxuei32.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, 0(a1), v8, v4
++	vamoaddei32.v x0, 0(a1), v8, v4
++	vamoaddei32.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei32.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei32.v v4, 0(a1), v8, v4
++	vamoswapei32.v x0, 0(a1), v8, v4
++	vamoswapei32.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, 0(a1), v8, v4
++	vamoxorei32.v x0, 0(a1), v8, v4
++	vamoxorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei32.v x0, 0(a1), v8, v4, v0.t
++	vamoandei32.v v4, 0(a1), v8, v4
++	vamoandei32.v x0, 0(a1), v8, v4
++	vamoandei32.v v4, 0(a1), v8, v4, v0.t
++	vamoandei32.v x0, 0(a1), v8, v4, v0.t
++	vamoorei32.v v4, 0(a1), v8, v4
++	vamoorei32.v x0, 0(a1), v8, v4
++	vamoorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoorei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei32.v v4, 0(a1), v8, v4
++	vamominei32.v x0, 0(a1), v8, v4
++	vamominei32.v v4, 0(a1), v8, v4, v0.t
++	vamominei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei32.v v4, 0(a1), v8, v4
++	vamomaxei32.v x0, 0(a1), v8, v4
++	vamomaxei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei32.v x0, 0(a1), v8, v4, v0.t
++	vamominuei32.v v4, 0(a1), v8, v4
++	vamominuei32.v x0, 0(a1), v8, v4
++	vamominuei32.v v4, 0(a1), v8, v4, v0.t
++	vamominuei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v v4, 0(a1), v8, v4
++	vamomaxuei32.v x0, 0(a1), v8, v4
++	vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, (a1), v8, v4
++	vamoaddei64.v x0, (a1), v8, v4
++	vamoaddei64.v v4, (a1), v8, v4, v0.t
++	vamoaddei64.v x0, (a1), v8, v4, v0.t
++	vamoswapei64.v v4, (a1), v8, v4
++	vamoswapei64.v x0, (a1), v8, v4
++	vamoswapei64.v v4, (a1), v8, v4, v0.t
++	vamoswapei64.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, (a1), v8, v4
++	vamoxorei64.v x0, (a1), v8, v4
++	vamoxorei64.v v4, (a1), v8, v4, v0.t
++	vamoxorei64.v x0, (a1), v8, v4, v0.t
++	vamoandei64.v v4, (a1), v8, v4
++	vamoandei64.v x0, (a1), v8, v4
++	vamoandei64.v v4, (a1), v8, v4, v0.t
++	vamoandei64.v x0, (a1), v8, v4, v0.t
++	vamoorei64.v v4, (a1), v8, v4
++	vamoorei64.v x0, (a1), v8, v4
++	vamoorei64.v v4, (a1), v8, v4, v0.t
++	vamoorei64.v x0, (a1), v8, v4, v0.t
++
++	vamominei64.v v4, (a1), v8, v4
++	vamominei64.v x0, (a1), v8, v4
++	vamominei64.v v4, (a1), v8, v4, v0.t
++	vamominei64.v x0, (a1), v8, v4, v0.t
++	vamomaxei64.v v4, (a1), v8, v4
++	vamomaxei64.v x0, (a1), v8, v4
++	vamomaxei64.v v4, (a1), v8, v4, v0.t
++	vamomaxei64.v x0, (a1), v8, v4, v0.t
++	vamominuei64.v v4, (a1), v8, v4
++	vamominuei64.v x0, (a1), v8, v4
++	vamominuei64.v v4, (a1), v8, v4, v0.t
++	vamominuei64.v x0, (a1), v8, v4, v0.t
++	vamomaxuei64.v v4, (a1), v8, v4
++	vamomaxuei64.v x0, (a1), v8, v4
++	vamomaxuei64.v v4, (a1), v8, v4, v0.t
++	vamomaxuei64.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, 0(a1), v8, v4
++	vamoaddei64.v x0, 0(a1), v8, v4
++	vamoaddei64.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei64.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei64.v v4, 0(a1), v8, v4
++	vamoswapei64.v x0, 0(a1), v8, v4
++	vamoswapei64.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, 0(a1), v8, v4
++	vamoxorei64.v x0, 0(a1), v8, v4
++	vamoxorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei64.v x0, 0(a1), v8, v4, v0.t
++	vamoandei64.v v4, 0(a1), v8, v4
++	vamoandei64.v x0, 0(a1), v8, v4
++	vamoandei64.v v4, 0(a1), v8, v4, v0.t
++	vamoandei64.v x0, 0(a1), v8, v4, v0.t
++	vamoorei64.v v4, 0(a1), v8, v4
++	vamoorei64.v x0, 0(a1), v8, v4
++	vamoorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoorei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei64.v v4, 0(a1), v8, v4
++	vamominei64.v x0, 0(a1), v8, v4
++	vamominei64.v v4, 0(a1), v8, v4, v0.t
++	vamominei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei64.v v4, 0(a1), v8, v4
++	vamomaxei64.v x0, 0(a1), v8, v4
++	vamomaxei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei64.v x0, 0(a1), v8, v4, v0.t
++	vamominuei64.v v4, 0(a1), v8, v4
++	vamominuei64.v x0, 0(a1), v8, v4
++	vamominuei64.v v4, 0(a1), v8, v4, v0.t
++	vamominuei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v v4, 0(a1), v8, v4
++	vamomaxuei64.v x0, 0(a1), v8, v4
++	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
++	# Aliases
++	vwcvt.x.x.v v4, v8
++	vwcvtu.x.x.v v4, v8
++	vwcvt.x.x.v v4, v8, v0.t
++	vwcvtu.x.x.v v4, v8, v0.t
++
++	vwaddu.vv v4, v8, v12
++	vwaddu.vx v4, v8, a1
++	vwaddu.vv v4, v8, v12, v0.t
++	vwaddu.vx v4, v8, a1, v0.t
++	vwsubu.vv v4, v8, v12
++	vwsubu.vx v4, v8, a1
++	vwsubu.vv v4, v8, v12, v0.t
++	vwsubu.vx v4, v8, a1, v0.t
++	vwadd.vv v4, v8, v12
++	vwadd.vx v4, v8, a1
++	vwadd.vv v4, v8, v12, v0.t
++	vwadd.vx v4, v8, a1, v0.t
++	vwsub.vv v4, v8, v12
++	vwsub.vx v4, v8, a1
++	vwsub.vv v4, v8, v12, v0.t
++	vwsub.vx v4, v8, a1, v0.t
++	vwaddu.wv v4, v8, v12
++	vwaddu.wx v4, v8, a1
++	vwaddu.wv v4, v8, v12, v0.t
++	vwaddu.wx v4, v8, a1, v0.t
++	vwsubu.wv v4, v8, v12
++	vwsubu.wx v4, v8, a1
++	vwsubu.wv v4, v8, v12, v0.t
++	vwsubu.wx v4, v8, a1, v0.t
++	vwadd.wv v4, v8, v12
++	vwadd.wx v4, v8, a1
++	vwadd.wv v4, v8, v12, v0.t
++	vwadd.wx v4, v8, a1, v0.t
++	vwsub.wv v4, v8, v12
++	vwsub.wx v4, v8, a1
++	vwsub.wv v4, v8, v12, v0.t
++	vwsub.wx v4, v8, a1, v0.t
++
++	vsll.vv v4, v8, v12
++	vsll.vx v4, v8, a1
++	vsll.vi v4, v8, 1
++	vsll.vi v4, v8, 31
++	vsll.vv v4, v8, v12, v0.t
++	vsll.vx v4, v8, a1, v0.t
++	vsll.vi v4, v8, 1, v0.t
++	vsll.vi v4, v8, 31, v0.t
++	vsrl.vv v4, v8, v12
++	vsrl.vx v4, v8, a1
++	vsrl.vi v4, v8, 1
++	vsrl.vi v4, v8, 31
++	vsrl.vv v4, v8, v12, v0.t
++	vsrl.vx v4, v8, a1, v0.t
++	vsrl.vi v4, v8, 1, v0.t
++	vsrl.vi v4, v8, 31, v0.t
++	vsra.vv v4, v8, v12
++	vsra.vx v4, v8, a1
++	vsra.vi v4, v8, 1
++	vsra.vi v4, v8, 31
++	vsra.vv v4, v8, v12, v0.t
++	vsra.vx v4, v8, a1, v0.t
++	vsra.vi v4, v8, 1, v0.t
++	vsra.vi v4, v8, 31, v0.t
++
++	# Aliases
++	vncvt.x.x.w v4, v8
++	vncvt.x.x.w v4, v8, v0.t
++
++	vnsrl.wv v4, v8, v12
++	vnsrl.wx v4, v8, a1
++	vnsrl.wi v4, v8, 1
++	vnsrl.wi v4, v8, 31
++	vnsrl.wv v4, v8, v12, v0.t
++	vnsrl.wx v4, v8, a1, v0.t
++	vnsrl.wi v4, v8, 1, v0.t
++	vnsrl.wi v4, v8, 31, v0.t
++	vnsra.wv v4, v8, v12
++	vnsra.wx v4, v8, a1
++	vnsra.wi v4, v8, 1
++	vnsra.wi v4, v8, 31
++	vnsra.wv v4, v8, v12, v0.t
++	vnsra.wx v4, v8, a1, v0.t
++	vnsra.wi v4, v8, 1, v0.t
++	vnsra.wi v4, v8, 31, v0.t
++
++	vwmul.vv v4, v8, v12
++	vwmul.vx v4, v8, a1
++	vwmul.vv v4, v8, v12, v0.t
++	vwmul.vx v4, v8, a1, v0.t
++	vwmulu.vv v4, v8, v12
++	vwmulu.vx v4, v8, a1
++	vwmulu.vv v4, v8, v12, v0.t
++	vwmulu.vx v4, v8, a1, v0.t
++	vwmulsu.vv v4, v8, v12
++	vwmulsu.vx v4, v8, a1
++	vwmulsu.vv v4, v8, v12, v0.t
++	vwmulsu.vx v4, v8, a1, v0.t
++
++	vwmaccu.vv v4, v12, v8
++	vwmaccu.vx v4, a1, v8
++	vwmaccu.vv v4, v12, v8, v0.t
++	vwmaccu.vx v4, a1, v8, v0.t
++	vwmacc.vv v4, v12, v8
++	vwmacc.vx v4, a1, v8
++	vwmacc.vv v4, v12, v8, v0.t
++	vwmacc.vx v4, a1, v8, v0.t
++	vwmaccsu.vv v4, v12, v8
++	vwmaccsu.vx v4, a1, v8
++	vwmaccsu.vv v4, v12, v8, v0.t
++	vwmaccsu.vx v4, a1, v8, v0.t
++	vwmaccus.vx v4, a1, v8
++	vwmaccus.vx v4, a1, v8, v0.t
++
++	vsaddu.vv v4, v8, v12
++	vsaddu.vx v4, v8, a1
++	vsaddu.vi v4, v8, 15
++	vsaddu.vi v4, v8, -16
++	vsaddu.vv v4, v8, v12, v0.t
++	vsaddu.vx v4, v8, a1, v0.t
++	vsaddu.vi v4, v8, 15, v0.t
++	vsaddu.vi v4, v8, -16, v0.t
++	vsadd.vv v4, v8, v12
++	vsadd.vx v4, v8, a1
++	vsadd.vi v4, v8, 15
++	vsadd.vi v4, v8, -16
++	vsadd.vv v4, v8, v12, v0.t
++	vsadd.vx v4, v8, a1, v0.t
++	vsadd.vi v4, v8, 15, v0.t
++	vsadd.vi v4, v8, -16, v0.t
++	vssubu.vv v4, v8, v12
++	vssubu.vx v4, v8, a1
++	vssubu.vv v4, v8, v12, v0.t
++	vssubu.vx v4, v8, a1, v0.t
++	vssub.vv v4, v8, v12
++	vssub.vx v4, v8, a1
++	vssub.vv v4, v8, v12, v0.t
++	vssub.vx v4, v8, a1, v0.t
++
++	vaaddu.vv v4, v8, v12
++	vaaddu.vx v4, v8, a1
++	vaaddu.vv v4, v8, v12, v0.t
++	vaaddu.vx v4, v8, a1, v0.t
++	vaadd.vv v4, v8, v12
++	vaadd.vx v4, v8, a1
++	vaadd.vv v4, v8, v12, v0.t
++	vaadd.vx v4, v8, a1, v0.t
++	vasubu.vv v4, v8, v12
++	vasubu.vx v4, v8, a1
++	vasubu.vv v4, v8, v12, v0.t
++	vasubu.vx v4, v8, a1, v0.t
++	vasub.vv v4, v8, v12
++	vasub.vx v4, v8, a1
++	vasub.vv v4, v8, v12, v0.t
++	vasub.vx v4, v8, a1, v0.t
++
++	vsmul.vv v4, v8, v12
++	vsmul.vx v4, v8, a1
++	vsmul.vv v4, v8, v12, v0.t
++	vsmul.vx v4, v8, a1, v0.t
++
++	vssrl.vv v4, v8, v12
++	vssrl.vx v4, v8, a1
++	vssrl.vi v4, v8, 1
++	vssrl.vi v4, v8, 31
++	vssrl.vv v4, v8, v12, v0.t
++	vssrl.vx v4, v8, a1, v0.t
++	vssrl.vi v4, v8, 1, v0.t
++	vssrl.vi v4, v8, 31, v0.t
++	vssra.vv v4, v8, v12
++	vssra.vx v4, v8, a1
++	vssra.vi v4, v8, 1
++	vssra.vi v4, v8, 31
++	vssra.vv v4, v8, v12, v0.t
++	vssra.vx v4, v8, a1, v0.t
++	vssra.vi v4, v8, 1, v0.t
++	vssra.vi v4, v8, 31, v0.t
++
++	vnclipu.wv v4, v8, v12
++	vnclipu.wx v4, v8, a1
++	vnclipu.wi v4, v8, 1
++	vnclipu.wi v4, v8, 31
++	vnclipu.wv v4, v8, v12, v0.t
++	vnclipu.wx v4, v8, a1, v0.t
++	vnclipu.wi v4, v8, 1, v0.t
++	vnclipu.wi v4, v8, 31, v0.t
++	vnclip.wv v4, v8, v12
++	vnclip.wx v4, v8, a1
++	vnclip.wi v4, v8, 1
++	vnclip.wi v4, v8, 31
++	vnclip.wv v4, v8, v12, v0.t
++	vnclip.wx v4, v8, a1, v0.t
++	vnclip.wi v4, v8, 1, v0.t
++	vnclip.wi v4, v8, 31, v0.t
++
++	vfwadd.vv v4, v8, v12
++	vfwadd.vf v4, v8, fa2
++	vfwadd.vv v4, v8, v12, v0.t
++	vfwadd.vf v4, v8, fa2, v0.t
++	vfwsub.vv v4, v8, v12
++	vfwsub.vf v4, v8, fa2
++	vfwsub.vv v4, v8, v12, v0.t
++	vfwsub.vf v4, v8, fa2, v0.t
++	vfwadd.wv v4, v8, v12
++	vfwadd.wf v4, v8, fa2
++	vfwadd.wv v4, v8, v12, v0.t
++	vfwadd.wf v4, v8, fa2, v0.t
++	vfwsub.wv v4, v8, v12
++	vfwsub.wf v4, v8, fa2
++	vfwsub.wv v4, v8, v12, v0.t
++	vfwsub.wf v4, v8, fa2, v0.t
++
++	vfwmul.vv v4, v8, v12
++	vfwmul.vf v4, v8, fa2
++	vfwmul.vv v4, v8, v12, v0.t
++	vfwmul.vf v4, v8, fa2, v0.t
++
++	vfwmacc.vv v4, v12, v8
++	vfwmacc.vf v4, fa2, v8
++	vfwnmacc.vv v4, v12, v8
++	vfwnmacc.vf v4, fa2, v8
++	vfwmsac.vv v4, v12, v8
++	vfwmsac.vf v4, fa2, v8
++	vfwnmsac.vv v4, v12, v8
++	vfwnmsac.vf v4, fa2, v8
++	vfwmacc.vv v4, v12, v8, v0.t
++	vfwmacc.vf v4, fa2, v8, v0.t
++	vfwnmacc.vv v4, v12, v8, v0.t
++	vfwnmacc.vf v4, fa2, v8, v0.t
++	vfwmsac.vv v4, v12, v8, v0.t
++	vfwmsac.vf v4, fa2, v8, v0.t
++	vfwnmsac.vv v4, v12, v8, v0.t
++	vfwnmsac.vf v4, fa2, v8, v0.t
++
++	vfsqrt.v v4, v8
++	vfsqrt.v v4, v8, v0.t
++	vfrsqrte7.v v4, v8
++	vfrsqrte7.v v4, v8, v0.t
++	vfrsqrt7.v v4, v8
++	vfrsqrt7.v v4, v8, v0.t
++	vfrece7.v v4, v8
++	vfrece7.v v4, v8, v0.t
++	vfrec7.v v4, v8
++	vfrec7.v v4, v8, v0.t
++	vfclass.v v4, v8
++	vfclass.v v4, v8, v0.t
++	
++	vfcvt.xu.f.v v4, v8
++	vfcvt.x.f.v v4, v8
++	vfcvt.rtz.xu.f.v v4, v8
++	vfcvt.rtz.x.f.v v4, v8
++	vfcvt.f.xu.v v4, v8
++	vfcvt.f.x.v v4, v8
++	vfcvt.xu.f.v v4, v8, v0.t
++	vfcvt.x.f.v v4, v8, v0.t
++	vfcvt.rtz.xu.f.v v4, v8, v0.t
++	vfcvt.rtz.x.f.v v4, v8, v0.t
++	vfcvt.f.xu.v v4, v8, v0.t
++	vfcvt.f.x.v v4, v8, v0.t
++
++	vfwcvt.xu.f.v v4, v8
++	vfwcvt.x.f.v v4, v8
++	vfwcvt.rtz.xu.f.v v4, v8
++	vfwcvt.rtz.x.f.v v4, v8
++	vfwcvt.f.xu.v v4, v8
++	vfwcvt.f.x.v v4, v8
++	vfwcvt.f.f.v v4, v8
++	vfwcvt.xu.f.v v4, v8, v0.t
++	vfwcvt.x.f.v v4, v8, v0.t
++	vfwcvt.rtz.xu.f.v v4, v8, v0.t
++	vfwcvt.rtz.x.f.v v4, v8, v0.t
++	vfwcvt.f.xu.v v4, v8, v0.t
++	vfwcvt.f.x.v v4, v8, v0.t
++	vfwcvt.f.f.v v4, v8, v0.t
++
++	vfncvt.xu.f.w v4, v8
++	vfncvt.x.f.w v4, v8
++	vfncvt.rtz.xu.f.w v4, v8
++	vfncvt.rtz.x.f.w v4, v8
++	vfncvt.f.xu.w v4, v8
++	vfncvt.f.x.w v4, v8
++	vfncvt.f.f.w v4, v8
++	vfncvt.rod.f.f.w v4, v8
++	vfncvt.xu.f.w v4, v8, v0.t
++	vfncvt.x.f.w v4, v8, v0.t
++	vfncvt.rtz.xu.f.w v4, v8, v0.t
++	vfncvt.rtz.x.f.w v4, v8, v0.t
++	vfncvt.f.xu.w v4, v8, v0.t
++	vfncvt.f.x.w v4, v8, v0.t
++	vfncvt.f.f.w v4, v8, v0.t
++	vfncvt.rod.f.f.w v4, v8, v0.t
++
++	vredsum.vs v4, v8, v12
++	vredmaxu.vs v4, v8, v8
++	vredmax.vs v4, v8, v8
++	vredminu.vs v4, v8, v8
++	vredmin.vs v4, v8, v8
++	vredand.vs v4, v8, v12
++	vredor.vs v4, v8, v12
++	vredxor.vs v4, v8, v12
++	vredsum.vs v4, v8, v12, v0.t
++	vredmaxu.vs v4, v8, v8, v0.t
++	vredmax.vs v4, v8, v8, v0.t
++	vredminu.vs v4, v8, v8, v0.t
++	vredmin.vs v4, v8, v8, v0.t
++	vredand.vs v4, v8, v12, v0.t
++	vredor.vs v4, v8, v12, v0.t
++	vredxor.vs v4, v8, v12, v0.t
++
++	vwredsumu.vs v4, v8, v12
++	vwredsum.vs v4, v8, v12
++	vwredsumu.vs v4, v8, v12, v0.t
++	vwredsum.vs v4, v8, v12, v0.t
++
++	vfredosum.vs v4, v8, v12
++	vfredsum.vs v4, v8, v12
++	vfredmax.vs v4, v8, v12
++	vfredmin.vs v4, v8, v12
++	vfredosum.vs v4, v8, v12, v0.t
++	vfredsum.vs v4, v8, v12, v0.t
++	vfredmax.vs v4, v8, v12, v0.t
++	vfredmin.vs v4, v8, v12, v0.t
++
++	vfwredosum.vs v4, v8, v12
++	vfwredsum.vs v4, v8, v12
++	vfwredosum.vs v4, v8, v12, v0.t
++	vfwredsum.vs v4, v8, v12, v0.t
++
++	vmsbf.m v4, v8
++	vmsif.m v4, v8
++	vmsof.m v4, v8
++	viota.m v4, v8
++	
++	vmsbf.m v4, v8, v0.t
++	vmsif.m v4, v8, v0.t
++	vmsof.m v4, v8, v0.t
++	viota.m v4, v8, v0.t
++
++	vrgatherei16.vv v4, v8, v12
++	vrgatherei16.vv v4, v8, v12, v0.t
++
++	vmv2r.v v2, v4
++	vmv4r.v v4, v8
++	vmv8r.v v0, v8
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
+new file mode 100644
+index 0000000000..4f2b611f53
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
+@@ -0,0 +1,3 @@
++#as: -march=rv32iav0p10
++#source: vector-insns-fail-zvamo.s
++#error_output: vector-insns-fail-zvamo.l
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+new file mode 100644
+index 0000000000..6207fb2fee
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
+@@ -0,0 +1,109 @@
++.*: Assembler messages:
++.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
++.*Error: illegal operands `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
++.*Error: illegal operands `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
+new file mode 100644
+index 0000000000..0fd3c26a58
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
+@@ -0,0 +1,217 @@
++# Vector AMO Operations
++
++	vamoaddei8.v v0, (a1), v4, v0		# OK
++	vamoaddei8.v v4, (a1), v4, v0		# vd must match vs3
++	vamoaddei8.v v0, (a1), v4, v0, v0.t	# vd overlap vm
++	vamoaddei8.v x0, (a1), v4, v0		# OK
++	vamoaddei8.v x0, (a1), v4, v0, v0.t	# vs3 overlap vm
++
++	vamoswapei8.v v0, (a1), v4, v0
++	vamoswapei8.v v4, (a1), v4, v0
++	vamoswapei8.v v0, (a1), v4, v0, v0.t
++	vamoswapei8.v x0, (a1), v4, v0
++	vamoswapei8.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei8.v v0, (a1), v4, v0
++	vamoxorei8.v v4, (a1), v4, v0
++	vamoxorei8.v v0, (a1), v4, v0, v0.t
++	vamoxorei8.v x0, (a1), v4, v0
++	vamoxorei8.v x0, (a1), v4, v0, v0.t
++
++	vamoandei8.v v0, (a1), v4, v0
++	vamoandei8.v v4, (a1), v4, v0
++	vamoandei8.v v0, (a1), v4, v0, v0.t
++	vamoandei8.v x0, (a1), v4, v0
++	vamoandei8.v x0, (a1), v4, v0, v0.t
++
++	vamoorei8.v v0, (a1), v4, v0
++	vamoorei8.v v4, (a1), v4, v0
++	vamoorei8.v v0, (a1), v4, v0, v0.t
++	vamoorei8.v x0, (a1), v4, v0
++	vamoorei8.v x0, (a1), v4, v0, v0.t
++
++	vamominei8.v v0, (a1), v4, v0
++	vamominei8.v v4, (a1), v4, v0
++	vamominei8.v v0, (a1), v4, v0, v0.t
++	vamominei8.v x0, (a1), v4, v0
++	vamominei8.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei8.v v0, (a1), v4, v0
++	vamomaxei8.v v4, (a1), v4, v0
++	vamomaxei8.v v0, (a1), v4, v0, v0.t
++	vamomaxei8.v x0, (a1), v4, v0
++	vamomaxei8.v x0, (a1), v4, v0, v0.t
++
++	vamominuei8.v v0, (a1), v4, v0
++	vamominuei8.v v4, (a1), v4, v0
++	vamominuei8.v v0, (a1), v4, v0, v0.t
++	vamominuei8.v x0, (a1), v4, v0
++	vamominuei8.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei8.v v0, (a1), v4, v0
++	vamomaxuei8.v v4, (a1), v4, v0
++	vamomaxuei8.v v0, (a1), v4, v0, v0.t
++	vamomaxuei8.v x0, (a1), v4, v0
++	vamomaxuei8.v x0, (a1), v4, v0, v0.t
++
++	vamoaddei16.v v0, (a1), v4, v0
++	vamoaddei16.v v4, (a1), v4, v0
++	vamoaddei16.v v0, (a1), v4, v0, v0.t
++	vamoaddei16.v x0, (a1), v4, v0
++	vamoaddei16.v x0, (a1), v4, v0, v0.t
++
++	vamoswapei16.v v0, (a1), v4, v0
++	vamoswapei16.v v0, (a1), v4, v0, v0.t
++	vamoswapei16.v v4, (a1), v4, v0
++	vamoswapei16.v x0, (a1), v4, v0
++	vamoswapei16.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei16.v v0, (a1), v4, v0
++	vamoxorei16.v v0, (a1), v4, v0, v0.t
++	vamoxorei16.v v4, (a1), v4, v0
++	vamoxorei16.v x0, (a1), v4, v0
++	vamoxorei16.v x0, (a1), v4, v0, v0.t
++
++	vamoandei16.v v0, (a1), v4, v0
++	vamoandei16.v v0, (a1), v4, v0, v0.t
++	vamoandei16.v v4, (a1), v4, v0
++	vamoandei16.v x0, (a1), v4, v0
++	vamoandei16.v x0, (a1), v4, v0, v0.t
++
++	vamoorei16.v v0, (a1), v4, v0
++	vamoorei16.v v0, (a1), v4, v0, v0.t
++	vamoorei16.v v4, (a1), v4, v0
++	vamoorei16.v x0, (a1), v4, v0
++	vamoorei16.v x0, (a1), v4, v0, v0.t
++
++	vamominei16.v v0, (a1), v4, v0
++	vamominei16.v v0, (a1), v4, v0, v0.t
++	vamominei16.v v4, (a1), v4, v0
++	vamominei16.v x0, (a1), v4, v0
++	vamominei16.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei16.v v0, (a1), v4, v0
++	vamomaxei16.v v0, (a1), v4, v0, v0.t
++	vamomaxei16.v v4, (a1), v4, v0
++	vamomaxei16.v x0, (a1), v4, v0
++	vamomaxei16.v x0, (a1), v4, v0, v0.t
++
++	vamominuei16.v v0, (a1), v4, v0
++	vamominuei16.v v0, (a1), v4, v0, v0.t
++	vamominuei16.v v4, (a1), v4, v0
++	vamominuei16.v x0, (a1), v4, v0
++	vamominuei16.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei16.v v0, (a1), v4, v0
++	vamomaxuei16.v v0, (a1), v4, v0, v0.t
++	vamomaxuei16.v v4, (a1), v4, v0
++	vamomaxuei16.v x0, (a1), v4, v0
++	vamomaxuei16.v x0, (a1), v4, v0, v0.t
++
++	vamoaddei32.v v0, (a1), v4, v0
++	vamoaddei32.v v0, (a1), v4, v0, v0.t
++	vamoaddei32.v v4, (a1), v4, v0
++	vamoaddei32.v x0, (a1), v4, v0
++	vamoaddei32.v x0, (a1), v4, v0, v0.t
++
++	vamoswapei32.v v0, (a1), v4, v0
++	vamoswapei32.v v4, (a1), v4, v0
++	vamoswapei32.v v0, (a1), v4, v0, v0.t
++	vamoswapei32.v x0, (a1), v4, v0
++	vamoswapei32.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei32.v v0, (a1), v4, v0
++	vamoxorei32.v v4, (a1), v4, v0
++	vamoxorei32.v v0, (a1), v4, v0, v0.t
++	vamoxorei32.v x0, (a1), v4, v0
++	vamoxorei32.v x0, (a1), v4, v0, v0.t
++
++	vamoandei32.v v0, (a1), v4, v0
++	vamoandei32.v v4, (a1), v4, v0
++	vamoandei32.v v0, (a1), v4, v0, v0.t
++	vamoandei32.v x0, (a1), v4, v0
++	vamoandei32.v x0, (a1), v4, v0, v0.t
++
++	vamoorei32.v v0, (a1), v4, v0
++	vamoorei32.v v4, (a1), v4, v0
++	vamoorei32.v v0, (a1), v4, v0, v0.t
++	vamoorei32.v x0, (a1), v4, v0
++	vamoorei32.v x0, (a1), v4, v0, v0.t
++
++	vamominei32.v v0, (a1), v4, v0
++	vamominei32.v v4, (a1), v4, v0
++	vamominei32.v v0, (a1), v4, v0, v0.t
++	vamominei32.v x0, (a1), v4, v0
++	vamominei32.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei32.v v0, (a1), v4, v0
++	vamomaxei32.v v4, (a1), v4, v0
++	vamomaxei32.v v0, (a1), v4, v0, v0.t
++	vamomaxei32.v x0, (a1), v4, v0
++	vamomaxei32.v x0, (a1), v4, v0, v0.t
++
++	vamominuei32.v v0, (a1), v4, v0
++	vamominuei32.v v4, (a1), v4, v0
++	vamominuei32.v v0, (a1), v4, v0, v0.t
++	vamominuei32.v x0, (a1), v4, v0
++	vamominuei32.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei32.v v0, (a1), v4, v0
++	vamomaxuei32.v v4, (a1), v4, v0
++	vamomaxuei32.v v0, (a1), v4, v0, v0.t
++	vamomaxuei32.v x0, (a1), v4, v0
++	vamomaxuei32.v x0, (a1), v4, v0, v0.t
++
++	vamoaddei64.v v0, (a1), v4, v0
++	vamoaddei64.v v4, (a1), v4, v0
++	vamoaddei64.v v0, (a1), v4, v0, v0.t
++	vamoaddei64.v x0, (a1), v4, v0
++	vamoaddei64.v x0, (a1), v4, v0, v0.t
++
++	vamoswapei64.v v0, (a1), v4, v0
++	vamoswapei64.v v4, (a1), v4, v0
++	vamoswapei64.v v0, (a1), v4, v0, v0.t
++	vamoswapei64.v x0, (a1), v4, v0
++	vamoswapei64.v x0, (a1), v4, v0, v0.t
++
++	vamoxorei64.v v0, (a1), v4, v0
++	vamoxorei64.v v4, (a1), v4, v0
++	vamoxorei64.v v0, (a1), v4, v0, v0.t
++	vamoxorei64.v x0, (a1), v4, v0
++	vamoxorei64.v x0, (a1), v4, v0, v0.t
++
++	vamoandei64.v v0, (a1), v4, v0
++	vamoandei64.v v4, (a1), v4, v0
++	vamoandei64.v v0, (a1), v4, v0, v0.t
++	vamoandei64.v x0, (a1), v4, v0
++	vamoandei64.v x0, (a1), v4, v0, v0.t
++
++	vamoorei64.v v0, (a1), v4, v0
++	vamoorei64.v v4, (a1), v4, v0
++	vamoorei64.v v0, (a1), v4, v0, v0.t
++	vamoorei64.v x0, (a1), v4, v0
++	vamoorei64.v x0, (a1), v4, v0, v0.t
++
++	vamominei64.v v0, (a1), v4, v0
++	vamominei64.v v4, (a1), v4, v0
++	vamominei64.v v0, (a1), v4, v0, v0.t
++	vamominei64.v x0, (a1), v4, v0
++	vamominei64.v x0, (a1), v4, v0, v0.t
++
++	vamomaxei64.v v0, (a1), v4, v0
++	vamomaxei64.v v4, (a1), v4, v0
++	vamomaxei64.v v0, (a1), v4, v0, v0.t
++	vamomaxei64.v x0, (a1), v4, v0
++	vamomaxei64.v x0, (a1), v4, v0, v0.t
++
++	vamominuei64.v v0, (a1), v4, v0
++	vamominuei64.v v4, (a1), v4, v0
++	vamominuei64.v v0, (a1), v4, v0, v0.t
++	vamominuei64.v x0, (a1), v4, v0
++	vamominuei64.v x0, (a1), v4, v0, v0.t
++
++	vamomaxuei64.v v0, (a1), v4, v0
++	vamomaxuei64.v v4, (a1), v4, v0
++	vamomaxuei64.v v0, (a1), v4, v0, v0.t
++	vamomaxuei64.v x0, (a1), v4, v0
++	vamomaxuei64.v x0, (a1), v4, v0, v0.t
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+new file mode 100644
+index 0000000000..207a410c28
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
+@@ -0,0 +1,29 @@
++#as: -march=rv32iv0p10
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
++[ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
++[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
++[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
++[ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
++[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
++[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
++[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+new file mode 100644
+index 0000000000..afbb7ccb36
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
+@@ -0,0 +1,9 @@
++	vmsge.vx v4, v8, a1		# unmasked va >= x
++	vmsge.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
++	vmsge.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
++	vmsge.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
++
++	vmsgeu.vx v4, v8, a1		# unmasked va >= x
++	vmsgeu.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
++	vmsgeu.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
++	vmsgeu.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
+new file mode 100644
+index 0000000000..0556a22a7b
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns.d
+@@ -0,0 +1,1944 @@
++#as: -march=rv32iafv0p10
++#objdump: -dr
++
++.*:[ 	]+file format .*
++
++
++Disassembly of section .text:
++
++0+000 <.text>:
++[ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+vsetvl[ 	]+a0,a1,a2
++[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
++[ 	]+[0-9a-f]+:[ 	]+0095f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+02b5f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0335f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+03b5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0385f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+03f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,mf2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0365f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+02d5f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
++[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
++[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+0e95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma
++[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
++[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
++[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c005f557[ 	]+vsetivli[ 	]+a0,11,e8,m1,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+fff5f557[ 	]+vsetivli[ 	]+a0,11,e1024,mf2,ta,ma
++[ 	]+[0-9a-f]+:[ 	]+c095f557[ 	]+vsetivli[ 	]+a0,11,e16,m2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c2b5f557[ 	]+vsetivli[ 	]+a0,11,e256,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c335f557[ 	]+vsetivli[ 	]+a0,11,e512,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c3b5f557[ 	]+vsetivli[ 	]+a0,11,e1024,m8,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c385f557[ 	]+vsetivli[ 	]+a0,11,e1024,m1,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c3f5f557[ 	]+vsetivli[ 	]+a0,11,e1024,mf2,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c365f557[ 	]+vsetivli[ 	]+a0,11,e512,mf4,tu,mu
++[ 	]+[0-9a-f]+:[ 	]+c2d5f557[ 	]+vsetivli[ 	]+a0,11,e256,mf8,tu,mu
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++[ 	]+[0-9a-f]+:[ 	]+a085e22f[ 	]+vamomaxei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685e22f[ 	]+vamominuei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285e22f[ 	]+vamominuei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485e22f[ 	]+vamominuei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085e22f[ 	]+vamominuei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e685e22f[ 	]+vamomaxuei32.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e285e22f[ 	]+vamomaxuei32.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+e485e22f[ 	]+vamomaxuei32.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+e085e22f[ 	]+vamomaxuei32.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0685f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0285f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0485f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0a85f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2685f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2285f22f[ 	]+vamoxorei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+2485f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+2085f22f[ 	]+vamoxorei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6685f22f[ 	]+vamoandei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6285f22f[ 	]+vamoandei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+6485f22f[ 	]+vamoandei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+6085f22f[ 	]+vamoandei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4685f22f[ 	]+vamoorei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4285f22f[ 	]+vamoorei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+4485f22f[ 	]+vamoorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+4085f22f[ 	]+vamoorei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8685f22f[ 	]+vamominei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8285f22f[ 	]+vamominei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+8485f22f[ 	]+vamominei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+8085f22f[ 	]+vamominei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
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++[ 	]+[0-9a-f]+:[ 	]+a485f22f[ 	]+vamomaxei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+a085f22f[ 	]+vamomaxei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c685f22f[ 	]+vamominuei64.v[ 	]+v4,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c285f22f[ 	]+vamominuei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+c485f22f[ 	]+vamominuei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c085f22f[ 	]+vamominuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
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++[ 	]+[0-9a-f]+:[ 	]+e085f22f[ 	]+vamomaxuei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
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++[ 	]+[0-9a-f]+:[ 	]+0485f22f[ 	]+vamoaddei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0085f22f[ 	]+vamoaddei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
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++[ 	]+[0-9a-f]+:[ 	]+0a85f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4
++[ 	]+[0-9a-f]+:[ 	]+0c85f22f[ 	]+vamoswapei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0885f22f[ 	]+vamoswapei64.v[ 	]+zero,\(a1\),v8,v4,v0.t
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++[ 	]+[0-9a-f]+:[ 	]+2485f22f[ 	]+vamoxorei64.v[ 	]+v4,\(a1\),v8,v4,v0.t
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++[ 	]+[0-9a-f]+:[ 	]+0a862257[ 	]+vredor.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0e862257[ 	]+vredxor.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+00862257[ 	]+vredsum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+18842257[ 	]+vredmaxu.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1c842257[ 	]+vredmax.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+10842257[ 	]+vredminu.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+14842257[ 	]+vredmin.vs[ 	]+v4,v8,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+04862257[ 	]+vredand.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+08862257[ 	]+vredor.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0c862257[ 	]+vredxor.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c2860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c6860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c0860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c4860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+0e861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+vfredusum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+1e861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+16861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+0c861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+vfredusum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+1c861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+14861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+ce861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+vfwredusum.vs[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+vfwredusum.vs[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+vmclr.m[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+7e422257[ 	]+vmset.m[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+76842257[ 	]+vmnot.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+66862257[ 	]+vmand.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+76862257[ 	]+vmnand.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandnot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+vmxor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+vmor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+vmnor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmornot.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+vmxnor.mm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vpopc.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42c8a557[ 	]+vfirst.m[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+5280a257[ 	]+vmsbf.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+5281a257[ 	]+vmsif.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+52812257[ 	]+vmsof.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+52882257[ 	]+viota.m[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
++[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vpopc.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+40c8a557[ 	]+vfirst.m[ 	]+a0,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5080a257[ 	]+vmsbf.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5081a257[ 	]+vmsif.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+50812257[ 	]+vmsof.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+50882257[ 	]+viota.m[ 	]+v4,v8,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5008a257[ 	]+vid.v[ 	]+v4,v0.t
++[ 	]+[0-9a-f]+:[ 	]+42c02557[ 	]+vmv.x.s[ 	]+a0,v12
++[ 	]+[0-9a-f]+:[ 	]+42056257[ 	]+vmv.s.x[ 	]+v4,a0
++[ 	]+[0-9a-f]+:[ 	]+42801557[ 	]+vfmv.f.s[ 	]+fa0,v8
++[ 	]+[0-9a-f]+:[ 	]+4205d257[ 	]+vfmv.s.f[ 	]+v4,fa1
++[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+vslideup.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+vslideup.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+vslideup.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+vslidedown.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+vslideup.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+vslideup.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+vslideup.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+vslidedown.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a85d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1
++[ 	]+[0-9a-f]+:[ 	]+3e85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1
++[ 	]+[0-9a-f]+:[ 	]+3885d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3c85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+vrgather.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+vrgather.vx[ 	]+v4,v8,a1
++[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+vrgather.vi[ 	]+v4,v8,0
++[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+vrgather.vi[ 	]+v4,v8,31
++[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+vrgather.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+vrgather.vx[ 	]+v4,v8,a1,v0.t
++[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
++[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
++[ 	]+[0-9a-f]+:[ 	]+3a860257[ 	]+vrgatherei16.vv[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+38860257[ 	]+vrgatherei16.vv[ 	]+v4,v8,v12,v0.t
++[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
++[ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
++[ 	]+[0-9a-f]+:[ 	]+9e40b157[ 	]+vmv2r.v[ 	]+v2,v4
++[ 	]+[0-9a-f]+:[ 	]+9e81b257[ 	]+vmv4r.v[ 	]+v4,v8
++[ 	]+[0-9a-f]+:[ 	]+9e83b057[ 	]+vmv8r.v[ 	]+v0,v8
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
+new file mode 100644
+index 0000000000..380e0441c9
+--- /dev/null
++++ b/gas/testsuite/gas/riscv/vector-insns.s
+@@ -0,0 +1,2185 @@
++	vsetvl a0, a1, a2
++	vsetvli a0, a1, 0
++	vsetvli a0, a1, 0x7ff
++	vsetvli a0, a1, e16, m2
++	vsetvli a0, a1, e256, m8
++	vsetvli a0, a1, e512, m8
++	vsetvli a0, a1, e1024, m8
++	vsetvli a0, a1, e1024, m1
++	vsetvli a0, a1, e1024, mf2
++	vsetvli a0, a1, e512, mf4
++	vsetvli a0, a1, e256, mf8
++	vsetvli a0, a1, e256, m2, ta
++	vsetvli a0, a1, e256, m2, ma
++	vsetvli a0, a1, e256, m2, tu
++	vsetvli a0, a1, e256, m2, mu
++	vsetvli a0, a1, e256, m2, ta, ma
++	vsetvli a0, a1, e256, m2, tu, ma
++	vsetvli a0, a1, e256, m2, ta, mu
++	vsetvli a0, a1, e256, m2, tu, mu
++	vsetivli a0, 0xb, 0
++	vsetivli a0, 0xb, 0x3ff
++	vsetivli a0, 0xb, e16, m2
++	vsetivli a0, 0xb, e256, m8
++	vsetivli a0, 0xb, e512, m8
++	vsetivli a0, 0xb, e1024, m8
++	vsetivli a0, 0xb, e1024, m1
++	vsetivli a0, 0xb, e1024, mf2
++	vsetivli a0, 0xb, e512, mf4
++	vsetivli a0, 0xb, e256, mf8
++	vsetivli a0, 0xb, e256, m2, ta
++	vsetivli a0, 0xb, e256, m2, ma
++	vsetivli a0, 0xb, e256, m2, tu
++	vsetivli a0, 0xb, e256, m2, mu
++	vsetivli a0, 0xb, e256, m2, ta, ma
++	vsetivli a0, 0xb, e256, m2, tu, ma
++	vsetivli a0, 0xb, e256, m2, ta, mu
++	vsetivli a0, 0xb, e256, m2, tu, mu
++
++	vle1.v v4, (a0)
++	vle1.v v4, 0(a0)
++	vse1.v v4, (a0)
++	vse1.v v4, 0(a0)
++
++	vle8.v v4, (a0)
++	vle8.v v4, 0(a0)
++	vle8.v v4, (a0), v0.t
++	vse8.v v4, (a0)
++	vse8.v v4, 0(a0)
++	vse8.v v4, (a0), v0.t
++
++	vle16.v v4, (a0)
++	vle16.v v4, 0(a0)
++	vle16.v v4, (a0), v0.t
++	vse16.v v4, (a0)
++	vse16.v v4, 0(a0)
++	vse16.v v4, (a0), v0.t
++
++	vle32.v v4, (a0)
++	vle32.v v4, 0(a0)
++	vle32.v v4, (a0), v0.t
++	vse32.v v4, (a0)
++	vse32.v v4, 0(a0)
++	vse32.v v4, (a0), v0.t
++
++	vle64.v v4, (a0)
++	vle64.v v4, 0(a0)
++	vle64.v v4, (a0), v0.t
++	vse64.v v4, (a0)
++	vse64.v v4, 0(a0)
++	vse64.v v4, (a0), v0.t
++
++	vlse8.v v4, (a0), a1
++	vlse8.v v4, 0(a0), a1
++	vlse8.v v4, (a0), a1, v0.t
++	vsse8.v v4, (a0), a1
++	vsse8.v v4, 0(a0), a1
++	vsse8.v v4, (a0), a1, v0.t
++
++	vlse16.v v4, (a0), a1
++	vlse16.v v4, 0(a0), a1
++	vlse16.v v4, (a0), a1, v0.t
++	vsse16.v v4, (a0), a1
++	vsse16.v v4, 0(a0), a1
++	vsse16.v v4, (a0), a1, v0.t
++
++	vlse32.v v4, (a0), a1
++	vlse32.v v4, 0(a0), a1
++	vlse32.v v4, (a0), a1, v0.t
++	vsse32.v v4, (a0), a1
++	vsse32.v v4, 0(a0), a1
++	vsse32.v v4, (a0), a1, v0.t
++
++	vlse64.v v4, (a0), a1
++	vlse64.v v4, 0(a0), a1
++	vlse64.v v4, (a0), a1, v0.t
++	vsse64.v v4, (a0), a1
++	vsse64.v v4, 0(a0), a1
++	vsse64.v v4, (a0), a1, v0.t
++
++	vloxei8.v v4, (a0), v12
++	vloxei8.v v4, 0(a0), v12
++	vloxei8.v v4, (a0), v12, v0.t
++	vsoxei8.v v4, (a0), v12
++	vsoxei8.v v4, 0(a0), v12
++	vsoxei8.v v4, (a0), v12, v0.t
++	vluxei8.v v4, (a0), v12
++	vluxei8.v v4, 0(a0), v12
++	vluxei8.v v4, (a0), v12, v0.t
++	vsuxei8.v v4, (a0), v12
++	vsuxei8.v v4, 0(a0), v12
++	vsuxei8.v v4, (a0), v12, v0.t
++
++	vloxei16.v v4, (a0), v12
++	vloxei16.v v4, 0(a0), v12
++	vloxei16.v v4, (a0), v12, v0.t
++	vsoxei16.v v4, (a0), v12
++	vsoxei16.v v4, 0(a0), v12
++	vsoxei16.v v4, (a0), v12, v0.t
++	vluxei16.v v4, (a0), v12
++	vluxei16.v v4, 0(a0), v12
++	vluxei16.v v4, (a0), v12, v0.t
++	vsuxei16.v v4, (a0), v12
++	vsuxei16.v v4, 0(a0), v12
++	vsuxei16.v v4, (a0), v12, v0.t
++
++	vloxei32.v v4, (a0), v12
++	vloxei32.v v4, 0(a0), v12
++	vloxei32.v v4, (a0), v12, v0.t
++	vsoxei32.v v4, (a0), v12
++	vsoxei32.v v4, 0(a0), v12
++	vsoxei32.v v4, (a0), v12, v0.t
++	vluxei32.v v4, (a0), v12
++	vluxei32.v v4, 0(a0), v12
++	vluxei32.v v4, (a0), v12, v0.t
++	vsuxei32.v v4, (a0), v12
++	vsuxei32.v v4, 0(a0), v12
++	vsuxei32.v v4, (a0), v12, v0.t
++
++	vloxei64.v v4, (a0), v12
++	vloxei64.v v4, 0(a0), v12
++	vloxei64.v v4, (a0), v12, v0.t
++	vsoxei64.v v4, (a0), v12
++	vsoxei64.v v4, 0(a0), v12
++	vsoxei64.v v4, (a0), v12, v0.t
++	vluxei64.v v4, (a0), v12
++	vluxei64.v v4, 0(a0), v12
++	vluxei64.v v4, (a0), v12, v0.t
++	vsuxei64.v v4, (a0), v12
++	vsuxei64.v v4, 0(a0), v12
++	vsuxei64.v v4, (a0), v12, v0.t
++
++	vle8ff.v v4, (a0)
++	vle8ff.v v4, 0(a0)
++	vle8ff.v v4, (a0), v0.t
++
++	vle16ff.v v4, (a0)
++	vle16ff.v v4, 0(a0)
++	vle16ff.v v4, (a0), v0.t
++
++	vle32ff.v v4, (a0)
++	vle32ff.v v4, 0(a0)
++	vle32ff.v v4, (a0), v0.t
++
++	vle64ff.v v4, (a0)
++	vle64ff.v v4, 0(a0)
++	vle64ff.v v4, (a0), v0.t
++
++	vlseg2e8.v v4, (a0)
++	vlseg2e8.v v4, 0(a0)
++	vlseg2e8.v v4, (a0), v0.t
++	vsseg2e8.v v4, (a0)
++	vsseg2e8.v v4, 0(a0)
++	vsseg2e8.v v4, (a0), v0.t
++
++	vlseg3e8.v v4, (a0)
++	vlseg3e8.v v4, 0(a0)
++	vlseg3e8.v v4, (a0), v0.t
++	vsseg3e8.v v4, (a0)
++	vsseg3e8.v v4, 0(a0)
++	vsseg3e8.v v4, (a0), v0.t
++
++	vlseg4e8.v v4, (a0)
++	vlseg4e8.v v4, 0(a0)
++	vlseg4e8.v v4, (a0), v0.t
++	vsseg4e8.v v4, (a0)
++	vsseg4e8.v v4, 0(a0)
++	vsseg4e8.v v4, (a0), v0.t
++
++	vlseg5e8.v v4, (a0)
++	vlseg5e8.v v4, 0(a0)
++	vlseg5e8.v v4, (a0), v0.t
++	vsseg5e8.v v4, (a0)
++	vsseg5e8.v v4, 0(a0)
++	vsseg5e8.v v4, (a0), v0.t
++
++	vlseg6e8.v v4, (a0)
++	vlseg6e8.v v4, 0(a0)
++	vlseg6e8.v v4, (a0), v0.t
++	vsseg6e8.v v4, (a0)
++	vsseg6e8.v v4, 0(a0)
++	vsseg6e8.v v4, (a0), v0.t
++
++	vlseg7e8.v v4, (a0)
++	vlseg7e8.v v4, 0(a0)
++	vlseg7e8.v v4, (a0), v0.t
++	vsseg7e8.v v4, (a0)
++	vsseg7e8.v v4, 0(a0)
++	vsseg7e8.v v4, (a0), v0.t
++
++	vlseg8e8.v v4, (a0)
++	vlseg8e8.v v4, 0(a0)
++	vlseg8e8.v v4, (a0), v0.t
++	vsseg8e8.v v4, (a0)
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++
++	vlseg8e64ff.v v4, (a0)
++	vlseg8e64ff.v v4, 0(a0)
++	vlseg8e64ff.v v4, (a0), v0.t
++
++	vl1r.v v3, (a0)
++	vl1r.v v3, 0(a0)
++	vl1re8.v v3, (a0)
++	vl1re8.v v3, 0(a0)
++	vl1re16.v v3, (a0)
++	vl1re16.v v3, 0(a0)
++	vl1re32.v v3, (a0)
++	vl1re32.v v3, 0(a0)
++	vl1re64.v v3, (a0)
++	vl1re64.v v3, 0(a0)
++
++	vl2r.v v2, (a0)
++	vl2r.v v2, 0(a0)
++	vl2re8.v v2, (a0)
++	vl2re8.v v2, 0(a0)
++	vl2re16.v v2, (a0)
++	vl2re16.v v2, 0(a0)
++	vl2re32.v v2, (a0)
++	vl2re32.v v2, 0(a0)
++	vl2re64.v v2, (a0)
++	vl2re64.v v2, 0(a0)
++
++	vl4r.v v4, (a0)
++	vl4r.v v4, 0(a0)
++	vl4re8.v v4, (a0)
++	vl4re8.v v4, 0(a0)
++	vl4re16.v v4, (a0)
++	vl4re16.v v4, 0(a0)
++	vl4re32.v v4, (a0)
++	vl4re32.v v4, 0(a0)
++	vl4re64.v v4, (a0)
++	vl4re64.v v4, 0(a0)
++
++	vl8r.v v8, (a0)
++	vl8r.v v8, 0(a0)
++	vl8re8.v v8, (a0)
++	vl8re8.v v8, 0(a0)
++	vl8re16.v v8, (a0)
++	vl8re16.v v8, 0(a0)
++	vl8re32.v v8, (a0)
++	vl8re32.v v8, 0(a0)
++	vl8re64.v v8, (a0)
++	vl8re64.v v8, 0(a0)
++
++	vs1r.v v3, (a1)
++	vs1r.v v3, 0(a1)
++	vs2r.v v2, (a1)
++	vs2r.v v2, 0(a1)
++	vs4r.v v4, (a1)
++	vs4r.v v4, 0(a1)
++	vs8r.v v8, (a1)
++	vs8r.v v8, 0(a1)
++
++	vamoaddei8.v v4, (a1), v8, v4
++	vamoaddei8.v x0, (a1), v8, v4
++	vamoaddei8.v v4, (a1), v8, v4, v0.t
++	vamoaddei8.v x0, (a1), v8, v4, v0.t
++	vamoswapei8.v v4, (a1), v8, v4
++	vamoswapei8.v x0, (a1), v8, v4
++	vamoswapei8.v v4, (a1), v8, v4, v0.t
++	vamoswapei8.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, (a1), v8, v4
++	vamoxorei8.v x0, (a1), v8, v4
++	vamoxorei8.v v4, (a1), v8, v4, v0.t
++	vamoxorei8.v x0, (a1), v8, v4, v0.t
++	vamoandei8.v v4, (a1), v8, v4
++	vamoandei8.v x0, (a1), v8, v4
++	vamoandei8.v v4, (a1), v8, v4, v0.t
++	vamoandei8.v x0, (a1), v8, v4, v0.t
++	vamoorei8.v v4, (a1), v8, v4
++	vamoorei8.v x0, (a1), v8, v4
++	vamoorei8.v v4, (a1), v8, v4, v0.t
++	vamoorei8.v x0, (a1), v8, v4, v0.t
++
++	vamominei8.v v4, (a1), v8, v4
++	vamominei8.v x0, (a1), v8, v4
++	vamominei8.v v4, (a1), v8, v4, v0.t
++	vamominei8.v x0, (a1), v8, v4, v0.t
++	vamomaxei8.v v4, (a1), v8, v4
++	vamomaxei8.v x0, (a1), v8, v4
++	vamomaxei8.v v4, (a1), v8, v4, v0.t
++	vamomaxei8.v x0, (a1), v8, v4, v0.t
++	vamominuei8.v v4, (a1), v8, v4
++	vamominuei8.v x0, (a1), v8, v4
++	vamominuei8.v v4, (a1), v8, v4, v0.t
++	vamominuei8.v x0, (a1), v8, v4, v0.t
++	vamomaxuei8.v v4, (a1), v8, v4
++	vamomaxuei8.v x0, (a1), v8, v4
++	vamomaxuei8.v v4, (a1), v8, v4, v0.t
++	vamomaxuei8.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei8.v v4, 0(a1), v8, v4
++	vamoaddei8.v x0, 0(a1), v8, v4
++	vamoaddei8.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei8.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei8.v v4, 0(a1), v8, v4
++	vamoswapei8.v x0, 0(a1), v8, v4
++	vamoswapei8.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei8.v v4, 0(a1), v8, v4
++	vamoxorei8.v x0, 0(a1), v8, v4
++	vamoxorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei8.v x0, 0(a1), v8, v4, v0.t
++	vamoandei8.v v4, 0(a1), v8, v4
++	vamoandei8.v x0, 0(a1), v8, v4
++	vamoandei8.v v4, 0(a1), v8, v4, v0.t
++	vamoandei8.v x0, 0(a1), v8, v4, v0.t
++	vamoorei8.v v4, 0(a1), v8, v4
++	vamoorei8.v x0, 0(a1), v8, v4
++	vamoorei8.v v4, 0(a1), v8, v4, v0.t
++	vamoorei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei8.v v4, 0(a1), v8, v4
++	vamominei8.v x0, 0(a1), v8, v4
++	vamominei8.v v4, 0(a1), v8, v4, v0.t
++	vamominei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei8.v v4, 0(a1), v8, v4
++	vamomaxei8.v x0, 0(a1), v8, v4
++	vamomaxei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei8.v x0, 0(a1), v8, v4, v0.t
++	vamominuei8.v v4, 0(a1), v8, v4
++	vamominuei8.v x0, 0(a1), v8, v4
++	vamominuei8.v v4, 0(a1), v8, v4, v0.t
++	vamominuei8.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v v4, 0(a1), v8, v4
++	vamomaxuei8.v x0, 0(a1), v8, v4
++	vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, (a1), v8, v4
++	vamoaddei16.v x0, (a1), v8, v4
++	vamoaddei16.v v4, (a1), v8, v4, v0.t
++	vamoaddei16.v x0, (a1), v8, v4, v0.t
++	vamoswapei16.v v4, (a1), v8, v4
++	vamoswapei16.v x0, (a1), v8, v4
++	vamoswapei16.v v4, (a1), v8, v4, v0.t
++	vamoswapei16.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, (a1), v8, v4
++	vamoxorei16.v x0, (a1), v8, v4
++	vamoxorei16.v v4, (a1), v8, v4, v0.t
++	vamoxorei16.v x0, (a1), v8, v4, v0.t
++	vamoandei16.v v4, (a1), v8, v4
++	vamoandei16.v x0, (a1), v8, v4
++	vamoandei16.v v4, (a1), v8, v4, v0.t
++	vamoandei16.v x0, (a1), v8, v4, v0.t
++	vamoorei16.v v4, (a1), v8, v4
++	vamoorei16.v x0, (a1), v8, v4
++	vamoorei16.v v4, (a1), v8, v4, v0.t
++	vamoorei16.v x0, (a1), v8, v4, v0.t
++
++	vamominei16.v v4, (a1), v8, v4
++	vamominei16.v x0, (a1), v8, v4
++	vamominei16.v v4, (a1), v8, v4, v0.t
++	vamominei16.v x0, (a1), v8, v4, v0.t
++	vamomaxei16.v v4, (a1), v8, v4
++	vamomaxei16.v x0, (a1), v8, v4
++	vamomaxei16.v v4, (a1), v8, v4, v0.t
++	vamomaxei16.v x0, (a1), v8, v4, v0.t
++	vamominuei16.v v4, (a1), v8, v4
++	vamominuei16.v x0, (a1), v8, v4
++	vamominuei16.v v4, (a1), v8, v4, v0.t
++	vamominuei16.v x0, (a1), v8, v4, v0.t
++	vamomaxuei16.v v4, (a1), v8, v4
++	vamomaxuei16.v x0, (a1), v8, v4
++	vamomaxuei16.v v4, (a1), v8, v4, v0.t
++	vamomaxuei16.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei16.v v4, 0(a1), v8, v4
++	vamoaddei16.v x0, 0(a1), v8, v4
++	vamoaddei16.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei16.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei16.v v4, 0(a1), v8, v4
++	vamoswapei16.v x0, 0(a1), v8, v4
++	vamoswapei16.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei16.v v4, 0(a1), v8, v4
++	vamoxorei16.v x0, 0(a1), v8, v4
++	vamoxorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei16.v x0, 0(a1), v8, v4, v0.t
++	vamoandei16.v v4, 0(a1), v8, v4
++	vamoandei16.v x0, 0(a1), v8, v4
++	vamoandei16.v v4, 0(a1), v8, v4, v0.t
++	vamoandei16.v x0, 0(a1), v8, v4, v0.t
++	vamoorei16.v v4, 0(a1), v8, v4
++	vamoorei16.v x0, 0(a1), v8, v4
++	vamoorei16.v v4, 0(a1), v8, v4, v0.t
++	vamoorei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei16.v v4, 0(a1), v8, v4
++	vamominei16.v x0, 0(a1), v8, v4
++	vamominei16.v v4, 0(a1), v8, v4, v0.t
++	vamominei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei16.v v4, 0(a1), v8, v4
++	vamomaxei16.v x0, 0(a1), v8, v4
++	vamomaxei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei16.v x0, 0(a1), v8, v4, v0.t
++	vamominuei16.v v4, 0(a1), v8, v4
++	vamominuei16.v x0, 0(a1), v8, v4
++	vamominuei16.v v4, 0(a1), v8, v4, v0.t
++	vamominuei16.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v v4, 0(a1), v8, v4
++	vamomaxuei16.v x0, 0(a1), v8, v4
++	vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, (a1), v8, v4
++	vamoaddei32.v x0, (a1), v8, v4
++	vamoaddei32.v v4, (a1), v8, v4, v0.t
++	vamoaddei32.v x0, (a1), v8, v4, v0.t
++	vamoswapei32.v v4, (a1), v8, v4
++	vamoswapei32.v x0, (a1), v8, v4
++	vamoswapei32.v v4, (a1), v8, v4, v0.t
++	vamoswapei32.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, (a1), v8, v4
++	vamoxorei32.v x0, (a1), v8, v4
++	vamoxorei32.v v4, (a1), v8, v4, v0.t
++	vamoxorei32.v x0, (a1), v8, v4, v0.t
++	vamoandei32.v v4, (a1), v8, v4
++	vamoandei32.v x0, (a1), v8, v4
++	vamoandei32.v v4, (a1), v8, v4, v0.t
++	vamoandei32.v x0, (a1), v8, v4, v0.t
++	vamoorei32.v v4, (a1), v8, v4
++	vamoorei32.v x0, (a1), v8, v4
++	vamoorei32.v v4, (a1), v8, v4, v0.t
++	vamoorei32.v x0, (a1), v8, v4, v0.t
++
++	vamominei32.v v4, (a1), v8, v4
++	vamominei32.v x0, (a1), v8, v4
++	vamominei32.v v4, (a1), v8, v4, v0.t
++	vamominei32.v x0, (a1), v8, v4, v0.t
++	vamomaxei32.v v4, (a1), v8, v4
++	vamomaxei32.v x0, (a1), v8, v4
++	vamomaxei32.v v4, (a1), v8, v4, v0.t
++	vamomaxei32.v x0, (a1), v8, v4, v0.t
++	vamominuei32.v v4, (a1), v8, v4
++	vamominuei32.v x0, (a1), v8, v4
++	vamominuei32.v v4, (a1), v8, v4, v0.t
++	vamominuei32.v x0, (a1), v8, v4, v0.t
++	vamomaxuei32.v v4, (a1), v8, v4
++	vamomaxuei32.v x0, (a1), v8, v4
++	vamomaxuei32.v v4, (a1), v8, v4, v0.t
++	vamomaxuei32.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei32.v v4, 0(a1), v8, v4
++	vamoaddei32.v x0, 0(a1), v8, v4
++	vamoaddei32.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei32.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei32.v v4, 0(a1), v8, v4
++	vamoswapei32.v x0, 0(a1), v8, v4
++	vamoswapei32.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei32.v v4, 0(a1), v8, v4
++	vamoxorei32.v x0, 0(a1), v8, v4
++	vamoxorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei32.v x0, 0(a1), v8, v4, v0.t
++	vamoandei32.v v4, 0(a1), v8, v4
++	vamoandei32.v x0, 0(a1), v8, v4
++	vamoandei32.v v4, 0(a1), v8, v4, v0.t
++	vamoandei32.v x0, 0(a1), v8, v4, v0.t
++	vamoorei32.v v4, 0(a1), v8, v4
++	vamoorei32.v x0, 0(a1), v8, v4
++	vamoorei32.v v4, 0(a1), v8, v4, v0.t
++	vamoorei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei32.v v4, 0(a1), v8, v4
++	vamominei32.v x0, 0(a1), v8, v4
++	vamominei32.v v4, 0(a1), v8, v4, v0.t
++	vamominei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei32.v v4, 0(a1), v8, v4
++	vamomaxei32.v x0, 0(a1), v8, v4
++	vamomaxei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei32.v x0, 0(a1), v8, v4, v0.t
++	vamominuei32.v v4, 0(a1), v8, v4
++	vamominuei32.v x0, 0(a1), v8, v4
++	vamominuei32.v v4, 0(a1), v8, v4, v0.t
++	vamominuei32.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v v4, 0(a1), v8, v4
++	vamomaxuei32.v x0, 0(a1), v8, v4
++	vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, (a1), v8, v4
++	vamoaddei64.v x0, (a1), v8, v4
++	vamoaddei64.v v4, (a1), v8, v4, v0.t
++	vamoaddei64.v x0, (a1), v8, v4, v0.t
++	vamoswapei64.v v4, (a1), v8, v4
++	vamoswapei64.v x0, (a1), v8, v4
++	vamoswapei64.v v4, (a1), v8, v4, v0.t
++	vamoswapei64.v x0, (a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, (a1), v8, v4
++	vamoxorei64.v x0, (a1), v8, v4
++	vamoxorei64.v v4, (a1), v8, v4, v0.t
++	vamoxorei64.v x0, (a1), v8, v4, v0.t
++	vamoandei64.v v4, (a1), v8, v4
++	vamoandei64.v x0, (a1), v8, v4
++	vamoandei64.v v4, (a1), v8, v4, v0.t
++	vamoandei64.v x0, (a1), v8, v4, v0.t
++	vamoorei64.v v4, (a1), v8, v4
++	vamoorei64.v x0, (a1), v8, v4
++	vamoorei64.v v4, (a1), v8, v4, v0.t
++	vamoorei64.v x0, (a1), v8, v4, v0.t
++
++	vamominei64.v v4, (a1), v8, v4
++	vamominei64.v x0, (a1), v8, v4
++	vamominei64.v v4, (a1), v8, v4, v0.t
++	vamominei64.v x0, (a1), v8, v4, v0.t
++	vamomaxei64.v v4, (a1), v8, v4
++	vamomaxei64.v x0, (a1), v8, v4
++	vamomaxei64.v v4, (a1), v8, v4, v0.t
++	vamomaxei64.v x0, (a1), v8, v4, v0.t
++	vamominuei64.v v4, (a1), v8, v4
++	vamominuei64.v x0, (a1), v8, v4
++	vamominuei64.v v4, (a1), v8, v4, v0.t
++	vamominuei64.v x0, (a1), v8, v4, v0.t
++	vamomaxuei64.v v4, (a1), v8, v4
++	vamomaxuei64.v x0, (a1), v8, v4
++	vamomaxuei64.v v4, (a1), v8, v4, v0.t
++	vamomaxuei64.v x0, (a1), v8, v4, v0.t
++
++	vamoaddei64.v v4, 0(a1), v8, v4
++	vamoaddei64.v x0, 0(a1), v8, v4
++	vamoaddei64.v v4, 0(a1), v8, v4, v0.t
++	vamoaddei64.v x0, 0(a1), v8, v4, v0.t
++	vamoswapei64.v v4, 0(a1), v8, v4
++	vamoswapei64.v x0, 0(a1), v8, v4
++	vamoswapei64.v v4, 0(a1), v8, v4, v0.t
++	vamoswapei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamoxorei64.v v4, 0(a1), v8, v4
++	vamoxorei64.v x0, 0(a1), v8, v4
++	vamoxorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoxorei64.v x0, 0(a1), v8, v4, v0.t
++	vamoandei64.v v4, 0(a1), v8, v4
++	vamoandei64.v x0, 0(a1), v8, v4
++	vamoandei64.v v4, 0(a1), v8, v4, v0.t
++	vamoandei64.v x0, 0(a1), v8, v4, v0.t
++	vamoorei64.v v4, 0(a1), v8, v4
++	vamoorei64.v x0, 0(a1), v8, v4
++	vamoorei64.v v4, 0(a1), v8, v4, v0.t
++	vamoorei64.v x0, 0(a1), v8, v4, v0.t
++
++	vamominei64.v v4, 0(a1), v8, v4
++	vamominei64.v x0, 0(a1), v8, v4
++	vamominei64.v v4, 0(a1), v8, v4, v0.t
++	vamominei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxei64.v v4, 0(a1), v8, v4
++	vamomaxei64.v x0, 0(a1), v8, v4
++	vamomaxei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxei64.v x0, 0(a1), v8, v4, v0.t
++	vamominuei64.v v4, 0(a1), v8, v4
++	vamominuei64.v x0, 0(a1), v8, v4
++	vamominuei64.v v4, 0(a1), v8, v4, v0.t
++	vamominuei64.v x0, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v v4, 0(a1), v8, v4
++	vamomaxuei64.v x0, 0(a1), v8, v4
++	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
++	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
++
++	vneg.v v4, v8
++	vneg.v v4, v8, v0.t
++
++	vadd.vv v4, v8, v12
++	vadd.vx v4, v8, a1
++	vadd.vi v4, v8, 15
++	vadd.vi v4, v8, -16
++	vadd.vv v4, v8, v12, v0.t
++	vadd.vx v4, v8, a1, v0.t
++	vadd.vi v4, v8, 15, v0.t
++	vadd.vi v4, v8, -16, v0.t
++	vsub.vv v4, v8, v12
++	vsub.vx v4, v8, a1
++	vrsub.vx v4, v8, a1
++	vrsub.vi v4, v8, 15
++	vrsub.vi v4, v8, -16
++	vsub.vv v4, v8, v12, v0.t
++	vsub.vx v4, v8, a1, v0.t
++	vrsub.vx v4, v8, a1, v0.t
++	vrsub.vi v4, v8, 15, v0.t
++	vrsub.vi v4, v8, -16, v0.t
++
++	# Aliases
++	vwcvt.x.x.v v4, v8
++	vwcvtu.x.x.v v4, v8
++	vwcvt.x.x.v v4, v8, v0.t
++	vwcvtu.x.x.v v4, v8, v0.t
++
++	vwaddu.vv v4, v8, v12
++	vwaddu.vx v4, v8, a1
++	vwaddu.vv v4, v8, v12, v0.t
++	vwaddu.vx v4, v8, a1, v0.t
++	vwsubu.vv v4, v8, v12
++	vwsubu.vx v4, v8, a1
++	vwsubu.vv v4, v8, v12, v0.t
++	vwsubu.vx v4, v8, a1, v0.t
++	vwadd.vv v4, v8, v12
++	vwadd.vx v4, v8, a1
++	vwadd.vv v4, v8, v12, v0.t
++	vwadd.vx v4, v8, a1, v0.t
++	vwsub.vv v4, v8, v12
++	vwsub.vx v4, v8, a1
++	vwsub.vv v4, v8, v12, v0.t
++	vwsub.vx v4, v8, a1, v0.t
++	vwaddu.wv v4, v8, v12
++	vwaddu.wx v4, v8, a1
++	vwaddu.wv v4, v8, v12, v0.t
++	vwaddu.wx v4, v8, a1, v0.t
++	vwsubu.wv v4, v8, v12
++	vwsubu.wx v4, v8, a1
++	vwsubu.wv v4, v8, v12, v0.t
++	vwsubu.wx v4, v8, a1, v0.t
++	vwadd.wv v4, v8, v12
++	vwadd.wx v4, v8, a1
++	vwadd.wv v4, v8, v12, v0.t
++	vwadd.wx v4, v8, a1, v0.t
++	vwsub.wv v4, v8, v12
++	vwsub.wx v4, v8, a1
++	vwsub.wv v4, v8, v12, v0.t
++	vwsub.wx v4, v8, a1, v0.t
++
++	vzext.vf2 v4, v8
++	vzext.vf2 v4, v8, v0.t
++	vsext.vf2 v4, v8
++	vsext.vf2 v4, v8, v0.t
++	vzext.vf4 v4, v8
++	vzext.vf4 v4, v8, v0.t
++	vsext.vf4 v4, v8
++	vsext.vf4 v4, v8, v0.t
++	vzext.vf8 v4, v8
++	vzext.vf8 v4, v8, v0.t
++	vsext.vf8 v4, v8
++	vsext.vf8 v4, v8, v0.t
++
++	vadc.vvm v4, v8, v12, v0
++	vadc.vxm v4, v8, a1, v0
++	vadc.vim v4, v8, 15, v0
++	vadc.vim v4, v8, -16, v0
++	vmadc.vvm v4, v8, v12, v0
++	vmadc.vxm v4, v8, a1, v0
++	vmadc.vim v4, v8, 15, v0
++	vmadc.vim v4, v8, -16, v0
++	vmadc.vv v4, v8, v12
++	vmadc.vx v4, v8, a1
++	vmadc.vi v4, v8, 15
++	vmadc.vi v4, v8, -16
++	vsbc.vvm v4, v8, v12, v0
++	vsbc.vxm v4, v8, a1, v0
++	vmsbc.vvm v4, v8, v12, v0
++	vmsbc.vxm v4, v8, a1, v0
++	vmsbc.vv v4, v8, v12
++	vmsbc.vx v4, v8, a1
++
++	# Aliases
++	vnot.v v4, v8
++	vnot.v v4, v8, v0.t
++
++	vand.vv v4, v8, v12
++	vand.vx v4, v8, a1
++	vand.vi v4, v8, 15
++	vand.vi v4, v8, -16
++	vand.vv v4, v8, v12, v0.t
++	vand.vx v4, v8, a1, v0.t
++	vand.vi v4, v8, 15, v0.t
++	vand.vi v4, v8, -16, v0.t
++	vor.vv v4, v8, v12
++	vor.vx v4, v8, a1
++	vor.vi v4, v8, 15
++	vor.vi v4, v8, -16
++	vor.vv v4, v8, v12, v0.t
++	vor.vx v4, v8, a1, v0.t
++	vor.vi v4, v8, 15, v0.t
++	vor.vi v4, v8, -16, v0.t
++	vxor.vv v4, v8, v12
++	vxor.vx v4, v8, a1
++	vxor.vi v4, v8, 15
++	vxor.vi v4, v8, -16
++	vxor.vv v4, v8, v12, v0.t
++	vxor.vx v4, v8, a1, v0.t
++	vxor.vi v4, v8, 15, v0.t
++	vxor.vi v4, v8, -16, v0.t
++
++	vsll.vv v4, v8, v12
++	vsll.vx v4, v8, a1
++	vsll.vi v4, v8, 1
++	vsll.vi v4, v8, 31
++	vsll.vv v4, v8, v12, v0.t
++	vsll.vx v4, v8, a1, v0.t
++	vsll.vi v4, v8, 1, v0.t
++	vsll.vi v4, v8, 31, v0.t
++	vsrl.vv v4, v8, v12
++	vsrl.vx v4, v8, a1
++	vsrl.vi v4, v8, 1
++	vsrl.vi v4, v8, 31
++	vsrl.vv v4, v8, v12, v0.t
++	vsrl.vx v4, v8, a1, v0.t
++	vsrl.vi v4, v8, 1, v0.t
++	vsrl.vi v4, v8, 31, v0.t
++	vsra.vv v4, v8, v12
++	vsra.vx v4, v8, a1
++	vsra.vi v4, v8, 1
++	vsra.vi v4, v8, 31
++	vsra.vv v4, v8, v12, v0.t
++	vsra.vx v4, v8, a1, v0.t
++	vsra.vi v4, v8, 1, v0.t
++	vsra.vi v4, v8, 31, v0.t
++
++	# Aliases
++	vncvt.x.x.w v4, v8
++	vncvt.x.x.w v4, v8, v0.t
++
++	vnsrl.wv v4, v8, v12
++	vnsrl.wx v4, v8, a1
++	vnsrl.wi v4, v8, 1
++	vnsrl.wi v4, v8, 31
++	vnsrl.wv v4, v8, v12, v0.t
++	vnsrl.wx v4, v8, a1, v0.t
++	vnsrl.wi v4, v8, 1, v0.t
++	vnsrl.wi v4, v8, 31, v0.t
++	vnsra.wv v4, v8, v12
++	vnsra.wx v4, v8, a1
++	vnsra.wi v4, v8, 1
++	vnsra.wi v4, v8, 31
++	vnsra.wv v4, v8, v12, v0.t
++	vnsra.wx v4, v8, a1, v0.t
++	vnsra.wi v4, v8, 1, v0.t
++	vnsra.wi v4, v8, 31, v0.t
++
++	# Aliases
++	vmsgt.vv v4, v8, v12
++	vmsgtu.vv v4, v8, v12
++	vmsge.vv v4, v8, v12
++	vmsgeu.vv v4, v8, v12
++	vmsgt.vv v4, v8, v12, v0.t
++	vmsgtu.vv v4, v8, v12, v0.t
++	vmsge.vv v4, v8, v12, v0.t
++	vmsgeu.vv v4, v8, v12, v0.t
++	vmslt.vi v4, v8, 16
++	vmslt.vi v4, v8, -15
++	vmsltu.vi v4, v8, 16
++	vmsltu.vi v4, v8, -15
++	vmsge.vi v4, v8, 16
++	vmsge.vi v4, v8, -15
++	vmsgeu.vi v4, v8, 16
++	vmsgeu.vi v4, v8, -15
++	vmslt.vi v4, v8, 16, v0.t
++	vmslt.vi v4, v8, -15, v0.t
++	vmsltu.vi v4, v8, 16, v0.t
++	vmsltu.vi v4, v8, -15, v0.t
++	vmsge.vi v4, v8, 16, v0.t
++	vmsge.vi v4, v8, -15, v0.t
++	vmsgeu.vi v4, v8, 16, v0.t
++	vmsgeu.vi v4, v8, -15, v0.t
++
++	vmseq.vv v4, v8, v12
++	vmseq.vx v4, v8, a1
++	vmseq.vi v4, v8, 15
++	vmseq.vi v4, v8, -16
++	vmseq.vv v4, v8, v12, v0.t
++	vmseq.vx v4, v8, a1, v0.t
++	vmseq.vi v4, v8, 15, v0.t
++	vmseq.vi v4, v8, -16, v0.t
++	vmsne.vv v4, v8, v12
++	vmsne.vx v4, v8, a1
++	vmsne.vi v4, v8, 15
++	vmsne.vi v4, v8, -16
++	vmsne.vv v4, v8, v12, v0.t
++	vmsne.vx v4, v8, a1, v0.t
++	vmsne.vi v4, v8, 15, v0.t
++	vmsne.vi v4, v8, -16, v0.t
++	vmsltu.vv v4, v8, v12
++	vmsltu.vx v4, v8, a1
++	vmsltu.vv v4, v8, v12, v0.t
++	vmsltu.vx v4, v8, a1, v0.t
++	vmslt.vv v4, v8, v12
++	vmslt.vx v4, v8, a1
++	vmslt.vv v4, v8, v12, v0.t
++	vmslt.vx v4, v8, a1, v0.t
++	vmsleu.vv v4, v8, v12
++	vmsleu.vx v4, v8, a1
++	vmsleu.vi v4, v8, 15
++	vmsleu.vi v4, v8, -16
++	vmsleu.vv v4, v8, v12, v0.t
++	vmsleu.vx v4, v8, a1, v0.t
++	vmsleu.vi v4, v8, 15, v0.t
++	vmsleu.vi v4, v8, -16, v0.t
++	vmsle.vv v4, v8, v12
++	vmsle.vx v4, v8, a1
++	vmsle.vi v4, v8, 15
++	vmsle.vi v4, v8, -16
++	vmsle.vv v4, v8, v12, v0.t
++	vmsle.vx v4, v8, a1, v0.t
++	vmsle.vi v4, v8, 15, v0.t
++	vmsle.vi v4, v8, -16, v0.t
++	vmsgtu.vx v4, v8, a1
++	vmsgtu.vi v4, v8, 15
++	vmsgtu.vi v4, v8, -16
++	vmsgtu.vx v4, v8, a1, v0.t
++	vmsgtu.vi v4, v8, 15, v0.t
++	vmsgtu.vi v4, v8, -16, v0.t
++	vmsgt.vx v4, v8, a1
++	vmsgt.vi v4, v8, 15
++	vmsgt.vi v4, v8, -16
++	vmsgt.vx v4, v8, a1, v0.t
++	vmsgt.vi v4, v8, 15, v0.t
++	vmsgt.vi v4, v8, -16, v0.t
++
++	vminu.vv v4, v8, v12
++	vminu.vx v4, v8, a1
++	vminu.vv v4, v8, v12, v0.t
++	vminu.vx v4, v8, a1, v0.t
++	vmin.vv v4, v8, v12
++	vmin.vx v4, v8, a1
++	vmin.vv v4, v8, v12, v0.t
++	vmin.vx v4, v8, a1, v0.t
++	vmaxu.vv v4, v8, v12
++	vmaxu.vx v4, v8, a1
++	vmaxu.vv v4, v8, v12, v0.t
++	vmaxu.vx v4, v8, a1, v0.t
++	vmax.vv v4, v8, v12
++	vmax.vx v4, v8, a1
++	vmax.vv v4, v8, v12, v0.t
++	vmax.vx v4, v8, a1, v0.t
++
++	vmul.vv v4, v8, v12
++	vmul.vx v4, v8, a1
++	vmul.vv v4, v8, v12, v0.t
++	vmul.vx v4, v8, a1, v0.t
++	vmulh.vv v4, v8, v12
++	vmulh.vx v4, v8, a1
++	vmulh.vv v4, v8, v12, v0.t
++	vmulh.vx v4, v8, a1, v0.t
++	vmulhu.vv v4, v8, v12
++	vmulhu.vx v4, v8, a1
++	vmulhu.vv v4, v8, v12, v0.t
++	vmulhu.vx v4, v8, a1, v0.t
++	vmulhsu.vv v4, v8, v12
++	vmulhsu.vx v4, v8, a1
++	vmulhsu.vv v4, v8, v12, v0.t
++	vmulhsu.vx v4, v8, a1, v0.t
++
++	vwmul.vv v4, v8, v12
++	vwmul.vx v4, v8, a1
++	vwmul.vv v4, v8, v12, v0.t
++	vwmul.vx v4, v8, a1, v0.t
++	vwmulu.vv v4, v8, v12
++	vwmulu.vx v4, v8, a1
++	vwmulu.vv v4, v8, v12, v0.t
++	vwmulu.vx v4, v8, a1, v0.t
++	vwmulsu.vv v4, v8, v12
++	vwmulsu.vx v4, v8, a1
++	vwmulsu.vv v4, v8, v12, v0.t
++	vwmulsu.vx v4, v8, a1, v0.t
++
++	vmacc.vv v4, v12, v8
++	vmacc.vx v4, a1, v8
++	vmacc.vv v4, v12, v8, v0.t
++	vmacc.vx v4, a1, v8, v0.t
++	vnmsac.vv v4, v12, v8
++	vnmsac.vx v4, a1, v8
++	vnmsac.vv v4, v12, v8, v0.t
++	vnmsac.vx v4, a1, v8, v0.t
++	vmadd.vv v4, v12, v8
++	vmadd.vx v4, a1, v8
++	vmadd.vv v4, v12, v8, v0.t
++	vmadd.vx v4, a1, v8, v0.t
++	vnmsub.vv v4, v12, v8
++	vnmsub.vx v4, a1, v8
++	vnmsub.vv v4, v12, v8, v0.t
++	vnmsub.vx v4, a1, v8, v0.t
++
++	vwmaccu.vv v4, v12, v8
++	vwmaccu.vx v4, a1, v8
++	vwmaccu.vv v4, v12, v8, v0.t
++	vwmaccu.vx v4, a1, v8, v0.t
++	vwmacc.vv v4, v12, v8
++	vwmacc.vx v4, a1, v8
++	vwmacc.vv v4, v12, v8, v0.t
++	vwmacc.vx v4, a1, v8, v0.t
++	vwmaccsu.vv v4, v12, v8
++	vwmaccsu.vx v4, a1, v8
++	vwmaccsu.vv v4, v12, v8, v0.t
++	vwmaccsu.vx v4, a1, v8, v0.t
++	vwmaccus.vx v4, a1, v8
++	vwmaccus.vx v4, a1, v8, v0.t
++
++	vdivu.vv v4, v8, v12
++	vdivu.vx v4, v8, a1
++	vdivu.vv v4, v8, v12, v0.t
++	vdivu.vx v4, v8, a1, v0.t
++	vdiv.vv v4, v8, v12
++	vdiv.vx v4, v8, a1
++	vdiv.vv v4, v8, v12, v0.t
++	vdiv.vx v4, v8, a1, v0.t
++	vremu.vv v4, v8, v12
++	vremu.vx v4, v8, a1
++	vremu.vv v4, v8, v12, v0.t
++	vremu.vx v4, v8, a1, v0.t
++	vrem.vv v4, v8, v12
++	vrem.vx v4, v8, a1
++	vrem.vv v4, v8, v12, v0.t
++	vrem.vx v4, v8, a1, v0.t
++
++	vmerge.vvm v4, v8, v12, v0
++	vmerge.vxm v4, v8, a1, v0
++	vmerge.vim v4, v8, 15, v0
++	vmerge.vim v4, v8, -16, v0
++
++	vmv.v.v v8, v12
++	vmv.v.x v8, a1
++	vmv.v.i v8, 15
++	vmv.v.i v8, -16
++
++	vsaddu.vv v4, v8, v12
++	vsaddu.vx v4, v8, a1
++	vsaddu.vi v4, v8, 15
++	vsaddu.vi v4, v8, -16
++	vsaddu.vv v4, v8, v12, v0.t
++	vsaddu.vx v4, v8, a1, v0.t
++	vsaddu.vi v4, v8, 15, v0.t
++	vsaddu.vi v4, v8, -16, v0.t
++	vsadd.vv v4, v8, v12
++	vsadd.vx v4, v8, a1
++	vsadd.vi v4, v8, 15
++	vsadd.vi v4, v8, -16
++	vsadd.vv v4, v8, v12, v0.t
++	vsadd.vx v4, v8, a1, v0.t
++	vsadd.vi v4, v8, 15, v0.t
++	vsadd.vi v4, v8, -16, v0.t
++	vssubu.vv v4, v8, v12
++	vssubu.vx v4, v8, a1
++	vssubu.vv v4, v8, v12, v0.t
++	vssubu.vx v4, v8, a1, v0.t
++	vssub.vv v4, v8, v12
++	vssub.vx v4, v8, a1
++	vssub.vv v4, v8, v12, v0.t
++	vssub.vx v4, v8, a1, v0.t
++
++	vaaddu.vv v4, v8, v12
++	vaaddu.vx v4, v8, a1
++	vaaddu.vv v4, v8, v12, v0.t
++	vaaddu.vx v4, v8, a1, v0.t
++	vaadd.vv v4, v8, v12
++	vaadd.vx v4, v8, a1
++	vaadd.vv v4, v8, v12, v0.t
++	vaadd.vx v4, v8, a1, v0.t
++	vasubu.vv v4, v8, v12
++	vasubu.vx v4, v8, a1
++	vasubu.vv v4, v8, v12, v0.t
++	vasubu.vx v4, v8, a1, v0.t
++	vasub.vv v4, v8, v12
++	vasub.vx v4, v8, a1
++	vasub.vv v4, v8, v12, v0.t
++	vasub.vx v4, v8, a1, v0.t
++
++	vsmul.vv v4, v8, v12
++	vsmul.vx v4, v8, a1
++	vsmul.vv v4, v8, v12, v0.t
++	vsmul.vx v4, v8, a1, v0.t
++
++	vssrl.vv v4, v8, v12
++	vssrl.vx v4, v8, a1
++	vssrl.vi v4, v8, 1
++	vssrl.vi v4, v8, 31
++	vssrl.vv v4, v8, v12, v0.t
++	vssrl.vx v4, v8, a1, v0.t
++	vssrl.vi v4, v8, 1, v0.t
++	vssrl.vi v4, v8, 31, v0.t
++	vssra.vv v4, v8, v12
++	vssra.vx v4, v8, a1
++	vssra.vi v4, v8, 1
++	vssra.vi v4, v8, 31
++	vssra.vv v4, v8, v12, v0.t
++	vssra.vx v4, v8, a1, v0.t
++	vssra.vi v4, v8, 1, v0.t
++	vssra.vi v4, v8, 31, v0.t
++
++	vnclipu.wv v4, v8, v12
++	vnclipu.wx v4, v8, a1
++	vnclipu.wi v4, v8, 1
++	vnclipu.wi v4, v8, 31
++	vnclipu.wv v4, v8, v12, v0.t
++	vnclipu.wx v4, v8, a1, v0.t
++	vnclipu.wi v4, v8, 1, v0.t
++	vnclipu.wi v4, v8, 31, v0.t
++	vnclip.wv v4, v8, v12
++	vnclip.wx v4, v8, a1
++	vnclip.wi v4, v8, 1
++	vnclip.wi v4, v8, 31
++	vnclip.wv v4, v8, v12, v0.t
++	vnclip.wx v4, v8, a1, v0.t
++	vnclip.wi v4, v8, 1, v0.t
++	vnclip.wi v4, v8, 31, v0.t
++
++	vfadd.vv v4, v8, v12
++	vfadd.vf v4, v8, fa2
++	vfadd.vv v4, v8, v12, v0.t
++	vfadd.vf v4, v8, fa2, v0.t
++	vfsub.vv v4, v8, v12
++	vfsub.vf v4, v8, fa2
++	vfsub.vv v4, v8, v12, v0.t
++	vfsub.vf v4, v8, fa2, v0.t
++	vfrsub.vf v4, v8, fa2
++	vfrsub.vf v4, v8, fa2, v0.t
++
++	vfwadd.vv v4, v8, v12
++	vfwadd.vf v4, v8, fa2
++	vfwadd.vv v4, v8, v12, v0.t
++	vfwadd.vf v4, v8, fa2, v0.t
++	vfwsub.vv v4, v8, v12
++	vfwsub.vf v4, v8, fa2
++	vfwsub.vv v4, v8, v12, v0.t
++	vfwsub.vf v4, v8, fa2, v0.t
++	vfwadd.wv v4, v8, v12
++	vfwadd.wf v4, v8, fa2
++	vfwadd.wv v4, v8, v12, v0.t
++	vfwadd.wf v4, v8, fa2, v0.t
++	vfwsub.wv v4, v8, v12
++	vfwsub.wf v4, v8, fa2
++	vfwsub.wv v4, v8, v12, v0.t
++	vfwsub.wf v4, v8, fa2, v0.t
++
++	vfmul.vv v4, v8, v12
++	vfmul.vf v4, v8, fa2
++	vfmul.vv v4, v8, v12, v0.t
++	vfmul.vf v4, v8, fa2, v0.t
++	vfdiv.vv v4, v8, v12
++	vfdiv.vf v4, v8, fa2
++	vfdiv.vv v4, v8, v12, v0.t
++	vfdiv.vf v4, v8, fa2, v0.t
++	vfrdiv.vf v4, v8, fa2
++	vfrdiv.vf v4, v8, fa2, v0.t
++
++	vfwmul.vv v4, v8, v12
++	vfwmul.vf v4, v8, fa2
++	vfwmul.vv v4, v8, v12, v0.t
++	vfwmul.vf v4, v8, fa2, v0.t
++
++	vfmadd.vv v4, v12, v8
++	vfmadd.vf v4, fa2, v8
++	vfnmadd.vv v4, v12, v8
++	vfnmadd.vf v4, fa2, v8
++	vfmsub.vv v4, v12, v8
++	vfmsub.vf v4, fa2, v8
++	vfnmsub.vv v4, v12, v8
++	vfnmsub.vf v4, fa2, v8
++	vfmadd.vv v4, v12, v8, v0.t
++	vfmadd.vf v4, fa2, v8, v0.t
++	vfnmadd.vv v4, v12, v8, v0.t
++	vfnmadd.vf v4, fa2, v8, v0.t
++	vfmsub.vv v4, v12, v8, v0.t
++	vfmsub.vf v4, fa2, v8, v0.t
++	vfnmsub.vv v4, v12, v8, v0.t
++	vfnmsub.vf v4, fa2, v8, v0.t
++	vfmacc.vv v4, v12, v8
++	vfmacc.vf v4, fa2, v8
++	vfnmacc.vv v4, v12, v8
++	vfnmacc.vf v4, fa2, v8
++	vfmsac.vv v4, v12, v8
++	vfmsac.vf v4, fa2, v8
++	vfnmsac.vv v4, v12, v8
++	vfnmsac.vf v4, fa2, v8
++	vfmacc.vv v4, v12, v8, v0.t
++	vfmacc.vf v4, fa2, v8, v0.t
++	vfnmacc.vv v4, v12, v8, v0.t
++	vfnmacc.vf v4, fa2, v8, v0.t
++	vfmsac.vv v4, v12, v8, v0.t
++	vfmsac.vf v4, fa2, v8, v0.t
++	vfnmsac.vv v4, v12, v8, v0.t
++	vfnmsac.vf v4, fa2, v8, v0.t
++
++	vfwmacc.vv v4, v12, v8
++	vfwmacc.vf v4, fa2, v8
++	vfwnmacc.vv v4, v12, v8
++	vfwnmacc.vf v4, fa2, v8
++	vfwmsac.vv v4, v12, v8
++	vfwmsac.vf v4, fa2, v8
++	vfwnmsac.vv v4, v12, v8
++	vfwnmsac.vf v4, fa2, v8
++	vfwmacc.vv v4, v12, v8, v0.t
++	vfwmacc.vf v4, fa2, v8, v0.t
++	vfwnmacc.vv v4, v12, v8, v0.t
++	vfwnmacc.vf v4, fa2, v8, v0.t
++	vfwmsac.vv v4, v12, v8, v0.t
++	vfwmsac.vf v4, fa2, v8, v0.t
++	vfwnmsac.vv v4, v12, v8, v0.t
++	vfwnmsac.vf v4, fa2, v8, v0.t
++
++	vfsqrt.v v4, v8
++	vfsqrt.v v4, v8, v0.t
++	vfrsqrte7.v v4, v8
++	vfrsqrte7.v v4, v8, v0.t
++	vfrsqrt7.v v4, v8
++	vfrsqrt7.v v4, v8, v0.t
++	vfrece7.v v4, v8
++	vfrece7.v v4, v8, v0.t
++	vfrec7.v v4, v8
++	vfrec7.v v4, v8, v0.t
++	vfclass.v v4, v8
++	vfclass.v v4, v8, v0.t
++
++	vfmin.vv v4, v8, v12
++	vfmin.vf v4, v8, fa2
++	vfmax.vv v4, v8, v12
++	vfmax.vf v4, v8, fa2
++	vfmin.vv v4, v8, v12, v0.t
++	vfmin.vf v4, v8, fa2, v0.t
++	vfmax.vv v4, v8, v12, v0.t
++	vfmax.vf v4, v8, fa2, v0.t
++
++	vfneg.v v4, v8
++	vfneg.v v4, v8, v0.t
++	vfabs.v v4, v8
++	vfabs.v v4, v8, v0.t
++
++	vfsgnj.vv v4, v8, v12
++	vfsgnj.vf v4, v8, fa2
++	vfsgnjn.vv v4, v8, v12
++	vfsgnjn.vf v4, v8, fa2
++	vfsgnjx.vv v4, v8, v12
++	vfsgnjx.vf v4, v8, fa2
++	vfsgnj.vv v4, v8, v12, v0.t
++	vfsgnj.vf v4, v8, fa2, v0.t
++	vfsgnjn.vv v4, v8, v12, v0.t
++	vfsgnjn.vf v4, v8, fa2, v0.t
++	vfsgnjx.vv v4, v8, v12, v0.t
++	vfsgnjx.vf v4, v8, fa2, v0.t
++
++	# Aliases
++	vmfgt.vv v4, v8, v12
++	vmfge.vv v4, v8, v12
++	vmfgt.vv v4, v8, v12, v0.t
++	vmfge.vv v4, v8, v12, v0.t
++
++	vmfeq.vv v4, v8, v12
++	vmfeq.vf v4, v8, fa2
++	vmfne.vv v4, v8, v12
++	vmfne.vf v4, v8, fa2
++	vmflt.vv v4, v8, v12
++	vmflt.vf v4, v8, fa2
++	vmfle.vv v4, v8, v12
++	vmfle.vf v4, v8, fa2
++	vmfgt.vf v4, v8, fa2
++	vmfge.vf v4, v8, fa2
++	vmfeq.vv v4, v8, v12, v0.t
++	vmfeq.vf v4, v8, fa2, v0.t
++	vmfne.vv v4, v8, v12, v0.t
++	vmfne.vf v4, v8, fa2, v0.t
++	vmflt.vv v4, v8, v12, v0.t
++	vmflt.vf v4, v8, fa2, v0.t
++	vmfle.vv v4, v8, v12, v0.t
++	vmfle.vf v4, v8, fa2, v0.t
++	vmfgt.vf v4, v8, fa2, v0.t
++	vmfge.vf v4, v8, fa2, v0.t
++
++	vfmerge.vfm v4, v8, fa2, v0
++	vfmv.v.f v4, fa1
++
++	vfcvt.xu.f.v v4, v8
++	vfcvt.x.f.v v4, v8
++	vfcvt.rtz.xu.f.v v4, v8
++	vfcvt.rtz.x.f.v v4, v8
++	vfcvt.f.xu.v v4, v8
++	vfcvt.f.x.v v4, v8
++	vfcvt.xu.f.v v4, v8, v0.t
++	vfcvt.x.f.v v4, v8, v0.t
++	vfcvt.rtz.xu.f.v v4, v8, v0.t
++	vfcvt.rtz.x.f.v v4, v8, v0.t
++	vfcvt.f.xu.v v4, v8, v0.t
++	vfcvt.f.x.v v4, v8, v0.t
++
++	vfwcvt.xu.f.v v4, v8
++	vfwcvt.x.f.v v4, v8
++	vfwcvt.rtz.xu.f.v v4, v8
++	vfwcvt.rtz.x.f.v v4, v8
++	vfwcvt.f.xu.v v4, v8
++	vfwcvt.f.x.v v4, v8
++	vfwcvt.f.f.v v4, v8
++	vfwcvt.xu.f.v v4, v8, v0.t
++	vfwcvt.x.f.v v4, v8, v0.t
++	vfwcvt.rtz.xu.f.v v4, v8, v0.t
++	vfwcvt.rtz.x.f.v v4, v8, v0.t
++	vfwcvt.f.xu.v v4, v8, v0.t
++	vfwcvt.f.x.v v4, v8, v0.t
++	vfwcvt.f.f.v v4, v8, v0.t
++
++	vfncvt.xu.f.w v4, v8
++	vfncvt.x.f.w v4, v8
++	vfncvt.rtz.xu.f.w v4, v8
++	vfncvt.rtz.x.f.w v4, v8
++	vfncvt.f.xu.w v4, v8
++	vfncvt.f.x.w v4, v8
++	vfncvt.f.f.w v4, v8
++	vfncvt.rod.f.f.w v4, v8
++	vfncvt.xu.f.w v4, v8, v0.t
++	vfncvt.x.f.w v4, v8, v0.t
++	vfncvt.rtz.xu.f.w v4, v8, v0.t
++	vfncvt.rtz.x.f.w v4, v8, v0.t
++	vfncvt.f.xu.w v4, v8, v0.t
++	vfncvt.f.x.w v4, v8, v0.t
++	vfncvt.f.f.w v4, v8, v0.t
++	vfncvt.rod.f.f.w v4, v8, v0.t
++
++	vredsum.vs v4, v8, v12
++	vredmaxu.vs v4, v8, v8
++	vredmax.vs v4, v8, v8
++	vredminu.vs v4, v8, v8
++	vredmin.vs v4, v8, v8
++	vredand.vs v4, v8, v12
++	vredor.vs v4, v8, v12
++	vredxor.vs v4, v8, v12
++	vredsum.vs v4, v8, v12, v0.t
++	vredmaxu.vs v4, v8, v8, v0.t
++	vredmax.vs v4, v8, v8, v0.t
++	vredminu.vs v4, v8, v8, v0.t
++	vredmin.vs v4, v8, v8, v0.t
++	vredand.vs v4, v8, v12, v0.t
++	vredor.vs v4, v8, v12, v0.t
++	vredxor.vs v4, v8, v12, v0.t
++
++	vwredsumu.vs v4, v8, v12
++	vwredsum.vs v4, v8, v12
++	vwredsumu.vs v4, v8, v12, v0.t
++	vwredsum.vs v4, v8, v12, v0.t
++
++	vfredosum.vs v4, v8, v12
++	vfredsum.vs v4, v8, v12
++	vfredmax.vs v4, v8, v12
++	vfredmin.vs v4, v8, v12
++	vfredosum.vs v4, v8, v12, v0.t
++	vfredsum.vs v4, v8, v12, v0.t
++	vfredmax.vs v4, v8, v12, v0.t
++	vfredmin.vs v4, v8, v12, v0.t
++
++	vfwredosum.vs v4, v8, v12
++	vfwredsum.vs v4, v8, v12
++	vfwredosum.vs v4, v8, v12, v0.t
++	vfwredsum.vs v4, v8, v12, v0.t
++
++	# Aliases
++	vmcpy.m v4, v8
++	vmmv.m v4, v8
++	vmclr.m v4
++	vmset.m v4
++	vmnot.m v4, v8
++
++	vmand.mm v4, v8, v12
++	vmnand.mm v4, v8, v12
++	vmandnot.mm v4, v8, v12
++	vmxor.mm v4, v8, v12
++	vmor.mm v4, v8, v12
++	vmnor.mm v4, v8, v12
++	vmornot.mm v4, v8, v12
++	vmxnor.mm v4, v8, v12
++
++	vpopc.m a0, v12
++	vfirst.m a0, v12
++	vmsbf.m v4, v8
++	vmsif.m v4, v8
++	vmsof.m v4, v8
++	viota.m v4, v8
++	vid.v v4
++	vpopc.m a0, v12, v0.t
++	vfirst.m a0, v12, v0.t
++	vmsbf.m v4, v8, v0.t
++	vmsif.m v4, v8, v0.t
++	vmsof.m v4, v8, v0.t
++	viota.m v4, v8, v0.t
++	vid.v v4, v0.t
++
++	vmv.x.s a0, v12
++	vmv.s.x v4, a0
++
++	vfmv.f.s fa0, v8
++	vfmv.s.f v4, fa1
++
++	vslideup.vx v4, v8, a1
++	vslideup.vi v4, v8, 0
++	vslideup.vi v4, v8, 31
++	vslidedown.vx v4, v8, a1
++	vslidedown.vi v4, v8, 0
++	vslidedown.vi v4, v8, 31
++	vslideup.vx v4, v8, a1, v0.t
++	vslideup.vi v4, v8, 0, v0.t
++	vslideup.vi v4, v8, 31, v0.t
++	vslidedown.vx v4, v8, a1, v0.t
++	vslidedown.vi v4, v8, 0, v0.t
++	vslidedown.vi v4, v8, 31, v0.t
++
++	vslide1up.vx v4, v8, a1
++	vslide1down.vx v4, v8, a1
++	vslide1up.vx v4, v8, a1, v0.t
++	vslide1down.vx v4, v8, a1, v0.t
++
++	vfslide1up.vf v4, v8, fa1
++	vfslide1down.vf v4, v8, fa1
++	vfslide1up.vf v4, v8, fa1, v0.t
++	vfslide1down.vf v4, v8, fa1, v0.t
++
++	vrgather.vv v4, v8, v12
++	vrgather.vx v4, v8, a1
++	vrgather.vi v4, v8, 0
++	vrgather.vi v4, v8, 31
++	vrgather.vv v4, v8, v12, v0.t
++	vrgather.vx v4, v8, a1, v0.t
++	vrgather.vi v4, v8, 0, v0.t
++	vrgather.vi v4, v8, 31, v0.t
++
++	vrgatherei16.vv v4, v8, v12
++	vrgatherei16.vv v4, v8, v12, v0.t
++
++	vcompress.vm v4, v8, v12
++
++	vmv1r.v v1, v2
++	vmv2r.v v2, v4
++	vmv4r.v v4, v8
++	vmv8r.v v0, v8
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
+index 1a80dbf87d..a62eada16a 100644
+--- a/include/opcode/riscv-opc.h
++++ b/include/opcode/riscv-opc.h
+@@ -755,7 +755,1903 @@
+ #define MASK_C_LDSP  0xe003
+ #define MATCH_C_SDSP 0xe002
+ #define MASK_C_SDSP  0xe003
+-/* Privileged CSR addresses.  */
++
++/* RVV */
++/* Version 1.0-draft-20210130.  */
++
++/* Temporary configuration-setting encoding info
++
++`-` means zimm
++
++31 30 zimm  RS2   RS1/uimm funct3 RD    opcode
++1  0  00000 xxxxx xxxxx    111    xxxxx 1010111 vsetvl
++1  1  ----- ----- xxxxx    111    xxxxx 1010111 vsetivli
++0  -  ----- ----- xxxxx    111    xxxxx 1010111 vsetvli
++*/
++
++#define MATCH_VSETVL   0x80007057
++#define MASK_VSETVL    0xfe00707f
++#define MATCH_VSETIVLI 0xc0007057
++#define MASK_VSETIVLI  0xc000707f
++#define MATCH_VSETVLI  0x00007057
++#define MASK_VSETVLI   0x8000707f
++
++/* Temporary Load/store encoding info
++
++MOP load
++00 unit-stride		LE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
++01 indexed-unordered	VLUXEI<EEW>
++10 strided		VLSE<EEW>
++11 indexed-ordered	VLOXEI<EEW>
++
++MOP store
++00 unit-stride		VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
++01 indexed-unordered	VSUXEI<EEW>
++10 strided		VSSE<EEW>
++11 indexed-ordered	VSOXEI<EEW>
++
++VM 0 masked
++VM 1 unmasked
++
++LUMOP
++00000 unit-stride load
++01000 unit-stride, whole registers load
++01011 unit-stride, mask load, EEW = 1
++10000 unit-stride first-fault
++xxxxx other encodings reserved, x != 0
++
++SUMOP
++00000 unit-stride store
++01000 unit-stride, whole registers store
++01011 unit-stride, mask store, EEW = 1
++0xxxx other encodings reserved, x != 0
++
++`-` means EEW =
++MEW WIDTH
++x   001   FLH/FSH
++x   010   FLW/FSW
++x   011   FLD/FSW
++x   100   FLQ/FSQ
++0   000   VLxE8/VSxE8, VLxEI8/VSxEI8, VL<nf>RE8, VS<nf>R
++0   101   VLxE16/VSxE16, VLxEI16/VSxEI16, VL<nf>RE16
++0   110   VLxE32/VSxE32, VLxEI32/VSxEI32, VL<nf>RE32
++0   111   VLxE64/VSxE64, VLxEI64/VSxEI64, VL<nf>RE64
++1   000   Reserved (VLxE128/VSxE128, VL<nf>RE128)
++1   101   Reserved (VLxE256/VSxE256, VL<nf>RE256)
++1   110   Reserved (VLxE512/VSxE512, VL<nf>RE512)
++1   111   Reserved (VLxE1024/VSxE1024, VL<nf>RE1024)
++
++NF  MEW MOP VM LUMOP/RS2 RS1   WIDTH VD    opcode
++000 -   00  x  00000     xxxxx ---   xxxxx 0000111 VLE<EEW>
++000 -   00  x  00000     xxxxx ---   xxxxx 0100111 VSE<EEW>
++000 -   00  1  01011     xxxxx ---   xxxxx 0000111 VLE, EEW = 1
++000 -   00  1  01011     xxxxx ---   xxxxx 0100111 VSE, EEW = 1
++000 -   10  x  xxxxx     xxxxx ---   xxxxx 0000111 VLSE<EEW>
++000 -   10  x  xxxxx     xxxxx ---   xxxxx 0100111 VSSE<EEW>
++000 0   11  x  xxxxx     xxxxx ---   xxxxx 0000111 VLOXE<EEW>I
++000 0   11  x  xxxxx     xxxxx ---   xxxxx 0100111 VSOXE<EEW>I
++000 0   01  x  xxxxx     xxxxx ---   xxxxx 0000111 VLUXE<EEW>I
++000 0   01  x  xxxxx     xxxxx ---   xxxxx 0100111 VSUXE<EEW>I
++000 -   00  x  10000     xxxxx ---   xxxxx 0000111 VLE<EEW>FF
++xxx -   00  1  01000     xxxxx ---   xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
++xxx 0   00  1  01000     xxxxx 000   xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
++
++xxx -   00  x  00000     xxxxx ---   xxxxx 0000111 VLSEG<nf>E<EEW>
++xxx -   00  x  00000     xxxxx ---   xxxxx 0100111 VSSEG<nf>E<EEW>
++xxx -   10  x  00000     xxxxx ---   xxxxx 0000111 VLSSEG<nf>E<EEW>
++xxx -   10  x  00000     xxxxx ---   xxxxx 0100111 VSSSEG<nf>E<EEW>
++xxx -   11  x  00000     xxxxx ---   xxxxx 0000111 VLOXSEG<nf>E<EEW>I
++xxx -   11  x  00000     xxxxx ---   xxxxx 0100111 VSOXSEG<nf>E<EEW>I
++xxx -   01  x  00000     xxxxx ---   xxxxx 0000111 VLUXSEG<nf>E<EEW>I
++xxx -   01  x  00000     xxxxx ---   xxxxx 0100111 VSUXSEG<nf>E<EEW>I
++xxx -   00  x  10000     xxxxx ---   xxxxx 0000111 VLSEG<nf>E<EEW>FF
++*/
++
++#define MATCH_VLE1V    0x02b00007
++#define MASK_VLE1V     0xfff0707f
++#define MATCH_VSE1V    0x02b00027
++#define MASK_VSE1V     0xfff0707f
++
++#define MATCH_VLE8V    0x00000007
++#define MASK_VLE8V     0xfdf0707f
++#define MATCH_VLE16V   0x00005007
++#define MASK_VLE16V    0xfdf0707f
++#define MATCH_VLE32V   0x00006007
++#define MASK_VLE32V    0xfdf0707f
++#define MATCH_VLE64V   0x00007007
++#define MASK_VLE64V    0xfdf0707f
++
++#define MATCH_VSE8V    0x00000027
++#define MASK_VSE8V     0xfdf0707f
++#define MATCH_VSE16V   0x00005027
++#define MASK_VSE16V    0xfdf0707f
++#define MATCH_VSE32V   0x00006027
++#define MASK_VSE32V    0xfdf0707f
++#define MATCH_VSE64V   0x00007027
++#define MASK_VSE64V    0xfdf0707f
++
++#define MATCH_VLSE8V    0x08000007
++#define MASK_VLSE8V     0xfc00707f
++#define MATCH_VLSE16V   0x08005007
++#define MASK_VLSE16V    0xfc00707f
++#define MATCH_VLSE32V   0x08006007
++#define MASK_VLSE32V    0xfc00707f
++#define MATCH_VLSE64V   0x08007007
++#define MASK_VLSE64V    0xfc00707f
++
++#define MATCH_VSSE8V    0x08000027
++#define MASK_VSSE8V     0xfc00707f
++#define MATCH_VSSE16V   0x08005027
++#define MASK_VSSE16V    0xfc00707f
++#define MATCH_VSSE32V   0x08006027
++#define MASK_VSSE32V    0xfc00707f
++#define MATCH_VSSE64V   0x08007027
++#define MASK_VSSE64V    0xfc00707f
++
++#define MATCH_VLOXEI8V    0x0c000007
++#define MASK_VLOXEI8V     0xfc00707f
++#define MATCH_VLOXEI16V   0x0c005007
++#define MASK_VLOXEI16V    0xfc00707f
++#define MATCH_VLOXEI32V   0x0c006007
++#define MASK_VLOXEI32V    0xfc00707f
++#define MATCH_VLOXEI64V   0x0c007007
++#define MASK_VLOXEI64V    0xfc00707f
++
++#define MATCH_VSOXEI8V    0x0c000027
++#define MASK_VSOXEI8V     0xfc00707f
++#define MATCH_VSOXEI16V   0x0c005027
++#define MASK_VSOXEI16V    0xfc00707f
++#define MATCH_VSOXEI32V   0x0c006027
++#define MASK_VSOXEI32V    0xfc00707f
++#define MATCH_VSOXEI64V   0x0c007027
++#define MASK_VSOXEI64V    0xfc00707f
++
++#define MATCH_VLUXEI8V    0x04000007
++#define MASK_VLUXEI8V     0xfc00707f
++#define MATCH_VLUXEI16V   0x04005007
++#define MASK_VLUXEI16V    0xfc00707f
++#define MATCH_VLUXEI32V   0x04006007
++#define MASK_VLUXEI32V    0xfc00707f
++#define MATCH_VLUXEI64V   0x04007007
++#define MASK_VLUXEI64V    0xfc00707f
++
++#define MATCH_VSUXEI8V    0x04000027
++#define MASK_VSUXEI8V     0xfc00707f
++#define MATCH_VSUXEI16V   0x04005027
++#define MASK_VSUXEI16V    0xfc00707f
++#define MATCH_VSUXEI32V   0x04006027
++#define MASK_VSUXEI32V    0xfc00707f
++#define MATCH_VSUXEI64V   0x04007027
++#define MASK_VSUXEI64V    0xfc00707f
++
++#define MATCH_VLE8FFV    0x01000007
++#define MASK_VLE8FFV     0xfdf0707f
++#define MATCH_VLE16FFV   0x01005007
++#define MASK_VLE16FFV    0xfdf0707f
++#define MATCH_VLE32FFV   0x01006007
++#define MASK_VLE32FFV    0xfdf0707f
++#define MATCH_VLE64FFV   0x01007007
++#define MASK_VLE64FFV    0xfdf0707f
++
++#define MATCH_VLSEG2E8V  0x20000007
++#define MASK_VLSEG2E8V   0xfdf0707f
++#define MATCH_VSSEG2E8V  0x20000027
++#define MASK_VSSEG2E8V   0xfdf0707f
++#define MATCH_VLSEG3E8V  0x40000007
++#define MASK_VLSEG3E8V   0xfdf0707f
++#define MATCH_VSSEG3E8V  0x40000027
++#define MASK_VSSEG3E8V   0xfdf0707f
++#define MATCH_VLSEG4E8V  0x60000007
++#define MASK_VLSEG4E8V   0xfdf0707f
++#define MATCH_VSSEG4E8V  0x60000027
++#define MASK_VSSEG4E8V   0xfdf0707f
++#define MATCH_VLSEG5E8V  0x80000007
++#define MASK_VLSEG5E8V   0xfdf0707f
++#define MATCH_VSSEG5E8V  0x80000027
++#define MASK_VSSEG5E8V   0xfdf0707f
++#define MATCH_VLSEG6E8V  0xa0000007
++#define MASK_VLSEG6E8V   0xfdf0707f
++#define MATCH_VSSEG6E8V  0xa0000027
++#define MASK_VSSEG6E8V   0xfdf0707f
++#define MATCH_VLSEG7E8V  0xc0000007
++#define MASK_VLSEG7E8V   0xfdf0707f
++#define MATCH_VSSEG7E8V  0xc0000027
++#define MASK_VSSEG7E8V   0xfdf0707f
++#define MATCH_VLSEG8E8V  0xe0000007
++#define MASK_VLSEG8E8V   0xfdf0707f
++#define MATCH_VSSEG8E8V  0xe0000027
++#define MASK_VSSEG8E8V   0xfdf0707f
++
++#define MATCH_VLSEG2E16V  0x20005007
++#define MASK_VLSEG2E16V   0xfdf0707f
++#define MATCH_VSSEG2E16V  0x20005027
++#define MASK_VSSEG2E16V   0xfdf0707f
++#define MATCH_VLSEG3E16V  0x40005007
++#define MASK_VLSEG3E16V   0xfdf0707f
++#define MATCH_VSSEG3E16V  0x40005027
++#define MASK_VSSEG3E16V   0xfdf0707f
++#define MATCH_VLSEG4E16V  0x60005007
++#define MASK_VLSEG4E16V   0xfdf0707f
++#define MATCH_VSSEG4E16V  0x60005027
++#define MASK_VSSEG4E16V   0xfdf0707f
++#define MATCH_VLSEG5E16V  0x80005007
++#define MASK_VLSEG5E16V   0xfdf0707f
++#define MATCH_VSSEG5E16V  0x80005027
++#define MASK_VSSEG5E16V   0xfdf0707f
++#define MATCH_VLSEG6E16V  0xa0005007
++#define MASK_VLSEG6E16V   0xfdf0707f
++#define MATCH_VSSEG6E16V  0xa0005027
++#define MASK_VSSEG6E16V   0xfdf0707f
++#define MATCH_VLSEG7E16V  0xc0005007
++#define MASK_VLSEG7E16V   0xfdf0707f
++#define MATCH_VSSEG7E16V  0xc0005027
++#define MASK_VSSEG7E16V   0xfdf0707f
++#define MATCH_VLSEG8E16V  0xe0005007
++#define MASK_VLSEG8E16V   0xfdf0707f
++#define MATCH_VSSEG8E16V  0xe0005027
++#define MASK_VSSEG8E16V   0xfdf0707f
++
++#define MATCH_VLSEG2E32V  0x20006007
++#define MASK_VLSEG2E32V   0xfdf0707f
++#define MATCH_VSSEG2E32V  0x20006027
++#define MASK_VSSEG2E32V   0xfdf0707f
++#define MATCH_VLSEG3E32V  0x40006007
++#define MASK_VLSEG3E32V   0xfdf0707f
++#define MATCH_VSSEG3E32V  0x40006027
++#define MASK_VSSEG3E32V   0xfdf0707f
++#define MATCH_VLSEG4E32V  0x60006007
++#define MASK_VLSEG4E32V   0xfdf0707f
++#define MATCH_VSSEG4E32V  0x60006027
++#define MASK_VSSEG4E32V   0xfdf0707f
++#define MATCH_VLSEG5E32V  0x80006007
++#define MASK_VLSEG5E32V   0xfdf0707f
++#define MATCH_VSSEG5E32V  0x80006027
++#define MASK_VSSEG5E32V   0xfdf0707f
++#define MATCH_VLSEG6E32V  0xa0006007
++#define MASK_VLSEG6E32V   0xfdf0707f
++#define MATCH_VSSEG6E32V  0xa0006027
++#define MASK_VSSEG6E32V   0xfdf0707f
++#define MATCH_VLSEG7E32V  0xc0006007
++#define MASK_VLSEG7E32V   0xfdf0707f
++#define MATCH_VSSEG7E32V  0xc0006027
++#define MASK_VSSEG7E32V   0xfdf0707f
++#define MATCH_VLSEG8E32V  0xe0006007
++#define MASK_VLSEG8E32V   0xfdf0707f
++#define MATCH_VSSEG8E32V  0xe0006027
++#define MASK_VSSEG8E32V   0xfdf0707f
++
++#define MATCH_VLSEG2E64V  0x20007007
++#define MASK_VLSEG2E64V   0xfdf0707f
++#define MATCH_VSSEG2E64V  0x20007027
++#define MASK_VSSEG2E64V   0xfdf0707f
++#define MATCH_VLSEG3E64V  0x40007007
++#define MASK_VLSEG3E64V   0xfdf0707f
++#define MATCH_VSSEG3E64V  0x40007027
++#define MASK_VSSEG3E64V   0xfdf0707f
++#define MATCH_VLSEG4E64V  0x60007007
++#define MASK_VLSEG4E64V   0xfdf0707f
++#define MATCH_VSSEG4E64V  0x60007027
++#define MASK_VSSEG4E64V   0xfdf0707f
++#define MATCH_VLSEG5E64V  0x80007007
++#define MASK_VLSEG5E64V   0xfdf0707f
++#define MATCH_VSSEG5E64V  0x80007027
++#define MASK_VSSEG5E64V   0xfdf0707f
++#define MATCH_VLSEG6E64V  0xa0007007
++#define MASK_VLSEG6E64V   0xfdf0707f
++#define MATCH_VSSEG6E64V  0xa0007027
++#define MASK_VSSEG6E64V   0xfdf0707f
++#define MATCH_VLSEG7E64V  0xc0007007
++#define MASK_VLSEG7E64V   0xfdf0707f
++#define MATCH_VSSEG7E64V  0xc0007027
++#define MASK_VSSEG7E64V   0xfdf0707f
++#define MATCH_VLSEG8E64V  0xe0007007
++#define MASK_VLSEG8E64V   0xfdf0707f
++#define MATCH_VSSEG8E64V  0xe0007027
++#define MASK_VSSEG8E64V   0xfdf0707f
++
++#define MATCH_VLSSEG2E8V  0x28000007
++#define MASK_VLSSEG2E8V   0xfc00707f
++#define MATCH_VSSSEG2E8V  0x28000027
++#define MASK_VSSSEG2E8V   0xfc00707f
++#define MATCH_VLSSEG3E8V  0x48000007
++#define MASK_VLSSEG3E8V   0xfc00707f
++#define MATCH_VSSSEG3E8V  0x48000027
++#define MASK_VSSSEG3E8V   0xfc00707f
++#define MATCH_VLSSEG4E8V  0x68000007
++#define MASK_VLSSEG4E8V   0xfc00707f
++#define MATCH_VSSSEG4E8V  0x68000027
++#define MASK_VSSSEG4E8V   0xfc00707f
++#define MATCH_VLSSEG5E8V  0x88000007
++#define MASK_VLSSEG5E8V   0xfc00707f
++#define MATCH_VSSSEG5E8V  0x88000027
++#define MASK_VSSSEG5E8V   0xfc00707f
++#define MATCH_VLSSEG6E8V  0xa8000007
++#define MASK_VLSSEG6E8V   0xfc00707f
++#define MATCH_VSSSEG6E8V  0xa8000027
++#define MASK_VSSSEG6E8V   0xfc00707f
++#define MATCH_VLSSEG7E8V  0xc8000007
++#define MASK_VLSSEG7E8V   0xfc00707f
++#define MATCH_VSSSEG7E8V  0xc8000027
++#define MASK_VSSSEG7E8V   0xfc00707f
++#define MATCH_VLSSEG8E8V  0xe8000007
++#define MASK_VLSSEG8E8V   0xfc00707f
++#define MATCH_VSSSEG8E8V  0xe8000027
++#define MASK_VSSSEG8E8V   0xfc00707f
++
++#define MATCH_VLSSEG2E16V  0x28005007
++#define MASK_VLSSEG2E16V   0xfc00707f
++#define MATCH_VSSSEG2E16V  0x28005027
++#define MASK_VSSSEG2E16V   0xfc00707f
++#define MATCH_VLSSEG3E16V  0x48005007
++#define MASK_VLSSEG3E16V   0xfc00707f
++#define MATCH_VSSSEG3E16V  0x48005027
++#define MASK_VSSSEG3E16V   0xfc00707f
++#define MATCH_VLSSEG4E16V  0x68005007
++#define MASK_VLSSEG4E16V   0xfc00707f
++#define MATCH_VSSSEG4E16V  0x68005027
++#define MASK_VSSSEG4E16V   0xfc00707f
++#define MATCH_VLSSEG5E16V  0x88005007
++#define MASK_VLSSEG5E16V   0xfc00707f
++#define MATCH_VSSSEG5E16V  0x88005027
++#define MASK_VSSSEG5E16V   0xfc00707f
++#define MATCH_VLSSEG6E16V  0xa8005007
++#define MASK_VLSSEG6E16V   0xfc00707f
++#define MATCH_VSSSEG6E16V  0xa8005027
++#define MASK_VSSSEG6E16V   0xfc00707f
++#define MATCH_VLSSEG7E16V  0xc8005007
++#define MASK_VLSSEG7E16V   0xfc00707f
++#define MATCH_VSSSEG7E16V  0xc8005027
++#define MASK_VSSSEG7E16V   0xfc00707f
++#define MATCH_VLSSEG8E16V  0xe8005007
++#define MASK_VLSSEG8E16V   0xfc00707f
++#define MATCH_VSSSEG8E16V  0xe8005027
++#define MASK_VSSSEG8E16V   0xfc00707f
++
++#define MATCH_VLSSEG2E32V  0x28006007
++#define MASK_VLSSEG2E32V   0xfc00707f
++#define MATCH_VSSSEG2E32V  0x28006027
++#define MASK_VSSSEG2E32V   0xfc00707f
++#define MATCH_VLSSEG3E32V  0x48006007
++#define MASK_VLSSEG3E32V   0xfc00707f
++#define MATCH_VSSSEG3E32V  0x48006027
++#define MASK_VSSSEG3E32V   0xfc00707f
++#define MATCH_VLSSEG4E32V  0x68006007
++#define MASK_VLSSEG4E32V   0xfc00707f
++#define MATCH_VSSSEG4E32V  0x68006027
++#define MASK_VSSSEG4E32V   0xfc00707f
++#define MATCH_VLSSEG5E32V  0x88006007
++#define MASK_VLSSEG5E32V   0xfc00707f
++#define MATCH_VSSSEG5E32V  0x88006027
++#define MASK_VSSSEG5E32V   0xfc00707f
++#define MATCH_VLSSEG6E32V  0xa8006007
++#define MASK_VLSSEG6E32V   0xfc00707f
++#define MATCH_VSSSEG6E32V  0xa8006027
++#define MASK_VSSSEG6E32V   0xfc00707f
++#define MATCH_VLSSEG7E32V  0xc8006007
++#define MASK_VLSSEG7E32V   0xfc00707f
++#define MATCH_VSSSEG7E32V  0xc8006027
++#define MASK_VSSSEG7E32V   0xfc00707f
++#define MATCH_VLSSEG8E32V  0xe8006007
++#define MASK_VLSSEG8E32V   0xfc00707f
++#define MATCH_VSSSEG8E32V  0xe8006027
++#define MASK_VSSSEG8E32V   0xfc00707f
++
++#define MATCH_VLSSEG2E64V  0x28007007
++#define MASK_VLSSEG2E64V   0xfc00707f
++#define MATCH_VSSSEG2E64V  0x28007027
++#define MASK_VSSSEG2E64V   0xfc00707f
++#define MATCH_VLSSEG3E64V  0x48007007
++#define MASK_VLSSEG3E64V   0xfc00707f
++#define MATCH_VSSSEG3E64V  0x48007027
++#define MASK_VSSSEG3E64V   0xfc00707f
++#define MATCH_VLSSEG4E64V  0x68007007
++#define MASK_VLSSEG4E64V   0xfc00707f
++#define MATCH_VSSSEG4E64V  0x68007027
++#define MASK_VSSSEG4E64V   0xfc00707f
++#define MATCH_VLSSEG5E64V  0x88007007
++#define MASK_VLSSEG5E64V   0xfc00707f
++#define MATCH_VSSSEG5E64V  0x88007027
++#define MASK_VSSSEG5E64V   0xfc00707f
++#define MATCH_VLSSEG6E64V  0xa8007007
++#define MASK_VLSSEG6E64V   0xfc00707f
++#define MATCH_VSSSEG6E64V  0xa8007027
++#define MASK_VSSSEG6E64V   0xfc00707f
++#define MATCH_VLSSEG7E64V  0xc8007007
++#define MASK_VLSSEG7E64V   0xfc00707f
++#define MATCH_VSSSEG7E64V  0xc8007027
++#define MASK_VSSSEG7E64V   0xfc00707f
++#define MATCH_VLSSEG8E64V  0xe8007007
++#define MASK_VLSSEG8E64V   0xfc00707f
++#define MATCH_VSSSEG8E64V  0xe8007027
++#define MASK_VSSSEG8E64V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI8V  0x2c000007
++#define MASK_VLOXSEG2EI8V   0xfc00707f
++#define MATCH_VSOXSEG2EI8V  0x2c000027
++#define MASK_VSOXSEG2EI8V   0xfc00707f
++#define MATCH_VLOXSEG3EI8V  0x4c000007
++#define MASK_VLOXSEG3EI8V   0xfc00707f
++#define MATCH_VSOXSEG3EI8V  0x4c000027
++#define MASK_VSOXSEG3EI8V   0xfc00707f
++#define MATCH_VLOXSEG4EI8V  0x6c000007
++#define MASK_VLOXSEG4EI8V   0xfc00707f
++#define MATCH_VSOXSEG4EI8V  0x6c000027
++#define MASK_VSOXSEG4EI8V   0xfc00707f
++#define MATCH_VLOXSEG5EI8V  0x8c000007
++#define MASK_VLOXSEG5EI8V   0xfc00707f
++#define MATCH_VSOXSEG5EI8V  0x8c000027
++#define MASK_VSOXSEG5EI8V   0xfc00707f
++#define MATCH_VLOXSEG6EI8V  0xac000007
++#define MASK_VLOXSEG6EI8V   0xfc00707f
++#define MATCH_VSOXSEG6EI8V  0xac000027
++#define MASK_VSOXSEG6EI8V   0xfc00707f
++#define MATCH_VLOXSEG7EI8V  0xcc000007
++#define MASK_VLOXSEG7EI8V   0xfc00707f
++#define MATCH_VSOXSEG7EI8V  0xcc000027
++#define MASK_VSOXSEG7EI8V   0xfc00707f
++#define MATCH_VLOXSEG8EI8V  0xec000007
++#define MASK_VLOXSEG8EI8V   0xfc00707f
++#define MATCH_VSOXSEG8EI8V  0xec000027
++#define MASK_VSOXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI8V  0x24000007
++#define MASK_VLUXSEG2EI8V   0xfc00707f
++#define MATCH_VSUXSEG2EI8V  0x24000027
++#define MASK_VSUXSEG2EI8V   0xfc00707f
++#define MATCH_VLUXSEG3EI8V  0x44000007
++#define MASK_VLUXSEG3EI8V   0xfc00707f
++#define MATCH_VSUXSEG3EI8V  0x44000027
++#define MASK_VSUXSEG3EI8V   0xfc00707f
++#define MATCH_VLUXSEG4EI8V  0x64000007
++#define MASK_VLUXSEG4EI8V   0xfc00707f
++#define MATCH_VSUXSEG4EI8V  0x64000027
++#define MASK_VSUXSEG4EI8V   0xfc00707f
++#define MATCH_VLUXSEG5EI8V  0x84000007
++#define MASK_VLUXSEG5EI8V   0xfc00707f
++#define MATCH_VSUXSEG5EI8V  0x84000027
++#define MASK_VSUXSEG5EI8V   0xfc00707f
++#define MATCH_VLUXSEG6EI8V  0xa4000007
++#define MASK_VLUXSEG6EI8V   0xfc00707f
++#define MATCH_VSUXSEG6EI8V  0xa4000027
++#define MASK_VSUXSEG6EI8V   0xfc00707f
++#define MATCH_VLUXSEG7EI8V  0xc4000007
++#define MASK_VLUXSEG7EI8V   0xfc00707f
++#define MATCH_VSUXSEG7EI8V  0xc4000027
++#define MASK_VSUXSEG7EI8V   0xfc00707f
++#define MATCH_VLUXSEG8EI8V  0xe4000007
++#define MASK_VLUXSEG8EI8V   0xfc00707f
++#define MATCH_VSUXSEG8EI8V  0xe4000027
++#define MASK_VSUXSEG8EI8V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI16V  0x2c005007
++#define MASK_VLOXSEG2EI16V   0xfc00707f
++#define MATCH_VSOXSEG2EI16V  0x2c005027
++#define MASK_VSOXSEG2EI16V   0xfc00707f
++#define MATCH_VLOXSEG3EI16V  0x4c005007
++#define MASK_VLOXSEG3EI16V   0xfc00707f
++#define MATCH_VSOXSEG3EI16V  0x4c005027
++#define MASK_VSOXSEG3EI16V   0xfc00707f
++#define MATCH_VLOXSEG4EI16V  0x6c005007
++#define MASK_VLOXSEG4EI16V   0xfc00707f
++#define MATCH_VSOXSEG4EI16V  0x6c005027
++#define MASK_VSOXSEG4EI16V   0xfc00707f
++#define MATCH_VLOXSEG5EI16V  0x8c005007
++#define MASK_VLOXSEG5EI16V   0xfc00707f
++#define MATCH_VSOXSEG5EI16V  0x8c005027
++#define MASK_VSOXSEG5EI16V   0xfc00707f
++#define MATCH_VLOXSEG6EI16V  0xac005007
++#define MASK_VLOXSEG6EI16V   0xfc00707f
++#define MATCH_VSOXSEG6EI16V  0xac005027
++#define MASK_VSOXSEG6EI16V   0xfc00707f
++#define MATCH_VLOXSEG7EI16V  0xcc005007
++#define MASK_VLOXSEG7EI16V   0xfc00707f
++#define MATCH_VSOXSEG7EI16V  0xcc005027
++#define MASK_VSOXSEG7EI16V   0xfc00707f
++#define MATCH_VLOXSEG8EI16V  0xec005007
++#define MASK_VLOXSEG8EI16V   0xfc00707f
++#define MATCH_VSOXSEG8EI16V  0xec005027
++#define MASK_VSOXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI16V  0x24005007
++#define MASK_VLUXSEG2EI16V   0xfc00707f
++#define MATCH_VSUXSEG2EI16V  0x24005027
++#define MASK_VSUXSEG2EI16V   0xfc00707f
++#define MATCH_VLUXSEG3EI16V  0x44005007
++#define MASK_VLUXSEG3EI16V   0xfc00707f
++#define MATCH_VSUXSEG3EI16V  0x44005027
++#define MASK_VSUXSEG3EI16V   0xfc00707f
++#define MATCH_VLUXSEG4EI16V  0x64005007
++#define MASK_VLUXSEG4EI16V   0xfc00707f
++#define MATCH_VSUXSEG4EI16V  0x64005027
++#define MASK_VSUXSEG4EI16V   0xfc00707f
++#define MATCH_VLUXSEG5EI16V  0x84005007
++#define MASK_VLUXSEG5EI16V   0xfc00707f
++#define MATCH_VSUXSEG5EI16V  0x84005027
++#define MASK_VSUXSEG5EI16V   0xfc00707f
++#define MATCH_VLUXSEG6EI16V  0xa4005007
++#define MASK_VLUXSEG6EI16V   0xfc00707f
++#define MATCH_VSUXSEG6EI16V  0xa4005027
++#define MASK_VSUXSEG6EI16V   0xfc00707f
++#define MATCH_VLUXSEG7EI16V  0xc4005007
++#define MASK_VLUXSEG7EI16V   0xfc00707f
++#define MATCH_VSUXSEG7EI16V  0xc4005027
++#define MASK_VSUXSEG7EI16V   0xfc00707f
++#define MATCH_VLUXSEG8EI16V  0xe4005007
++#define MASK_VLUXSEG8EI16V   0xfc00707f
++#define MATCH_VSUXSEG8EI16V  0xe4005027
++#define MASK_VSUXSEG8EI16V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI32V  0x2c006007
++#define MASK_VLOXSEG2EI32V   0xfc00707f
++#define MATCH_VSOXSEG2EI32V  0x2c006027
++#define MASK_VSOXSEG2EI32V   0xfc00707f
++#define MATCH_VLOXSEG3EI32V  0x4c006007
++#define MASK_VLOXSEG3EI32V   0xfc00707f
++#define MATCH_VSOXSEG3EI32V  0x4c006027
++#define MASK_VSOXSEG3EI32V   0xfc00707f
++#define MATCH_VLOXSEG4EI32V  0x6c006007
++#define MASK_VLOXSEG4EI32V   0xfc00707f
++#define MATCH_VSOXSEG4EI32V  0x6c006027
++#define MASK_VSOXSEG4EI32V   0xfc00707f
++#define MATCH_VLOXSEG5EI32V  0x8c006007
++#define MASK_VLOXSEG5EI32V   0xfc00707f
++#define MATCH_VSOXSEG5EI32V  0x8c006027
++#define MASK_VSOXSEG5EI32V   0xfc00707f
++#define MATCH_VLOXSEG6EI32V  0xac006007
++#define MASK_VLOXSEG6EI32V   0xfc00707f
++#define MATCH_VSOXSEG6EI32V  0xac006027
++#define MASK_VSOXSEG6EI32V   0xfc00707f
++#define MATCH_VLOXSEG7EI32V  0xcc006007
++#define MASK_VLOXSEG7EI32V   0xfc00707f
++#define MATCH_VSOXSEG7EI32V  0xcc006027
++#define MASK_VSOXSEG7EI32V   0xfc00707f
++#define MATCH_VLOXSEG8EI32V  0xec006007
++#define MASK_VLOXSEG8EI32V   0xfc00707f
++#define MATCH_VSOXSEG8EI32V  0xec006027
++#define MASK_VSOXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI32V  0x24006007
++#define MASK_VLUXSEG2EI32V   0xfc00707f
++#define MATCH_VSUXSEG2EI32V  0x24006027
++#define MASK_VSUXSEG2EI32V   0xfc00707f
++#define MATCH_VLUXSEG3EI32V  0x44006007
++#define MASK_VLUXSEG3EI32V   0xfc00707f
++#define MATCH_VSUXSEG3EI32V  0x44006027
++#define MASK_VSUXSEG3EI32V   0xfc00707f
++#define MATCH_VLUXSEG4EI32V  0x64006007
++#define MASK_VLUXSEG4EI32V   0xfc00707f
++#define MATCH_VSUXSEG4EI32V  0x64006027
++#define MASK_VSUXSEG4EI32V   0xfc00707f
++#define MATCH_VLUXSEG5EI32V  0x84006007
++#define MASK_VLUXSEG5EI32V   0xfc00707f
++#define MATCH_VSUXSEG5EI32V  0x84006027
++#define MASK_VSUXSEG5EI32V   0xfc00707f
++#define MATCH_VLUXSEG6EI32V  0xa4006007
++#define MASK_VLUXSEG6EI32V   0xfc00707f
++#define MATCH_VSUXSEG6EI32V  0xa4006027
++#define MASK_VSUXSEG6EI32V   0xfc00707f
++#define MATCH_VLUXSEG7EI32V  0xc4006007
++#define MASK_VLUXSEG7EI32V   0xfc00707f
++#define MATCH_VSUXSEG7EI32V  0xc4006027
++#define MASK_VSUXSEG7EI32V   0xfc00707f
++#define MATCH_VLUXSEG8EI32V  0xe4006007
++#define MASK_VLUXSEG8EI32V   0xfc00707f
++#define MATCH_VSUXSEG8EI32V  0xe4006027
++#define MASK_VSUXSEG8EI32V   0xfc00707f
++
++#define MATCH_VLOXSEG2EI64V  0x2c007007
++#define MASK_VLOXSEG2EI64V   0xfc00707f
++#define MATCH_VSOXSEG2EI64V  0x2c007027
++#define MASK_VSOXSEG2EI64V   0xfc00707f
++#define MATCH_VLOXSEG3EI64V  0x4c007007
++#define MASK_VLOXSEG3EI64V   0xfc00707f
++#define MATCH_VSOXSEG3EI64V  0x4c007027
++#define MASK_VSOXSEG3EI64V   0xfc00707f
++#define MATCH_VLOXSEG4EI64V  0x6c007007
++#define MASK_VLOXSEG4EI64V   0xfc00707f
++#define MATCH_VSOXSEG4EI64V  0x6c007027
++#define MASK_VSOXSEG4EI64V   0xfc00707f
++#define MATCH_VLOXSEG5EI64V  0x8c007007
++#define MASK_VLOXSEG5EI64V   0xfc00707f
++#define MATCH_VSOXSEG5EI64V  0x8c007027
++#define MASK_VSOXSEG5EI64V   0xfc00707f
++#define MATCH_VLOXSEG6EI64V  0xac007007
++#define MASK_VLOXSEG6EI64V   0xfc00707f
++#define MATCH_VSOXSEG6EI64V  0xac007027
++#define MASK_VSOXSEG6EI64V   0xfc00707f
++#define MATCH_VLOXSEG7EI64V  0xcc007007
++#define MASK_VLOXSEG7EI64V   0xfc00707f
++#define MATCH_VSOXSEG7EI64V  0xcc007027
++#define MASK_VSOXSEG7EI64V   0xfc00707f
++#define MATCH_VLOXSEG8EI64V  0xec007007
++#define MASK_VLOXSEG8EI64V   0xfc00707f
++#define MATCH_VSOXSEG8EI64V  0xec007027
++#define MASK_VSOXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLUXSEG2EI64V  0x24007007
++#define MASK_VLUXSEG2EI64V   0xfc00707f
++#define MATCH_VSUXSEG2EI64V  0x24007027
++#define MASK_VSUXSEG2EI64V   0xfc00707f
++#define MATCH_VLUXSEG3EI64V  0x44007007
++#define MASK_VLUXSEG3EI64V   0xfc00707f
++#define MATCH_VSUXSEG3EI64V  0x44007027
++#define MASK_VSUXSEG3EI64V   0xfc00707f
++#define MATCH_VLUXSEG4EI64V  0x64007007
++#define MASK_VLUXSEG4EI64V   0xfc00707f
++#define MATCH_VSUXSEG4EI64V  0x64007027
++#define MASK_VSUXSEG4EI64V   0xfc00707f
++#define MATCH_VLUXSEG5EI64V  0x84007007
++#define MASK_VLUXSEG5EI64V   0xfc00707f
++#define MATCH_VSUXSEG5EI64V  0x84007027
++#define MASK_VSUXSEG5EI64V   0xfc00707f
++#define MATCH_VLUXSEG6EI64V  0xa4007007
++#define MASK_VLUXSEG6EI64V   0xfc00707f
++#define MATCH_VSUXSEG6EI64V  0xa4007027
++#define MASK_VSUXSEG6EI64V   0xfc00707f
++#define MATCH_VLUXSEG7EI64V  0xc4007007
++#define MASK_VLUXSEG7EI64V   0xfc00707f
++#define MATCH_VSUXSEG7EI64V  0xc4007027
++#define MASK_VSUXSEG7EI64V   0xfc00707f
++#define MATCH_VLUXSEG8EI64V  0xe4007007
++#define MASK_VLUXSEG8EI64V   0xfc00707f
++#define MATCH_VSUXSEG8EI64V  0xe4007027
++#define MASK_VSUXSEG8EI64V   0xfc00707f
++
++#define MATCH_VLSEG2E8FFV  0x21000007
++#define MASK_VLSEG2E8FFV   0xfdf0707f
++#define MATCH_VLSEG3E8FFV  0x41000007
++#define MASK_VLSEG3E8FFV   0xfdf0707f
++#define MATCH_VLSEG4E8FFV  0x61000007
++#define MASK_VLSEG4E8FFV   0xfdf0707f
++#define MATCH_VLSEG5E8FFV  0x81000007
++#define MASK_VLSEG5E8FFV   0xfdf0707f
++#define MATCH_VLSEG6E8FFV  0xa1000007
++#define MASK_VLSEG6E8FFV   0xfdf0707f
++#define MATCH_VLSEG7E8FFV  0xc1000007
++#define MASK_VLSEG7E8FFV   0xfdf0707f
++#define MATCH_VLSEG8E8FFV  0xe1000007
++#define MASK_VLSEG8E8FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E16FFV  0x21005007
++#define MASK_VLSEG2E16FFV   0xfdf0707f
++#define MATCH_VLSEG3E16FFV  0x41005007
++#define MASK_VLSEG3E16FFV   0xfdf0707f
++#define MATCH_VLSEG4E16FFV  0x61005007
++#define MASK_VLSEG4E16FFV   0xfdf0707f
++#define MATCH_VLSEG5E16FFV  0x81005007
++#define MASK_VLSEG5E16FFV   0xfdf0707f
++#define MATCH_VLSEG6E16FFV  0xa1005007
++#define MASK_VLSEG6E16FFV   0xfdf0707f
++#define MATCH_VLSEG7E16FFV  0xc1005007
++#define MASK_VLSEG7E16FFV   0xfdf0707f
++#define MATCH_VLSEG8E16FFV  0xe1005007
++#define MASK_VLSEG8E16FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E32FFV  0x21006007
++#define MASK_VLSEG2E32FFV   0xfdf0707f
++#define MATCH_VLSEG3E32FFV  0x41006007
++#define MASK_VLSEG3E32FFV   0xfdf0707f
++#define MATCH_VLSEG4E32FFV  0x61006007
++#define MASK_VLSEG4E32FFV   0xfdf0707f
++#define MATCH_VLSEG5E32FFV  0x81006007
++#define MASK_VLSEG5E32FFV   0xfdf0707f
++#define MATCH_VLSEG6E32FFV  0xa1006007
++#define MASK_VLSEG6E32FFV   0xfdf0707f
++#define MATCH_VLSEG7E32FFV  0xc1006007
++#define MASK_VLSEG7E32FFV   0xfdf0707f
++#define MATCH_VLSEG8E32FFV  0xe1006007
++#define MASK_VLSEG8E32FFV   0xfdf0707f
++
++#define MATCH_VLSEG2E64FFV  0x21007007
++#define MASK_VLSEG2E64FFV   0xfdf0707f
++#define MATCH_VLSEG3E64FFV  0x41007007
++#define MASK_VLSEG3E64FFV   0xfdf0707f
++#define MATCH_VLSEG4E64FFV  0x61007007
++#define MASK_VLSEG4E64FFV   0xfdf0707f
++#define MATCH_VLSEG5E64FFV  0x81007007
++#define MASK_VLSEG5E64FFV   0xfdf0707f
++#define MATCH_VLSEG6E64FFV  0xa1007007
++#define MASK_VLSEG6E64FFV   0xfdf0707f
++#define MATCH_VLSEG7E64FFV  0xc1007007
++#define MASK_VLSEG7E64FFV   0xfdf0707f
++#define MATCH_VLSEG8E64FFV  0xe1007007
++#define MASK_VLSEG8E64FFV   0xfdf0707f
++
++#define MATCH_VL1RE8V    0x02800007
++#define MASK_VL1RE8V     0xfff0707f
++#define MATCH_VL1RE16V   0x02805007
++#define MASK_VL1RE16V    0xfff0707f
++#define MATCH_VL1RE32V   0x02806007
++#define MASK_VL1RE32V    0xfff0707f
++#define MATCH_VL1RE64V   0x02807007
++#define MASK_VL1RE64V    0xfff0707f
++
++#define MATCH_VL2RE8V    0x22800007
++#define MASK_VL2RE8V     0xfff0707f
++#define MATCH_VL2RE16V   0x22805007
++#define MASK_VL2RE16V    0xfff0707f
++#define MATCH_VL2RE32V   0x22806007
++#define MASK_VL2RE32V    0xfff0707f
++#define MATCH_VL2RE64V   0x22807007
++#define MASK_VL2RE64V    0xfff0707f
++
++#define MATCH_VL4RE8V    0x62800007
++#define MASK_VL4RE8V     0xfff0707f
++#define MATCH_VL4RE16V   0x62805007
++#define MASK_VL4RE16V    0xfff0707f
++#define MATCH_VL4RE32V   0x62806007
++#define MASK_VL4RE32V    0xfff0707f
++#define MATCH_VL4RE64V   0x62807007
++#define MASK_VL4RE64V    0xfff0707f
++
++#define MATCH_VL8RE8V    0xe2800007
++#define MASK_VL8RE8V     0xfff0707f
++#define MATCH_VL8RE16V   0xe2805007
++#define MASK_VL8RE16V    0xfff0707f
++#define MATCH_VL8RE32V   0xe2806007
++#define MASK_VL8RE32V    0xfff0707f
++#define MATCH_VL8RE64V   0xe2807007
++#define MASK_VL8RE64V    0xfff0707f
++
++#define MATCH_VS1RV  0x02800027
++#define MASK_VS1RV   0xfff0707f
++#define MATCH_VS2RV  0x22800027
++#define MASK_VS2RV   0xfff0707f
++#define MATCH_VS4RV  0x62800027
++#define MASK_VS4RV   0xfff0707f
++#define MATCH_VS8RV  0xe2800027
++#define MASK_VS8RV   0xfff0707f
++
++/* Temporary AMO encoding info
++
++width
++010 AMO*.W
++011 AMO*.D
++100 AMO*.Q
++000 VAMO*EI8.V
++101 VAMO*EI16.V
++110 VAMO*EI32.V
++111 VAMO*EI64.V
++
++amoop
++00001 vamoswap
++00000 vamoadd
++00100 vamoxor
++01100 vamoand
++01000 vamoor
++10000 vamomin
++10100 vamomax
++11000 vamominu
++11100 vamomaxu
++
++   31-27 26 25 24-20 19-15 14-12 11-7    6-0
++   amoop wd vm  vs2   rs1  width vs3/vd  opcode
++   00001 x 1 xxxxx xxxxx 110 xxxxx 0101111
++   0000 1x1x xxxx xxxx x110 xxxx x010 1111
++   1111 1010 0000 0000 0111 0000 0111 1111 */
++
++#define MATCH_VAMOADDEI8V   0x0000002f
++#define MASK_VAMOADDEI8V    0xf800707f
++#define MATCH_VAMOSWAPEI8V  0x0800002f
++#define MASK_VAMOSWAPEI8V   0xf800707f
++#define MATCH_VAMOXOREI8V   0x2000002f
++#define MASK_VAMOXOREI8V    0xf800707f
++#define MATCH_VAMOANDEI8V   0x6000002f
++#define MASK_VAMOANDEI8V    0xf800707f
++#define MATCH_VAMOOREI8V    0x4000002f
++#define MASK_VAMOOREI8V     0xf800707f
++#define MATCH_VAMOMINEI8V   0x8000002f
++#define MASK_VAMOMINEI8V    0xf800707f
++#define MATCH_VAMOMAXEI8V   0xa000002f
++#define MASK_VAMOMAXEI8V    0xf800707f
++#define MATCH_VAMOMINUEI8V  0xc000002f
++#define MASK_VAMOMINUEI8V   0xf800707f
++#define MATCH_VAMOMAXUEI8V  0xe000002f
++#define MASK_VAMOMAXUEI8V   0xf800707f
++
++#define MATCH_VAMOADDEI16V   0x0000502f
++#define MASK_VAMOADDEI16V    0xf800707f
++#define MATCH_VAMOSWAPEI16V  0x0800502f
++#define MASK_VAMOSWAPEI16V   0xf800707f
++#define MATCH_VAMOXOREI16V   0x2000502f
++#define MASK_VAMOXOREI16V    0xf800707f
++#define MATCH_VAMOANDEI16V   0x6000502f
++#define MASK_VAMOANDEI16V    0xf800707f
++#define MATCH_VAMOOREI16V    0x4000502f
++#define MASK_VAMOOREI16V     0xf800707f
++#define MATCH_VAMOMINEI16V   0x8000502f
++#define MASK_VAMOMINEI16V    0xf800707f
++#define MATCH_VAMOMAXEI16V   0xa000502f
++#define MASK_VAMOMAXEI16V    0xf800707f
++#define MATCH_VAMOMINUEI16V  0xc000502f
++#define MASK_VAMOMINUEI16V   0xf800707f
++#define MATCH_VAMOMAXUEI16V  0xe000502f
++#define MASK_VAMOMAXUEI16V   0xf800707f
++
++#define MATCH_VAMOADDEI32V   0x0000602f
++#define MASK_VAMOADDEI32V    0xf800707f
++#define MATCH_VAMOSWAPEI32V  0x0800602f
++#define MASK_VAMOSWAPEI32V   0xf800707f
++#define MATCH_VAMOXOREI32V   0x2000602f
++#define MASK_VAMOXOREI32V    0xf800707f
++#define MATCH_VAMOANDEI32V   0x6000602f
++#define MASK_VAMOANDEI32V    0xf800707f
++#define MATCH_VAMOOREI32V    0x4000602f
++#define MASK_VAMOOREI32V     0xf800707f
++#define MATCH_VAMOMINEI32V   0x8000602f
++#define MASK_VAMOMINEI32V    0xf800707f
++#define MATCH_VAMOMAXEI32V   0xa000602f
++#define MASK_VAMOMAXEI32V    0xf800707f
++#define MATCH_VAMOMINUEI32V  0xc000602f
++#define MASK_VAMOMINUEI32V   0xf800707f
++#define MATCH_VAMOMAXUEI32V  0xe000602f
++#define MASK_VAMOMAXUEI32V   0xf800707f
++
++#define MATCH_VAMOADDEI64V   0x0000702f
++#define MASK_VAMOADDEI64V    0xf800707f
++#define MATCH_VAMOSWAPEI64V  0x0800702f
++#define MASK_VAMOSWAPEI64V   0xf800707f
++#define MATCH_VAMOXOREI64V   0x2000702f
++#define MASK_VAMOXOREI64V    0xf800707f
++#define MATCH_VAMOANDEI64V   0x6000702f
++#define MASK_VAMOANDEI64V    0xf800707f
++#define MATCH_VAMOOREI64V    0x4000702f
++#define MASK_VAMOOREI64V     0xf800707f
++#define MATCH_VAMOMINEI64V   0x8000702f
++#define MASK_VAMOMINEI64V    0xf800707f
++#define MATCH_VAMOMAXEI64V   0xa000702f
++#define MASK_VAMOMAXEI64V    0xf800707f
++#define MATCH_VAMOMINUEI64V  0xc000702f
++#define MASK_VAMOMINUEI64V   0xf800707f
++#define MATCH_VAMOMAXUEI64V  0xe000702f
++#define MASK_VAMOMAXUEI64V   0xf800707f
++
++/* Temporary ALU encoding info
++
++funct3
++000 OPIVV vv
++001 OPFVV vv
++010 OPMVV vv
++011 OPIVI vi  simm[4:0]
++100 OPIVX vx  GPR x-reg rs1
++101 OPFVF vf  FP f-reg rs1
++110 OPMVX vx  GPR x-reg rs1
++111 OPCFG si  GPR x-reg rs1 & rs2/imm
++
++INT OPI
++funct6
++000000 vadd
++000001
++000010 vsub
++000011 vrsub
++000100 vminu
++000101 vmin
++000110 vmaxu
++000111 vmax
++001000
++001001 vand
++001010 vor
++001011 vxor
++001100 vrgather
++001101
++001110 vslideup, vrgatherei16
++001111 vslidedown
++010000 vadc
++010001 vmadc
++010010 vsbc
++010011 vmsbc
++010100
++010101
++010110
++010111 vmerge/vmv
++011000 vmseq
++011001 vmsne
++011010 vmsltu
++011011 vmslt
++011100 vmsleu
++011101 vmsle
++011110 vmsgtu
++011111 vmsgt
++100000 vsaddu
++100001 vsadd
++100010 vssubu
++100011 vssub
++100100
++100101 vsll
++100110
++100111 vmv<nf>r (nf = 1, 2, 4, 8)
++101000 vsrl
++101001 vsra
++101010 vssrl
++101011 vssra
++101100 vnsrl
++101101 vnsra
++101110 vnclipu
++101111 vnclip
++110000 vwredsumu
++110001 vwredsum
++110010
++110011
++110100
++110101
++110110
++110111
++111000 vdotu **
++111001 vdot **
++111010
++111011
++111100 vqmaccu
++111101 vqmacc
++111110 vqmaccus
++111111 vqmaccsu
++
++INT OPM
++funct6
++000000 vredsum
++000001 vredand
++000010 vredor
++000011 vredxor
++000100 vredminu
++000101 vredmin
++000110 vredmaxu
++000111 vredmax
++001000 vaaddu
++001001 vaadd
++001010 vasubu
++001011 vasub
++001100
++001101
++001110 vslide1up
++001111 vslide1down
++010000 VRXUNARY0/VWXUNARY0
++010001
++010010 VXUNARY0
++010011
++010100 VMUNARY0
++010101
++010110
++010111 vcompress
++011000 vmandnot
++011001 vmand
++011010 vmor
++011011 vmxor
++011100 vmornot
++011101 vmnand
++011110 vmnor
++011111 vmxnor
++100000 vdivu
++100001 vdiv
++100010 vremu
++100011 vrem
++100100 vmulhu
++100101 vmul
++100110 vmulhsu
++100111 vmulh
++101000
++101001 vmadd
++101010
++101011 vnmsub
++101100
++101101 vmacc
++101110
++101111 vnmsac
++110000 vwaddu
++110001 vwadd
++110010 vwsubu
++110011 vwsub
++110100 vwaddu.w
++110101 vwadd.w
++110110 vwsubu.w
++110111 vwsub.w
++111000 vwmulu
++111001
++111010 vwmulsu
++111011 vwmul
++111100 vwmaccu
++111101 vwmacc
++111110 vwmaccus
++111111 vwmaccsu
++
++VRXUNARY0
++vs2, funct3=X
++00000 vmv.s.x
++
++VWXUNARY0
++vs1, funct3=V
++00000 vmv.x.s
++10000 vpopc
++10001 vfirst
++
++VXUNARY0
++vs1, funct3=V
++00010 vzext.vf8
++00011 vsext.vf8
++00100 vzext.vf4
++00101 vsext.vf4
++00110 vzext.vf2
++00111 vsext.vf2
++
++VMUNARY0
++rs1
++00001 vmsbf
++00010 vmsof
++00011 vmsif
++10000 viota
++10001 vid
++
++VFLOAT
++funct6
++000000 vfadd
++000001 vfredsum
++000010 vfsub
++000011 vfredosum
++000100 vfmin
++000101 vfredmin
++000110 vfmax
++000111 vfredmax
++001000 vfsgnj
++001001 vfsgnn
++001010 vfsgnx
++001011
++001100
++001101
++001110 vfslide1up
++001111 vfslide1down
++010000 VRFUNARY0/VWFUNARY0
++010001
++010010 VFUNARY0
++010011 VFUNARY1
++010100
++010101
++010110
++010111 vfmerge/vfmv
++011000 vmfeq
++011001 vmfle
++011010
++011011 vmflt
++011100 vmfne
++011101 vmfgt
++011110
++011111 vmfge
++100000 vfdiv
++100001 vfrdiv
++100010
++100011
++100100 vfmul
++100101
++100110
++100111 vfrsub
++101000 vfmadd
++101001 vfnmadd
++101010 vfmsub
++101011 vfnmsub
++101100 vfmacc
++101101 vfnmacc
++101110 vfmsac
++101111 vfnmsac
++110000 vfwadd
++110001 vfwredsum
++110010 vfwsub
++110011 vfwredosum
++110100 vfwadd.w
++110101
++110110 vfwsub.w
++110111
++111000 vfwmul
++111001 vfdot
++111010
++111011
++111100 vfwmacc
++111101 vfwnmacc
++111110 vfwmsac
++111111 vfwnmsac
++
++VRFUNARY0
++vs2, funct3=F
++00000 vfmv.s.f
++
++VWFUNARY0
++vs1, funct3=V
++00000 vfmv.f.s
++
++VFUNARY0
++vs1
++00000 vfcvt.xu.f.v
++00001 vfcvt.x.f.v
++00010 vfcvt.f.xu.v
++00011 vfcvt.f.x.v
++00110 vfcvt.rtz.xu.f.v
++00111 vfcvt.rtz.x.f.v
++
++01000 vfwcvt.xu.f.v
++01001 vfwcvt.x.f.v
++01010 vfwcvt.f.xu.v
++01011 vfwcvt.f.x.v
++01100 vfwcvt.f.f.v
++01110 vfwcvt.rtz.xu.f.v
++01111 vfwcvt.rtz.x.f.v
++
++10000 vfncvt.xu.f.w
++10001 vfncvt.x.f.w
++10010 vfncvt.f.xu.w
++10011 vfncvt.f.x.w
++10100 vfncvt.f.f.w
++10101 vfncvt.rod.f.f.w
++10110 vfncvt.rtz.xu.f.v
++10111 vfncvt.rtz.x.f.v
++
++VFUNARY1
++vs1
++00000 vfsqrt.v
++00100 vfrsqrte7.v
++00101 vfrece7.v
++10000 vfclass.v
++
++31-26 25 24-20   19-15     14-12 11-7 6-0
++funct6 VM  VS2  VS1/RS1/IMM funct3 VD   opcode
++010000 x xxxxx 00000 001 xxxxx 1010111
++0100 00xx xxxx 0000 0001 xxxx x101 0111
++*/
++
++#define MATCH_VADDVV  0x00000057
++#define MASK_VADDVV   0xfc00707f
++#define MATCH_VADDVX  0x00004057
++#define MASK_VADDVX   0xfc00707f
++#define MATCH_VADDVI  0x00003057
++#define MASK_VADDVI   0xfc00707f
++#define MATCH_VSUBVV  0x08000057
++#define MASK_VSUBVV   0xfc00707f
++#define MATCH_VSUBVX  0x08004057
++#define MASK_VSUBVX   0xfc00707f
++#define MATCH_VRSUBVX 0x0c004057
++#define MASK_VRSUBVX  0xfc00707f
++#define MATCH_VRSUBVI 0x0c003057
++#define MASK_VRSUBVI  0xfc00707f
++
++#define MATCH_VWCVTXXV  0xc4006057
++#define MASK_VWCVTXXV   0xfc0ff07f
++#define MATCH_VWCVTUXXV 0xc0006057
++#define MASK_VWCVTUXXV  0xfc0ff07f
++
++#define MATCH_VWADDVV  0xc4002057
++#define MASK_VWADDVV   0xfc00707f
++#define MATCH_VWADDVX  0xc4006057
++#define MASK_VWADDVX   0xfc00707f
++#define MATCH_VWSUBVV  0xcc002057
++#define MASK_VWSUBVV   0xfc00707f
++#define MATCH_VWSUBVX  0xcc006057
++#define MASK_VWSUBVX   0xfc00707f
++#define MATCH_VWADDWV  0xd4002057
++#define MASK_VWADDWV   0xfc00707f
++#define MATCH_VWADDWX  0xd4006057
++#define MASK_VWADDWX   0xfc00707f
++#define MATCH_VWSUBWV  0xdc002057
++#define MASK_VWSUBWV   0xfc00707f
++#define MATCH_VWSUBWX  0xdc006057
++#define MASK_VWSUBWX   0xfc00707f
++#define MATCH_VWADDUVV  0xc0002057
++#define MASK_VWADDUVV   0xfc00707f
++#define MATCH_VWADDUVX  0xc0006057
++#define MASK_VWADDUVX   0xfc00707f
++#define MATCH_VWSUBUVV  0xc8002057
++#define MASK_VWSUBUVV   0xfc00707f
++#define MATCH_VWSUBUVX  0xc8006057
++#define MASK_VWSUBUVX   0xfc00707f
++#define MATCH_VWADDUWV  0xd0002057
++#define MASK_VWADDUWV   0xfc00707f
++#define MATCH_VWADDUWX  0xd0006057
++#define MASK_VWADDUWX   0xfc00707f
++#define MATCH_VWSUBUWV  0xd8002057
++#define MASK_VWSUBUWV   0xfc00707f
++#define MATCH_VWSUBUWX  0xd8006057
++#define MASK_VWSUBUWX   0xfc00707f
++
++#define MATCH_VZEXT_VF8 0x48012057
++#define MASK_VZEXT_VF8  0xfc0ff07f
++#define MATCH_VSEXT_VF8 0x4801a057
++#define MASK_VSEXT_VF8  0xfc0ff07f
++#define MATCH_VZEXT_VF4 0x48022057
++#define MASK_VZEXT_VF4  0xfc0ff07f
++#define MATCH_VSEXT_VF4 0x4802a057
++#define MASK_VSEXT_VF4  0xfc0ff07f
++#define MATCH_VZEXT_VF2 0x48032057
++#define MASK_VZEXT_VF2  0xfc0ff07f
++#define MATCH_VSEXT_VF2 0x4803a057
++#define MASK_VSEXT_VF2  0xfc0ff07f
++
++#define MATCH_VADCVVM  0x40000057
++#define MASK_VADCVVM   0xfe00707f
++#define MATCH_VADCVXM  0x40004057
++#define MASK_VADCVXM   0xfe00707f
++#define MATCH_VADCVIM  0x40003057
++#define MASK_VADCVIM   0xfe00707f
++#define MATCH_VMADCVVM 0x44000057
++#define MASK_VMADCVVM  0xfe00707f
++#define MATCH_VMADCVXM 0x44004057
++#define MASK_VMADCVXM  0xfe00707f
++#define MATCH_VMADCVIM 0x44003057
++#define MASK_VMADCVIM  0xfe00707f
++#define MATCH_VMADCVV  0x46000057
++#define MASK_VMADCVV   0xfe00707f
++#define MATCH_VMADCVX  0x46004057
++#define MASK_VMADCVX   0xfe00707f
++#define MATCH_VMADCVI  0x46003057
++#define MASK_VMADCVI   0xfe00707f
++#define MATCH_VSBCVVM  0x48000057
++#define MASK_VSBCVVM   0xfe00707f
++#define MATCH_VSBCVXM  0x48004057
++#define MASK_VSBCVXM   0xfe00707f
++#define MATCH_VMSBCVVM 0x4c000057
++#define MASK_VMSBCVVM  0xfe00707f
++#define MATCH_VMSBCVXM 0x4c004057
++#define MASK_VMSBCVXM  0xfe00707f
++#define MATCH_VMSBCVV  0x4e000057
++#define MASK_VMSBCVV   0xfe00707f
++#define MATCH_VMSBCVX  0x4e004057
++#define MASK_VMSBCVX   0xfe00707f
++
++#define MATCH_VNOTV   0x2c0fb057
++#define MASK_VNOTV    0xfc0ff07f
++
++#define MATCH_VANDVV  0x24000057
++#define MASK_VANDVV   0xfc00707f
++#define MATCH_VANDVX  0x24004057
++#define MASK_VANDVX   0xfc00707f
++#define MATCH_VANDVI  0x24003057
++#define MASK_VANDVI   0xfc00707f
++#define MATCH_VORVV   0x28000057
++#define MASK_VORVV    0xfc00707f
++#define MATCH_VORVX   0x28004057
++#define MASK_VORVX    0xfc00707f
++#define MATCH_VORVI   0x28003057
++#define MASK_VORVI    0xfc00707f
++#define MATCH_VXORVV  0x2c000057
++#define MASK_VXORVV   0xfc00707f
++#define MATCH_VXORVX  0x2c004057
++#define MASK_VXORVX   0xfc00707f
++#define MATCH_VXORVI  0x2c003057
++#define MASK_VXORVI   0xfc00707f
++
++#define MATCH_VSLLVV 0x94000057
++#define MASK_VSLLVV  0xfc00707f
++#define MATCH_VSLLVX 0x94004057
++#define MASK_VSLLVX  0xfc00707f
++#define MATCH_VSLLVI 0x94003057
++#define MASK_VSLLVI  0xfc00707f
++#define MATCH_VSRLVV 0xa0000057
++#define MASK_VSRLVV  0xfc00707f
++#define MATCH_VSRLVX 0xa0004057
++#define MASK_VSRLVX  0xfc00707f
++#define MATCH_VSRLVI 0xa0003057
++#define MASK_VSRLVI  0xfc00707f
++#define MATCH_VSRAVV 0xa4000057
++#define MASK_VSRAVV  0xfc00707f
++#define MATCH_VSRAVX 0xa4004057
++#define MASK_VSRAVX  0xfc00707f
++#define MATCH_VSRAVI 0xa4003057
++#define MASK_VSRAVI  0xfc00707f
++
++#define MATCH_VNCVTXXW 0xb0004057
++#define MASK_VNCVTXXW  0xfc0ff07f
++
++#define MATCH_VNSRLWV  0xb0000057
++#define MASK_VNSRLWV   0xfc00707f
++#define MATCH_VNSRLWX  0xb0004057
++#define MASK_VNSRLWX   0xfc00707f
++#define MATCH_VNSRLWI  0xb0003057
++#define MASK_VNSRLWI   0xfc00707f
++#define MATCH_VNSRAWV  0xb4000057
++#define MASK_VNSRAWV   0xfc00707f
++#define MATCH_VNSRAWX  0xb4004057
++#define MASK_VNSRAWX   0xfc00707f
++#define MATCH_VNSRAWI  0xb4003057
++#define MASK_VNSRAWI   0xfc00707f
++
++#define MATCH_VMSEQVV  0x60000057
++#define MASK_VMSEQVV   0xfc00707f
++#define MATCH_VMSEQVX  0x60004057
++#define MASK_VMSEQVX   0xfc00707f
++#define MATCH_VMSEQVI  0x60003057
++#define MASK_VMSEQVI   0xfc00707f
++#define MATCH_VMSNEVV  0x64000057
++#define MASK_VMSNEVV   0xfc00707f
++#define MATCH_VMSNEVX  0x64004057
++#define MASK_VMSNEVX   0xfc00707f
++#define MATCH_VMSNEVI  0x64003057
++#define MASK_VMSNEVI   0xfc00707f
++#define MATCH_VMSLTVV  0x6c000057
++#define MASK_VMSLTVV   0xfc00707f
++#define MATCH_VMSLTVX  0x6c004057
++#define MASK_VMSLTVX   0xfc00707f
++#define MATCH_VMSLTUVV 0x68000057
++#define MASK_VMSLTUVV  0xfc00707f
++#define MATCH_VMSLTUVX 0x68004057
++#define MASK_VMSLTUVX  0xfc00707f
++#define MATCH_VMSLEVV  0x74000057
++#define MASK_VMSLEVV   0xfc00707f
++#define MATCH_VMSLEVX  0x74004057
++#define MASK_VMSLEVX   0xfc00707f
++#define MATCH_VMSLEVI  0x74003057
++#define MASK_VMSLEVI   0xfc00707f
++#define MATCH_VMSLEUVV 0x70000057
++#define MASK_VMSLEUVV  0xfc00707f
++#define MATCH_VMSLEUVX 0x70004057
++#define MASK_VMSLEUVX  0xfc00707f
++#define MATCH_VMSLEUVI 0x70003057
++#define MASK_VMSLEUVI  0xfc00707f
++#define MATCH_VMSGTVX  0x7c004057
++#define MASK_VMSGTVX   0xfc00707f
++#define MATCH_VMSGTVI  0x7c003057
++#define MASK_VMSGTVI   0xfc00707f
++#define MATCH_VMSGTUVX 0x78004057
++#define MASK_VMSGTUVX  0xfc00707f
++#define MATCH_VMSGTUVI 0x78003057
++#define MASK_VMSGTUVI  0xfc00707f
++
++#define MATCH_VMINVV  0x14000057
++#define MASK_VMINVV   0xfc00707f
++#define MATCH_VMINVX  0x14004057
++#define MASK_VMINVX   0xfc00707f
++#define MATCH_VMAXVV  0x1c000057
++#define MASK_VMAXVV   0xfc00707f
++#define MATCH_VMAXVX  0x1c004057
++#define MASK_VMAXVX   0xfc00707f
++#define MATCH_VMINUVV 0x10000057
++#define MASK_VMINUVV  0xfc00707f
++#define MATCH_VMINUVX 0x10004057
++#define MASK_VMINUVX  0xfc00707f
++#define MATCH_VMAXUVV 0x18000057
++#define MASK_VMAXUVV  0xfc00707f
++#define MATCH_VMAXUVX 0x18004057
++#define MASK_VMAXUVX  0xfc00707f
++
++#define MATCH_VMULVV    0x94002057
++#define MASK_VMULVV     0xfc00707f
++#define MATCH_VMULVX    0x94006057
++#define MASK_VMULVX     0xfc00707f
++#define MATCH_VMULHVV   0x9c002057
++#define MASK_VMULHVV    0xfc00707f
++#define MATCH_VMULHVX   0x9c006057
++#define MASK_VMULHVX    0xfc00707f
++#define MATCH_VMULHUVV  0x90002057
++#define MASK_VMULHUVV   0xfc00707f
++#define MATCH_VMULHUVX  0x90006057
++#define MASK_VMULHUVX   0xfc00707f
++#define MATCH_VMULHSUVV 0x98002057
++#define MASK_VMULHSUVV  0xfc00707f
++#define MATCH_VMULHSUVX 0x98006057
++#define MASK_VMULHSUVX  0xfc00707f
++
++#define MATCH_VWMULVV   0xec002057
++#define MASK_VWMULVV    0xfc00707f
++#define MATCH_VWMULVX   0xec006057
++#define MASK_VWMULVX    0xfc00707f
++#define MATCH_VWMULUVV  0xe0002057
++#define MASK_VWMULUVV   0xfc00707f
++#define MATCH_VWMULUVX  0xe0006057
++#define MASK_VWMULUVX   0xfc00707f
++#define MATCH_VWMULSUVV 0xe8002057
++#define MASK_VWMULSUVV  0xfc00707f
++#define MATCH_VWMULSUVX 0xe8006057
++#define MASK_VWMULSUVX  0xfc00707f
++
++#define MATCH_VMACCVV  0xb4002057
++#define MASK_VMACCVV   0xfc00707f
++#define MATCH_VMACCVX  0xb4006057
++#define MASK_VMACCVX   0xfc00707f
++#define MATCH_VNMSACVV 0xbc002057
++#define MASK_VNMSACVV  0xfc00707f
++#define MATCH_VNMSACVX 0xbc006057
++#define MASK_VNMSACVX  0xfc00707f
++#define MATCH_VMADDVV  0xa4002057
++#define MASK_VMADDVV   0xfc00707f
++#define MATCH_VMADDVX  0xa4006057
++#define MASK_VMADDVX   0xfc00707f
++#define MATCH_VNMSUBVV 0xac002057
++#define MASK_VNMSUBVV  0xfc00707f
++#define MATCH_VNMSUBVX 0xac006057
++#define MASK_VNMSUBVX  0xfc00707f
++
++#define MATCH_VWMACCUVV  0xf0002057
++#define MASK_VWMACCUVV   0xfc00707f
++#define MATCH_VWMACCUVX  0xf0006057
++#define MASK_VWMACCUVX   0xfc00707f
++#define MATCH_VWMACCVV   0xf4002057
++#define MASK_VWMACCVV    0xfc00707f
++#define MATCH_VWMACCVX   0xf4006057
++#define MASK_VWMACCVX    0xfc00707f
++#define MATCH_VWMACCSUVV 0xfc002057
++#define MASK_VWMACCSUVV  0xfc00707f
++#define MATCH_VWMACCSUVX 0xfc006057
++#define MASK_VWMACCSUVX  0xfc00707f
++#define MATCH_VWMACCUSVX 0xf8006057
++#define MASK_VWMACCUSVX  0xfc00707f
++
++#define MATCH_VQMACCUVV  0xf0000057
++#define MASK_VQMACCUVV   0xfc00707f
++#define MATCH_VQMACCUVX  0xf0004057
++#define MASK_VQMACCUVX   0xfc00707f
++#define MATCH_VQMACCVV   0xf4000057
++#define MASK_VQMACCVV    0xfc00707f
++#define MATCH_VQMACCVX   0xf4004057
++#define MASK_VQMACCVX    0xfc00707f
++#define MATCH_VQMACCSUVV 0xfc000057
++#define MASK_VQMACCSUVV  0xfc00707f
++#define MATCH_VQMACCSUVX 0xfc004057
++#define MASK_VQMACCSUVX  0xfc00707f
++#define MATCH_VQMACCUSVX 0xf8004057
++#define MASK_VQMACCUSVX  0xfc00707f
++
++#define MATCH_VDIVVV  0x84002057
++#define MASK_VDIVVV   0xfc00707f
++#define MATCH_VDIVVX  0x84006057
++#define MASK_VDIVVX   0xfc00707f
++#define MATCH_VDIVUVV 0x80002057
++#define MASK_VDIVUVV  0xfc00707f
++#define MATCH_VDIVUVX 0x80006057
++#define MASK_VDIVUVX  0xfc00707f
++#define MATCH_VREMVV  0x8c002057
++#define MASK_VREMVV   0xfc00707f
++#define MATCH_VREMVX  0x8c006057
++#define MASK_VREMVX   0xfc00707f
++#define MATCH_VREMUVV 0x88002057
++#define MASK_VREMUVV  0xfc00707f
++#define MATCH_VREMUVX 0x88006057
++#define MASK_VREMUVX  0xfc00707f
++
++#define MATCH_VMERGEVVM 0x5c000057
++#define MASK_VMERGEVVM  0xfe00707f
++#define MATCH_VMERGEVXM 0x5c004057
++#define MASK_VMERGEVXM  0xfe00707f
++#define MATCH_VMERGEVIM 0x5c003057
++#define MASK_VMERGEVIM  0xfe00707f
++
++#define MATCH_VMVVV    0x5e000057
++#define MASK_VMVVV     0xfff0707f
++#define MATCH_VMVVX    0x5e004057
++#define MASK_VMVVX     0xfff0707f
++#define MATCH_VMVVI    0x5e003057
++#define MASK_VMVVI     0xfff0707f
++
++#define MATCH_VSADDUVV 0x80000057
++#define MASK_VSADDUVV  0xfc00707f
++#define MATCH_VSADDUVX 0x80004057
++#define MASK_VSADDUVX  0xfc00707f
++#define MATCH_VSADDUVI 0x80003057
++#define MASK_VSADDUVI  0xfc00707f
++#define MATCH_VSADDVV  0x84000057
++#define MASK_VSADDVV   0xfc00707f
++#define MATCH_VSADDVX  0x84004057
++#define MASK_VSADDVX   0xfc00707f
++#define MATCH_VSADDVI  0x84003057
++#define MASK_VSADDVI   0xfc00707f
++#define MATCH_VSSUBUVV 0x88000057
++#define MASK_VSSUBUVV  0xfc00707f
++#define MATCH_VSSUBUVX 0x88004057
++#define MASK_VSSUBUVX  0xfc00707f
++#define MATCH_VSSUBVV  0x8c000057
++#define MASK_VSSUBVV   0xfc00707f
++#define MATCH_VSSUBVX  0x8c004057
++#define MASK_VSSUBVX   0xfc00707f
++
++#define MATCH_VAADDUVV 0x20002057
++#define MASK_VAADDUVV  0xfc00707f
++#define MATCH_VAADDUVX 0x20006057
++#define MASK_VAADDUVX  0xfc00707f
++#define MATCH_VAADDVV  0x24002057
++#define MASK_VAADDVV   0xfc00707f
++#define MATCH_VAADDVX  0x24006057
++#define MASK_VAADDVX   0xfc00707f
++#define MATCH_VASUBUVV 0x28002057
++#define MASK_VASUBUVV  0xfc00707f
++#define MATCH_VASUBUVX 0x28006057
++#define MASK_VASUBUVX  0xfc00707f
++#define MATCH_VASUBVV  0x2c002057
++#define MASK_VASUBVV   0xfc00707f
++#define MATCH_VASUBVX  0x2c006057
++#define MASK_VASUBVX   0xfc00707f
++
++#define MATCH_VSMULVV  0x9c000057
++#define MASK_VSMULVV   0xfc00707f
++#define MATCH_VSMULVX  0x9c004057
++#define MASK_VSMULVX   0xfc00707f
++
++#define MATCH_VSSRLVV   0xa8000057
++#define MASK_VSSRLVV    0xfc00707f
++#define MATCH_VSSRLVX   0xa8004057
++#define MASK_VSSRLVX    0xfc00707f
++#define MATCH_VSSRLVI   0xa8003057
++#define MASK_VSSRLVI    0xfc00707f
++#define MATCH_VSSRAVV   0xac000057
++#define MASK_VSSRAVV    0xfc00707f
++#define MATCH_VSSRAVX   0xac004057
++#define MASK_VSSRAVX    0xfc00707f
++#define MATCH_VSSRAVI   0xac003057
++#define MASK_VSSRAVI    0xfc00707f
++
++#define MATCH_VNCLIPUWV 0xb8000057
++#define MASK_VNCLIPUWV  0xfc00707f
++#define MATCH_VNCLIPUWX 0xb8004057
++#define MASK_VNCLIPUWX  0xfc00707f
++#define MATCH_VNCLIPUWI 0xb8003057
++#define MASK_VNCLIPUWI  0xfc00707f
++#define MATCH_VNCLIPWV  0xbc000057
++#define MASK_VNCLIPWV   0xfc00707f
++#define MATCH_VNCLIPWX  0xbc004057
++#define MASK_VNCLIPWX   0xfc00707f
++#define MATCH_VNCLIPWI  0xbc003057
++#define MASK_VNCLIPWI   0xfc00707f
++
++#define MATCH_VFADDVV  0x00001057
++#define MASK_VFADDVV   0xfc00707f
++#define MATCH_VFADDVF  0x00005057
++#define MASK_VFADDVF   0xfc00707f
++#define MATCH_VFSUBVV  0x08001057
++#define MASK_VFSUBVV   0xfc00707f
++#define MATCH_VFSUBVF  0x08005057
++#define MASK_VFSUBVF   0xfc00707f
++#define MATCH_VFRSUBVF 0x9c005057
++#define MASK_VFRSUBVF  0xfc00707f
++
++#define MATCH_VFWADDVV  0xc0001057
++#define MASK_VFWADDVV   0xfc00707f
++#define MATCH_VFWADDVF  0xc0005057
++#define MASK_VFWADDVF   0xfc00707f
++#define MATCH_VFWSUBVV  0xc8001057
++#define MASK_VFWSUBVV   0xfc00707f
++#define MATCH_VFWSUBVF  0xc8005057
++#define MASK_VFWSUBVF   0xfc00707f
++#define MATCH_VFWADDWV  0xd0001057
++#define MASK_VFWADDWV   0xfc00707f
++#define MATCH_VFWADDWF  0xd0005057
++#define MASK_VFWADDWF   0xfc00707f
++#define MATCH_VFWSUBWV  0xd8001057
++#define MASK_VFWSUBWV   0xfc00707f
++#define MATCH_VFWSUBWF  0xd8005057
++#define MASK_VFWSUBWF   0xfc00707f
++
++#define MATCH_VFMULVV  0x90001057
++#define MASK_VFMULVV   0xfc00707f
++#define MATCH_VFMULVF  0x90005057
++#define MASK_VFMULVF   0xfc00707f
++#define MATCH_VFDIVVV  0x80001057
++#define MASK_VFDIVVV   0xfc00707f
++#define MATCH_VFDIVVF  0x80005057
++#define MASK_VFDIVVF   0xfc00707f
++#define MATCH_VFRDIVVF 0x84005057
++#define MASK_VFRDIVVF  0xfc00707f
++
++#define MATCH_VFWMULVV 0xe0001057
++#define MASK_VFWMULVV  0xfc00707f
++#define MATCH_VFWMULVF 0xe0005057
++#define MASK_VFWMULVF  0xfc00707f
++
++#define MATCH_VFMADDVV  0xa0001057
++#define MASK_VFMADDVV   0xfc00707f
++#define MATCH_VFMADDVF  0xa0005057
++#define MASK_VFMADDVF   0xfc00707f
++#define MATCH_VFNMADDVV 0xa4001057
++#define MASK_VFNMADDVV  0xfc00707f
++#define MATCH_VFNMADDVF 0xa4005057
++#define MASK_VFNMADDVF  0xfc00707f
++#define MATCH_VFMSUBVV  0xa8001057
++#define MASK_VFMSUBVV   0xfc00707f
++#define MATCH_VFMSUBVF  0xa8005057
++#define MASK_VFMSUBVF   0xfc00707f
++#define MATCH_VFNMSUBVV 0xac001057
++#define MASK_VFNMSUBVV  0xfc00707f
++#define MATCH_VFNMSUBVF 0xac005057
++#define MASK_VFNMSUBVF  0xfc00707f
++#define MATCH_VFMACCVV  0xb0001057
++#define MASK_VFMACCVV   0xfc00707f
++#define MATCH_VFMACCVF  0xb0005057
++#define MASK_VFMACCVF   0xfc00707f
++#define MATCH_VFNMACCVV 0xb4001057
++#define MASK_VFNMACCVV  0xfc00707f
++#define MATCH_VFNMACCVF 0xb4005057
++#define MASK_VFNMACCVF  0xfc00707f
++#define MATCH_VFMSACVV  0xb8001057
++#define MASK_VFMSACVV   0xfc00707f
++#define MATCH_VFMSACVF  0xb8005057
++#define MASK_VFMSACVF   0xfc00707f
++#define MATCH_VFNMSACVV 0xbc001057
++#define MASK_VFNMSACVV  0xfc00707f
++#define MATCH_VFNMSACVF 0xbc005057
++#define MASK_VFNMSACVF  0xfc00707f
++
++#define MATCH_VFWMACCVV  0xf0001057
++#define MASK_VFWMACCVV   0xfc00707f
++#define MATCH_VFWMACCVF  0xf0005057
++#define MASK_VFWMACCVF   0xfc00707f
++#define MATCH_VFWNMACCVV 0xf4001057
++#define MASK_VFWNMACCVV  0xfc00707f
++#define MATCH_VFWNMACCVF 0xf4005057
++#define MASK_VFWNMACCVF  0xfc00707f
++#define MATCH_VFWMSACVV  0xf8001057
++#define MASK_VFWMSACVV   0xfc00707f
++#define MATCH_VFWMSACVF  0xf8005057
++#define MASK_VFWMSACVF   0xfc00707f
++#define MATCH_VFWNMSACVV 0xfc001057
++#define MASK_VFWNMSACVV  0xfc00707f
++#define MATCH_VFWNMSACVF 0xfc005057
++#define MASK_VFWNMSACVF  0xfc00707f
++
++#define MATCH_VFSQRTV    0x4c001057
++#define MASK_VFSQRTV     0xfc0ff07f
++#define MATCH_VFRSQRT7V  0x4c021057
++#define MASK_VFRSQRT7V   0xfc0ff07f
++#define MATCH_VFREC7V    0x4c029057
++#define MASK_VFREC7V     0xfc0ff07f
++#define MATCH_VFCLASSV   0x4c081057
++#define MASK_VFCLASSV    0xfc0ff07f
++
++#define MATCH_VFMINVV  0x10001057
++#define MASK_VFMINVV   0xfc00707f
++#define MATCH_VFMINVF  0x10005057
++#define MASK_VFMINVF   0xfc00707f
++#define MATCH_VFMAXVV  0x18001057
++#define MASK_VFMAXVV   0xfc00707f
++#define MATCH_VFMAXVF  0x18005057
++#define MASK_VFMAXVF   0xfc00707f
++
++#define MATCH_VFSGNJVV  0x20001057
++#define MASK_VFSGNJVV   0xfc00707f
++#define MATCH_VFSGNJVF  0x20005057
++#define MASK_VFSGNJVF   0xfc00707f
++#define MATCH_VFSGNJNVV 0x24001057
++#define MASK_VFSGNJNVV  0xfc00707f
++#define MATCH_VFSGNJNVF 0x24005057
++#define MASK_VFSGNJNVF  0xfc00707f
++#define MATCH_VFSGNJXVV 0x28001057
++#define MASK_VFSGNJXVV  0xfc00707f
++#define MATCH_VFSGNJXVF 0x28005057
++#define MASK_VFSGNJXVF  0xfc00707f
++
++#define MATCH_VMFEQVV   0x60001057
++#define MASK_VMFEQVV    0xfc00707f
++#define MATCH_VMFEQVF   0x60005057
++#define MASK_VMFEQVF    0xfc00707f
++#define MATCH_VMFNEVV   0x70001057
++#define MASK_VMFNEVV    0xfc00707f
++#define MATCH_VMFNEVF   0x70005057
++#define MASK_VMFNEVF    0xfc00707f
++#define MATCH_VMFLTVV   0x6c001057
++#define MASK_VMFLTVV    0xfc00707f
++#define MATCH_VMFLTVF   0x6c005057
++#define MASK_VMFLTVF    0xfc00707f
++#define MATCH_VMFLEVV  0x64001057
++#define MASK_VMFLEVV   0xfc00707f
++#define MATCH_VMFLEVF  0x64005057
++#define MASK_VMFLEVF   0xfc00707f
++#define MATCH_VMFGTVF   0x74005057
++#define MASK_VMFGTVF    0xfc00707f
++#define MATCH_VMFGEVF  0x7c005057
++#define MASK_VMFGEVF   0xfc00707f
++
++#define MATCH_VFMERGEVFM 0x5c005057
++#define MASK_VFMERGEVFM  0xfe00707f
++#define MATCH_VFMVVF     0x5e005057
++#define MASK_VFMVVF      0xfff0707f
++
++#define MATCH_VFCVTXUFV 0x48001057
++#define MASK_VFCVTXUFV  0xfc0ff07f
++#define MATCH_VFCVTXFV 0x48009057
++#define MASK_VFCVTXFV  0xfc0ff07f
++#define MATCH_VFCVTFXUV 0x48011057
++#define MASK_VFCVTFXUV  0xfc0ff07f
++#define MATCH_VFCVTFXV 0x48019057
++#define MASK_VFCVTFXV  0xfc0ff07f
++#define MATCH_VFCVTRTZXUFV 0x48031057
++#define MASK_VFCVTRTZXUFV  0xfc0ff07f
++#define MATCH_VFCVTRTZXFV 0x48039057
++#define MASK_VFCVTRTZXFV  0xfc0ff07f
++#define MATCH_VFWCVTXUFV 0x48041057
++#define MASK_VFWCVTXUFV  0xfc0ff07f
++#define MATCH_VFWCVTXFV 0x48049057
++#define MASK_VFWCVTXFV  0xfc0ff07f
++#define MATCH_VFWCVTFXUV 0x48051057
++#define MASK_VFWCVTFXUV  0xfc0ff07f
++#define MATCH_VFWCVTFXV 0x48059057
++#define MASK_VFWCVTFXV  0xfc0ff07f
++#define MATCH_VFWCVTFFV 0x48061057
++#define MASK_VFWCVTFFV  0xfc0ff07f
++#define MATCH_VFWCVTRTZXUFV 0x48071057
++#define MASK_VFWCVTRTZXUFV  0xfc0ff07f
++#define MATCH_VFWCVTRTZXFV 0x48079057
++#define MASK_VFWCVTRTZXFV  0xfc0ff07f
++#define MATCH_VFNCVTXUFW 0x48081057
++#define MASK_VFNCVTXUFW  0xfc0ff07f
++#define MATCH_VFNCVTXFW 0x48089057
++#define MASK_VFNCVTXFW  0xfc0ff07f
++#define MATCH_VFNCVTFXUW 0x48091057
++#define MASK_VFNCVTFXUW  0xfc0ff07f
++#define MATCH_VFNCVTFXW 0x48099057
++#define MASK_VFNCVTFXW  0xfc0ff07f
++#define MATCH_VFNCVTFFW 0x480a1057
++#define MASK_VFNCVTFFW  0xfc0ff07f
++#define MATCH_VFNCVTRODFFW 0x480a9057
++#define MASK_VFNCVTRODFFW  0xfc0ff07f
++#define MATCH_VFNCVTRTZXUFW 0x480b1057
++#define MASK_VFNCVTRTZXUFW  0xfc0ff07f
++#define MATCH_VFNCVTRTZXFW 0x480b9057
++#define MASK_VFNCVTRTZXFW  0xfc0ff07f
++
++#define MATCH_VREDSUMVS  0x00002057
++#define MASK_VREDSUMVS   0xfc00707f
++#define MATCH_VREDMAXVS  0x1c002057
++#define MASK_VREDMAXVS   0xfc00707f
++#define MATCH_VREDMAXUVS 0x18002057
++#define MASK_VREDMAXUVS  0xfc00707f
++#define MATCH_VREDMINVS  0x14002057
++#define MASK_VREDMINVS   0xfc00707f
++#define MATCH_VREDMINUVS 0x10002057
++#define MASK_VREDMINUVS  0xfc00707f
++#define MATCH_VREDANDVS  0x04002057
++#define MASK_VREDANDVS   0xfc00707f
++#define MATCH_VREDORVS   0x08002057
++#define MASK_VREDORVS    0xfc00707f
++#define MATCH_VREDXORVS  0x0c002057
++#define MASK_VREDXORVS   0xfc00707f
++
++#define MATCH_VWREDSUMUVS 0xc0000057
++#define MASK_VWREDSUMUVS  0xfc00707f
++#define MATCH_VWREDSUMVS  0xc4000057
++#define MASK_VWREDSUMVS   0xfc00707f
++
++#define MATCH_VFREDOSUMVS 0x0c001057
++#define MASK_VFREDOSUMVS  0xfc00707f
++#define MATCH_VFREDSUMVS  0x04001057
++#define MASK_VFREDSUMVS   0xfc00707f
++#define MATCH_VFREDMAXVS  0x1c001057
++#define MASK_VFREDMAXVS   0xfc00707f
++#define MATCH_VFREDMINVS  0x14001057
++#define MASK_VFREDMINVS   0xfc00707f
++
++#define MATCH_VFWREDOSUMVS 0xcc001057
++#define MASK_VFWREDOSUMVS  0xfc00707f
++#define MATCH_VFWREDSUMVS  0xc4001057
++#define MASK_VFWREDSUMVS   0xfc00707f
++
++#define MATCH_VMANDMM    0x66002057
++#define MASK_VMANDMM     0xfe00707f
++#define MATCH_VMNANDMM   0x76002057
++#define MASK_VMNANDMM    0xfe00707f
++#define MATCH_VMANDNOTMM 0x62002057
++#define MASK_VMANDNOTMM  0xfe00707f
++#define MATCH_VMXORMM    0x6e002057
++#define MASK_VMXORMM     0xfe00707f
++#define MATCH_VMORMM     0x6a002057
++#define MASK_VMORMM      0xfe00707f
++#define MATCH_VMNORMM    0x7a002057
++#define MASK_VMNORMM     0xfe00707f
++#define MATCH_VMORNOTMM  0x72002057
++#define MASK_VMORNOTMM   0xfe00707f
++#define MATCH_VMXNORMM   0x7e002057
++#define MASK_VMXNORMM    0xfe00707f
++
++#define MATCH_VPOPCM   0x40082057
++#define MASK_VPOPCM    0xfc0ff07f
++#define MATCH_VFIRSTM  0x4008a057
++#define MASK_VFIRSTM   0xfc0ff07f
++
++#define MATCH_VMSBFM   0x5000a057
++#define MASK_VMSBFM    0xfc0ff07f
++#define MATCH_VMSIFM   0x5001a057
++#define MASK_VMSIFM    0xfc0ff07f
++#define MATCH_VMSOFM   0x50012057
++#define MASK_VMSOFM    0xfc0ff07f
++#define MATCH_VIOTAM   0x50082057
++#define MASK_VIOTAM    0xfc0ff07f
++#define MATCH_VIDV     0x5008a057
++#define MASK_VIDV      0xfdfff07f
++
++#define MATCH_VMVXS    0x42002057
++#define MASK_VMVXS     0xfe0ff07f
++#define MATCH_VMVSX    0x42006057
++#define MASK_VMVSX     0xfff0707f
++
++#define MATCH_VFMVFS   0x42001057
++#define MASK_VFMVFS    0xfe0ff07f
++#define MATCH_VFMVSF   0x42005057
++#define MASK_VFMVSF    0xfff0707f
++
++#define MATCH_VSLIDEUPVX   0x38004057
++#define MASK_VSLIDEUPVX    0xfc00707f
++#define MATCH_VSLIDEUPVI   0x38003057
++#define MASK_VSLIDEUPVI    0xfc00707f
++#define MATCH_VSLIDEDOWNVX 0x3c004057
++#define MASK_VSLIDEDOWNVX  0xfc00707f
++#define MATCH_VSLIDEDOWNVI 0x3c003057
++#define MASK_VSLIDEDOWNVI  0xfc00707f
++
++#define MATCH_VSLIDE1UPVX   0x38006057
++#define MASK_VSLIDE1UPVX    0xfc00707f
++#define MATCH_VSLIDE1DOWNVX 0x3c006057
++#define MASK_VSLIDE1DOWNVX  0xfc00707f
++
++#define MATCH_VFSLIDE1UPVF   0x38005057
++#define MASK_VFSLIDE1UPVF    0xfc00707f
++#define MATCH_VFSLIDE1DOWNVF 0x3c005057
++#define MASK_VFSLIDE1DOWNVF  0xfc00707f
++
++#define MATCH_VRGATHERVV      0x30000057
++#define MASK_VRGATHERVV       0xfc00707f
++#define MATCH_VRGATHERVX      0x30004057
++#define MASK_VRGATHERVX       0xfc00707f
++#define MATCH_VRGATHERVI      0x30003057
++#define MASK_VRGATHERVI       0xfc00707f
++#define MATCH_VRGATHEREI16VV  0x38000057
++#define MASK_VRGATHEREI16VV   0xfc00707f
++
++#define MATCH_VCOMPRESSVM   0x5e002057
++#define MASK_VCOMPRESSVM    0xfe00707f
++
++#define MATCH_VMV1RV 0x9e003057
++#define MASK_VMV1RV  0xfe0ff07f
++#define MATCH_VMV2RV 0x9e00b057
++#define MASK_VMV2RV  0xfe0ff07f
++#define MATCH_VMV4RV 0x9e01b057
++#define MASK_VMV4RV  0xfe0ff07f
++#define MATCH_VMV8RV 0x9e03b057
++#define MASK_VMV8RV  0xfe0ff07f
++
++#define MATCH_VDOTVV    0xe4000057
++#define MASK_VDOTVV     0xfc00707f
++#define MATCH_VDOTUVV   0xe0000057
++#define MASK_VDOTUVV    0xfc00707f
++#define MATCH_VFDOTVV   0xe4001057
++#define MASK_VFDOTVV    0xfc00707f
++/* END RVV */
++
++#define MATCH_CUSTOM0 0xb
++#define MASK_CUSTOM0  0x707f
++#define MATCH_CUSTOM0_RS1 0x200b
++#define MASK_CUSTOM0_RS1  0x707f
++#define MATCH_CUSTOM0_RS1_RS2 0x300b
++#define MASK_CUSTOM0_RS1_RS2  0x707f
++#define MATCH_CUSTOM0_RD 0x400b
++#define MASK_CUSTOM0_RD  0x707f
++#define MATCH_CUSTOM0_RD_RS1 0x600b
++#define MASK_CUSTOM0_RD_RS1  0x707f
++#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
++#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM1 0x2b
++#define MASK_CUSTOM1  0x707f
++#define MATCH_CUSTOM1_RS1 0x202b
++#define MASK_CUSTOM1_RS1  0x707f
++#define MATCH_CUSTOM1_RS1_RS2 0x302b
++#define MASK_CUSTOM1_RS1_RS2  0x707f
++#define MATCH_CUSTOM1_RD 0x402b
++#define MASK_CUSTOM1_RD  0x707f
++#define MATCH_CUSTOM1_RD_RS1 0x602b
++#define MASK_CUSTOM1_RD_RS1  0x707f
++#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
++#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM2 0x5b
++#define MASK_CUSTOM2  0x707f
++#define MATCH_CUSTOM2_RS1 0x205b
++#define MASK_CUSTOM2_RS1  0x707f
++#define MATCH_CUSTOM2_RS1_RS2 0x305b
++#define MASK_CUSTOM2_RS1_RS2  0x707f
++#define MATCH_CUSTOM2_RD 0x405b
++#define MASK_CUSTOM2_RD  0x707f
++#define MATCH_CUSTOM2_RD_RS1 0x605b
++#define MASK_CUSTOM2_RD_RS1  0x707f
++#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
++#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
++#define MATCH_CUSTOM3 0x7b
++#define MASK_CUSTOM3  0x707f
++#define MATCH_CUSTOM3_RS1 0x207b
++#define MASK_CUSTOM3_RS1  0x707f
++#define MATCH_CUSTOM3_RS1_RS2 0x307b
++#define MASK_CUSTOM3_RS1_RS2  0x707f
++#define MATCH_CUSTOM3_RD 0x407b
++#define MASK_CUSTOM3_RD  0x707f
++#define MATCH_CUSTOM3_RD_RS1 0x607b
++#define MASK_CUSTOM3_RD_RS1  0x707f
++#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
++#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
++/* Privileged CSR addresses (v1.11).  */
+ #define CSR_USTATUS 0x0
+ #define CSR_UIE 0x4
+ #define CSR_UTVEC 0x5
+@@ -990,6 +2886,13 @@
+ #define CSR_FFLAGS 0x1
+ #define CSR_FRM 0x2
+ #define CSR_FCSR 0x3
++#define CSR_VSTART 0x008
++#define CSR_VXSAT 0x009
++#define CSR_VXRM 0x00a
++#define CSR_VCSR 0x00f
++#define CSR_VL 0xc20
++#define CSR_VTYPE 0xc21
++#define CSR_VLENB 0xc22
+ #define CSR_DCSR 0x7b0
+ #define CSR_DPC 0x7b1
+ #define CSR_DSCRATCH0 0x7b2
+@@ -1002,7 +2905,7 @@
+ #define CSR_TCONTROL 0x7a5
+ #define CSR_MCONTEXT 0x7a8
+ #define CSR_SCONTEXT 0x7aa
+-#endif /* RISCV_ENCODING_H */
++#endif /* RISCV_ENCODING_H.  */
+ #ifdef DECLARE_INSN
+ DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+ DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
+@@ -1606,6 +3509,13 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
+ DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
++DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+@@ -1632,4 +3542,4 @@ DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
+ DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+ DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+-#endif /* DECLARE_CSR_ALIAS */
++#endif /* DECLARE_CSR_ALIAS */
+\ No newline at end of file
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index ae8c6bd33f..a785cb1490 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -52,6 +52,28 @@ static const char * const riscv_pred_succ[16] =
+   "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
+ };
+ 
++/* List of vsetvli vsew constants.  */
++static const char * const riscv_vsew[8] =
++{
++  "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
++};
++
++/* List of vsetvli vlmul constants.  */
++static const char * const riscv_vlmul[8] =
++{
++  "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
++};
++
++static const char * const riscv_vta[2] =
++{
++  "tu", "ta"
++};
++
++static const char * const riscv_vma[2] =
++{
++  "mu", "ma"
++};
++
+ #define RVC_JUMP_BITS 11
+ #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
+ 
+@@ -101,6 +123,16 @@ static const char * const riscv_pred_succ[16] =
+   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
+ #define EXTRACT_CJTYPE_IMM(x) \
+   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
++#define EXTRACT_RVV_VI_IMM(x) \
++  (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
++#define EXTRACT_RVV_VI_UIMM(x) \
++  (RV_X(x, 15, 5))
++#define EXTRACT_RVV_OFFSET(x) \
++  (RV_X(x, 29, 3))
++#define EXTRACT_RVV_VB_IMM(x) \
++  (RV_X(x, 20, 10))
++#define EXTRACT_RVV_VC_IMM(x) \
++  (RV_X(x, 20, 11))
+ 
+ #define ENCODE_ITYPE_IMM(x) \
+   (RV_X(x, 0, 12) << 20)
+@@ -142,6 +174,10 @@ static const char * const riscv_pred_succ[16] =
+   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
+ #define ENCODE_CJTYPE_IMM(x) \
+   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
++#define ENCODE_RVV_VB_IMM(x) \
++  (RV_X(x, 0, 10) << 20)
++#define ENCODE_RVV_VC_IMM(x) \
++  (RV_X(x, 0, 11) << 20)
+ 
+ #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
+ #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
+@@ -165,6 +201,8 @@ static const char * const riscv_pred_succ[16] =
+ #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
+ #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
+ #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
++#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
++#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
+ 
+ #define RISCV_RTYPE(insn, rd, rs1, rs2) \
+   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
+@@ -261,6 +299,35 @@ static const char * const riscv_pred_succ[16] =
+ #define OP_MASK_CFUNCT2		0x3
+ #define OP_SH_CFUNCT2		5
+ 
++/* RVV fields.  */
++
++#define OP_MASK_VD		0x1f
++#define OP_SH_VD		7
++#define OP_MASK_VS1		0x1f
++#define OP_SH_VS1		15
++#define OP_MASK_VS2		0x1f
++#define OP_SH_VS2		20
++#define OP_MASK_VIMM		0x1f
++#define OP_SH_VIMM		15
++#define OP_MASK_VMASK		0x1
++#define OP_SH_VMASK		25
++#define OP_MASK_VFUNCT6		0x3f
++#define OP_SH_VFUNCT6		26
++
++#define OP_MASK_VLMUL		0x7
++#define OP_SH_VLMUL		0
++#define OP_MASK_VSEW		0x7
++#define OP_SH_VSEW		3
++#define OP_MASK_VTA		0x1
++#define OP_SH_VTA		6
++#define OP_MASK_VMA		0x1
++#define OP_SH_VMA		7
++#define OP_MASK_VTYPE_RES	0x1
++#define OP_SH_VTYPE_RES 	10
++
++#define OP_MASK_VWD		0x1
++#define OP_SH_VWD		26
++
+ /* ABI names for selected x-registers.  */
+ 
+ #define X_RA 1
+@@ -274,6 +341,8 @@ static const char * const riscv_pred_succ[16] =
+ 
+ #define NGPR 32
+ #define NFPR 32
++#define NVECR 32
++#define NVECM 1
+ 
+ /* These fake label defines are use by both the assembler, and
+    libopcodes.  The assembler uses this when it needs to generate a fake
+@@ -331,6 +400,10 @@ enum riscv_insn_class
+   INSN_CLASS_ZBT,
+   INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
+   INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
++  INSN_CLASS_V,
++  INSN_CLASS_V_AND_F,
++  INSN_CLASS_V_OR_ZVAMO,
++  INSN_CLASS_V_OR_ZVLSSEG,
+ };
+ 
+ /* This structure holds information for a particular instruction.  */
+@@ -371,6 +444,9 @@ struct riscv_opcode
+   unsigned long pinfo;
+ };
+ 
++
++#define RISCV_UNKNOWN_VERSION -1
++
+ /* Instruction is a simple alias (e.g. "mv" for "addi").  */
+ #define	INSN_ALIAS		0x00000001
+ 
+@@ -434,6 +510,8 @@ enum
+   M_ZEXTW,
+   M_SEXTB,
+   M_SEXTH,
++  M_VMSGE,
++  M_VMSGEU,
+   M_NUM_MACROS
+ };
+ 
+@@ -442,8 +520,10 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
+ extern const char * const riscv_gpr_names_abi[NGPR];
+ extern const char * const riscv_fpr_names_numeric[NFPR];
+ extern const char * const riscv_fpr_names_abi[NFPR];
++extern const char * const riscv_vecr_names_numeric[NVECR];
++extern const char * const riscv_vecm_names_numeric[NVECM];
+ 
+ extern const struct riscv_opcode riscv_opcodes[];
+ extern const struct riscv_opcode riscv_insn_types[];
+ 
+-#endif /* _RISCV_H_ */
++#endif /* _RISCV_H_ */
+\ No newline at end of file
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
+index fe8dfb88d9..a36756cb4c 100644
+--- a/opcodes/riscv-dis.c
++++ b/opcodes/riscv-dis.c
+@@ -43,15 +43,17 @@ struct riscv_private_data
+ 
+ static const char * const *riscv_gpr_names;
+ static const char * const *riscv_fpr_names;
++static const char * const *riscv_vecr_names;
+ 
+-/* If set, disassemble as most general instruction.  */
+-static int no_aliases;
++/* Other options.  */
++static int no_aliases;	/* If set disassemble as most general inst.  */
+ 
+ static void
+ set_default_riscv_dis_options (void)
+ {
+   riscv_gpr_names = riscv_gpr_names_abi;
+   riscv_fpr_names = riscv_fpr_names_abi;
++  riscv_vecr_names = riscv_vecr_names_numeric;
+   no_aliases = 0;
+ }
+ 
+@@ -411,6 +413,88 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+ 	  print (info->stream, "%d", rs1);
+ 	  break;
+ 
++	case 'V': /* RVV */
++	  switch (*++d)
++	    {
++	    case 'd':
++	    case 'f':
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
++	      break;
++
++	    case 'e':
++	      if (!EXTRACT_OPERAND (VWD, l))
++		print (info->stream, "%s", riscv_gpr_names[0]);
++	      else
++		print (info->stream, "%s",
++		       riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
++	      break;
++
++	    case 's':
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VS1, l)]);
++	      break;
++
++	    case 't':
++	    case 'u': /* VS1 == VS2 already verified at this point.  */
++	    case 'v': /* VD == VS1 == VS2 already verified at this point.  */
++	      print (info->stream, "%s",
++		      riscv_vecr_names[EXTRACT_OPERAND (VS2, l)]);
++	      break;
++
++	    case '0':
++	      print (info->stream, "%s", riscv_vecr_names[0]);
++	      break;
++
++	    case 'b':
++	    case 'c':
++	      {
++		int imm = (*d == 'b') ? EXTRACT_RVV_VB_IMM (l)
++				      : EXTRACT_RVV_VC_IMM (l);
++		unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
++		unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
++		unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
++		unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
++		unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
++
++		if (imm_vsew < ARRAY_SIZE (riscv_vsew)
++		    && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
++		    && imm_vta < ARRAY_SIZE (riscv_vta)
++		    && imm_vma < ARRAY_SIZE (riscv_vma)
++		    && ! imm_vtype_res)
++		  print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew],
++			 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
++			 riscv_vma[imm_vma]);
++		else
++		  print (info->stream, "%d", imm);
++	      }
++	      break;
++
++	    case 'i':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
++	      break;
++
++	    case 'j':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
++	      break;
++
++	    case 'k':
++	      print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
++	      break;
++
++	    case 'm':
++	      if (! EXTRACT_OPERAND (VMASK, l))
++		print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
++	      break;
++
++	    default:
++	      /* xgettext:c-format */
++	      print (info->stream, _("# internal error, undefined modifier (V%c)"),
++		     *d);
++	      return;
++	    }
++	  break;
++
+ 	default:
+ 	  /* xgettext:c-format */
+ 	  print (info->stream, _("# internal error, undefined modifier (%c)"),
+@@ -653,4 +737,4 @@ with the -M switch (multiple options should be separated by commas):\n"));
+                   (1.9, 1.9.1, 1.10, 1.11).\n"));
+ 
+   fprintf (stream, _("\n"));
+-}
++}
+\ No newline at end of file
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 3d9240262c..745c7a990b 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -182,6 +182,20 @@ const char * const riscv_fpr_names_abi[NFPR] =
+   "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11"
+ };
+ 
++const char * const riscv_vecr_names_numeric[NVECR] =
++{
++  "v0",   "v1",   "v2",   "v3",   "v4",   "v5",   "v6",   "v7",
++  "v8",   "v9",   "v10",  "v11",  "v12",  "v13",  "v14",  "v15",
++  "v16",  "v17",  "v18",  "v19",  "v20",  "v21",  "v22",  "v23",
++  "v24",  "v25",  "v26",  "v27",  "v28",  "v29",  "v30",  "v31"
++};
++
++const char * const riscv_vecm_names_numeric[NVECM] =
++{
++  "v0.t"
++};
++
++
+ /* The order of overloaded instructions matters.  Label arguments and
+    register arguments look the same. Instructions that can have either
+    for arguments must apear in the correct order in this table for the
+@@ -209,6 +223,11 @@ const char * const riscv_fpr_names_abi[NFPR] =
+ #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
+ #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
++#define MASK_VD  (OP_MASK_VD << OP_SH_VD)
++#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
++#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
++#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
++
+ 
+ static int
+ match_opcode (const struct riscv_opcode *op, insn_t insn)
+@@ -231,6 +250,47 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
+   return match_opcode (op, insn) && rs1 == rs2;
+ }
+ 
++static int
++match_vs1_eq_vs2 (const struct riscv_opcode *op,
++		  insn_t insn)
++{
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  return match_opcode (op, insn) && vs1 == vs2;
++}
++
++static int
++match_vs1_eq_vs2_neq_vm (const struct riscv_opcode *op,
++			 insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn) && vs1 == vs2;
++
++  if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn) && vs1 == vs2;
++  return 0;
++}
++
++static int
++match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
++			insn_t insn)
++{
++  int vd =  (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  return match_opcode (op, insn) && vd == vs1 && vs1 == vs2;
++}
++
++
+ static int
+ match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
+ {
+@@ -324,6 +384,249 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
+   return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
+ }
+ 
++
++/* These are used to check the vector constraints.  */
++
++static int
++match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				       insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0)
++    return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if (vs1 >= vd && vs1 <= (vd + 1))
++    return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 >= vd && vs2 <= (vd + 1))
++    return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 1))
++    return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
++			       insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if ((vs2 % 2) != 0) return 0;
++    //*error = "illegal operands vs2 must be multiple of 2";
++  else if (vs1 >= vd && vs1 <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			       insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if (vs2 >= vd && vs2 <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_widen_vd_neq_vm (const struct riscv_opcode *op,
++		       insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % 2) != 0) return 0;
++   // *error = "illegal operands vd must be multiple of 2";
++  else if ((vs2 % 2) != 0) return 0;
++   // *error = "illegal operands vs2 must be multiple of 2";
++  else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
++   // *error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vs2 % 2) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of 2";
++  else if (vd >= vs2 && vd <= (vs2 + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vd >= vm && vd <= (vm + 1)) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
++			  insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if (vs1 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
++				 insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  if (vs1 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs1";
++  else if (vs2 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
++			 insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if (vs2 == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vs2";
++  else if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else 
++    return match_opcode (op, insn);
++  return 0;
++}
++
++/* v[m]adc and v[m]sbc use the vm encoding to encode the
++   carry-in v0 register.  The carry-in v0 register can not
++   overlap with the vd, too.  Therefore, we use the same
++   match_vd_neq_vm to check the overlap constraints.  */
++
++static int
++match_vd_neq_vm (const struct riscv_opcode *op,
++		 insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if (!vm && vm == vd) return 0;
++    //*error = "illegal operands vd cannot overlap vm";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vls_nf_rv (const struct riscv_opcode *op,
++		 insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int nf = ((insn & (0x7 << 29) ) >> 29) + 1;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % nf) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of nf";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++static int
++match_vmv_nf_rv (const struct riscv_opcode *op,
++		 insn_t insn)
++{
++  int vd = (insn & MASK_VD) >> OP_SH_VD;
++  int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
++  int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
++
++  //if (!constraints || error == NULL)
++  //  return match_opcode (op, insn);
++
++  if ((vd % nf) != 0) return 0;
++    //*error = "illegal operands vd must be multiple of nf";
++  else if ((vs2 % nf) != 0) return 0;
++    //*error = "illegal operands vs2 must be multiple of nf";
++  else
++    return match_opcode (op, insn);
++  return 0;
++}
++
++
+ const struct riscv_opcode riscv_opcodes[] =
+ {
+ /* name, xlen, isa, operands, match, mask, match_func, pinfo.  */
+@@ -1144,6 +1447,806 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"fsrw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
+ {"fsriw",     64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+ 
++/* RVV */
++{"vsetvl",     0, INSN_CLASS_V,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
++{"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
++{"vsetivli",   0, INSN_CLASS_V,  "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
++
++{"vle1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
++{"vse1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
++
++{"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
++{"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
++{"vle32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
++{"vle64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vse8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
++{"vse16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
++{"vse32.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
++{"vse64.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vlse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
++{"vlse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
++{"vlse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
++{"vlse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsse8.v",    0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
++{"vsse16.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
++{"vsse32.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
++{"vsse64.v",   0, INSN_CLASS_V,  "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
++
++{"vloxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vloxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vloxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vloxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsoxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsoxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vluxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vluxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vluxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vluxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
++{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
++
++{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
++{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
++{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
++{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
++{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
++
++{"vlsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
++{"vlsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
++
++{"vloxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vloxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vloxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsoxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vluxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vluxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++{"vsuxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
++
++{"vlseg2e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vlseg2e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg3e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg4e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg5e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg6e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg7e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
++{"vlseg8e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
++
++{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
++{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
++{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
++{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
++{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
++
++{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
++{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
++{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
++{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
++
++{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
++{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
++{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
++{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
++
++{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
++{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
++{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
++
++{"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
++
++{"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
++{"vadd.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
++{"vadd.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
++{"vsub.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_vd_neq_vm, 0 },
++{"vsub.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_vd_neq_vm, 0 },
++{"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
++{"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
++
++{"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
++{"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
++
++{"vwaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwsubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwsubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwsub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwaddu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwaddu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
++{"vwsubu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwsubu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
++{"vwadd.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwadd.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
++{"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
++{"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
++
++{"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
++{"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
++{"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
++{"vsext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_vd_neq_vm, 0 },
++{"vzext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_vd_neq_vm, 0 },
++{"vsext.vf8",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_vd_neq_vm, 0 },
++
++{"vadc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_vd_neq_vm, 0 },
++{"vadc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_vd_neq_vm, 0 },
++{"vadc.vim",   0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_vd_neq_vm, 0 },
++{"vmadc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
++{"vmadc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
++{"vmadc.vim",  0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
++{"vmadc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
++{"vmadc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
++{"vmadc.vi",   0, INSN_CLASS_V,  "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
++{"vsbc.vvm",   0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_vd_neq_vm, 0 },
++{"vsbc.vxm",   0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_vd_neq_vm, 0 },
++{"vmsbc.vvm",  0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
++{"vmsbc.vxm",  0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
++{"vmsbc.vv",   0, INSN_CLASS_V,  "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
++{"vmsbc.vx",   0, INSN_CLASS_V,  "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
++
++{"vnot.v",     0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_vd_neq_vm, INSN_ALIAS },
++
++{"vand.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_vd_neq_vm, 0 },
++{"vand.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_vd_neq_vm, 0 },
++{"vand.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_vd_neq_vm, 0 },
++{"vor.vv",     0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_vd_neq_vm, 0 },
++{"vor.vx",     0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_vd_neq_vm, 0 },
++{"vor.vi",     0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_vd_neq_vm, 0 },
++{"vxor.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_vd_neq_vm, 0 },
++{"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
++{"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
++
++{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
++{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
++{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
++{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
++{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
++{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
++{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
++{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
++{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
++
++{"vncvt.x.x.w",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
++
++{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++
++{"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
++{"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
++{"vmseq.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
++{"vmsne.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
++{"vmsne.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
++{"vmsne.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
++{"vmsltu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
++{"vmsltu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
++{"vmslt.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
++{"vmslt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
++{"vmsleu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
++{"vmsleu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
++{"vmsleu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
++{"vmsle.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
++{"vmsle.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
++{"vmsle.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
++{"vmsgtu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
++{"vmsgtu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
++{"vmsgt.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
++{"vmsgt.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
++
++/* These aliases are for assembly but not disassembly.  */
++{"vmsgt.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
++{"vmsgtu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
++{"vmsge.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
++{"vmsgeu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
++{"vmslt.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
++{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, INSN_ALIAS },
++{"vmsltu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
++{"vmsge.vi",   0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
++{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, INSN_ALIAS },
++{"vmsgeu.vi",  0, INSN_CLASS_V,  "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
++
++{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
++{"vmsge.vx",   0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
++{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
++{"vmsgeu.vx",  0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
++
++{"vminu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_vd_neq_vm, 0},
++{"vminu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_vd_neq_vm, 0},
++{"vmin.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_vd_neq_vm, 0},
++{"vmin.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_vd_neq_vm, 0},
++{"vmaxu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_vd_neq_vm, 0},
++{"vmaxu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_vd_neq_vm, 0},
++{"vmax.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_vd_neq_vm, 0},
++{"vmax.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_vd_neq_vm, 0},
++
++{"vmul.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_vd_neq_vm, 0 },
++{"vmul.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_vd_neq_vm, 0 },
++{"vmulh.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_vd_neq_vm, 0 },
++{"vmulh.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_vd_neq_vm, 0 },
++{"vmulhu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_vd_neq_vm, 0 },
++{"vmulhu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_vd_neq_vm, 0 },
++{"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
++{"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
++
++{"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwmulu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmulu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++{"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
++{"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
++
++{"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
++{"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
++{"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
++{"vnmsac.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_vd_neq_vm, 0},
++{"vmadd.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_vd_neq_vm, 0},
++{"vmadd.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_vd_neq_vm, 0},
++{"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
++{"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
++
++{"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmaccsu.vv", 0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vwmaccsu.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vwmaccus.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
++{"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
++{"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
++{"vdiv.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_vd_neq_vm, 0 },
++{"vremu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_vd_neq_vm, 0 },
++{"vremu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_vd_neq_vm, 0 },
++{"vrem.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_vd_neq_vm, 0 },
++{"vrem.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_vd_neq_vm, 0 },
++
++{"vmerge.vvm", 0, INSN_CLASS_V,  "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
++{"vmerge.vxm", 0, INSN_CLASS_V,  "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
++{"vmerge.vim", 0, INSN_CLASS_V,  "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
++
++{"vmv.v.v",    0, INSN_CLASS_V,  "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
++{"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
++{"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
++
++{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
++{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
++{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
++{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
++{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
++{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
++{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
++{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
++{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
++{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
++
++{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
++{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
++{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
++{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
++{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
++{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
++{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
++{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
++
++{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
++{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
++
++{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
++{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
++{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
++{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
++{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
++{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
++
++{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
++{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
++
++{"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
++{"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
++{"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
++{"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
++{"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
++
++{"vfwadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwadd.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
++{"vfwadd.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
++{"vfwsub.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
++{"vfwsub.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
++
++{"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
++{"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
++{"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
++{"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
++{"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
++
++{"vfwmul.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmul.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
++{"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
++{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
++{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_vd_neq_vm, 0},
++{"vfmsub.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_vd_neq_vm, 0},
++{"vfmsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_vd_neq_vm, 0},
++{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_vd_neq_vm, 0},
++{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_vd_neq_vm, 0},
++{"vfmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_vd_neq_vm, 0},
++{"vfmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_vd_neq_vm, 0},
++{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_vd_neq_vm, 0},
++{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_vd_neq_vm, 0},
++{"vfmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_vd_neq_vm, 0},
++{"vfmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_vd_neq_vm, 0},
++{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
++{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
++
++{"vfwmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
++{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
++{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
++{"vfrec7.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
++{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
++{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
++
++{"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
++{"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
++{"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
++{"vfmax.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
++
++{"vfneg.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
++{"vfabs.v",    0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
++
++{"vfsgnj.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
++{"vfsgnj.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
++{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
++{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_vd_neq_vm, 0},
++{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vd_neq_vm, 0},
++{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_vd_neq_vm, 0},
++
++{"vmfeq.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
++{"vmfeq.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
++{"vmfne.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
++{"vmfne.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
++{"vmflt.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
++{"vmflt.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
++{"vmfle.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
++{"vmfle.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
++{"vmfgt.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
++{"vmfge.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
++
++/* These aliases are for assembly but not disassembly.  */
++{"vmfgt.vv",    0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
++{"vmfge.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
++
++{"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
++{"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
++
++{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
++{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
++{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
++{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
++{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
++{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
++
++{"vfwcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
++{"vfwcvt.f.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
++
++{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
++
++{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
++{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
++{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
++{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
++{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
++{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
++{"vredor.vs",  0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
++{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
++
++{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
++{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
++
++{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
++{"vfredusum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
++{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
++{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
++
++{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
++{"vfwredusum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
++
++{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, INSN_ALIAS},
++{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, INSN_ALIAS},
++{"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++{"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++{"vmclr.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
++{"vmset.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
++{"vmnot.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
++
++{"vmand.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
++{"vmnand.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
++{"vmxor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
++{"vmor.mm",    0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
++{"vmnor.mm",   0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
++{"vmxnor.mm",  0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
++
++{"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
++{"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
++{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
++{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
++{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
++{"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
++{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
++
++{"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
++{"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
++
++{"vfmv.f.s",   0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
++{"vfmv.s.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
++
++{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2_neq_vm, 0},
++{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2_neq_vm, 0},
++{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_vd_neq_vm, 0},
++{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_vd_neq_vm, 0},
++
++{"vslide1up.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2_neq_vm, 0},
++{"vslide1down.vx",  0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_vd_neq_vm, 0},
++{"vfslide1up.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2_neq_vm, 0},
++{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_vd_neq_vm, 0},
++
++{"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++{"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
++{"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
++{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
++
++{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
++
++{"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
++{"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
++{"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
++{"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
++/* END RVV */
++
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+ };
+@@ -1160,6 +2263,26 @@ const struct riscv_opcode riscv_insn_types[] =
+ {"r",       0, INSN_CLASS_F,       "O4,F3,F7,D,s,T",    0, 0, match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,       "O4,F3,F7,d,S,T",    0, 0, match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,       "O4,F3,F7,D,S,T",    0, 0, match_opcode, 0 },
++
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,s,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,s,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,Vs,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,t",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,d,Vs,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,T",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,s,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,s,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,d,S,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,S,Vt",    0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,Vs,t",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,Vs,T",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,s,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,Vd,S,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,d,Vs,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V_AND_F,  "O4,F3,F7,D,Vs,Vt",   0,    0,  match_opcode, 0 },
++{"r",       0, INSN_CLASS_V,        "O4,F3,F7,Vd,Vs,Vt",  0,    0,  match_opcode, 0 },
+ {"r",       0, INSN_CLASS_I,       "O4,F3,F2,d,s,t,r",  0, 0, match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,       "O4,F3,F2,D,s,t,r",  0, 0, match_opcode, 0 },
+ {"r",       0, INSN_CLASS_F,       "O4,F3,F2,d,S,t,r",  0, 0, match_opcode, 0 },
+@@ -1257,4 +2380,4 @@ const struct riscv_opcode riscv_insn_types[] =
+ 
+ /* Terminate the list.  */
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
+-};
++};
+\ No newline at end of file
+-- 
+2.33.1
+

+ 95 - 0
recipes-devtools/binutils/binutils/0003-binutils-nativesdk-Search-for-alternative-ld.so.conf.patch

@@ -0,0 +1,95 @@
+From d49016d3faf684319bf3ac37450558920d70be03 Mon Sep 17 00:00:00 2001
+From: Richard Purdie <richard.purdie@linuxfoundation.org>
+Date: Wed, 19 Feb 2020 09:51:16 -0800
+Subject: [PATCH] binutils-nativesdk: Search for alternative ld.so.conf in SDK
+ installation
+
+We need binutils to look at our ld.so.conf file within the SDK to ensure
+we search the SDK's libdirs as well as those from the host system.
+
+We therefore pass in the directory to the code using a define, then add
+it to a section we relocate in a similar way to the way we relocate the
+gcc internal paths. This ensures that ld works correctly in our buildtools
+tarball.
+
+Standard sysroot relocation doesn't work since we're not in a sysroot,
+we want to use both the host system and SDK libs.
+
+Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
+2020/1/17
+Upstream-Status: Inappropriate [OE specific tweak]
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ ld/Makefile.am | 3 ++-
+ ld/Makefile.in | 3 ++-
+ ld/ldelf.c     | 2 +-
+ ld/ldmain.c    | 1 +
+ ld/ldmain.h    | 1 +
+ 5 files changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/ld/Makefile.am b/ld/Makefile.am
+index f8e99325361..fd196541f59 100644
+--- a/ld/Makefile.am
++++ b/ld/Makefile.am
+@@ -42,7 +42,8 @@ ZLIBINC = @zlibinc@
+ 
+ ELF_CLFAGS=-DELF_LIST_OPTIONS=@elf_list_options@ \
+ 	   -DELF_SHLIB_LIST_OPTIONS=@elf_shlib_list_options@ \
+-	   -DELF_PLT_UNWIND_LIST_OPTIONS=@elf_plt_unwind_list_options@
++	   -DELF_PLT_UNWIND_LIST_OPTIONS=@elf_plt_unwind_list_options@ \
++           -DSYSCONFDIR="\"$(sysconfdir)\""
+ WARN_CFLAGS = @WARN_CFLAGS@
+ NO_WERROR = @NO_WERROR@
+ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
+diff --git a/ld/Makefile.in b/ld/Makefile.in
+index ef2e99e08da..cb8f5bfb70e 100644
+--- a/ld/Makefile.in
++++ b/ld/Makefile.in
+@@ -555,7 +555,8 @@ ZLIB = @zlibdir@ -lz
+ ZLIBINC = @zlibinc@
+ ELF_CLFAGS = -DELF_LIST_OPTIONS=@elf_list_options@ \
+ 	   -DELF_SHLIB_LIST_OPTIONS=@elf_shlib_list_options@ \
+-	   -DELF_PLT_UNWIND_LIST_OPTIONS=@elf_plt_unwind_list_options@
++	   -DELF_PLT_UNWIND_LIST_OPTIONS=@elf_plt_unwind_list_options@ \
++           -DSYSCONFDIR="\"$(sysconfdir)\""
+ 
+ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
+ 
+diff --git a/ld/ldelf.c b/ld/ldelf.c
+index 21e655bb55c..d1615003ede 100644
+--- a/ld/ldelf.c
++++ b/ld/ldelf.c
+@@ -911,7 +911,7 @@ ldelf_check_ld_so_conf (const struct bfd_link_needed_list *l, int force,
+ 
+       info.path = NULL;
+       info.len = info.alloc = 0;
+-      tmppath = concat (ld_sysroot, prefix, "/etc/ld.so.conf",
++      tmppath = concat (ld_sysconfdir, "/etc/ld.so.conf",
+ 			(const char *) NULL);
+       if (!ldelf_parse_ld_so_conf (&info, tmppath))
+ 	{
+diff --git a/ld/ldmain.c b/ld/ldmain.c
+index 42660eb9a3c..5a4a4d5da3d 100644
+--- a/ld/ldmain.c
++++ b/ld/ldmain.c
+@@ -70,6 +70,7 @@ char *program_name;
+ 
+ /* The prefix for system library directories.  */
+ const char *ld_sysroot;
++char ld_sysconfdir[4096] __attribute__ ((section (".gccrelocprefix"))) = SYSCONFDIR;
+ 
+ /* The canonical representation of ld_sysroot.  */
+ char *ld_canon_sysroot;
+diff --git a/ld/ldmain.h b/ld/ldmain.h
+index 39d08a6c378..4c3519e7970 100644
+--- a/ld/ldmain.h
++++ b/ld/ldmain.h
+@@ -23,6 +23,7 @@
+ 
+ extern char *program_name;
+ extern const char *ld_sysroot;
++extern char ld_sysconfdir[4096];
+ extern char *ld_canon_sysroot;
+ extern int ld_canon_sysroot_len;
+ extern FILE *saved_script_handle;

+ 55 - 0
recipes-devtools/binutils/binutils/0003-fix-unrecoginized-b-ext-issue.patch

@@ -0,0 +1,55 @@
+From 995a71ff7113fc95325ee2d8b51cc5a27ee617d8 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Mon, 11 Oct 2021 02:44:58 -0700
+Subject: [PATCH 03/11] fix unrecoginized "b" ext issue
+
+---
+ bfd/elfxx-riscv.c     |  3 ++-
+ gas/config/tc-riscv.c | 17 ++++++++++++++---
+ 2 files changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 39b69e2b0a..9999ec418a 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1077,7 +1077,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", NULL
++  "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause",
++  "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt", "zvamo", "zvlsseg",NULL
+ };
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 898ee89f96..2fb613467e 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -140,9 +140,20 @@ static const struct riscv_ext_version ext_version_table[] =
+ 
+   {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
+-  {"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-  {"zba",   ISA_SPEC_CLASS_DRAFT, 0, 93},
+-  {"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 93},
++  {"b",     ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zba",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbe",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbf",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbm",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbp",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbr",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++
++  {"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
++  {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+ 
+   /* Terminate the list.  */
+   {NULL, 0, 0, 0}
+-- 
+2.33.1
+

+ 0 - 523
recipes-devtools/binutils/binutils/0004-add-missed-sysroff-file.patch

@@ -1,523 +0,0 @@
-From 7a9c43b6434bdddd8557a8144369a0c9bcfba977 Mon Sep 17 00:00:00 2001
-From: "max.ma" <max.ma@starfivetech.com>
-Date: Wed, 2 Jun 2021 23:43:41 -0700
-Subject: [PATCH 04/28] add missed sysroff file
-
----
- binutils/sysroff.info | 504 ++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 504 insertions(+)
- create mode 100755 binutils/sysroff.info
-
-diff --git a/binutils/sysroff.info b/binutils/sysroff.info
-new file mode 100755
-index 0000000000..d82157669a
---- /dev/null
-+++ b/binutils/sysroff.info
-@@ -0,0 +1,504 @@
-+("cs" 0x0
-+ (("size") (1 byte) ("size"))
-+
-+ (("hd") (1 byte) ("hd"))
-+ (("hs") (1 byte) ("hs"))
-+ (("un") (1 byte) ("un"))
-+ (("us") (1 byte) ("us"))
-+
-+ (("sc") (1 byte) ("sc"))
-+ (("ss") (1 byte) ("ss"))
-+ (("er") (1 byte) ("er"))
-+ (("ed") (1 byte) ("ed"))
-+
-+ (("sh") (1 byte) ("sh"))
-+ (("ob") (1 byte) ("ob"))
-+ (("rl") (1 byte) ("rl"))
-+ (("du") (1 byte) ("du"))
-+
-+ (("dps") (1 byte) ("dps"))
-+ (("dsy") (1 byte) ("dsy"))
-+ (("dty") (1 byte) ("dty"))
-+ (("dln") (1 byte) ("dln"))
-+
-+ (("dso") (1 byte) ("dso"))
-+ (("dus") (1 byte) ("dus"))
-+ (("dss") (1 byte) ("dss"))
-+ (("dbt") (1 byte) ("dbt"))
-+
-+ (("dpp") (1 byte) ("dpp"))
-+ (("dfp") (1 byte) ("dfp"))
-+ (("den") (1 byte) ("den"))
-+ (("dds") (1 byte) ("dds"))
-+
-+ (("dar") (1 byte) ("dar"))
-+ (("dpt") (1 byte) ("dpt"))
-+ (("dul") (1 byte) ("dul"))
-+ (("dse") (1 byte) ("dse"))
-+
-+ (("dot") (1 byte) ("dot")))
-+
-+
-+("hd" 0x04
-+ (("module type") (4 bits) ("mt")
-+  (("MTYPE_ABS_LM" 	"0")
-+   ("MTYPE_REL_LM" 	"1")
-+   ("MTYPE_OMS_OR_LMS" 	"2")
-+   ("MTYPE_UNSPEC" 	"0xf")))
-+ (("spare")(4 bits) ("spare1"))
-+ (("creation date")( chars 12 bytes)( "cd"))
-+ (("number of units") (2 bytes) ("nu"))
-+ (("code") (1 byte) ("code"))
-+ (("version") (chars 4 bytes) ("ver"))
-+ (("address update") (1 byte) ("au"))
-+ (("segment identifier") (1 bit) ("si"))
-+ (("address field length") (4 bits) ("afl"))
-+ (("spare")(3 bits) ("spare2"))
-+ (("space size within segment") (1 byte) ("spcsz"))
-+ (("segment size")  	(1 byte) ("segsz"))
-+ (("segment shift") 	(1 byte) ("segsh"))
-+ (("entry point") 	(1 byte) ("ep"))
-+ (cond "ptr->ep"
-+       (cond "ptr->mt != MTYPE_ABS_LM"
-+	     (("unit appearance number") (2 bytes) ("uan"))
-+	     (("section appearance number") (2 bytes) ("sa")))
-+       (cond "segmented_p"
-+	     (("segment address") (segsize bytes) ("sad")))
-+       (("address") (addrsize bytes) ("address")))
-+ (("os name") (chars variable bytes) ("os"))
-+ (("sys name") (chars variable bytes) ("sys"))
-+ (("module name") (chars variable bytes) ("mn"))
-+ (("cpu") (chars variable bytes) ("cpu")))
-+
-+
-+("hs" 0x05
-+ (("neg number") (2 bytes) ("neg")))
-+
-+
-+("un" 0x06
-+ (("format") (2 bits) ("format")
-+  (("FORMAT_LM" "0")
-+   ("FORMAT_OM" "1")
-+   ("FORMAT_OMS_OR_LMS" "2")))
-+ (("spare") (6 bits) ("spare1"))
-+ (("number of sections") (2 bytes) ("nsections"))
-+ (("number of external refs") (2 bytes) ("nextrefs"))
-+ (("number of external defs") (2 bytes) ("nextdefs"))
-+ (("unit name") (chars variable byte) ("name"))
-+ (("tool name") (chars variable byte) ("tool"))
-+ (("creation date") (chars 12 bytes) ("tcd"))
-+ (("linker name") (chars variable byte) ("linker"))
-+ (("creation date") (chars 12 bytes) ("lcd")))
-+
-+
-+("us" 0x07
-+ (("negotiation number") (2 bytes) ("neg")))
-+
-+
-+("sc" 0x08
-+ (("format") (2 bits) ("format"))
-+ (("spare") (6 bits) ("spare"))
-+ (("segment address") (segsize bytes) ("segadd"))
-+ (("address") (addrsize bytes) ("addr"))
-+ (("length") (addrsize bytes) ("length"))
-+ (("alignment") (addrsize bytes) ("align"))
-+ (("contents") (4 bits) ("contents")
-+  (("CONTENTS_CODE" "0")
-+   ("CONTENTS_DATA" "1")
-+   ("CONTENTS_STACK" "2")
-+   ("CONTENTS_DUMMY" "3")
-+   ("CONTENTS_SPECIAL" "4")
-+   ("CONTENTS_NONSPEC" "0xf")))
-+ (("concat") (4 bits) ("concat")
-+  (("CONCAT_SIMPLE" "0")
-+   ("CONCAT_SHAREDC" "1")
-+   ("CONCAT_DUMMY" "2")
-+   ("CONCAT_GROUP" "3")
-+   ("CONCAT_SHARED" "4")
-+   ("CONCAT_PRIVATE" "5")
-+   ("CONCAT_UNSPEC" "0xf")))
-+ (("read") (2 bits) ("read"))
-+ (("write") (2 bits) ("write"))
-+ (("exec") (2 bits) ("exec"))
-+ (("initialized") (2 bits) ("init"))
-+ (("mode") (2 bits) ("mode"))
-+ (("spare") (6 bits) ("spare1"))
-+ (("name") (chars variable byte) ("name")))
-+
-+
-+("ss" 0x09
-+ (("neg number") (2 bytes) ("neg")))
-+
-+
-+("er" 0x0c
-+ (("symbol type") (2 bits) ("type")
-+  (("ER_ENTRY" "0")
-+   ("ER_DATA" "1")
-+   ("ER_NOTDEF" "2")
-+   ("ER_NOTSPEC" "3")))
-+ (("spare") (6 bits) ("spare"))
-+ (("symbol name") (chars variable byte) ("name")))
-+
-+
-+("ed" 0x14
-+ (("section appearance number") (2 bytes) ("section"))
-+ (("symbol type") (3 bits) ("type")
-+  (("ED_TYPE_ENTRY" "0")
-+   ("ED_TYPE_DATA" "1")
-+   ("ED_TYPE_CONST" "2")
-+   ("ED_TYPE_NOTSPEC" "7")))
-+ (("spare") (5 bits) ("spare"))
-+ (cond "ptr->type==ED_TYPE_ENTRY || ptr->type==ED_TYPE_DATA"
-+       (("symbol address") (addrsize bytes) ("address")))
-+ (cond "ptr->type==ED_TYPE_CONST"
-+       (("constant value") (addrsize bytes) ("constant")))
-+ (("symbol name") (chars variable byte) ("name")))
-+
-+
-+("sh" 0x1a
-+ (("unit appearance number") (2 bytes) ("unit"))
-+ (("section appearance number") (2 bytes) ("section")))
-+
-+
-+("ob" 0x1c
-+ (("starting address flag") (1 bit) ("saf"))
-+ (("compression flag") (1 bit) ("cpf"))
-+ (("spare") (6 bits) ("spare"))
-+ (cond "ptr->saf"
-+       ( ("starting address") (addrsize bytes) ("address")))
-+ (cond "ptr->cpf"
-+       (("comp reps") (addrsize bytes) ("compreps")))
-+ (("data") (barray counted byte) ("data")))
-+
-+
-+("rl" 0x20
-+ (("boundary of relocatable area") (4 bits) ("boundary"))
-+ (("address polarity") (1 bit) ("apol"))
-+ (("segment number") (1 bit) ("segment"))
-+ (("sign of relocation") (1 bit) ("sign"))
-+ (("check range") (1 bit) ("check"))
-+ (("reloc address") (addrsize bytes) ("addr"))
-+
-+ (("bit loc") (1 byte) ("bitloc"))
-+ (("field length") (1 byte) ("flen"))
-+ (("bcount") (1 byte) ("bcount"))
-+ (("operator") (1 byte) ("op")
-+  (("OP_RELOC_ADDR" "1")
-+   ("OP_SEC_REF" "0")
-+   ("OP_EXT_REF" "2")))
-+ (cond "ptr->op == OP_EXT_REF"
-+       (("symbol number") (2 bytes) ("symn"))	)
-+
-+ (cond "ptr->op == OP_SEC_REF"
-+       (("section number") (2 bytes) ("secn"))
-+       (("const opcode") (1 byte) ("copcode_is_3"))
-+       (("addend length") (1 byte) ("alength_is_4"))
-+       (("addend") (4 byte) ("addend"))
-+       (("plus opcode") (1 byte) ("aopcode_is_0x20")))
-+
-+ (cond "ptr->op == OP_RELOC_ADDR"
-+       (("dunno") (2 bytes) ("dunno")))
-+
-+ (("end")  (1 byte) ("end")))
-+
-+
-+("du" 0x30
-+ (("format") (2 bits) ("format"))
-+ (("optimized") (1 bit) ("optimized"))
-+ (("stackfrmt") (2 bits) ("stackfrmt"))
-+ (("spare") (3 bits) ("spare"))
-+ (("unit number") (2 bytes) ("unit"))
-+ (("sections") (2 bytes) ("sections"))
-+ (repeat "ptr->sections"
-+	 (("section appearance number") (2 bytes) ("san"))
-+	 (("address") (addrsize bytes) ("address"))
-+	 (("section length") (addrsize bytes) ("length")))
-+ (("tool name") (chars variable byte) ("tool"))
-+ (("creation date") (chars 12 bytes) ("date")))
-+
-+
-+("dsy" 0x34
-+ (("symbol type") (7 bits) ("type")
-+  (("STYPE_VAR" "0")
-+   ("STYPE_LAB" "1")
-+   ("STYPE_PROC" "2")
-+   ("STYPE_FUNC" "3")
-+   ("STYPE_TYPE" "4")
-+   ("STYPE_CONST" "5")
-+   ("STYPE_ENTRY" "6")
-+   ("STYPE_MEMBER" "7")
-+   ("STYPE_ENUM" "8")
-+   ("STYPE_TAG" "9")
-+   ("STYPE_PACKAGE" "10")
-+   ("STYPE_GENERIC" "11")
-+   ("STYPE_TASK" "12")
-+   ("STYPE_EXCEPTION" "13")
-+   ("STYPE_PARAMETER" "14")
-+   ("STYPE_EQUATE" "15")
-+   ("STYPE_UNSPEC" "0x7f")))
-+ (("assignment info") (1 bit) ("assign"))
-+ (("symbol id") (2 bytes) ("snumber"))
-+ (("symbol name") (chars variable bytes) ("sname"))
-+ (("nesting level") (2 bytes) ("nesting"))
-+ (cond "ptr->assign"
-+       (("assignment type") (1 byte)  ("ainfo")
-+	(("AINFO_REG" "1")
-+	 ("AINFO_STATIC_EXT_DEF" "2")
-+	 ("AINFO_STATIC_EXT_REF" "3")
-+	 ("AINFO_STATIC_INT" "4")
-+	 ("AINFO_STATIC_COM" "5")
-+	 ("AINFO_AUTO" "6")
-+	 ("AINFO_CONST" "7")
-+	 ("AINFO_UNSPEC" "0xff")))
-+       (("data length") (addrsize bytes) ("dlength"))
-+       (cond "ptr->ainfo == AINFO_STATIC_EXT_DEF
-+            || ptr->ainfo == AINFO_STATIC_INT
-+            || ptr->ainfo == AINFO_STATIC_COM"
-+	     (("section number")  (2 bytes) ("section")))
-+       (cond "ptr->ainfo == AINFO_STATIC_EXT_DEF
-+            || ptr->ainfo == AINFO_STATIC_INT
-+            || ptr->ainfo == AINFO_STATIC_COM
-+            || ptr->ainfo == AINFO_AUTO"
-+	     (("address") (addrsize bytes) ("address")))
-+       (cond "ptr->ainfo == AINFO_REG"
-+	     (("register name") (chars variable bytes) ("reg")))
-+       (cond "ptr->ainfo == AINFO_STATIC_EXT_DEF
-+	    || ptr->ainfo == AINFO_STATIC_EXT_REF"
-+	     (("external name") (chars variable bytes) ("ename")))
-+       (cond "ptr->ainfo == AINFO_CONST"
-+	     (("constant") (chars variable bytes) ("constant"))))
-+ (cond "ptr->type == STYPE_MEMBER"
-+       (("assignment unit") (1 bit) ("bitunit"))
-+       (("spare") (7 bits) ("spare2"))
-+       (("field length") (addrsize bytes) ("field_len"))
-+       (("field offset") (addrsize bytes) ("field_off"))
-+       (cond "ptr->bitunit"
-+	     (("bit offset") (addrsize bytes) ("field_bitoff"))))
-+ (cond "ptr->type== STYPE_ENUM"
-+       (("value length") (1 byte) ("evallen"))
-+       (("value") (4 bytes) ("evalue")))
-+ (cond "ptr->type == STYPE_CONST"
-+       (("value") (chars variable bytes) ("cvalue")))
-+ (cond "ptr->type == STYPE_EQUATE"
-+       (("value length") (1 byte) ("qvallen"))
-+       (("value") (4 bytes) ("qvalue"))
-+       (("basic type") (1 byte) ("btype"))
-+       (("size information") (addrsize bytes) ("sizeinfo"))
-+       (("sign") (2 bits) ("sign"))
-+       (("floating point type") (6 bits) ("flt_type")))
-+ (("source file number") (2 bytes) ("sfn"))
-+ (("source line number") (2 bytes) ("sln"))
-+ (("negotiation number") (2 bytes) ("neg"))
-+ (cond "ptr->type == STYPE_TAG"
-+       (("magic") (1 byte) ("magic"))))
-+
-+
-+
-+("dul" 0x52
-+ (("max declaration type flag") (1 bit) ("max_variable"))
-+ (("max spare") (7 bits) ("maxspare"))
-+ (cond "ptr->max_variable == 0"
-+       (("maximum") (addrsize bytes) ("max"))
-+       (("max mode") (chars variable bytes) ("maxmode")))
-+
-+ (("min declaration type flag") (1 bit) ("min_variable"))
-+ (("min spare") (7 bits) ("minspare"))
-+ (cond "ptr->min_variable == 0"
-+       (("minimum") (addrsize bytes) ("min"))
-+       (("min mode") (chars variable bytes) ("minmode"))))
-+
-+
-+("dty" 0x36
-+ (("end flag") (1 bit) ("end"))
-+ (("spare") (7 bits) ("spare"))
-+ (cond "!ptr->end"
-+       (("negotiation") (2 bytes) ("neg"))))
-+
-+
-+("dbt" 0x44
-+ (("basic type") (1 byte) ("btype")
-+  (("BTYPE_VOID" "0")
-+   ("BTYPE_UNDEF" "1")
-+   ("BTYPE_CHAR" "2")
-+   ("BTYPE_INT" "3")
-+   ("BTYPE_FLOAT" "4")
-+   ("BTYPE_BIT" "5")
-+   ("BTYPE_STRING" "6")
-+   ("BTYPE_DECIMAL" "7")
-+   ("BTYPE_ENUM" "8")
-+   ("BTYPE_STRUCT" "9")
-+   ("BTYPE_TYPE" "10")
-+   ("BTYPE_TAG" "11")
-+   ("BTYPE_UNSPEC" "0xff")))
-+ (("size info") (addrsize bytes) ("bitsize"))
-+ (("sign") (2 bits) ("sign")
-+  (("SIGN_SIGNED" "0")
-+   ("SIGN_UNSIGNED" "1")
-+   ("SIGN_UNSPEC" "3")))
-+ (("floating point type") (6 bits) ("fptype")
-+  (("FPTYPE_SINGLE" "0")
-+   ("FPTYPE_DOUBLE" "1")
-+   ("FPTYPE_EXTENDED" "2")
-+   ("FPTYPE_NOTSPEC" "0x3f")))
-+ (cond "ptr->btype==BTYPE_TAG || ptr->btype == BTYPE_TYPE"
-+       (("symbol id") (2 bytes) ("sid")))
-+ (("negotiation") (2 bytes) ("neg")))
-+
-+("dar" 0x4e
-+ (("element length" ) (addrsize bytes) ("length"))
-+ (("dims") (1 byte) ("dims"))
-+ (repeat "ptr->dims"
-+	 (("variable flag") (1 bit) ("variable")
-+	  (("VARIABLE_FIXED" "0")
-+	   ("VARIABLE_VARIABLE" "1")))
-+
-+	 (("subscript type") (1 bit) ("subtype")
-+	  (("SUB_INTEGER" "0")
-+	   ("SUB_TYPE"    "1")))
-+
-+	 (("spare") (6 bits) ("spare"))
-+
-+	 (cond "ptr->subtype[n] == SUB_TYPE"
-+	       (("sub symbol id") (2 bytes) ("sid")))
-+
-+	 (cond "ptr->subtype[n] == SUB_INTEGER"
-+	       (("max declaration type flag") (1 bit) ("max_variable"))
-+	       (("max spare") (7 bits) ("maxspare"))
-+	       ;; FIXME: next field should be conditional on max_variable,
-+	       (("maximum") (addrsize bytes) ("max"))
-+
-+	       (("min declaration type flag") (1 bit) ("min_variable"))
-+	       (("min spare") (7 bits) ("minspare"))
-+	       ;; FIXME: next field should be conditional on min_variable
-+	       (("minimum") (addrsize bytes) ("min"))))
-+ (("negotiation") (2 bytes) ("neg")))
-+
-+
-+("dso" 0x3a
-+ (("function name") (2 bytes) ("sid"))
-+ (("sp update count") (4 bytes) ("spupdates"))
-+ (repeat "ptr->spupdates"
-+	 (("update address") (addrsize bytes) ("address"))
-+	 (("offset") (addrsize bytes) ("offset"))))
-+
-+("dln" 0x38
-+ (("number of lines") (2 bytes) ("nln"))
-+ (repeat "ptr->nln"
-+	 (("source file number") (2 bytes) ("sfn"))
-+	 (("source line number") (2 bytes) ("sln"))
-+	 (("section number") (2 bytes) ("section"))
-+	 (("from address") (addrsize bytes) ("from_address"))
-+	 (("to address") (addrsize bytes) ("to_address"))
-+	 (("call count") (2 bytes) ("cc"))
-+	 )
-+ (("neg") (2 bytes) ("neg")))
-+
-+("dpp" 0x46
-+ (("start/end") (1 bit) ("end"))
-+ (("spare") (7 bits) ("spare"))
-+ (cond "!ptr->end"
-+       (("params") (1 byte) ("params"))
-+       (("neg number") (2 bytes) ("neg"))))
-+
-+("den" 0x4a
-+ (("start/end") (1 bit) ("end"))
-+ (("spare") (7 bits) ("spare"))
-+ (cond "!ptr->end"
-+       (("neg number") (2 bytes) ("neg"))))
-+
-+("dfp" 0x48
-+ (("start/end flag") (1 bit) ("end"))
-+ (("spare") (7 bits) ("spare"))
-+ (cond "!ptr->end"
-+       (("number of parameters") (1 byte) ("nparams"))
-+       (("neg number") (2 bytes) ("neg"))))
-+
-+("dds" 0x4c
-+ (("start/end") (1 bit) ("end"))
-+ (("spare") (7 bits) ("spare"))
-+ (cond "!ptr->end"
-+       (("neg number") (2 bytes) ("neg"))))
-+
-+("dpt" 0x50
-+ (("neg number") (2 bytes) ("neg"))
-+ (("dunno") (1 byte) ("dunno")))
-+
-+("dse" 0x54
-+ (("neg number") (2 bytes) ("neg"))
-+ (("dunno") (1 byte) ("dunno")))
-+
-+("dot" 0x56
-+ (("unknown") (1 byte) ("unknown")))
-+; FIXME: unknown field should be repeated symbol number?
-+
-+
-+("dss" 0x42
-+ (("type") (1 byte) ("type"))
-+ (("external/internal") (1 bit) ("internal"))
-+ (("spare") (7 bits) ("spare"))
-+ (cond "!ptr->internal"
-+       (  ("package name") (chars variable byte) ("package")))
-+ (cond "ptr->internal"
-+       (("symbol id") (2 bytes) ("id")))
-+ (("record type") (2 bytes) ("record"))
-+ (("rules") (chars variable byte) ("rules"))
-+ (("number of symbols") (2 bytes) ("nsymbols"))
-+ (("unknown" ) (2 bytes) ("fixme")))
-+
-+("pss" 0x40
-+ (("negotiation number") (2 bytes) ("efn"))
-+ (("number of source files") (2 bytes) ("ns"))
-+ (repeat "ptr->ns"
-+	 (("directory reference bit") (1 bit) ("drb"))
-+	 (("spare") (7 bits) ("spare"))
-+	 (("completed file name") (chars variable byte) ("fname"))
-+	 (cond "ptr->drb[n]"
-+	       (("directory apperance number") (2 bytes) ("dan"))))
-+
-+ (("number of directories") (2 bytes) ("ndir"))
-+ (repeat "ptr->ndir"
-+	 (("directory name") (chars variable bytes) ("dname"))))
-+
-+
-+; FIXME: the tr block has no contents. sysinfo, etc. aren't prepared
-+; to deal with that.
-+; ("tr" 0x7f)
-+
-+
-+("dus" 0x40
-+ (("negotiation number") (2 bytes) ("efn"))
-+ (("number of source files") (2 bytes) ("ns"))
-+ (repeat "ptr->ns"
-+	 (("directory reference bit") (1 bit) ("drb"))
-+	 (("spare") (7 bits) ("spare"))
-+	 (("completed file name") (chars variable byte) ("fname"))
-+	 (cond "ptr->drb[n]"
-+	       (("directory apperance number") (2 bytes) ("dan"))))
-+ (("number of directories") (2 bytes) ("ndir"))
-+ (repeat "ptr->ndir"
-+	 (("directory name") (chars variable bytes) ("dname"))))
-+
-+
-+("dps" 0x32
-+ (("start/end flag") (1 bit) ("end"))
-+ (("block type") (7 bits) ("type")
-+  (("BLOCK_TYPE_COMPUNIT" "0")
-+   ("BLOCK_TYPE_PROCEDURE" "2")
-+   ("BLOCK_TYPE_FUNCTION" "3")
-+   ("BLOCK_TYPE_BLOCK" "4")
-+   ("BLOCK_TYPE_BASIC" "9")))
-+ (cond "!ptr->end"
-+       (("optimization") (1 byte) ("opt"))
-+       (("section number") (2 bytes) ("san"))
-+       (("address") (addrsize bytes) ("address"))
-+       (("block size") (addrsize bytes) ("block_size"))
-+       (("nesting") (1 byte) ("nesting"))
-+       (cond "ptr->type == BLOCK_TYPE_PROCEDURE
-+	    || ptr->type == BLOCK_TYPE_FUNCTION"
-+	     (("return address") (1 bit) ("retaddr"))
-+	     (("interrupt function flag") (1 bit) ("intrflag"))
-+	     (("stack update flag") (1 bit) ("stackflag"))
-+	     (("intra page JMP") (1 bit) ("intrpagejmp"))
-+	     (("spare") (4 bits) ("spare")))
-+       (("neg number") (2 bytes) ("neg"))))
-+
--- 
-2.33.0
-

+ 41 - 0
recipes-devtools/binutils/binutils/0004-configure-widen-the-regexp-for-SH-architectures.patch

@@ -0,0 +1,41 @@
+From b8d43b6b8d98e176346871c92935458b06598c5b Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Mon, 2 Mar 2015 01:07:33 +0000
+Subject: [PATCH] configure: widen the regexp for SH architectures
+
+gprof needs to know about uclibc
+
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ configure    | 2 +-
+ configure.ac | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/configure b/configure
+index 3dd206525a7..e8ba1a1d3de 100755
+--- a/configure
++++ b/configure
+@@ -3892,7 +3892,7 @@ case "${target}" in
+   nvptx*-*-*)
+     noconfigdirs="$noconfigdirs target-libssp target-libstdc++-v3 target-libobjc"
+     ;;
+-  sh-*-*)
++  sh*-*-* | sh64-*-*)
+     case "${target}" in
+       sh*-*-elf)
+          ;;
+diff --git a/configure.ac b/configure.ac
+index 797a624621e..3a8a3ae1f3b 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -1175,7 +1175,7 @@ case "${target}" in
+   nvptx*-*-*)
+     noconfigdirs="$noconfigdirs target-libssp target-libstdc++-v3 target-libobjc"
+     ;;
+-  sh-*-*)
++  sh*-*-* | sh64-*-*)
+     case "${target}" in
+       sh*-*-elf)
+          ;;

+ 24 - 0
recipes-devtools/binutils/binutils/0004-set-v-ext-version-to-1.0-draft.patch

@@ -0,0 +1,24 @@
+From de7fa1850d5ae66372033951a59750fab96e4465 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Fri, 15 Oct 2021 01:06:59 -0700
+Subject: [PATCH 04/11] set v ext version to 1.0 draft
+
+---
+ gas/config/tc-riscv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 2fb613467e..cb8d8ef79e 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -155,6 +155,7 @@ static const struct riscv_ext_version ext_version_table[] =
+   {"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
+   {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+ 
++  {"v", ISA_SPEC_CLASS_DRAFT, 1, 0},
+   /* Terminate the list.  */
+   {NULL, 0, 0, 0}
+ };
+-- 
+2.33.1
+

+ 4 - 4
recipes-devtools/binutils/binutils/0005-Point-scripts-location-to-libdir.patch

@@ -1,4 +1,4 @@
-From 6a67d277941228d997b527990960413f8444fb81 Mon Sep 17 00:00:00 2001
+From 1a9fcaae50e63b993019bd4dc00219e43421efdc Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
 Date: Mon, 2 Mar 2015 01:09:58 +0000
 Subject: [PATCH] Point scripts location to libdir
@@ -12,7 +12,7 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
  2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/ld/Makefile.am b/ld/Makefile.am
-index 3b01357b651..b7a1f7491b0 100644
+index fd196541f59..d94fa7e64e1 100644
 --- a/ld/Makefile.am
 +++ b/ld/Makefile.am
 @@ -51,7 +51,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
@@ -25,10 +25,10 @@ index 3b01357b651..b7a1f7491b0 100644
  EMUL = @EMUL@
  EMULATION_OFILES = @EMULATION_OFILES@
 diff --git a/ld/Makefile.in b/ld/Makefile.in
-index a6382bf2a45..5ee3a4971be 100644
+index cb8f5bfb70e..9a58879c5ca 100644
 --- a/ld/Makefile.in
 +++ b/ld/Makefile.in
-@@ -562,7 +562,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
+@@ -563,7 +563,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)
  # We put the scripts in the directory $(scriptdir)/ldscripts.
  # We can't put the scripts in $(datadir) because the SEARCH_DIR
  # directives need to be different for native and cross linkers.

+ 27 - 0
recipes-devtools/binutils/binutils/0005-fix-incorrect-RCLASS_MAX.patch

@@ -0,0 +1,27 @@
+From 798531e05015ae09ddf9a71d6e6abff7df4f89c5 Mon Sep 17 00:00:00 2001
+From: "max.ma" <max.ma@starfivetech.com>
+Date: Fri, 15 Oct 2021 01:23:18 -0700
+Subject: [PATCH 05/11] fix incorrect RCLASS_MAX
+
+---
+ gas/config/tc-riscv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index cb8d8ef79e..3f6f7848b9 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -829,9 +829,9 @@ enum reg_class
+ {
+   RCLASS_GPR,
+   RCLASS_FPR,
+-  RCLASS_MAX,
+   RCLASS_VECR,
+   RCLASS_VECM,
++  RCLASS_MAX,
+   RCLASS_CSR
+ };
+ 
+-- 
+2.33.1
+

+ 0 - 5703
recipes-devtools/binutils/binutils/0005-support-Dubhe-V-extension.patch

@@ -1,5703 +0,0 @@
-From 2824e8fad46464ac663d078f95ebcb4e69184c6f Mon Sep 17 00:00:00 2001
-From: "eric.tang" <eric.tang@starfivetech.com>
-Date: Fri, 4 Jun 2021 14:26:05 +0800
-Subject: [PATCH 05/28] support Dubhe V extension
-
-Signed-off-by: eric.tang <eric.tang@starfivetech.com>
----
- gas/testsuite/gas/riscv/insn.d                |   47 +-
- gas/testsuite/gas/riscv/insn.s                |   64 +
- gas/testsuite/gas/riscv/v-zero-imm.d          |   17 +
- gas/testsuite/gas/riscv/v-zero-imm.s          |    8 +
- .../riscv/vector-insns-fail-arith-floatp.d    |    3 +
- .../riscv/vector-insns-fail-arith-floatp.l    |   39 +
- .../riscv/vector-insns-fail-arith-floatp.s    |  123 ++
- .../gas/riscv/vector-insns-fail-arith-int.d   |    3 +
- .../gas/riscv/vector-insns-fail-arith-int.l   |   62 +
- .../gas/riscv/vector-insns-fail-arith-int.s   |  187 ++
- .../gas/riscv/vector-insns-fail-load-store.d  |    3 +
- .../gas/riscv/vector-insns-fail-load-store.l  |   25 +
- .../gas/riscv/vector-insns-fail-load-store.s  |   43 +
- .../gas/riscv/vector-insns-fail-permutation.d |    3 +
- .../gas/riscv/vector-insns-fail-permutation.l |   19 +
- .../gas/riscv/vector-insns-fail-permutation.s |   37 +
- .../gas/riscv/vector-insns-fail-unsupport.d   |    3 +
- .../gas/riscv/vector-insns-fail-unsupport.l   | 1469 ++++++++++++++
- .../gas/riscv/vector-insns-fail-unsupport.s   | 1679 +++++++++++++++++
- .../gas/riscv/vector-insns-vmsgtvx.d          |   29 +
- .../gas/riscv/vector-insns-vmsgtvx.s          |    9 +
- gas/testsuite/gas/riscv/vector-insns.d        |  476 +++++
- gas/testsuite/gas/riscv/vector-insns.s        |  521 +++++
- opcodes/riscv-opc.c                           |  535 +-----
- 24 files changed, 4869 insertions(+), 535 deletions(-)
- create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
- create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
- create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
- create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
-
-diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
-index 8f0badfce1..e7a17b11d5 100644
---- a/gas/testsuite/gas/riscv/insn.d
-+++ b/gas/testsuite/gas/riscv/insn.d
-@@ -1,4 +1,4 @@
--#as: -march=rv32ifc
-+#as: -march=rv32ifcv0p10
- #objdump: -dr
- 
- .*:[ 	]+file format .*
-@@ -63,3 +63,48 @@ Disassembly of section .text:
- [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
- [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
- [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
-+[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad67587[ 	]+vlse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+08d675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3,v0.t
-+[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+0ad675a7[ 	]+vsse64.v[ 	]+v11,\(a2\),a3
-+[^:]+:[ 	]+00067587[ 	]+vle64.v[ 	]+v11,\(a2\),v0.t
-+[^:]+:[ 	]+000675a7[ 	]+vse64.v[ 	]+v11,\(a2\),v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d605d7[ 	]+vadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d615d7[ 	]+vfadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d615d7[ 	]+vfadd.vv[ 	]+v11,v13,v12,v0.t
-+[^:]+:[ 	]+00d645d7[ 	]+vadd.vx[ 	]+v11,v13,a2,v0.t
-+[^:]+:[ 	]+00d645d7[ 	]+vadd.vx[ 	]+v11,v13,a2,v0.t
-+[^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
-+[^:]+:[ 	]+00d655d7[ 	]+vfadd.vf[ 	]+v11,v13,fa2,v0.t
-+[^:]+:[ 	]+38d665d7[ 	]+vslide1up.vx[ 	]+v11,v13,a2,v0.t
-+[^:]+:[ 	]+3cd665d7[ 	]+vslide1down.vx[ 	]+v11,v13,a2,v0.t
-+[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e16,mf8,tu,mu
-+[^:]+:[ 	]+00d675d7[ 	]+vsetvli[ 	]+a1,a2,e16,mf8,tu,mu
-+[^:]+:[ 	]+00d035d7[ 	]+vadd.vi[ 	]+v11,v13,0,v0.t
-+[^:]+:[ 	]+00d0b5d7[ 	]+vadd.vi[ 	]+v11,v13,1,v0.t
-+[^:]+:[ 	]+00d7b5d7[ 	]+vadd.vi[ 	]+v11,v13,15,v0.t
-+[^:]+:[ 	]+00d835d7[ 	]+vadd.vi[ 	]+v11,v13,-16,v0.t
-+[^:]+:[ 	]+00df35d7[ 	]+vadd.vi[ 	]+v11,v13,-2,v0.t
-+[^:]+:[ 	]+00dfb5d7[ 	]+vadd.vi[ 	]+v11,v13,-1,v0.t
-diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
-index 6c08f49d43..5f2f75e88b 100644
---- a/gas/testsuite/gas/riscv/insn.s
-+++ b/gas/testsuite/gas/riscv/insn.s
-@@ -47,3 +47,67 @@ target:
- 	.insn r  0x33,  0,  0, fa0, a1, fa2
- 	.insn r  0x33,  0,  0, a0, fa1, fa2
- 	.insn r  0x33,  0,  0, fa0, fa1, fa2
-+
-+# vamo
-+# F3: width[14:12]
-+# F7: amoop[31:27] + wd[26] + vm[25]
-+
-+# vmem
-+# F3: width[14:12]
-+# F7: nf[31:29] + mop[28:26] + vm[25]
-+
-+	.insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
-+	.insn r LOAD_FP, 0x7, 0x4, v11, a2, a3
-+	.insn r LOAD_FP, 0x7, 0x4, v11, fa2, a3
-+	.insn r LOAD_FP, 0x7, 0x4, v11, a2, fa3
-+	.insn r LOAD_FP, 0x7, 0x4, v11, fa2, fa3
-+	.insn r 0x7, 0x7, 0x5, a1, v12, a3
-+	.insn r 0x7, 0x7, 0x5, fa1, v12, a3
-+	.insn r 0x7, 0x7, 0x5, a1, v12, fa3
-+	.insn r 0x7, 0x7, 0x5, fa1, v12, fa3
-+	.insn r 0x7, 0x7, 0x5, a1, a2, v13
-+	.insn r STORE_FP, 0x7, 0x4, fa1, a2, v13
-+	.insn r STORE_FP, 0x7, 0x4, a1, fa2, v13
-+	.insn r STORE_FP, 0x7, 0x4, fa1, fa2, v13
-+	.insn r STORE_FP, 0x7, 0x4, a1, v12, v13
-+	.insn r STORE_FP, 0x7, 0x4, fa1, v12, v13
-+	.insn r 0x27, 0x7, 0x5, v11, a2, v13
-+	.insn r 0x27, 0x7, 0x5, v11, fa2, v13
-+	.insn r 0x27, 0x7, 0x5, v11, v12, a3
-+	.insn r 0x27, 0x7, 0x5, v11, v12, fa3
-+	.insn r 0x27, 0x7, 0x5, v11, v12, v13
-+	# unit-stride
-+	.insn r LOAD_FP, 0x7, 0x0, v11, a2, x0
-+	#.insn r LOAD_FP, 0x7, 0x1, v11, a2, x16
-+	.insn r STORE_FP, 0x7, 0x0, v11, a2, x0
-+
-+# valu and vcfg
-+# F3: funct3[14:12]
-+# F7: F6[31:26] + vm[25]
-+
-+	.insn r 0x57, 0x0, 0x0, v11, a2, a3
-+	.insn r 0x57, 0x0, 0x0, v11, fa2, a3
-+	.insn r 0x57, 0x0, 0x0, v11, a2, fa3
-+	.insn r 0x57, 0x0, 0x0, v11, fa2, fa3
-+	.insn r 0x57, 0x0, 0x0, a1, v12, a3
-+	.insn r 0x57, 0x0, 0x0, fa1, v12, a3
-+	.insn r 0x57, 0x0, 0x0, a1, v12, fa3
-+	.insn r 0x57, 0x1, 0x0, fa1, v12, fa3
-+	.insn r 0x57, 0x1, 0x0, a1, a2, v13
-+	#.insn r 0x57, 0x2, 0x0, fa1, a2, v13
-+	#.insn r 0x57, 0x2, 0x0, a1, fa2, v13
-+	.insn r 0x57, 0x4, 0x0, fa1, fa2, v13
-+	.insn r 0x57, 0x4, 0x0, a1, v12, v13
-+	.insn r 0x57, 0x5, 0x0, fa1, v12, v13
-+	.insn r 0x57, 0x5, 0x0, v11, a2, v13
-+	.insn r 0x57, 0x6, 0x1c, v11, fa2, v13
-+	.insn r 0x57, 0x6, 0x1e, v11, v12, a3
-+	.insn r 0x57, 0x7, 0x0, v11, v12, fa3
-+	.insn r 0x57, 0x7, 0x0, v11, v12, v13
-+	# OPIVI
-+	.insn r 0x57, 0x3, 0x0, v11, x0, a3
-+	.insn r 0x57, 0x3, 0x0, v11, x1, a3
-+	.insn r 0x57, 0x3, 0x0, v11, x15, a3
-+	.insn r 0x57, 0x3, 0x0, v11, x16, a3
-+	.insn r 0x57, 0x3, 0x0, v11, x30, a3
-+	.insn r 0x57, 0x3, 0x0, v11, x31, a3
-diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
-new file mode 100644
-index 0000000000..b95c068a17
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/v-zero-imm.d
-@@ -0,0 +1,17 @@
-+#as: -march=rv32ifv0p10
-+#objdump: -dr
-+
-+.*:[ 	]+file format .*
-+
-+
-+Disassembly of section .text:
-+
-+0+000 <.text>:
-+[ 	]+[0-9a-f]+:[ 	]+768fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1
-+[ 	]+[0-9a-f]+:[ 	]+748fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+66840257[ 	]+vmsne.vv[ 	]+v4,v8,v8
-+[ 	]+[0-9a-f]+:[ 	]+64840257[ 	]+vmsne.vv[ 	]+v4,v8,v8,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+7e8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1
-+[ 	]+[0-9a-f]+:[ 	]+7c8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+62840257[ 	]+vmseq.vv[ 	]+v4,v8,v8
-+[ 	]+[0-9a-f]+:[ 	]+60840257[ 	]+vmseq.vv[ 	]+v4,v8,v8,v0.t
-diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
-new file mode 100644
-index 0000000000..98b7063880
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/v-zero-imm.s
-@@ -0,0 +1,8 @@
-+	vmslt.vi v4, v8, 0
-+	vmslt.vi v4, v8, 0, v0.t
-+	vmsltu.vi v4, v8, 0
-+	vmsltu.vi v4, v8, 0, v0.t
-+	vmsge.vi v4, v8, 0
-+	vmsge.vi v4, v8, 0, v0.t
-+	vmsgeu.vi v4, v8, 0
-+	vmsgeu.vi v4, v8, 0, v0.t
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
-new file mode 100644
-index 0000000000..d192761c06
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
-@@ -0,0 +1,3 @@
-+#as: -march=rv32ifv0p10
-+#source: vector-insns-fail-arith-floatp.s
-+#error_output: vector-insns-fail-arith-floatp.l
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
-new file mode 100644
-index 0000000000..b211327275
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
-@@ -0,0 +1,39 @@
-+.*: Assembler messages:
-+.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
-+.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfneg.v v0,v4,v0.t'
-+.*Error: illegal operands `vfabs.v v0,v4,v0.t'
-+.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
-new file mode 100644
-index 0000000000..28e1d35db7
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
-@@ -0,0 +1,123 @@
-+# Vector Single-Width Floating-Point Add/Subtract Instructions
-+
-+	vfadd.vv v4, v4, v8		# OK
-+	vfadd.vv v8, v4, v8		# OK
-+	vfadd.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vfadd.vf v4, v4, fa1		# OK
-+	vfadd.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+	vfsub.vv v4, v4, v8
-+	vfsub.vv v8, v4, v8
-+	vfsub.vv v0, v4, v8, v0.t
-+	vfsub.vf v4, v4, fa1
-+	vfsub.vf v0, v4, fa1, v0.t
-+
-+	vfrsub.vf v4, v4, fa1		# OK
-+	vfrsub.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+# Vector Single-Width Floating-Point Multiply/Divide Instructions
-+
-+	vfmul.vv v4, v4, v8		# OK
-+	vfmul.vv v8, v4, v8		# OK
-+	vfmul.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vfmul.vf v4, v4, fa1		# OK
-+	vfmul.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+	vfdiv.vv v4, v4, v8
-+	vfdiv.vv v8, v4, v8
-+	vfdiv.vv v0, v4, v8, v0.t
-+	vfdiv.vf v4, v4, fa1
-+	vfdiv.vf v0, v4, fa1, v0.t
-+
-+	vfrdiv.vf v4, v4, fa1		# OK
-+	vfrdiv.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
-+
-+	vfmacc.vv v4, v4, v8		# OK
-+	vfmacc.vv v8, v4, v8		# OK
-+	vfmacc.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vfmacc.vf v4, fa1, v4		# OK
-+	vfmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
-+
-+	vfnmacc.vv v4, v4, v8
-+	vfnmacc.vv v8, v4, v8
-+	vfnmacc.vv v0, v4, v8, v0.t
-+	vfnmacc.vf v4, fa1, v4
-+	vfnmacc.vf v0, fa1, v4, v0.t
-+
-+	vfmsac.vv v4, v4, v8
-+	vfmsac.vv v8, v4, v8
-+	vfmsac.vv v0, v4, v8, v0.t
-+	vfmsac.vf v4, fa1, v4
-+	vfmsac.vf v0, fa1, v4, v0.t
-+
-+	vfnmsac.vv v4, v4, v8
-+	vfnmsac.vv v8, v4, v8
-+	vfnmsac.vv v0, v4, v8, v0.t
-+	vfnmsac.vf v4, fa1, v4
-+	vfnmsac.vf v0, fa1, v4, v0.t
-+
-+	vfmadd.vv v4, v4, v8
-+	vfmadd.vv v8, v4, v8
-+	vfmadd.vv v0, v4, v8, v0.t
-+	vfmadd.vf v4, fa1, v4
-+	vfmadd.vf v0, fa1, v4, v0.t
-+
-+	vfnmadd.vv v4, v4, v8
-+	vfnmadd.vv v8, v4, v8
-+	vfnmadd.vv v0, v4, v8, v0.t
-+	vfnmadd.vf v4, fa1, v4
-+	vfnmadd.vf v0, fa1, v4, v0.t
-+
-+	vfmsub.vv v4, v4, v8
-+	vfmsub.vv v8, v4, v8
-+	vfmsub.vv v0, v4, v8, v0.t
-+	vfmsub.vf v4, fa1, v4
-+	vfmsub.vf v0, fa1, v4, v0.t
-+
-+	vfnmsub.vv v4, v4, v8
-+	vfnmsub.vv v8, v4, v8
-+	vfnmsub.vv v0, v4, v8, v0.t
-+	vfnmsub.vf v4, fa1, v4
-+	vfnmsub.vf v0, fa1, v4, v0.t
-+
-+# Vector Floating-Point MIN/MAX Instructions
-+
-+	vfmin.vv v4, v4, v8		# OK
-+	vfmin.vv v8, v4, v8		# OK
-+	vfmin.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vfmin.vf v4, v4, fa1		# OK
-+	vfmin.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+	vfmax.vv v4, v4, v8
-+	vfmax.vv v8, v4, v8
-+	vfmax.vv v0, v4, v8, v0.t
-+	vfmax.vf v4, v4, fa1
-+	vfmax.vf v0, v4, fa1, v0.t
-+
-+# Vector Floating-Point Sign-Injection Instructions
-+
-+	vfneg.v v4, v4			# OK
-+	vfneg.v v0, v4, v0.t		# vd overlap vm
-+	vfabs.v v4, v4			# OK
-+	vfabs.v v0, v4, v0.t		# vd overlap vm
-+
-+	vfsgnj.vv v4, v4, v8		# OK
-+	vfsgnj.vv v8, v4, v8		# OK
-+	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vfsgnj.vf v4, v4, fa1		# OK
-+	vfsgnj.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+	vfsgnjn.vv v4, v4, v8
-+	vfsgnjn.vv v8, v4, v8
-+	vfsgnjn.vv v0, v4, v8, v0.t
-+	vfsgnjn.vf v4, v4, fa1
-+	vfsgnjn.vf v0, v4, fa1, v0.t
-+
-+	vfsgnjx.vv v4, v4, v8
-+	vfsgnjx.vv v8, v4, v8
-+	vfsgnjx.vv v0, v4, v8, v0.t
-+	vfsgnjx.vf v4, v4, fa1
-+	vfsgnjx.vf v0, v4, fa1, v0.t
-+
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
-new file mode 100644
-index 0000000000..746f8d1964
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
-@@ -0,0 +1,3 @@
-+#as: -march=rv32iv0p10
-+#source: vector-insns-fail-arith-int.s
-+#error_output: vector-insns-fail-arith-int.l
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
-new file mode 100644
-index 0000000000..40f4f7717e
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
-@@ -0,0 +1,62 @@
-+.*: Assembler messages:
-+.*Error: illegal operands `vneg.v v0,v4,v0.t'
-+.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
-+.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
-+.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
-+.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
-+.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
-+.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
-+.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
-+.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
-+.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
-+.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
-+.*Error: illegal operands `vadc.vim v0,v4,15,v0'
-+.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
-+.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
-+.*Error: illegal operands `vnot.v v0,v4,v0.t'
-+.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
-+.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
-+.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
-+.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
-+.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
-+.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
-+.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
-+.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
-new file mode 100644
-index 0000000000..af0d1737ff
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
-@@ -0,0 +1,187 @@
-+# Vector Single-Width Integer Add and Subtract
-+
-+	vneg.v v4, v4			# OK
-+	vneg.v v0, v4, v0.t		# vd overlap vm
-+
-+	vadd.vv v4, v4, v8		# OK
-+	vadd.vv v8, v4, v8		# OK
-+	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vadd.vx v4, v4, a1		# OK
-+	vadd.vx v0, v4, a1, v0.t	# vd overlap vm
-+	vadd.vi v4, v4, 15		# OK
-+	vadd.vi v0, v4, 15, v0.t	# vd overlap vm
-+
-+	vsub.vv v4, v4, v8		# OK
-+	vsub.vv v8, v4, v8		# OK
-+	vsub.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vsub.vx v4, v4, a1		# OK
-+	vsub.vx v0, v4, a1, v0.t	# vd overlap vm
-+
-+	vrsub.vx v4, v4, a1		# OK
-+	vrsub.vx v0, v4, a1, v0.t	# vd overlap vm
-+	vrsub.vi v4, v4, 15		# OK
-+	vrsub.vi v0, v4, 15, v0.t	# vd overlap vm
-+
-+# Vector Integer Extension
-+
-+	vzext.vf2 v4, v4		# OK
-+	vzext.vf2 v0, v4, v0.t		# vd overlap vm
-+	vsext.vf2 v4, v4
-+	vsext.vf2 v0, v4, v0.t
-+	vzext.vf4 v4, v4
-+	vzext.vf4 v0, v4, v0.t
-+	vsext.vf4 v4, v4
-+	vsext.vf4 v0, v4, v0.t
-+	vzext.vf8 v4, v4
-+	vzext.vf8 v0, v4, v0.t
-+	vsext.vf8 v4, v4
-+	vsext.vf8 v0, v4, v0.t
-+
-+# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
-+
-+	vadc.vvm v4, v4, v8, v0		# OK
-+	vadc.vvm v8, v4, v8, v0		# OK
-+	vadc.vvm v0, v4, v8, v0		# vd overlap vm
-+	vadc.vxm v4, v4, a1, v0		# OK
-+	vadc.vxm v0, v4, a1, v0		# vd overlap vm
-+	vadc.vim v4, v4, 15, v0		# OK
-+	vadc.vim v0, v4, 15, v0		# vd overlap vm
-+
-+	vsbc.vvm v4, v4, v8, v0		# OK
-+	vsbc.vvm v8, v4, v8, v0		# OK
-+	vsbc.vvm v0, v4, v8, v0		# vd overlap vm
-+	vsbc.vxm v4, v4, a1, v0		# OK
-+	vsbc.vxm v0, v4, a1, v0		# vd overlap vm
-+
-+# Vector Bitwise Logical Instructions
-+
-+	vnot.v v4, v4			# OK
-+	vnot.v v0, v4, v0.t		# vd overlap vm
-+
-+	vand.vv	v4, v4, v8		# OK
-+	vand.vv v8, v4, v8		# OK
-+	vand.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vand.vx v4, v4, a1		# OK
-+	vand.vx v0, v4, a1, v0.t	# vd overlap vm
-+	vand.vi v4, v4, 15		# OK
-+	vand.vi v0, v4, 15, v0.t	# vd overlap vm
-+
-+	vor.vv	v4, v4, v8
-+	vor.vv v8, v4, v8
-+	vor.vv v0, v4, v8, v0.t
-+	vor.vx v4, v4, a1
-+	vor.vx v0, v4, a1, v0.t
-+	vor.vi v4, v4, 15
-+	vor.vi v0, v4, 15, v0.t
-+
-+	vxor.vv	v4, v4, v8
-+	vxor.vv v8, v4, v8
-+	vxor.vv v0, v4, v8, v0.t
-+	vxor.vx v4, v4, a1
-+	vxor.vx v0, v4, a1, v0.t
-+	vxor.vi v4, v4, 15
-+	vxor.vi v0, v4, 15, v0.t
-+
-+# Vector Integer Min/Max Instructions
-+
-+	vminu.vv v4, v4, v8		# OK
-+	vminu.vv v8, v4, v8		# OK
-+	vminu.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vminu.vx v4, v4, a1		# OK
-+	vminu.vx v0, v4, a1, v0.t	# vd overlap vm
-+
-+	vmin.vv v4, v4, v8
-+	vmin.vv v8, v4, v8
-+	vmin.vv v0, v4, v8, v0.t
-+	vmin.vx v4, v4, a1
-+	vmin.vx v0, v4, a1, v0.t
-+
-+	vmaxu.vv v4, v4, v8
-+	vmaxu.vv v8, v4, v8
-+	vmaxu.vv v0, v4, v8, v0.t
-+	vmaxu.vx v4, v4, a1
-+	vmaxu.vx v0, v4, a1, v0.t
-+
-+	vmax.vv v4, v4, v8
-+	vmax.vv v8, v4, v8
-+	vmax.vv v0, v4, v8, v0.t
-+	vmax.vx v4, v4, a1
-+	vmax.vx v0, v4, a1, v0.t
-+
-+# Vector Single-Width Integer Multiply Instructions
-+
-+	vmul.vv v4, v4, v8		# OK
-+	vmul.vv v8, v4, v8		# OK
-+	vmul.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vmul.vx v4, v4, a1		# OK
-+	vmul.vx v0, v4, a1, v0.t	# vd overlap vm
-+
-+	vmulh.vv v4, v4, v8
-+	vmulh.vv v8, v4, v8
-+	vmulh.vv v0, v4, v8, v0.t
-+	vmulh.vx v4, v4, a1
-+	vmulh.vx v0, v4, a1, v0.t
-+
-+	vmulhu.vv v4, v4, v8
-+	vmulhu.vv v8, v4, v8
-+	vmulhu.vv v0, v4, v8, v0.t
-+	vmulhu.vx v4, v4, a1
-+	vmulhu.vx v0, v4, a1, v0.t
-+
-+	vmulhsu.vv v4, v4, v8
-+	vmulhsu.vv v8, v4, v8
-+	vmulhsu.vv v0, v4, v8, v0.t
-+	vmulhsu.vx v4, v4, a1
-+	vmulhsu.vx v0, v4, a1, v0.t
-+
-+# Vector Integer Divide Instructions
-+
-+	vdivu.vv v4, v4, v8		# OK
-+	vdivu.vv v8, v4, v8		# OK
-+	vdivu.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vdivu.vx v4, v4, a1		# OK
-+	vdivu.vx v0, v4, a1, v0.t	# vd overlap vm
-+
-+	vdiv.vv v4, v4, v8
-+	vdiv.vv v8, v4, v8
-+	vdiv.vv v0, v4, v8, v0.t
-+	vdiv.vx v4, v4, a1
-+	vdiv.vx v0, v4, a1, v0.t
-+
-+	vremu.vv v4, v4, v8
-+	vremu.vv v8, v4, v8
-+	vremu.vv v0, v4, v8, v0.t
-+	vremu.vx v4, v4, a1
-+	vremu.vx v0, v4, a1, v0.t
-+
-+	vrem.vv v4, v4, v8
-+	vrem.vv v8, v4, v8
-+	vrem.vv v0, v4, v8, v0.t
-+	vrem.vx v4, v4, a1
-+	vrem.vx v0, v4, a1, v0.t
-+
-+# Vector Single-Width Integer Multiply-Add Instructions
-+
-+	vmacc.vv v4, v4, v8		# OK
-+	vmacc.vv v8, v4, v8		# OK
-+	vmacc.vv v0, v4, v8, v0.t	# vd overlap vm
-+	vmacc.vx v4, a1, v4		# OK
-+	vmacc.vx v0, a1, v4, v0.t	# vd overlap vm
-+
-+	vnmsac.vv v4, v4, v8
-+	vnmsac.vv v8, v4, v8
-+	vnmsac.vv v0, v4, v8, v0.t
-+	vnmsac.vx v4, a1, v4
-+	vnmsac.vx v0, a1, v4, v0.t
-+
-+	vmadd.vv v4, v4, v8
-+	vmadd.vv v8, v4, v8
-+	vmadd.vv v0, v4, v8, v0.t
-+	vmadd.vx v4, a1, v4
-+	vmadd.vx v0, a1, v4, v0.t
-+
-+	vnmsub.vv v4, v4, v8
-+	vnmsub.vv v8, v4, v8
-+	vnmsub.vv v0, v4, v8, v0.t
-+	vnmsub.vx v4, a1, v4
-+	vnmsub.vx v0, a1, v4, v0.t
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
-new file mode 100644
-index 0000000000..7d3d6bfe78
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
-@@ -0,0 +1,3 @@
-+#as: -march=rv32iv0p10
-+#source: vector-insns-fail-load-store.s
-+#error_output: vector-insns-fail-load-store.l
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
-new file mode 100644
-index 0000000000..47259a3a7e
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
-@@ -0,0 +1,25 @@
-+.*: Assembler messages:
-+.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
-+.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
-+.*Error: illegal operands `vloxei8.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vloxei16.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vloxei32.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vloxei64.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vsoxei8.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vsoxei16.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vsoxei32.v v0,\(a0\),v4,v0.t'
-+.*Error: illegal operands `vsoxei64.v v0,\(a0\),v4,v0.t'
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
-new file mode 100644
-index 0000000000..ce3b9ec013
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
-@@ -0,0 +1,43 @@
-+# Vector Unit-Stride Loads and Stores
-+
-+	vle8.v v0, (a0), v0.t		# vd overlap vm
-+	vle16.v v0, (a0), v0.t
-+	vle32.v v0, (a0), v0.t
-+	vle64.v v0, (a0), v0.t
-+
-+	vse8.v v0, (a0), v0.t		# vd overlap vm
-+	vse16.v v0, (a0), v0.t
-+	vse32.v v0, (a0), v0.t
-+	vse64.v v0, (a0), v0.t
-+
-+# Vector Strided Loads and Stores
-+
-+	vlse8.v v0, (a0), a1, v0.t	# vd overlap vm
-+	vlse16.v v0, (a0), a1, v0.t
-+	vlse32.v v0, (a0), a1, v0.t
-+	vlse64.v v0, (a0), a1, v0.t
-+
-+	vsse8.v v0, (a0), a1, v0.t
-+	vsse16.v v0, (a0), a1, v0.t
-+	vsse32.v v0, (a0), a1, v0.t
-+	vsse64.v v0, (a0), a1, v0.t
-+
-+# Vector Ordered Indexed Loads and Stores
-+
-+	vloxei8.v v4, (a0), v4		# OK
-+	vloxei8.v v0, (a0), v4, v0.t	# vd overlap vm
-+	vloxei16.v v4, (a0), v4
-+	vloxei16.v v0, (a0), v4, v0.t
-+	vloxei32.v v4, (a0), v4
-+	vloxei32.v v0, (a0), v4, v0.t
-+	vloxei64.v v4, (a0), v4
-+	vloxei64.v v0, (a0), v4, v0.t
-+
-+	vsoxei8.v v4, (a0), v4
-+	vsoxei8.v v0, (a0), v4, v0.t
-+	vsoxei16.v v4, (a0), v4
-+	vsoxei16.v v0, (a0), v4, v0.t
-+	vsoxei32.v v4, (a0), v4
-+	vsoxei32.v v0, (a0), v4, v0.t
-+	vsoxei64.v v4, (a0), v4
-+	vsoxei64.v v0, (a0), v4, v0.t
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
-new file mode 100644
-index 0000000000..ebdd2b1051
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
-@@ -0,0 +1,3 @@
-+#as: -march=rv32ifv0p10
-+#source: vector-insns-fail-permutation.s
-+#error_output: vector-insns-fail-permutation.l
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
-new file mode 100644
-index 0000000000..682f1cd9a4
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
-@@ -0,0 +1,19 @@
-+.*: Assembler messages:
-+.*Error: illegal operands `vslideup.vx v4,v4,a1'
-+.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vslideup.vi v4,v4,31'
-+.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
-+.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
-+.*Error: illegal operands `vslide1up.vx v4,v4,a1'
-+.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
-+.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
-+.*Error: illegal operands `vrgather.vx v4,v4,a1'
-+.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
-+.*Error: illegal operands `vrgather.vi v4,v4,31'
-+.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
-+.*Error: illegal operands `vcompress.vm v4,v4,v8'
-+.*Error: illegal operands `vcompress.vm v8,v4,v8'
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
-new file mode 100644
-index 0000000000..834bee925b
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
-@@ -0,0 +1,37 @@
-+# Vector Slideup Instructions
-+
-+	vslideup.vx v4, v4, a1			# vd overlap vs2
-+	vslideup.vx v0, v4, a1, v0.t		# vd overlap vm
-+	vslideup.vi v4, v4, 31			# vd overlap vs2
-+	vslideup.vi v0, v4, 31, v0.t		# vd overlap vm
-+
-+	vslidedown.vx v4, v4, a1		# OK
-+	vslidedown.vx v0, v4, a1, v0.t		# vd overlap vm
-+	vslidedown.vi v4, v4, 31		# OK
-+	vslidedown.vi v0, v4, 31, v0.t		# vd overlap vm
-+
-+	vslide1up.vx v4, v4, a1			# vd overlap vs2
-+	vslide1up.vx v0, v4, a1, v0.t		# vd overlap vm
-+	vfslide1up.vf v4, v4, fa1		# vd overlap vs2
-+	vfslide1up.vf v0, v4, fa1, v0.t		# vd overlap vm
-+
-+	vslide1down.vx v4, v4, a1		# OK
-+	vslide1down.vx v0, v4, a1, v0.t		# vd overlap vm
-+	vfslide1down.vf v4, v4, fa1		# OK
-+	vfslide1down.vf v0, v4, fa1, v0.t	# vd overlap vm
-+
-+# Vector Register Gather Instructions
-+
-+	vrgather.vv v4, v4, v8			# vd overlap vs2
-+	vrgather.vv v8, v4, v8			# vd overlap vs1
-+	vrgather.vv v0, v4, v8, v0.t		# vd overlap vm
-+	vrgather.vx v4, v4, a1			# vd overlap vs2
-+	vrgather.vx v0, v4, a1, v0.t		# vd overlap vm
-+	vrgather.vi v4, v4, 31			# vd overlap vs2
-+	vrgather.vi v0, v4, 31, v0.t		# vd overlap vm
-+
-+# Vector Compress Instruction
-+
-+	vcompress.vm v4, v4, v8			# vd overlap vs2
-+	vcompress.vm v8, v4, v8			# vd overlap vs1
-+
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
-new file mode 100644
-index 0000000000..cca6928e7d
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
-@@ -0,0 +1,3 @@
-+#as: -march=rv32iv0p10 
-+#source: vector-insns-fail-unsupport.s
-+#error_output: vector-insns-fail-unsupport.l
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
-new file mode 100644
-index 0000000000..ae2230cb9e
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
-@@ -0,0 +1,1469 @@
-+.*: Assembler messages:
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,0'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,0x3ff'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e16,m2'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m8'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,m8'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m8'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m1'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,mf2'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,mf4'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,mf8'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ma'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,mu'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,ma'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,ma'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,mu'
-+.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,mu'
-+.*: Error: unrecognized opcode `vle1.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vle1.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vse1.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vse1.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vle8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vle16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vle32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vle64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e8.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e16.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e32.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1'
-+.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t'
-+.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12'
-+.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t'
-+.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e8ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e16ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e32ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
-+.*: Error: unrecognized opcode `vl1r.v v3,\(a0\)'
-+.*: Error: unrecognized opcode `vl1r.v v3,0\(a0\)'
-+.*: Error: unrecognized opcode `vl1re8.v v3,\(a0\)'
-+.*: Error: unrecognized opcode `vl1re8.v v3,0\(a0\)'
-+.*: Error: unrecognized opcode `vl1re16.v v3,\(a0\)'
-+.*: Error: unrecognized opcode `vl1re16.v v3,0\(a0\)'
-+.*: Error: unrecognized opcode `vl1re32.v v3,\(a0\)'
-+.*: Error: unrecognized opcode `vl1re32.v v3,0\(a0\)'
-+.*: Error: unrecognized opcode `vl1re64.v v3,\(a0\)'
-+.*: Error: unrecognized opcode `vl1re64.v v3,0\(a0\)'
-+.*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
-+.*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
-+.*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
-+.*: Error: unrecognized opcode `vl2re8.v v2,0\(a0\)'
-+.*: Error: unrecognized opcode `vl2re16.v v2,\(a0\)'
-+.*: Error: unrecognized opcode `vl2re16.v v2,0\(a0\)'
-+.*: Error: unrecognized opcode `vl2re32.v v2,\(a0\)'
-+.*: Error: unrecognized opcode `vl2re32.v v2,0\(a0\)'
-+.*: Error: unrecognized opcode `vl2re64.v v2,\(a0\)'
-+.*: Error: unrecognized opcode `vl2re64.v v2,0\(a0\)'
-+.*: Error: unrecognized opcode `vl4r.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vl4r.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vl4re8.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vl4re8.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vl4re16.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vl4re16.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vl4re32.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vl4re32.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vl4re64.v v4,\(a0\)'
-+.*: Error: unrecognized opcode `vl4re64.v v4,0\(a0\)'
-+.*: Error: unrecognized opcode `vl8r.v v8,\(a0\)'
-+.*: Error: unrecognized opcode `vl8r.v v8,0\(a0\)'
-+.*: Error: unrecognized opcode `vl8re8.v v8,\(a0\)'
-+.*: Error: unrecognized opcode `vl8re8.v v8,0\(a0\)'
-+.*: Error: unrecognized opcode `vl8re16.v v8,\(a0\)'
-+.*: Error: unrecognized opcode `vl8re16.v v8,0\(a0\)'
-+.*: Error: unrecognized opcode `vl8re32.v v8,\(a0\)'
-+.*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
-+.*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
-+.*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
-+.*: Error: unrecognized opcode `vs1r.v v3,\(a1\)'
-+.*: Error: unrecognized opcode `vs1r.v v3,0\(a1\)'
-+.*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
-+.*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
-+.*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
-+.*: Error: unrecognized opcode `vs4r.v v4,0\(a1\)'
-+.*: Error: unrecognized opcode `vs8r.v v8,\(a1\)'
-+.*: Error: unrecognized opcode `vs8r.v v8,0\(a1\)'
-+.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4'
-+.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4,v0.t'
-+.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8'
-+.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8'
-+.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsll.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vsll.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vsll.vi v4,v8,1'
-+.*: Error: unrecognized opcode `vsll.vi v4,v8,31'
-+.*: Error: unrecognized opcode `vsll.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vsll.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsll.vi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vsll.vi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vsrl.vi v4,v8,1'
-+.*: Error: unrecognized opcode `vsrl.vi v4,v8,31'
-+.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsrl.vi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vsrl.vi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vsra.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vsra.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vsra.vi v4,v8,1'
-+.*: Error: unrecognized opcode `vsra.vi v4,v8,31'
-+.*: Error: unrecognized opcode `vsra.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vsra.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsra.vi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vsra.vi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8'
-+.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1'
-+.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31'
-+.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vnsra.wi v4,v8,1'
-+.*: Error: unrecognized opcode `vnsra.wi v4,v8,31'
-+.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vnsra.wi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vnsra.wi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8'
-+.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8,v0.t'
-+.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8'
-+.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8,v0.t'
-+.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8'
-+.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8,v0.t'
-+.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8'
-+.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8,v0.t'
-+.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15'
-+.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16'
-+.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15,v0.t'
-+.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16,v0.t'
-+.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vsadd.vi v4,v8,15'
-+.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16'
-+.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsadd.vi v4,v8,15,v0.t'
-+.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16,v0.t'
-+.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vssub.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vssub.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vssub.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vssub.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vasub.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vasub.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vasub.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vasub.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vssrl.vi v4,v8,1'
-+.*: Error: unrecognized opcode `vssrl.vi v4,v8,31'
-+.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vssrl.vi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vssrl.vi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vssra.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vssra.vx v4,v8,a1'
-+.*: Error: unrecognized opcode `vssra.vi v4,v8,1'
-+.*: Error: unrecognized opcode `vssra.vi v4,v8,31'
-+.*: Error: unrecognized opcode `vssra.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vssra.vx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vssra.vi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vssra.vi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1'
-+.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31'
-+.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1'
-+.*: Error: unrecognized opcode `vnclip.wi v4,v8,1'
-+.*: Error: unrecognized opcode `vnclip.wi v4,v8,31'
-+.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1,v0.t'
-+.*: Error: unrecognized opcode `vnclip.wi v4,v8,1,v0.t'
-+.*: Error: unrecognized opcode `vnclip.wi v4,v8,31,v0.t'
-+.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2'
-+.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2,v0.t'
-+.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2'
-+.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2,v0.t'
-+.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2'
-+.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2,v0.t'
-+.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2'
-+.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2,v0.t'
-+.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2'
-+.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2,v0.t'
-+.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8'
-+.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8'
-+.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8'
-+.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8'
-+.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8'
-+.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8,v0.t'
-+.*: Error: unrecognized opcode `vfsqrt.v v4,v8'
-+.*: Error: unrecognized opcode `vfsqrt.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8'
-+.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8'
-+.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfrece7.v v4,v8'
-+.*: Error: unrecognized opcode `vfrece7.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfrec7.v v4,v8'
-+.*: Error: unrecognized opcode `vfrec7.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfclass.v v4,v8'
-+.*: Error: unrecognized opcode `vfclass.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8'
-+.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8'
-+.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8'
-+.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8'
-+.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8'
-+.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8'
-+.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8'
-+.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8'
-+.*: Error: unrecognized opcode `vredand.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vredor.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8,v0.t'
-+.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8,v0.t'
-+.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8,v0.t'
-+.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8,v0.t'
-+.*: Error: unrecognized opcode `vredand.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vredor.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12'
-+.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vmsbf.m v4,v8'
-+.*: Error: unrecognized opcode `vmsif.m v4,v8'
-+.*: Error: unrecognized opcode `vmsof.m v4,v8'
-+.*: Error: unrecognized opcode `viota.m v4,v8'
-+.*: Error: unrecognized opcode `vid.v v4'
-+.*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
-+.*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
-+.*: Error: unrecognized opcode `vid.v v4,v0.t'
-+.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
-+.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
-+.*: Error: unrecognized opcode `vmv1r.v v1,v2'
-+.*: Error: unrecognized opcode `vmv2r.v v2,v4'
-+.*: Error: unrecognized opcode `vmv4r.v v4,v8'
-+.*: Error: unrecognized opcode `vmv8r.v v0,v8'
-diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
-new file mode 100644
-index 0000000000..0116ac2c06
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
-@@ -0,0 +1,1679 @@
-+	
-+	vsetivli a0, 0xb, 0
-+	vsetivli a0, 0xb, 0x3ff
-+	vsetivli a0, 0xb, e16, m2
-+	vsetivli a0, 0xb, e256, m8
-+	vsetivli a0, 0xb, e512, m8
-+	vsetivli a0, 0xb, e1024, m8
-+	vsetivli a0, 0xb, e1024, m1
-+	vsetivli a0, 0xb, e1024, mf2
-+	vsetivli a0, 0xb, e512, mf4
-+	vsetivli a0, 0xb, e256, mf8
-+	vsetivli a0, 0xb, e256, m2, ta
-+	vsetivli a0, 0xb, e256, m2, ma
-+	vsetivli a0, 0xb, e256, m2, tu
-+	vsetivli a0, 0xb, e256, m2, mu
-+	vsetivli a0, 0xb, e256, m2, ta, ma
-+	vsetivli a0, 0xb, e256, m2, tu, ma
-+	vsetivli a0, 0xb, e256, m2, ta, mu
-+	vsetivli a0, 0xb, e256, m2, tu, mu
-+
-+	vle1.v v4, (a0)
-+	vle1.v v4, 0(a0)
-+	vse1.v v4, (a0)
-+	vse1.v v4, 0(a0)
-+
-+	
-+	vluxei8.v v4, (a0), v12
-+	vluxei8.v v4, 0(a0), v12
-+	vluxei8.v v4, (a0), v12, v0.t
-+	vsuxei8.v v4, (a0), v12
-+	vsuxei8.v v4, 0(a0), v12
-+	vsuxei8.v v4, (a0), v12, v0.t
-+
-+	
-+	vluxei16.v v4, (a0), v12
-+	vluxei16.v v4, 0(a0), v12
-+	vluxei16.v v4, (a0), v12, v0.t
-+	vsuxei16.v v4, (a0), v12
-+	vsuxei16.v v4, 0(a0), v12
-+	vsuxei16.v v4, (a0), v12, v0.t
-+
-+	
-+	vluxei32.v v4, (a0), v12
-+	vluxei32.v v4, 0(a0), v12
-+	vluxei32.v v4, (a0), v12, v0.t
-+	vsuxei32.v v4, (a0), v12
-+	vsuxei32.v v4, 0(a0), v12
-+	vsuxei32.v v4, (a0), v12, v0.t
-+
-+	
-+	vluxei64.v v4, (a0), v12
-+	vluxei64.v v4, 0(a0), v12
-+	vluxei64.v v4, (a0), v12, v0.t
-+	vsuxei64.v v4, (a0), v12
-+	vsuxei64.v v4, 0(a0), v12
-+	vsuxei64.v v4, (a0), v12, v0.t
-+
-+	vle8ff.v v4, (a0)
-+	vle8ff.v v4, 0(a0)
-+	vle8ff.v v4, (a0), v0.t
-+
-+	vle16ff.v v4, (a0)
-+	vle16ff.v v4, 0(a0)
-+	vle16ff.v v4, (a0), v0.t
-+
-+	vle32ff.v v4, (a0)
-+	vle32ff.v v4, 0(a0)
-+	vle32ff.v v4, (a0), v0.t
-+
-+	vle64ff.v v4, (a0)
-+	vle64ff.v v4, 0(a0)
-+	vle64ff.v v4, (a0), v0.t
-+
-+	vlseg2e8.v v4, (a0)
-+	vlseg2e8.v v4, 0(a0)
-+	vlseg2e8.v v4, (a0), v0.t
-+	vsseg2e8.v v4, (a0)
-+	vsseg2e8.v v4, 0(a0)
-+	vsseg2e8.v v4, (a0), v0.t
-+
-+	vlseg3e8.v v4, (a0)
-+	vlseg3e8.v v4, 0(a0)
-+	vlseg3e8.v v4, (a0), v0.t
-+	vsseg3e8.v v4, (a0)
-+	vsseg3e8.v v4, 0(a0)
-+	vsseg3e8.v v4, (a0), v0.t
-+
-+	vlseg4e8.v v4, (a0)
-+	vlseg4e8.v v4, 0(a0)
-+	vlseg4e8.v v4, (a0), v0.t
-+	vsseg4e8.v v4, (a0)
-+	vsseg4e8.v v4, 0(a0)
-+	vsseg4e8.v v4, (a0), v0.t
-+
-+	vlseg5e8.v v4, (a0)
-+	vlseg5e8.v v4, 0(a0)
-+	vlseg5e8.v v4, (a0), v0.t
-+	vsseg5e8.v v4, (a0)
-+	vsseg5e8.v v4, 0(a0)
-+	vsseg5e8.v v4, (a0), v0.t
-+
-+	vlseg6e8.v v4, (a0)
-+	vlseg6e8.v v4, 0(a0)
-+	vlseg6e8.v v4, (a0), v0.t
-+	vsseg6e8.v v4, (a0)
-+	vsseg6e8.v v4, 0(a0)
-+	vsseg6e8.v v4, (a0), v0.t
-+
-+	vlseg7e8.v v4, (a0)
-+	vlseg7e8.v v4, 0(a0)
-+	vlseg7e8.v v4, (a0), v0.t
-+	vsseg7e8.v v4, (a0)
-+	vsseg7e8.v v4, 0(a0)
-+	vsseg7e8.v v4, (a0), v0.t
-+
-+	vlseg8e8.v v4, (a0)
-+	vlseg8e8.v v4, 0(a0)
-+	vlseg8e8.v v4, (a0), v0.t
-+	vsseg8e8.v v4, (a0)
-+	vsseg8e8.v v4, 0(a0)
-+	vsseg8e8.v v4, (a0), v0.t
-+
-+	vlseg2e16.v v4, (a0)
-+	vlseg2e16.v v4, 0(a0)
-+	vlseg2e16.v v4, (a0), v0.t
-+	vsseg2e16.v v4, (a0)
-+	vsseg2e16.v v4, 0(a0)
-+	vsseg2e16.v v4, (a0), v0.t
-+
-+	vlseg3e16.v v4, (a0)
-+	vlseg3e16.v v4, 0(a0)
-+	vlseg3e16.v v4, (a0), v0.t
-+	vsseg3e16.v v4, (a0)
-+	vsseg3e16.v v4, 0(a0)
-+	vsseg3e16.v v4, (a0), v0.t
-+
-+	vlseg4e16.v v4, (a0)
-+	vlseg4e16.v v4, 0(a0)
-+	vlseg4e16.v v4, (a0), v0.t
-+	vsseg4e16.v v4, (a0)
-+	vsseg4e16.v v4, 0(a0)
-+	vsseg4e16.v v4, (a0), v0.t
-+
-+	vlseg5e16.v v4, (a0)
-+	vlseg5e16.v v4, 0(a0)
-+	vlseg5e16.v v4, (a0), v0.t
-+	vsseg5e16.v v4, (a0)
-+	vsseg5e16.v v4, 0(a0)
-+	vsseg5e16.v v4, (a0), v0.t
-+
-+	vlseg6e16.v v4, (a0)
-+	vlseg6e16.v v4, 0(a0)
-+	vlseg6e16.v v4, (a0), v0.t
-+	vsseg6e16.v v4, (a0)
-+	vsseg6e16.v v4, 0(a0)
-+	vsseg6e16.v v4, (a0), v0.t
-+
-+	vlseg7e16.v v4, (a0)
-+	vlseg7e16.v v4, 0(a0)
-+	vlseg7e16.v v4, (a0), v0.t
-+	vsseg7e16.v v4, (a0)
-+	vsseg7e16.v v4, 0(a0)
-+	vsseg7e16.v v4, (a0), v0.t
-+
-+	vlseg8e16.v v4, (a0)
-+	vlseg8e16.v v4, 0(a0)
-+	vlseg8e16.v v4, (a0), v0.t
-+	vsseg8e16.v v4, (a0)
-+	vsseg8e16.v v4, 0(a0)
-+	vsseg8e16.v v4, (a0), v0.t
-+
-+	vlseg2e32.v v4, (a0)
-+	vlseg2e32.v v4, 0(a0)
-+	vlseg2e32.v v4, (a0), v0.t
-+	vsseg2e32.v v4, (a0)
-+	vsseg2e32.v v4, 0(a0)
-+	vsseg2e32.v v4, (a0), v0.t
-+
-+	vlseg3e32.v v4, (a0)
-+	vlseg3e32.v v4, 0(a0)
-+	vlseg3e32.v v4, (a0), v0.t
-+	vsseg3e32.v v4, (a0)
-+	vsseg3e32.v v4, 0(a0)
-+	vsseg3e32.v v4, (a0), v0.t
-+
-+	vlseg4e32.v v4, (a0)
-+	vlseg4e32.v v4, 0(a0)
-+	vlseg4e32.v v4, (a0), v0.t
-+	vsseg4e32.v v4, (a0)
-+	vsseg4e32.v v4, 0(a0)
-+	vsseg4e32.v v4, (a0), v0.t
-+
-+	vlseg5e32.v v4, (a0)
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-+	vl4re8.v v4, 0(a0)
-+	vl4re16.v v4, (a0)
-+	vl4re16.v v4, 0(a0)
-+	vl4re32.v v4, (a0)
-+	vl4re32.v v4, 0(a0)
-+	vl4re64.v v4, (a0)
-+	vl4re64.v v4, 0(a0)
-+
-+	vl8r.v v8, (a0)
-+	vl8r.v v8, 0(a0)
-+	vl8re8.v v8, (a0)
-+	vl8re8.v v8, 0(a0)
-+	vl8re16.v v8, (a0)
-+	vl8re16.v v8, 0(a0)
-+	vl8re32.v v8, (a0)
-+	vl8re32.v v8, 0(a0)
-+	vl8re64.v v8, (a0)
-+	vl8re64.v v8, 0(a0)
-+
-+	vs1r.v v3, (a1)
-+	vs1r.v v3, 0(a1)
-+	vs2r.v v2, (a1)
-+	vs2r.v v2, 0(a1)
-+	vs4r.v v4, (a1)
-+	vs4r.v v4, 0(a1)
-+	vs8r.v v8, (a1)
-+	vs8r.v v8, 0(a1)
-+
-+	vamoaddei8.v v4, (a1), v8, v4
-+	vamoaddei8.v x0, (a1), v8, v4
-+	vamoaddei8.v v4, (a1), v8, v4, v0.t
-+	vamoaddei8.v x0, (a1), v8, v4, v0.t
-+	vamoswapei8.v v4, (a1), v8, v4
-+	vamoswapei8.v x0, (a1), v8, v4
-+	vamoswapei8.v v4, (a1), v8, v4, v0.t
-+	vamoswapei8.v x0, (a1), v8, v4, v0.t
-+
-+	vamoxorei8.v v4, (a1), v8, v4
-+	vamoxorei8.v x0, (a1), v8, v4
-+	vamoxorei8.v v4, (a1), v8, v4, v0.t
-+	vamoxorei8.v x0, (a1), v8, v4, v0.t
-+	vamoandei8.v v4, (a1), v8, v4
-+	vamoandei8.v x0, (a1), v8, v4
-+	vamoandei8.v v4, (a1), v8, v4, v0.t
-+	vamoandei8.v x0, (a1), v8, v4, v0.t
-+	vamoorei8.v v4, (a1), v8, v4
-+	vamoorei8.v x0, (a1), v8, v4
-+	vamoorei8.v v4, (a1), v8, v4, v0.t
-+	vamoorei8.v x0, (a1), v8, v4, v0.t
-+
-+	vamominei8.v v4, (a1), v8, v4
-+	vamominei8.v x0, (a1), v8, v4
-+	vamominei8.v v4, (a1), v8, v4, v0.t
-+	vamominei8.v x0, (a1), v8, v4, v0.t
-+	vamomaxei8.v v4, (a1), v8, v4
-+	vamomaxei8.v x0, (a1), v8, v4
-+	vamomaxei8.v v4, (a1), v8, v4, v0.t
-+	vamomaxei8.v x0, (a1), v8, v4, v0.t
-+	vamominuei8.v v4, (a1), v8, v4
-+	vamominuei8.v x0, (a1), v8, v4
-+	vamominuei8.v v4, (a1), v8, v4, v0.t
-+	vamominuei8.v x0, (a1), v8, v4, v0.t
-+	vamomaxuei8.v v4, (a1), v8, v4
-+	vamomaxuei8.v x0, (a1), v8, v4
-+	vamomaxuei8.v v4, (a1), v8, v4, v0.t
-+	vamomaxuei8.v x0, (a1), v8, v4, v0.t
-+
-+	vamoaddei8.v v4, 0(a1), v8, v4
-+	vamoaddei8.v x0, 0(a1), v8, v4
-+	vamoaddei8.v v4, 0(a1), v8, v4, v0.t
-+	vamoaddei8.v x0, 0(a1), v8, v4, v0.t
-+	vamoswapei8.v v4, 0(a1), v8, v4
-+	vamoswapei8.v x0, 0(a1), v8, v4
-+	vamoswapei8.v v4, 0(a1), v8, v4, v0.t
-+	vamoswapei8.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoxorei8.v v4, 0(a1), v8, v4
-+	vamoxorei8.v x0, 0(a1), v8, v4
-+	vamoxorei8.v v4, 0(a1), v8, v4, v0.t
-+	vamoxorei8.v x0, 0(a1), v8, v4, v0.t
-+	vamoandei8.v v4, 0(a1), v8, v4
-+	vamoandei8.v x0, 0(a1), v8, v4
-+	vamoandei8.v v4, 0(a1), v8, v4, v0.t
-+	vamoandei8.v x0, 0(a1), v8, v4, v0.t
-+	vamoorei8.v v4, 0(a1), v8, v4
-+	vamoorei8.v x0, 0(a1), v8, v4
-+	vamoorei8.v v4, 0(a1), v8, v4, v0.t
-+	vamoorei8.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamominei8.v v4, 0(a1), v8, v4
-+	vamominei8.v x0, 0(a1), v8, v4
-+	vamominei8.v v4, 0(a1), v8, v4, v0.t
-+	vamominei8.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxei8.v v4, 0(a1), v8, v4
-+	vamomaxei8.v x0, 0(a1), v8, v4
-+	vamomaxei8.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxei8.v x0, 0(a1), v8, v4, v0.t
-+	vamominuei8.v v4, 0(a1), v8, v4
-+	vamominuei8.v x0, 0(a1), v8, v4
-+	vamominuei8.v v4, 0(a1), v8, v4, v0.t
-+	vamominuei8.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxuei8.v v4, 0(a1), v8, v4
-+	vamomaxuei8.v x0, 0(a1), v8, v4
-+	vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoaddei16.v v4, (a1), v8, v4
-+	vamoaddei16.v x0, (a1), v8, v4
-+	vamoaddei16.v v4, (a1), v8, v4, v0.t
-+	vamoaddei16.v x0, (a1), v8, v4, v0.t
-+	vamoswapei16.v v4, (a1), v8, v4
-+	vamoswapei16.v x0, (a1), v8, v4
-+	vamoswapei16.v v4, (a1), v8, v4, v0.t
-+	vamoswapei16.v x0, (a1), v8, v4, v0.t
-+
-+	vamoxorei16.v v4, (a1), v8, v4
-+	vamoxorei16.v x0, (a1), v8, v4
-+	vamoxorei16.v v4, (a1), v8, v4, v0.t
-+	vamoxorei16.v x0, (a1), v8, v4, v0.t
-+	vamoandei16.v v4, (a1), v8, v4
-+	vamoandei16.v x0, (a1), v8, v4
-+	vamoandei16.v v4, (a1), v8, v4, v0.t
-+	vamoandei16.v x0, (a1), v8, v4, v0.t
-+	vamoorei16.v v4, (a1), v8, v4
-+	vamoorei16.v x0, (a1), v8, v4
-+	vamoorei16.v v4, (a1), v8, v4, v0.t
-+	vamoorei16.v x0, (a1), v8, v4, v0.t
-+
-+	vamominei16.v v4, (a1), v8, v4
-+	vamominei16.v x0, (a1), v8, v4
-+	vamominei16.v v4, (a1), v8, v4, v0.t
-+	vamominei16.v x0, (a1), v8, v4, v0.t
-+	vamomaxei16.v v4, (a1), v8, v4
-+	vamomaxei16.v x0, (a1), v8, v4
-+	vamomaxei16.v v4, (a1), v8, v4, v0.t
-+	vamomaxei16.v x0, (a1), v8, v4, v0.t
-+	vamominuei16.v v4, (a1), v8, v4
-+	vamominuei16.v x0, (a1), v8, v4
-+	vamominuei16.v v4, (a1), v8, v4, v0.t
-+	vamominuei16.v x0, (a1), v8, v4, v0.t
-+	vamomaxuei16.v v4, (a1), v8, v4
-+	vamomaxuei16.v x0, (a1), v8, v4
-+	vamomaxuei16.v v4, (a1), v8, v4, v0.t
-+	vamomaxuei16.v x0, (a1), v8, v4, v0.t
-+
-+	vamoaddei16.v v4, 0(a1), v8, v4
-+	vamoaddei16.v x0, 0(a1), v8, v4
-+	vamoaddei16.v v4, 0(a1), v8, v4, v0.t
-+	vamoaddei16.v x0, 0(a1), v8, v4, v0.t
-+	vamoswapei16.v v4, 0(a1), v8, v4
-+	vamoswapei16.v x0, 0(a1), v8, v4
-+	vamoswapei16.v v4, 0(a1), v8, v4, v0.t
-+	vamoswapei16.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoxorei16.v v4, 0(a1), v8, v4
-+	vamoxorei16.v x0, 0(a1), v8, v4
-+	vamoxorei16.v v4, 0(a1), v8, v4, v0.t
-+	vamoxorei16.v x0, 0(a1), v8, v4, v0.t
-+	vamoandei16.v v4, 0(a1), v8, v4
-+	vamoandei16.v x0, 0(a1), v8, v4
-+	vamoandei16.v v4, 0(a1), v8, v4, v0.t
-+	vamoandei16.v x0, 0(a1), v8, v4, v0.t
-+	vamoorei16.v v4, 0(a1), v8, v4
-+	vamoorei16.v x0, 0(a1), v8, v4
-+	vamoorei16.v v4, 0(a1), v8, v4, v0.t
-+	vamoorei16.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamominei16.v v4, 0(a1), v8, v4
-+	vamominei16.v x0, 0(a1), v8, v4
-+	vamominei16.v v4, 0(a1), v8, v4, v0.t
-+	vamominei16.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxei16.v v4, 0(a1), v8, v4
-+	vamomaxei16.v x0, 0(a1), v8, v4
-+	vamomaxei16.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxei16.v x0, 0(a1), v8, v4, v0.t
-+	vamominuei16.v v4, 0(a1), v8, v4
-+	vamominuei16.v x0, 0(a1), v8, v4
-+	vamominuei16.v v4, 0(a1), v8, v4, v0.t
-+	vamominuei16.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxuei16.v v4, 0(a1), v8, v4
-+	vamomaxuei16.v x0, 0(a1), v8, v4
-+	vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoaddei32.v v4, (a1), v8, v4
-+	vamoaddei32.v x0, (a1), v8, v4
-+	vamoaddei32.v v4, (a1), v8, v4, v0.t
-+	vamoaddei32.v x0, (a1), v8, v4, v0.t
-+	vamoswapei32.v v4, (a1), v8, v4
-+	vamoswapei32.v x0, (a1), v8, v4
-+	vamoswapei32.v v4, (a1), v8, v4, v0.t
-+	vamoswapei32.v x0, (a1), v8, v4, v0.t
-+
-+	vamoxorei32.v v4, (a1), v8, v4
-+	vamoxorei32.v x0, (a1), v8, v4
-+	vamoxorei32.v v4, (a1), v8, v4, v0.t
-+	vamoxorei32.v x0, (a1), v8, v4, v0.t
-+	vamoandei32.v v4, (a1), v8, v4
-+	vamoandei32.v x0, (a1), v8, v4
-+	vamoandei32.v v4, (a1), v8, v4, v0.t
-+	vamoandei32.v x0, (a1), v8, v4, v0.t
-+	vamoorei32.v v4, (a1), v8, v4
-+	vamoorei32.v x0, (a1), v8, v4
-+	vamoorei32.v v4, (a1), v8, v4, v0.t
-+	vamoorei32.v x0, (a1), v8, v4, v0.t
-+
-+	vamominei32.v v4, (a1), v8, v4
-+	vamominei32.v x0, (a1), v8, v4
-+	vamominei32.v v4, (a1), v8, v4, v0.t
-+	vamominei32.v x0, (a1), v8, v4, v0.t
-+	vamomaxei32.v v4, (a1), v8, v4
-+	vamomaxei32.v x0, (a1), v8, v4
-+	vamomaxei32.v v4, (a1), v8, v4, v0.t
-+	vamomaxei32.v x0, (a1), v8, v4, v0.t
-+	vamominuei32.v v4, (a1), v8, v4
-+	vamominuei32.v x0, (a1), v8, v4
-+	vamominuei32.v v4, (a1), v8, v4, v0.t
-+	vamominuei32.v x0, (a1), v8, v4, v0.t
-+	vamomaxuei32.v v4, (a1), v8, v4
-+	vamomaxuei32.v x0, (a1), v8, v4
-+	vamomaxuei32.v v4, (a1), v8, v4, v0.t
-+	vamomaxuei32.v x0, (a1), v8, v4, v0.t
-+
-+	vamoaddei32.v v4, 0(a1), v8, v4
-+	vamoaddei32.v x0, 0(a1), v8, v4
-+	vamoaddei32.v v4, 0(a1), v8, v4, v0.t
-+	vamoaddei32.v x0, 0(a1), v8, v4, v0.t
-+	vamoswapei32.v v4, 0(a1), v8, v4
-+	vamoswapei32.v x0, 0(a1), v8, v4
-+	vamoswapei32.v v4, 0(a1), v8, v4, v0.t
-+	vamoswapei32.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoxorei32.v v4, 0(a1), v8, v4
-+	vamoxorei32.v x0, 0(a1), v8, v4
-+	vamoxorei32.v v4, 0(a1), v8, v4, v0.t
-+	vamoxorei32.v x0, 0(a1), v8, v4, v0.t
-+	vamoandei32.v v4, 0(a1), v8, v4
-+	vamoandei32.v x0, 0(a1), v8, v4
-+	vamoandei32.v v4, 0(a1), v8, v4, v0.t
-+	vamoandei32.v x0, 0(a1), v8, v4, v0.t
-+	vamoorei32.v v4, 0(a1), v8, v4
-+	vamoorei32.v x0, 0(a1), v8, v4
-+	vamoorei32.v v4, 0(a1), v8, v4, v0.t
-+	vamoorei32.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamominei32.v v4, 0(a1), v8, v4
-+	vamominei32.v x0, 0(a1), v8, v4
-+	vamominei32.v v4, 0(a1), v8, v4, v0.t
-+	vamominei32.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxei32.v v4, 0(a1), v8, v4
-+	vamomaxei32.v x0, 0(a1), v8, v4
-+	vamomaxei32.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxei32.v x0, 0(a1), v8, v4, v0.t
-+	vamominuei32.v v4, 0(a1), v8, v4
-+	vamominuei32.v x0, 0(a1), v8, v4
-+	vamominuei32.v v4, 0(a1), v8, v4, v0.t
-+	vamominuei32.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxuei32.v v4, 0(a1), v8, v4
-+	vamomaxuei32.v x0, 0(a1), v8, v4
-+	vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoaddei64.v v4, (a1), v8, v4
-+	vamoaddei64.v x0, (a1), v8, v4
-+	vamoaddei64.v v4, (a1), v8, v4, v0.t
-+	vamoaddei64.v x0, (a1), v8, v4, v0.t
-+	vamoswapei64.v v4, (a1), v8, v4
-+	vamoswapei64.v x0, (a1), v8, v4
-+	vamoswapei64.v v4, (a1), v8, v4, v0.t
-+	vamoswapei64.v x0, (a1), v8, v4, v0.t
-+
-+	vamoxorei64.v v4, (a1), v8, v4
-+	vamoxorei64.v x0, (a1), v8, v4
-+	vamoxorei64.v v4, (a1), v8, v4, v0.t
-+	vamoxorei64.v x0, (a1), v8, v4, v0.t
-+	vamoandei64.v v4, (a1), v8, v4
-+	vamoandei64.v x0, (a1), v8, v4
-+	vamoandei64.v v4, (a1), v8, v4, v0.t
-+	vamoandei64.v x0, (a1), v8, v4, v0.t
-+	vamoorei64.v v4, (a1), v8, v4
-+	vamoorei64.v x0, (a1), v8, v4
-+	vamoorei64.v v4, (a1), v8, v4, v0.t
-+	vamoorei64.v x0, (a1), v8, v4, v0.t
-+
-+	vamominei64.v v4, (a1), v8, v4
-+	vamominei64.v x0, (a1), v8, v4
-+	vamominei64.v v4, (a1), v8, v4, v0.t
-+	vamominei64.v x0, (a1), v8, v4, v0.t
-+	vamomaxei64.v v4, (a1), v8, v4
-+	vamomaxei64.v x0, (a1), v8, v4
-+	vamomaxei64.v v4, (a1), v8, v4, v0.t
-+	vamomaxei64.v x0, (a1), v8, v4, v0.t
-+	vamominuei64.v v4, (a1), v8, v4
-+	vamominuei64.v x0, (a1), v8, v4
-+	vamominuei64.v v4, (a1), v8, v4, v0.t
-+	vamominuei64.v x0, (a1), v8, v4, v0.t
-+	vamomaxuei64.v v4, (a1), v8, v4
-+	vamomaxuei64.v x0, (a1), v8, v4
-+	vamomaxuei64.v v4, (a1), v8, v4, v0.t
-+	vamomaxuei64.v x0, (a1), v8, v4, v0.t
-+
-+	vamoaddei64.v v4, 0(a1), v8, v4
-+	vamoaddei64.v x0, 0(a1), v8, v4
-+	vamoaddei64.v v4, 0(a1), v8, v4, v0.t
-+	vamoaddei64.v x0, 0(a1), v8, v4, v0.t
-+	vamoswapei64.v v4, 0(a1), v8, v4
-+	vamoswapei64.v x0, 0(a1), v8, v4
-+	vamoswapei64.v v4, 0(a1), v8, v4, v0.t
-+	vamoswapei64.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamoxorei64.v v4, 0(a1), v8, v4
-+	vamoxorei64.v x0, 0(a1), v8, v4
-+	vamoxorei64.v v4, 0(a1), v8, v4, v0.t
-+	vamoxorei64.v x0, 0(a1), v8, v4, v0.t
-+	vamoandei64.v v4, 0(a1), v8, v4
-+	vamoandei64.v x0, 0(a1), v8, v4
-+	vamoandei64.v v4, 0(a1), v8, v4, v0.t
-+	vamoandei64.v x0, 0(a1), v8, v4, v0.t
-+	vamoorei64.v v4, 0(a1), v8, v4
-+	vamoorei64.v x0, 0(a1), v8, v4
-+	vamoorei64.v v4, 0(a1), v8, v4, v0.t
-+	vamoorei64.v x0, 0(a1), v8, v4, v0.t
-+
-+	vamominei64.v v4, 0(a1), v8, v4
-+	vamominei64.v x0, 0(a1), v8, v4
-+	vamominei64.v v4, 0(a1), v8, v4, v0.t
-+	vamominei64.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxei64.v v4, 0(a1), v8, v4
-+	vamomaxei64.v x0, 0(a1), v8, v4
-+	vamomaxei64.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxei64.v x0, 0(a1), v8, v4, v0.t
-+	vamominuei64.v v4, 0(a1), v8, v4
-+	vamominuei64.v x0, 0(a1), v8, v4
-+	vamominuei64.v v4, 0(a1), v8, v4, v0.t
-+	vamominuei64.v x0, 0(a1), v8, v4, v0.t
-+	vamomaxuei64.v v4, 0(a1), v8, v4
-+	vamomaxuei64.v x0, 0(a1), v8, v4
-+	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
-+	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
-+	# Aliases
-+	vwcvt.x.x.v v4, v8
-+	vwcvtu.x.x.v v4, v8
-+	vwcvt.x.x.v v4, v8, v0.t
-+	vwcvtu.x.x.v v4, v8, v0.t
-+
-+	vwaddu.vv v4, v8, v12
-+	vwaddu.vx v4, v8, a1
-+	vwaddu.vv v4, v8, v12, v0.t
-+	vwaddu.vx v4, v8, a1, v0.t
-+	vwsubu.vv v4, v8, v12
-+	vwsubu.vx v4, v8, a1
-+	vwsubu.vv v4, v8, v12, v0.t
-+	vwsubu.vx v4, v8, a1, v0.t
-+	vwadd.vv v4, v8, v12
-+	vwadd.vx v4, v8, a1
-+	vwadd.vv v4, v8, v12, v0.t
-+	vwadd.vx v4, v8, a1, v0.t
-+	vwsub.vv v4, v8, v12
-+	vwsub.vx v4, v8, a1
-+	vwsub.vv v4, v8, v12, v0.t
-+	vwsub.vx v4, v8, a1, v0.t
-+	vwaddu.wv v4, v8, v12
-+	vwaddu.wx v4, v8, a1
-+	vwaddu.wv v4, v8, v12, v0.t
-+	vwaddu.wx v4, v8, a1, v0.t
-+	vwsubu.wv v4, v8, v12
-+	vwsubu.wx v4, v8, a1
-+	vwsubu.wv v4, v8, v12, v0.t
-+	vwsubu.wx v4, v8, a1, v0.t
-+	vwadd.wv v4, v8, v12
-+	vwadd.wx v4, v8, a1
-+	vwadd.wv v4, v8, v12, v0.t
-+	vwadd.wx v4, v8, a1, v0.t
-+	vwsub.wv v4, v8, v12
-+	vwsub.wx v4, v8, a1
-+	vwsub.wv v4, v8, v12, v0.t
-+	vwsub.wx v4, v8, a1, v0.t
-+
-+	vsll.vv v4, v8, v12
-+	vsll.vx v4, v8, a1
-+	vsll.vi v4, v8, 1
-+	vsll.vi v4, v8, 31
-+	vsll.vv v4, v8, v12, v0.t
-+	vsll.vx v4, v8, a1, v0.t
-+	vsll.vi v4, v8, 1, v0.t
-+	vsll.vi v4, v8, 31, v0.t
-+	vsrl.vv v4, v8, v12
-+	vsrl.vx v4, v8, a1
-+	vsrl.vi v4, v8, 1
-+	vsrl.vi v4, v8, 31
-+	vsrl.vv v4, v8, v12, v0.t
-+	vsrl.vx v4, v8, a1, v0.t
-+	vsrl.vi v4, v8, 1, v0.t
-+	vsrl.vi v4, v8, 31, v0.t
-+	vsra.vv v4, v8, v12
-+	vsra.vx v4, v8, a1
-+	vsra.vi v4, v8, 1
-+	vsra.vi v4, v8, 31
-+	vsra.vv v4, v8, v12, v0.t
-+	vsra.vx v4, v8, a1, v0.t
-+	vsra.vi v4, v8, 1, v0.t
-+	vsra.vi v4, v8, 31, v0.t
-+
-+	# Aliases
-+	vncvt.x.x.w v4, v8
-+	vncvt.x.x.w v4, v8, v0.t
-+
-+	vnsrl.wv v4, v8, v12
-+	vnsrl.wx v4, v8, a1
-+	vnsrl.wi v4, v8, 1
-+	vnsrl.wi v4, v8, 31
-+	vnsrl.wv v4, v8, v12, v0.t
-+	vnsrl.wx v4, v8, a1, v0.t
-+	vnsrl.wi v4, v8, 1, v0.t
-+	vnsrl.wi v4, v8, 31, v0.t
-+	vnsra.wv v4, v8, v12
-+	vnsra.wx v4, v8, a1
-+	vnsra.wi v4, v8, 1
-+	vnsra.wi v4, v8, 31
-+	vnsra.wv v4, v8, v12, v0.t
-+	vnsra.wx v4, v8, a1, v0.t
-+	vnsra.wi v4, v8, 1, v0.t
-+	vnsra.wi v4, v8, 31, v0.t
-+
-+	vwmul.vv v4, v8, v12
-+	vwmul.vx v4, v8, a1
-+	vwmul.vv v4, v8, v12, v0.t
-+	vwmul.vx v4, v8, a1, v0.t
-+	vwmulu.vv v4, v8, v12
-+	vwmulu.vx v4, v8, a1
-+	vwmulu.vv v4, v8, v12, v0.t
-+	vwmulu.vx v4, v8, a1, v0.t
-+	vwmulsu.vv v4, v8, v12
-+	vwmulsu.vx v4, v8, a1
-+	vwmulsu.vv v4, v8, v12, v0.t
-+	vwmulsu.vx v4, v8, a1, v0.t
-+
-+	vwmaccu.vv v4, v12, v8
-+	vwmaccu.vx v4, a1, v8
-+	vwmaccu.vv v4, v12, v8, v0.t
-+	vwmaccu.vx v4, a1, v8, v0.t
-+	vwmacc.vv v4, v12, v8
-+	vwmacc.vx v4, a1, v8
-+	vwmacc.vv v4, v12, v8, v0.t
-+	vwmacc.vx v4, a1, v8, v0.t
-+	vwmaccsu.vv v4, v12, v8
-+	vwmaccsu.vx v4, a1, v8
-+	vwmaccsu.vv v4, v12, v8, v0.t
-+	vwmaccsu.vx v4, a1, v8, v0.t
-+	vwmaccus.vx v4, a1, v8
-+	vwmaccus.vx v4, a1, v8, v0.t
-+
-+	vsaddu.vv v4, v8, v12
-+	vsaddu.vx v4, v8, a1
-+	vsaddu.vi v4, v8, 15
-+	vsaddu.vi v4, v8, -16
-+	vsaddu.vv v4, v8, v12, v0.t
-+	vsaddu.vx v4, v8, a1, v0.t
-+	vsaddu.vi v4, v8, 15, v0.t
-+	vsaddu.vi v4, v8, -16, v0.t
-+	vsadd.vv v4, v8, v12
-+	vsadd.vx v4, v8, a1
-+	vsadd.vi v4, v8, 15
-+	vsadd.vi v4, v8, -16
-+	vsadd.vv v4, v8, v12, v0.t
-+	vsadd.vx v4, v8, a1, v0.t
-+	vsadd.vi v4, v8, 15, v0.t
-+	vsadd.vi v4, v8, -16, v0.t
-+	vssubu.vv v4, v8, v12
-+	vssubu.vx v4, v8, a1
-+	vssubu.vv v4, v8, v12, v0.t
-+	vssubu.vx v4, v8, a1, v0.t
-+	vssub.vv v4, v8, v12
-+	vssub.vx v4, v8, a1
-+	vssub.vv v4, v8, v12, v0.t
-+	vssub.vx v4, v8, a1, v0.t
-+
-+	vaaddu.vv v4, v8, v12
-+	vaaddu.vx v4, v8, a1
-+	vaaddu.vv v4, v8, v12, v0.t
-+	vaaddu.vx v4, v8, a1, v0.t
-+	vaadd.vv v4, v8, v12
-+	vaadd.vx v4, v8, a1
-+	vaadd.vv v4, v8, v12, v0.t
-+	vaadd.vx v4, v8, a1, v0.t
-+	vasubu.vv v4, v8, v12
-+	vasubu.vx v4, v8, a1
-+	vasubu.vv v4, v8, v12, v0.t
-+	vasubu.vx v4, v8, a1, v0.t
-+	vasub.vv v4, v8, v12
-+	vasub.vx v4, v8, a1
-+	vasub.vv v4, v8, v12, v0.t
-+	vasub.vx v4, v8, a1, v0.t
-+
-+	vsmul.vv v4, v8, v12
-+	vsmul.vx v4, v8, a1
-+	vsmul.vv v4, v8, v12, v0.t
-+	vsmul.vx v4, v8, a1, v0.t
-+
-+	vssrl.vv v4, v8, v12
-+	vssrl.vx v4, v8, a1
-+	vssrl.vi v4, v8, 1
-+	vssrl.vi v4, v8, 31
-+	vssrl.vv v4, v8, v12, v0.t
-+	vssrl.vx v4, v8, a1, v0.t
-+	vssrl.vi v4, v8, 1, v0.t
-+	vssrl.vi v4, v8, 31, v0.t
-+	vssra.vv v4, v8, v12
-+	vssra.vx v4, v8, a1
-+	vssra.vi v4, v8, 1
-+	vssra.vi v4, v8, 31
-+	vssra.vv v4, v8, v12, v0.t
-+	vssra.vx v4, v8, a1, v0.t
-+	vssra.vi v4, v8, 1, v0.t
-+	vssra.vi v4, v8, 31, v0.t
-+
-+	vnclipu.wv v4, v8, v12
-+	vnclipu.wx v4, v8, a1
-+	vnclipu.wi v4, v8, 1
-+	vnclipu.wi v4, v8, 31
-+	vnclipu.wv v4, v8, v12, v0.t
-+	vnclipu.wx v4, v8, a1, v0.t
-+	vnclipu.wi v4, v8, 1, v0.t
-+	vnclipu.wi v4, v8, 31, v0.t
-+	vnclip.wv v4, v8, v12
-+	vnclip.wx v4, v8, a1
-+	vnclip.wi v4, v8, 1
-+	vnclip.wi v4, v8, 31
-+	vnclip.wv v4, v8, v12, v0.t
-+	vnclip.wx v4, v8, a1, v0.t
-+	vnclip.wi v4, v8, 1, v0.t
-+	vnclip.wi v4, v8, 31, v0.t
-+
-+	vfwadd.vv v4, v8, v12
-+	vfwadd.vf v4, v8, fa2
-+	vfwadd.vv v4, v8, v12, v0.t
-+	vfwadd.vf v4, v8, fa2, v0.t
-+	vfwsub.vv v4, v8, v12
-+	vfwsub.vf v4, v8, fa2
-+	vfwsub.vv v4, v8, v12, v0.t
-+	vfwsub.vf v4, v8, fa2, v0.t
-+	vfwadd.wv v4, v8, v12
-+	vfwadd.wf v4, v8, fa2
-+	vfwadd.wv v4, v8, v12, v0.t
-+	vfwadd.wf v4, v8, fa2, v0.t
-+	vfwsub.wv v4, v8, v12
-+	vfwsub.wf v4, v8, fa2
-+	vfwsub.wv v4, v8, v12, v0.t
-+	vfwsub.wf v4, v8, fa2, v0.t
-+
-+	vfwmul.vv v4, v8, v12
-+	vfwmul.vf v4, v8, fa2
-+	vfwmul.vv v4, v8, v12, v0.t
-+	vfwmul.vf v4, v8, fa2, v0.t
-+
-+	vfwmacc.vv v4, v12, v8
-+	vfwmacc.vf v4, fa2, v8
-+	vfwnmacc.vv v4, v12, v8
-+	vfwnmacc.vf v4, fa2, v8
-+	vfwmsac.vv v4, v12, v8
-+	vfwmsac.vf v4, fa2, v8
-+	vfwnmsac.vv v4, v12, v8
-+	vfwnmsac.vf v4, fa2, v8
-+	vfwmacc.vv v4, v12, v8, v0.t
-+	vfwmacc.vf v4, fa2, v8, v0.t
-+	vfwnmacc.vv v4, v12, v8, v0.t
-+	vfwnmacc.vf v4, fa2, v8, v0.t
-+	vfwmsac.vv v4, v12, v8, v0.t
-+	vfwmsac.vf v4, fa2, v8, v0.t
-+	vfwnmsac.vv v4, v12, v8, v0.t
-+	vfwnmsac.vf v4, fa2, v8, v0.t
-+
-+	vfsqrt.v v4, v8
-+	vfsqrt.v v4, v8, v0.t
-+	vfrsqrte7.v v4, v8
-+	vfrsqrte7.v v4, v8, v0.t
-+	vfrsqrt7.v v4, v8
-+	vfrsqrt7.v v4, v8, v0.t
-+	vfrece7.v v4, v8
-+	vfrece7.v v4, v8, v0.t
-+	vfrec7.v v4, v8
-+	vfrec7.v v4, v8, v0.t
-+	vfclass.v v4, v8
-+	vfclass.v v4, v8, v0.t
-+	
-+	vfcvt.xu.f.v v4, v8
-+	vfcvt.x.f.v v4, v8
-+	vfcvt.rtz.xu.f.v v4, v8
-+	vfcvt.rtz.x.f.v v4, v8
-+	vfcvt.f.xu.v v4, v8
-+	vfcvt.f.x.v v4, v8
-+	vfcvt.xu.f.v v4, v8, v0.t
-+	vfcvt.x.f.v v4, v8, v0.t
-+	vfcvt.rtz.xu.f.v v4, v8, v0.t
-+	vfcvt.rtz.x.f.v v4, v8, v0.t
-+	vfcvt.f.xu.v v4, v8, v0.t
-+	vfcvt.f.x.v v4, v8, v0.t
-+
-+	vfwcvt.xu.f.v v4, v8
-+	vfwcvt.x.f.v v4, v8
-+	vfwcvt.rtz.xu.f.v v4, v8
-+	vfwcvt.rtz.x.f.v v4, v8
-+	vfwcvt.f.xu.v v4, v8
-+	vfwcvt.f.x.v v4, v8
-+	vfwcvt.f.f.v v4, v8
-+	vfwcvt.xu.f.v v4, v8, v0.t
-+	vfwcvt.x.f.v v4, v8, v0.t
-+	vfwcvt.rtz.xu.f.v v4, v8, v0.t
-+	vfwcvt.rtz.x.f.v v4, v8, v0.t
-+	vfwcvt.f.xu.v v4, v8, v0.t
-+	vfwcvt.f.x.v v4, v8, v0.t
-+	vfwcvt.f.f.v v4, v8, v0.t
-+
-+	vfncvt.xu.f.w v4, v8
-+	vfncvt.x.f.w v4, v8
-+	vfncvt.rtz.xu.f.w v4, v8
-+	vfncvt.rtz.x.f.w v4, v8
-+	vfncvt.f.xu.w v4, v8
-+	vfncvt.f.x.w v4, v8
-+	vfncvt.f.f.w v4, v8
-+	vfncvt.rod.f.f.w v4, v8
-+	vfncvt.xu.f.w v4, v8, v0.t
-+	vfncvt.x.f.w v4, v8, v0.t
-+	vfncvt.rtz.xu.f.w v4, v8, v0.t
-+	vfncvt.rtz.x.f.w v4, v8, v0.t
-+	vfncvt.f.xu.w v4, v8, v0.t
-+	vfncvt.f.x.w v4, v8, v0.t
-+	vfncvt.f.f.w v4, v8, v0.t
-+	vfncvt.rod.f.f.w v4, v8, v0.t
-+
-+	vredsum.vs v4, v8, v12
-+	vredmaxu.vs v4, v8, v8
-+	vredmax.vs v4, v8, v8
-+	vredminu.vs v4, v8, v8
-+	vredmin.vs v4, v8, v8
-+	vredand.vs v4, v8, v12
-+	vredor.vs v4, v8, v12
-+	vredxor.vs v4, v8, v12
-+	vredsum.vs v4, v8, v12, v0.t
-+	vredmaxu.vs v4, v8, v8, v0.t
-+	vredmax.vs v4, v8, v8, v0.t
-+	vredminu.vs v4, v8, v8, v0.t
-+	vredmin.vs v4, v8, v8, v0.t
-+	vredand.vs v4, v8, v12, v0.t
-+	vredor.vs v4, v8, v12, v0.t
-+	vredxor.vs v4, v8, v12, v0.t
-+
-+	vwredsumu.vs v4, v8, v12
-+	vwredsum.vs v4, v8, v12
-+	vwredsumu.vs v4, v8, v12, v0.t
-+	vwredsum.vs v4, v8, v12, v0.t
-+
-+	vfredosum.vs v4, v8, v12
-+	vfredsum.vs v4, v8, v12
-+	vfredmax.vs v4, v8, v12
-+	vfredmin.vs v4, v8, v12
-+	vfredosum.vs v4, v8, v12, v0.t
-+	vfredsum.vs v4, v8, v12, v0.t
-+	vfredmax.vs v4, v8, v12, v0.t
-+	vfredmin.vs v4, v8, v12, v0.t
-+
-+	vfwredosum.vs v4, v8, v12
-+	vfwredsum.vs v4, v8, v12
-+	vfwredosum.vs v4, v8, v12, v0.t
-+	vfwredsum.vs v4, v8, v12, v0.t
-+
-+	vmsbf.m v4, v8
-+	vmsif.m v4, v8
-+	vmsof.m v4, v8
-+	viota.m v4, v8
-+	vid.v v4
-+	
-+	vmsbf.m v4, v8, v0.t
-+	vmsif.m v4, v8, v0.t
-+	vmsof.m v4, v8, v0.t
-+	viota.m v4, v8, v0.t
-+	vid.v v4, v0.t
-+
-+	vrgatherei16.vv v4, v8, v12
-+	vrgatherei16.vv v4, v8, v12, v0.t
-+
-+	vmv1r.v v1, v2
-+	vmv2r.v v2, v4
-+	vmv4r.v v4, v8
-+	vmv8r.v v0, v8
-diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
-new file mode 100644
-index 0000000000..207a410c28
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
-@@ -0,0 +1,29 @@
-+#as: -march=rv32iv0p10
-+#objdump: -dr
-+
-+.*:[ 	]+file format .*
-+
-+
-+Disassembly of section .text:
-+
-+0+000 <.text>:
-+[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
-+[ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
-+[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
-+[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
-+[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
-+[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
-+[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
-+[ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
-+[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
-+[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
-+[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
-+[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
-diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
-new file mode 100644
-index 0000000000..afbb7ccb36
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
-@@ -0,0 +1,9 @@
-+	vmsge.vx v4, v8, a1		# unmasked va >= x
-+	vmsge.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
-+	vmsge.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
-+	vmsge.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
-+
-+	vmsgeu.vx v4, v8, a1		# unmasked va >= x
-+	vmsgeu.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
-+	vmsgeu.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
-+	vmsgeu.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
-diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
-new file mode 100644
-index 0000000000..fe6a95cba5
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns.d
-@@ -0,0 +1,476 @@
-+#as: -march=rv32iafv0p10
-+#objdump: -dr
-+
-+.*:[ 	]+file format .*
-+
-+
-+Disassembly of section .text:
-+
-+0+000 <.text>:
-+[ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+vsetvl[ 	]+a0,a1,a2
-+[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
-+[ 	]+[0-9a-f]+:[ 	]+0095f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+02b5f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+0335f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+03b5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+0385f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+03f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,mf2,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+0365f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+02d5f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
-+[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
-+[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+0e95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma
-+[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
-+[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
-+[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
-+[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+02050207[ 	]+vle8.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+00050207[ 	]+vle8.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+vse8.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+02050227[ 	]+vse8.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+00050227[ 	]+vse8.v[ 	]+v4,\(a0\),v0.t
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-+[ 	]+[0-9a-f]+:[ 	]+02055207[ 	]+vle16.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+00055207[ 	]+vle16.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+vse16.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+02055227[ 	]+vse16.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+00055227[ 	]+vse16.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+vle32.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+02056207[ 	]+vle32.v[ 	]+v4,\(a0\)
-+[ 	]+[0-9a-f]+:[ 	]+00056207[ 	]+vle32.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+02056227[ 	]+vse32.v[ 	]+v4,\(a0\)
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-+[ 	]+[0-9a-f]+:[ 	]+00056227[ 	]+vse32.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+02057207[ 	]+vle64.v[ 	]+v4,\(a0\)
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-+[ 	]+[0-9a-f]+:[ 	]+00057207[ 	]+vle64.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+02057227[ 	]+vse64.v[ 	]+v4,\(a0\)
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-+[ 	]+[0-9a-f]+:[ 	]+00057227[ 	]+vse64.v[ 	]+v4,\(a0\),v0.t
-+[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1
-+[ 	]+[0-9a-f]+:[ 	]+0ab50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1
-+[ 	]+[0-9a-f]+:[ 	]+08b50207[ 	]+vlse8.v[ 	]+v4,\(a0\),a1,v0.t
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-+[ 	]+[0-9a-f]+:[ 	]+5c865257[ 	]+vfmerge.vfm[ 	]+v4,v8,fa2,v0
-+[ 	]+[0-9a-f]+:[ 	]+5e05d257[ 	]+vfmv.v.f[ 	]+v4,fa1
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-+[ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+vmclr.m[ 	]+v4
-+[ 	]+[0-9a-f]+:[ 	]+7e422257[ 	]+vmset.m[ 	]+v4
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-+[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandnot.mm[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+vmxor.mm[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+vmor.mm[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+vmnor.mm[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmornot.mm[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+vmxnor.mm[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vpopc.m[ 	]+a0,v12
-+[ 	]+[0-9a-f]+:[ 	]+42c8a557[ 	]+vfirst.m[ 	]+a0,v12
-+[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vpopc.m[ 	]+a0,v12,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+40c8a557[ 	]+vfirst.m[ 	]+a0,v12,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+42c02557[ 	]+vmv.x.s[ 	]+a0,v12
-+[ 	]+[0-9a-f]+:[ 	]+42056257[ 	]+vmv.s.x[ 	]+v4,a0
-+[ 	]+[0-9a-f]+:[ 	]+42801557[ 	]+vfmv.f.s[ 	]+fa0,v8
-+[ 	]+[0-9a-f]+:[ 	]+4205d257[ 	]+vfmv.s.f[ 	]+v4,fa1
-+[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+vslideup.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+vslideup.vi[ 	]+v4,v8,0
-+[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+vslideup.vi[ 	]+v4,v8,31
-+[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+vslidedown.vi[ 	]+v4,v8,0
-+[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31
-+[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+vslideup.vx[ 	]+v4,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+vslideup.vi[ 	]+v4,v8,0,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+vslideup.vi[ 	]+v4,v8,31,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+vslidedown.vi[ 	]+v4,v8,0,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3a85d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1
-+[ 	]+[0-9a-f]+:[ 	]+3e85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1
-+[ 	]+[0-9a-f]+:[ 	]+3885d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3c85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+vrgather.vv[ 	]+v4,v8,v12
-+[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+vrgather.vx[ 	]+v4,v8,a1
-+[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+vrgather.vi[ 	]+v4,v8,0
-+[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+vrgather.vi[ 	]+v4,v8,31
-+[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+vrgather.vv[ 	]+v4,v8,v12,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+vrgather.vx[ 	]+v4,v8,a1,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
-+[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
-diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
-new file mode 100644
-index 0000000000..a6f906e416
---- /dev/null
-+++ b/gas/testsuite/gas/riscv/vector-insns.s
-@@ -0,0 +1,521 @@
-+	vsetvl a0, a1, a2
-+	vsetvli a0, a1, 0
-+	vsetvli a0, a1, 0x7ff
-+	vsetvli a0, a1, e16, m2
-+	vsetvli a0, a1, e256, m8
-+	vsetvli a0, a1, e512, m8
-+	vsetvli a0, a1, e1024, m8
-+	vsetvli a0, a1, e1024, m1
-+	vsetvli a0, a1, e1024, mf2
-+	vsetvli a0, a1, e512, mf4
-+	vsetvli a0, a1, e256, mf8
-+	vsetvli a0, a1, e256, m2, ta
-+	vsetvli a0, a1, e256, m2, ma
-+	vsetvli a0, a1, e256, m2, tu
-+	vsetvli a0, a1, e256, m2, mu
-+	vsetvli a0, a1, e256, m2, ta, ma
-+	vsetvli a0, a1, e256, m2, tu, ma
-+	vsetvli a0, a1, e256, m2, ta, mu
-+	vsetvli a0, a1, e256, m2, tu, mu
-+
-+	vle8.v v4, (a0)
-+	vle8.v v4, 0(a0)
-+	vle8.v v4, (a0), v0.t
-+	vse8.v v4, (a0)
-+	vse8.v v4, 0(a0)
-+	vse8.v v4, (a0), v0.t
-+
-+	vle16.v v4, (a0)
-+	vle16.v v4, 0(a0)
-+	vle16.v v4, (a0), v0.t
-+	vse16.v v4, (a0)
-+	vse16.v v4, 0(a0)
-+	vse16.v v4, (a0), v0.t
-+
-+	vle32.v v4, (a0)
-+	vle32.v v4, 0(a0)
-+	vle32.v v4, (a0), v0.t
-+	vse32.v v4, (a0)
-+	vse32.v v4, 0(a0)
-+	vse32.v v4, (a0), v0.t
-+
-+	vle64.v v4, (a0)
-+	vle64.v v4, 0(a0)
-+	vle64.v v4, (a0), v0.t
-+	vse64.v v4, (a0)
-+	vse64.v v4, 0(a0)
-+	vse64.v v4, (a0), v0.t
-+
-+	vlse8.v v4, (a0), a1
-+	vlse8.v v4, 0(a0), a1
-+	vlse8.v v4, (a0), a1, v0.t
-+	vsse8.v v4, (a0), a1
-+	vsse8.v v4, 0(a0), a1
-+	vsse8.v v4, (a0), a1, v0.t
-+
-+	vlse16.v v4, (a0), a1
-+	vlse16.v v4, 0(a0), a1
-+	vlse16.v v4, (a0), a1, v0.t
-+	vsse16.v v4, (a0), a1
-+	vsse16.v v4, 0(a0), a1
-+	vsse16.v v4, (a0), a1, v0.t
-+
-+	vlse32.v v4, (a0), a1
-+	vlse32.v v4, 0(a0), a1
-+	vlse32.v v4, (a0), a1, v0.t
-+	vsse32.v v4, (a0), a1
-+	vsse32.v v4, 0(a0), a1
-+	vsse32.v v4, (a0), a1, v0.t
-+
-+	vlse64.v v4, (a0), a1
-+	vlse64.v v4, 0(a0), a1
-+	vlse64.v v4, (a0), a1, v0.t
-+	vsse64.v v4, (a0), a1
-+	vsse64.v v4, 0(a0), a1
-+	vsse64.v v4, (a0), a1, v0.t
-+
-+	vloxei8.v v4, (a0), v12
-+	vloxei8.v v4, 0(a0), v12
-+	vloxei8.v v4, (a0), v12, v0.t
-+	vsoxei8.v v4, (a0), v12
-+	vsoxei8.v v4, 0(a0), v12
-+	vsoxei8.v v4, (a0), v12, v0.t
-+
-+	vloxei16.v v4, (a0), v12
-+	vloxei16.v v4, 0(a0), v12
-+	vloxei16.v v4, (a0), v12, v0.t
-+	vsoxei16.v v4, (a0), v12
-+	vsoxei16.v v4, 0(a0), v12
-+	vsoxei16.v v4, (a0), v12, v0.t
-+
-+	vloxei32.v v4, (a0), v12
-+	vloxei32.v v4, 0(a0), v12
-+	vloxei32.v v4, (a0), v12, v0.t
-+	vsoxei32.v v4, (a0), v12
-+	vsoxei32.v v4, 0(a0), v12
-+	vsoxei32.v v4, (a0), v12, v0.t
-+
-+	vloxei64.v v4, (a0), v12
-+	vloxei64.v v4, 0(a0), v12
-+	vloxei64.v v4, (a0), v12, v0.t
-+	vsoxei64.v v4, (a0), v12
-+	vsoxei64.v v4, 0(a0), v12
-+	vsoxei64.v v4, (a0), v12, v0.t
-+
-+	vneg.v v4, v8
-+	vneg.v v4, v8, v0.t
-+
-+	vadd.vv v4, v8, v12
-+	vadd.vx v4, v8, a1
-+	vadd.vi v4, v8, 15
-+	vadd.vi v4, v8, -16
-+	vadd.vv v4, v8, v12, v0.t
-+	vadd.vx v4, v8, a1, v0.t
-+	vadd.vi v4, v8, 15, v0.t
-+	vadd.vi v4, v8, -16, v0.t
-+	vsub.vv v4, v8, v12
-+	vsub.vx v4, v8, a1
-+	vrsub.vx v4, v8, a1
-+	vrsub.vi v4, v8, 15
-+	vrsub.vi v4, v8, -16
-+	vsub.vv v4, v8, v12, v0.t
-+	vsub.vx v4, v8, a1, v0.t
-+	vrsub.vx v4, v8, a1, v0.t
-+	vrsub.vi v4, v8, 15, v0.t
-+	vrsub.vi v4, v8, -16, v0.t
-+
-+	# Aliases
-+	vzext.vf2 v4, v8
-+	vzext.vf2 v4, v8, v0.t
-+	vsext.vf2 v4, v8
-+	vsext.vf2 v4, v8, v0.t
-+	vzext.vf4 v4, v8
-+	vzext.vf4 v4, v8, v0.t
-+	vsext.vf4 v4, v8
-+	vsext.vf4 v4, v8, v0.t
-+	vzext.vf8 v4, v8
-+	vzext.vf8 v4, v8, v0.t
-+	vsext.vf8 v4, v8
-+	vsext.vf8 v4, v8, v0.t
-+
-+	vadc.vvm v4, v8, v12, v0
-+	vadc.vxm v4, v8, a1, v0
-+	vadc.vim v4, v8, 15, v0
-+	vadc.vim v4, v8, -16, v0
-+	vmadc.vvm v4, v8, v12, v0
-+	vmadc.vxm v4, v8, a1, v0
-+	vmadc.vim v4, v8, 15, v0
-+	vmadc.vim v4, v8, -16, v0
-+	vmadc.vv v4, v8, v12
-+	vmadc.vx v4, v8, a1
-+	vmadc.vi v4, v8, 15
-+	vmadc.vi v4, v8, -16
-+	vsbc.vvm v4, v8, v12, v0
-+	vsbc.vxm v4, v8, a1, v0
-+	vmsbc.vvm v4, v8, v12, v0
-+	vmsbc.vxm v4, v8, a1, v0
-+	vmsbc.vv v4, v8, v12
-+	vmsbc.vx v4, v8, a1
-+
-+	# Aliases
-+	vnot.v v4, v8
-+	vnot.v v4, v8, v0.t
-+
-+	vand.vv v4, v8, v12
-+	vand.vx v4, v8, a1
-+	vand.vi v4, v8, 15
-+	vand.vi v4, v8, -16
-+	vand.vv v4, v8, v12, v0.t
-+	vand.vx v4, v8, a1, v0.t
-+	vand.vi v4, v8, 15, v0.t
-+	vand.vi v4, v8, -16, v0.t
-+	vor.vv v4, v8, v12
-+	vor.vx v4, v8, a1
-+	vor.vi v4, v8, 15
-+	vor.vi v4, v8, -16
-+	vor.vv v4, v8, v12, v0.t
-+	vor.vx v4, v8, a1, v0.t
-+	vor.vi v4, v8, 15, v0.t
-+	vor.vi v4, v8, -16, v0.t
-+	vxor.vv v4, v8, v12
-+	vxor.vx v4, v8, a1
-+	vxor.vi v4, v8, 15
-+	vxor.vi v4, v8, -16
-+	vxor.vv v4, v8, v12, v0.t
-+	vxor.vx v4, v8, a1, v0.t
-+	vxor.vi v4, v8, 15, v0.t
-+	vxor.vi v4, v8, -16, v0.t
-+
-+	# Aliases
-+	vmsgt.vv v4, v8, v12
-+	vmsgtu.vv v4, v8, v12
-+	vmsge.vv v4, v8, v12
-+	vmsgeu.vv v4, v8, v12
-+	vmsgt.vv v4, v8, v12, v0.t
-+	vmsgtu.vv v4, v8, v12, v0.t
-+	vmsge.vv v4, v8, v12, v0.t
-+	vmsgeu.vv v4, v8, v12, v0.t
-+	vmslt.vi v4, v8, 16
-+	vmslt.vi v4, v8, -15
-+	vmsltu.vi v4, v8, 16
-+	vmsltu.vi v4, v8, -15
-+	vmsge.vi v4, v8, 16
-+	vmsge.vi v4, v8, -15
-+	vmsgeu.vi v4, v8, 16
-+	vmsgeu.vi v4, v8, -15
-+	vmslt.vi v4, v8, 16, v0.t
-+	vmslt.vi v4, v8, -15, v0.t
-+	vmsltu.vi v4, v8, 16, v0.t
-+	vmsltu.vi v4, v8, -15, v0.t
-+	vmsge.vi v4, v8, 16, v0.t
-+	vmsge.vi v4, v8, -15, v0.t
-+	vmsgeu.vi v4, v8, 16, v0.t
-+	vmsgeu.vi v4, v8, -15, v0.t
-+
-+	vmseq.vv v4, v8, v12
-+	vmseq.vx v4, v8, a1
-+	vmseq.vi v4, v8, 15
-+	vmseq.vi v4, v8, -16
-+	vmseq.vv v4, v8, v12, v0.t
-+	vmseq.vx v4, v8, a1, v0.t
-+	vmseq.vi v4, v8, 15, v0.t
-+	vmseq.vi v4, v8, -16, v0.t
-+	vmsne.vv v4, v8, v12
-+	vmsne.vx v4, v8, a1
-+	vmsne.vi v4, v8, 15
-+	vmsne.vi v4, v8, -16
-+	vmsne.vv v4, v8, v12, v0.t
-+	vmsne.vx v4, v8, a1, v0.t
-+	vmsne.vi v4, v8, 15, v0.t
-+	vmsne.vi v4, v8, -16, v0.t
-+	vmsltu.vv v4, v8, v12
-+	vmsltu.vx v4, v8, a1
-+	vmsltu.vv v4, v8, v12, v0.t
-+	vmsltu.vx v4, v8, a1, v0.t
-+	vmslt.vv v4, v8, v12
-+	vmslt.vx v4, v8, a1
-+	vmslt.vv v4, v8, v12, v0.t
-+	vmslt.vx v4, v8, a1, v0.t
-+	vmsleu.vv v4, v8, v12
-+	vmsleu.vx v4, v8, a1
-+	vmsleu.vi v4, v8, 15
-+	vmsleu.vi v4, v8, -16
-+	vmsleu.vv v4, v8, v12, v0.t
-+	vmsleu.vx v4, v8, a1, v0.t
-+	vmsleu.vi v4, v8, 15, v0.t
-+	vmsleu.vi v4, v8, -16, v0.t
-+	vmsle.vv v4, v8, v12
-+	vmsle.vx v4, v8, a1
-+	vmsle.vi v4, v8, 15
-+	vmsle.vi v4, v8, -16
-+	vmsle.vv v4, v8, v12, v0.t
-+	vmsle.vx v4, v8, a1, v0.t
-+	vmsle.vi v4, v8, 15, v0.t
-+	vmsle.vi v4, v8, -16, v0.t
-+	vmsgtu.vx v4, v8, a1
-+	vmsgtu.vi v4, v8, 15
-+	vmsgtu.vi v4, v8, -16
-+	vmsgtu.vx v4, v8, a1, v0.t
-+	vmsgtu.vi v4, v8, 15, v0.t
-+	vmsgtu.vi v4, v8, -16, v0.t
-+	vmsgt.vx v4, v8, a1
-+	vmsgt.vi v4, v8, 15
-+	vmsgt.vi v4, v8, -16
-+	vmsgt.vx v4, v8, a1, v0.t
-+	vmsgt.vi v4, v8, 15, v0.t
-+	vmsgt.vi v4, v8, -16, v0.t
-+
-+	vminu.vv v4, v8, v12
-+	vminu.vx v4, v8, a1
-+	vminu.vv v4, v8, v12, v0.t
-+	vminu.vx v4, v8, a1, v0.t
-+	vmin.vv v4, v8, v12
-+	vmin.vx v4, v8, a1
-+	vmin.vv v4, v8, v12, v0.t
-+	vmin.vx v4, v8, a1, v0.t
-+	vmaxu.vv v4, v8, v12
-+	vmaxu.vx v4, v8, a1
-+	vmaxu.vv v4, v8, v12, v0.t
-+	vmaxu.vx v4, v8, a1, v0.t
-+	vmax.vv v4, v8, v12
-+	vmax.vx v4, v8, a1
-+	vmax.vv v4, v8, v12, v0.t
-+	vmax.vx v4, v8, a1, v0.t
-+
-+	vmul.vv v4, v8, v12
-+	vmul.vx v4, v8, a1
-+	vmul.vv v4, v8, v12, v0.t
-+	vmul.vx v4, v8, a1, v0.t
-+	vmulh.vv v4, v8, v12
-+	vmulh.vx v4, v8, a1
-+	vmulh.vv v4, v8, v12, v0.t
-+	vmulh.vx v4, v8, a1, v0.t
-+	vmulhu.vv v4, v8, v12
-+	vmulhu.vx v4, v8, a1
-+	vmulhu.vv v4, v8, v12, v0.t
-+	vmulhu.vx v4, v8, a1, v0.t
-+	vmulhsu.vv v4, v8, v12
-+	vmulhsu.vx v4, v8, a1
-+	vmulhsu.vv v4, v8, v12, v0.t
-+	vmulhsu.vx v4, v8, a1, v0.t
-+
-+	vmacc.vv v4, v12, v8
-+	vmacc.vx v4, a1, v8
-+	vmacc.vv v4, v12, v8, v0.t
-+	vmacc.vx v4, a1, v8, v0.t
-+	vnmsac.vv v4, v12, v8
-+	vnmsac.vx v4, a1, v8
-+	vnmsac.vv v4, v12, v8, v0.t
-+	vnmsac.vx v4, a1, v8, v0.t
-+	vmadd.vv v4, v12, v8
-+	vmadd.vx v4, a1, v8
-+	vmadd.vv v4, v12, v8, v0.t
-+	vmadd.vx v4, a1, v8, v0.t
-+	vnmsub.vv v4, v12, v8
-+	vnmsub.vx v4, a1, v8
-+	vnmsub.vv v4, v12, v8, v0.t
-+	vnmsub.vx v4, a1, v8, v0.t
-+
-+	vdivu.vv v4, v8, v12
-+	vdivu.vx v4, v8, a1
-+	vdivu.vv v4, v8, v12, v0.t
-+	vdivu.vx v4, v8, a1, v0.t
-+	vdiv.vv v4, v8, v12
-+	vdiv.vx v4, v8, a1
-+	vdiv.vv v4, v8, v12, v0.t
-+	vdiv.vx v4, v8, a1, v0.t
-+	vremu.vv v4, v8, v12
-+	vremu.vx v4, v8, a1
-+	vremu.vv v4, v8, v12, v0.t
-+	vremu.vx v4, v8, a1, v0.t
-+	vrem.vv v4, v8, v12
-+	vrem.vx v4, v8, a1
-+	vrem.vv v4, v8, v12, v0.t
-+	vrem.vx v4, v8, a1, v0.t
-+
-+	vmerge.vvm v4, v8, v12, v0
-+	vmerge.vxm v4, v8, a1, v0
-+	vmerge.vim v4, v8, 15, v0
-+	vmerge.vim v4, v8, -16, v0
-+
-+	vmv.v.v v8, v12
-+	vmv.v.x v8, a1
-+	vmv.v.i v8, 15
-+	vmv.v.i v8, -16
-+
-+
-+
-+	vfadd.vv v4, v8, v12
-+	vfadd.vf v4, v8, fa2
-+	vfadd.vv v4, v8, v12, v0.t
-+	vfadd.vf v4, v8, fa2, v0.t
-+	vfsub.vv v4, v8, v12
-+	vfsub.vf v4, v8, fa2
-+	vfsub.vv v4, v8, v12, v0.t
-+	vfsub.vf v4, v8, fa2, v0.t
-+	vfrsub.vf v4, v8, fa2
-+	vfrsub.vf v4, v8, fa2, v0.t
-+
-+
-+	vfmul.vv v4, v8, v12
-+	vfmul.vf v4, v8, fa2
-+	vfmul.vv v4, v8, v12, v0.t
-+	vfmul.vf v4, v8, fa2, v0.t
-+	vfdiv.vv v4, v8, v12
-+	vfdiv.vf v4, v8, fa2
-+	vfdiv.vv v4, v8, v12, v0.t
-+	vfdiv.vf v4, v8, fa2, v0.t
-+	vfrdiv.vf v4, v8, fa2
-+	vfrdiv.vf v4, v8, fa2, v0.t
-+
-+	vfmadd.vv v4, v12, v8
-+	vfmadd.vf v4, fa2, v8
-+	vfnmadd.vv v4, v12, v8
-+	vfnmadd.vf v4, fa2, v8
-+	vfmsub.vv v4, v12, v8
-+	vfmsub.vf v4, fa2, v8
-+	vfnmsub.vv v4, v12, v8
-+	vfnmsub.vf v4, fa2, v8
-+	vfmadd.vv v4, v12, v8, v0.t
-+	vfmadd.vf v4, fa2, v8, v0.t
-+	vfnmadd.vv v4, v12, v8, v0.t
-+	vfnmadd.vf v4, fa2, v8, v0.t
-+	vfmsub.vv v4, v12, v8, v0.t
-+	vfmsub.vf v4, fa2, v8, v0.t
-+	vfnmsub.vv v4, v12, v8, v0.t
-+	vfnmsub.vf v4, fa2, v8, v0.t
-+	vfmacc.vv v4, v12, v8
-+	vfmacc.vf v4, fa2, v8
-+	vfnmacc.vv v4, v12, v8
-+	vfnmacc.vf v4, fa2, v8
-+	vfmsac.vv v4, v12, v8
-+	vfmsac.vf v4, fa2, v8
-+	vfnmsac.vv v4, v12, v8
-+	vfnmsac.vf v4, fa2, v8
-+	vfmacc.vv v4, v12, v8, v0.t
-+	vfmacc.vf v4, fa2, v8, v0.t
-+	vfnmacc.vv v4, v12, v8, v0.t
-+	vfnmacc.vf v4, fa2, v8, v0.t
-+	vfmsac.vv v4, v12, v8, v0.t
-+	vfmsac.vf v4, fa2, v8, v0.t
-+	vfnmsac.vv v4, v12, v8, v0.t
-+	vfnmsac.vf v4, fa2, v8, v0.t
-+
-+	vfmin.vv v4, v8, v12
-+	vfmin.vf v4, v8, fa2
-+	vfmax.vv v4, v8, v12
-+	vfmax.vf v4, v8, fa2
-+	vfmin.vv v4, v8, v12, v0.t
-+	vfmin.vf v4, v8, fa2, v0.t
-+	vfmax.vv v4, v8, v12, v0.t
-+	vfmax.vf v4, v8, fa2, v0.t
-+
-+	vfneg.v v4, v8
-+	vfneg.v v4, v8, v0.t
-+	vfabs.v v4, v8
-+	vfabs.v v4, v8, v0.t
-+
-+	vfsgnj.vv v4, v8, v12
-+	vfsgnj.vf v4, v8, fa2
-+	vfsgnjn.vv v4, v8, v12
-+	vfsgnjn.vf v4, v8, fa2
-+	vfsgnjx.vv v4, v8, v12
-+	vfsgnjx.vf v4, v8, fa2
-+	vfsgnj.vv v4, v8, v12, v0.t
-+	vfsgnj.vf v4, v8, fa2, v0.t
-+	vfsgnjn.vv v4, v8, v12, v0.t
-+	vfsgnjn.vf v4, v8, fa2, v0.t
-+	vfsgnjx.vv v4, v8, v12, v0.t
-+	vfsgnjx.vf v4, v8, fa2, v0.t
-+
-+	# Aliases
-+	vmfgt.vv v4, v8, v12
-+	vmfge.vv v4, v8, v12
-+	vmfgt.vv v4, v8, v12, v0.t
-+	vmfge.vv v4, v8, v12, v0.t
-+
-+	vmfeq.vv v4, v8, v12
-+	vmfeq.vf v4, v8, fa2
-+	vmfne.vv v4, v8, v12
-+	vmfne.vf v4, v8, fa2
-+	vmflt.vv v4, v8, v12
-+	vmflt.vf v4, v8, fa2
-+	vmfle.vv v4, v8, v12
-+	vmfle.vf v4, v8, fa2
-+	vmfgt.vf v4, v8, fa2
-+	vmfge.vf v4, v8, fa2
-+	vmfeq.vv v4, v8, v12, v0.t
-+	vmfeq.vf v4, v8, fa2, v0.t
-+	vmfne.vv v4, v8, v12, v0.t
-+	vmfne.vf v4, v8, fa2, v0.t
-+	vmflt.vv v4, v8, v12, v0.t
-+	vmflt.vf v4, v8, fa2, v0.t
-+	vmfle.vv v4, v8, v12, v0.t
-+	vmfle.vf v4, v8, fa2, v0.t
-+	vmfgt.vf v4, v8, fa2, v0.t
-+	vmfge.vf v4, v8, fa2, v0.t
-+
-+	vfmerge.vfm v4, v8, fa2, v0
-+	vfmv.v.f v4, fa1
-+
-+	# Aliases
-+	vmcpy.m v4, v8
-+	vmmv.m v4, v8
-+	vmclr.m v4
-+	vmset.m v4
-+	vmnot.m v4, v8
-+
-+	vmand.mm v4, v8, v12
-+	vmnand.mm v4, v8, v12
-+	vmandnot.mm v4, v8, v12
-+	vmxor.mm v4, v8, v12
-+	vmor.mm v4, v8, v12
-+	vmnor.mm v4, v8, v12
-+	vmornot.mm v4, v8, v12
-+	vmxnor.mm v4, v8, v12
-+
-+	vpopc.m a0, v12
-+	vfirst.m a0, v12
-+	vpopc.m a0, v12, v0.t
-+	vfirst.m a0, v12, v0.t
-+
-+	vmv.x.s a0, v12
-+	vmv.s.x v4, a0
-+
-+	vfmv.f.s fa0, v8
-+	vfmv.s.f v4, fa1
-+
-+	vslideup.vx v4, v8, a1
-+	vslideup.vi v4, v8, 0
-+	vslideup.vi v4, v8, 31
-+	vslidedown.vx v4, v8, a1
-+	vslidedown.vi v4, v8, 0
-+	vslidedown.vi v4, v8, 31
-+	vslideup.vx v4, v8, a1, v0.t
-+	vslideup.vi v4, v8, 0, v0.t
-+	vslideup.vi v4, v8, 31, v0.t
-+	vslidedown.vx v4, v8, a1, v0.t
-+	vslidedown.vi v4, v8, 0, v0.t
-+	vslidedown.vi v4, v8, 31, v0.t
-+
-+	vslide1up.vx v4, v8, a1
-+	vslide1down.vx v4, v8, a1
-+	vslide1up.vx v4, v8, a1, v0.t
-+	vslide1down.vx v4, v8, a1, v0.t
-+
-+	vfslide1up.vf v4, v8, fa1
-+	vfslide1down.vf v4, v8, fa1
-+	vfslide1up.vf v4, v8, fa1, v0.t
-+	vfslide1down.vf v4, v8, fa1, v0.t
-+
-+	vrgather.vv v4, v8, v12
-+	vrgather.vx v4, v8, a1
-+	vrgather.vi v4, v8, 0
-+	vrgather.vi v4, v8, 31
-+	vrgather.vv v4, v8, v12, v0.t
-+	vrgather.vx v4, v8, a1, v0.t
-+	vrgather.vi v4, v8, 0, v0.t
-+	vrgather.vi v4, v8, 31, v0.t
-+
-+	vcompress.vm v4, v8, v12
-+
-diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
-index b51e876977..df6b1659f8 100644
---- a/opcodes/riscv-opc.c
-+++ b/opcodes/riscv-opc.c
-@@ -1309,10 +1309,6 @@ const struct riscv_opcode riscv_opcodes[] =
- /* RVV */
- {"vsetvl",     0, INSN_CLASS_V,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
- {"vsetvli",    0, INSN_CLASS_V,  "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
--{"vsetivli",   0, INSN_CLASS_V,  "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
--
--{"vle1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
--{"vse1.v",     0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
- 
- {"vle8.v",     0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
- {"vle16.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
-@@ -1344,362 +1340,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vsoxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
- {"vsoxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
- 
--{"vluxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
--{"vluxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
--{"vluxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
--{"vluxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
--
--{"vsuxei8.v",   0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
--{"vsuxei16.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
--{"vsuxei32.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
--{"vsuxei64.v",  0, INSN_CLASS_V,  "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
--
--{"vle8ff.v",    0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
--{"vle16ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
--{"vle32ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
--{"vle64ff.v",   0, INSN_CLASS_V,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
--{"vsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
--{"vsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
--{"vsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
--{"vsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
--
--{"vlsseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg2e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg3e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg4e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg5e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg6e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg7e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
--{"vssseg8e8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
--
--{"vlsseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg2e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg3e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg4e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg5e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg6e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg7e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
--{"vssseg8e16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
--
--{"vlsseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg2e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg3e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg4e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg5e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg6e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg7e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
--{"vssseg8e32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
--
--{"vlsseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg2e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg3e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg4e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg5e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg6e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg7e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
--{"vlsseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
--{"vssseg8e64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
--
--{"vloxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vloxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vloxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vloxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vloxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsoxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vluxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg2ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg3ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg4ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg5ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg6ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg7ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg8ei8.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vluxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg2ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg3ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg4ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg5ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg6ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg7ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg8ei16.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vluxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg2ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg3ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg4ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg5ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg6ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg7ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg8ei32.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vluxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg2ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg3ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg4ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg5ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg6ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg7ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vluxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--{"vsuxseg8ei64.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
--
--{"vlseg2e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e8ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e16ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e32ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
--
--{"vlseg2e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg3e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg4e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg5e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg6e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg7e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
--{"vlseg8e64ff.v",  0, INSN_CLASS_V_OR_ZVLSSEG,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
--
--{"vl1r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
--{"vl1re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
--{"vl1re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
--{"vl1re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
--{"vl1re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
--
--{"vl2r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
--{"vl2re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
--{"vl2re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
--{"vl2re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
--{"vl2re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
--
--{"vl4r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
--{"vl4re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
--{"vl4re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
--{"vl4re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
--{"vl4re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
--
--{"vl8r.v",      0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
--{"vl8re8.v",    0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
--{"vl8re16.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
--{"vl8re32.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
--{"vl8re64.v",   0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
--
--{"vs1r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
--{"vs2r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
--{"vs4r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
--{"vs8r.v",  0, INSN_CLASS_V,  "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
--
--{"vamoaddei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
--{"vamoswapei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
--{"vamoxorei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
--{"vamoandei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
--{"vamoorei8.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
--{"vamominei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxei8.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
--{"vamominuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxuei8.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
--
--{"vamoaddei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
--{"vamoswapei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
--{"vamoxorei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
--{"vamoandei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
--{"vamoorei16.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
--{"vamominei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxei16.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
--{"vamominuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxuei16.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
--
--{"vamoaddei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
--{"vamoswapei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
--{"vamoxorei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
--{"vamoandei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
--{"vamoorei32.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
--{"vamominei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxei32.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
--{"vamominuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxuei32.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
--
--{"vamoaddei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
--{"vamoswapei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
--{"vamoxorei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
--{"vamoandei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
--{"vamoorei64.v",    0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
--{"vamominei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxei64.v",   0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
--{"vamominuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
--{"vamomaxuei64.v",  0, INSN_CLASS_V_OR_ZVAMO,  "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
--
- {"vneg.v",     0, INSN_CLASS_V,  "Vd,VtVm",  MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
- 
- {"vadd.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
-@@ -1710,26 +1350,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vrsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
- {"vrsub.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
- 
--{"vwcvt.x.x.v",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
--{"vwcvtu.x.x.v", 0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
--
--{"vwaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--{"vwsubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwsubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--{"vwadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--{"vwsub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwsub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--{"vwaddu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
--{"vwaddu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
--{"vwsubu.wv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
--{"vwsubu.wx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
--{"vwadd.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
--{"vwadd.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
--{"vwsub.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
--{"vwsub.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
--
- {"vzext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
- {"vsext.vf2",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
- {"vzext.vf4",  0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
-@@ -1765,25 +1385,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vxor.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
- {"vxor.vi",    0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
- 
--{"vsll.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
--{"vsll.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
--{"vsll.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
--{"vsrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
--{"vsrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
--{"vsrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
--{"vsra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
--{"vsra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
--{"vsra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
--
--{"vncvt.x.x.w",0, INSN_CLASS_V,  "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
--
--{"vnsrl.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnsrl.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnsrl.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnsra.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnsra.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnsra.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
--
- {"vmseq.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
- {"vmseq.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
- {"vmseq.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
-@@ -1840,13 +1441,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vmulhsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
- {"vmulhsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
- 
--{"vwmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--{"vwmulu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwmulu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--{"vwmulsu.vv", 0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
--{"vwmulsu.vx", 0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
--
- {"vmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
- {"vmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
- {"vnmsac.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
-@@ -1856,14 +1450,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vnmsub.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
- {"vnmsub.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
- 
--{"vwmaccu.vv",  0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vwmaccu.vx",  0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vwmacc.vv",   0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vwmacc.vx",   0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vwmaccsu.vv", 0, INSN_CLASS_V,  "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vwmaccsu.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vwmaccus.vx", 0, INSN_CLASS_V,  "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
--
- {"vdivu.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
- {"vdivu.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
- {"vdiv.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
-@@ -1881,67 +1467,18 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vmv.v.x",    0, INSN_CLASS_V,  "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
- {"vmv.v.i",    0, INSN_CLASS_V,  "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
- 
--{"vsaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
--{"vsaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
--{"vsaddu.vi",  0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
--{"vsadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
--{"vsadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
--{"vsadd.vi",   0, INSN_CLASS_V,  "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
--{"vssubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
--{"vssubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
--{"vssub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
--{"vssub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
--
--{"vaaddu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
--{"vaaddu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
--{"vaadd.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
--{"vaadd.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
--{"vasubu.vv",  0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
--{"vasubu.vx",  0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
--{"vasub.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
--{"vasub.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
--
--{"vsmul.vv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
--{"vsmul.vx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
--
--{"vssrl.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
--{"vssrl.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
--{"vssrl.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
--{"vssra.vv",    0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
--{"vssra.vx",    0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
--{"vssra.vi",    0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
--
--{"vnclipu.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnclipu.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnclipu.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnclip.wv",   0, INSN_CLASS_V,  "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
--{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
--
- {"vfadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
- {"vfadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
- {"vfsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
- {"vfsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
- {"vfrsub.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
- 
--{"vfwadd.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwadd.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwsub.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwsub.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwadd.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
--{"vfwadd.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
--{"vfwsub.wv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
--{"vfwsub.wf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
--
- {"vfmul.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
- {"vfmul.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
- {"vfdiv.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
- {"vfdiv.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
- {"vfrdiv.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
- 
--{"vfwmul.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwmul.vf",  0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
--
- {"vfmadd.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
- {"vfmadd.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
- {"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
-@@ -1959,22 +1496,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
- {"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
- 
--{"vfwmacc.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwmacc.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwmsac.vv",  0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwmsac.vf",  0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
--{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
--
--{"vfsqrt.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
--{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
--{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
--{"vfrec7.v",   0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
--{"vfrece7.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
--{"vfclass.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
--
- {"vfmin.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
- {"vfmin.vf",   0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
- {"vfmax.vv",   0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
-@@ -2008,50 +1529,6 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
- {"vfmv.v.f",   0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
- 
--{"vfcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
--{"vfcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
--{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
--{"vfcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
--{"vfcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
--{"vfcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
--
--{"vfwcvt.xu.f.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwcvt.x.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwcvt.rtz.x.f.v",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwcvt.f.xu.v",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwcvt.f.x.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
--{"vfwcvt.f.f.v",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
--
--{"vfncvt.xu.f.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.x.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.rtz.x.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.f.xu.w",     0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.f.x.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.f.f.w",      0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
--{"vfncvt.rod.f.f.w",  0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
--
--{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
--{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
--{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
--{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
--{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
--{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
--{"vredor.vs",  0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
--{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
--
--{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
--{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
--
--{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
--{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
--{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
--{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
--
--{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
--{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
--
- {"vmmv.m",     0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
- {"vmcpy.m",    0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
- {"vmclr.m",    0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
-@@ -2069,11 +1546,6 @@ const struct riscv_opcode riscv_opcodes[] =
- 
- {"vpopc.m",    0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
- {"vfirst.m",   0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
--{"vmsbf.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
--{"vmsif.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
--{"vmsof.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
--{"viota.m",    0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
--{"vid.v",      0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
- 
- {"vmv.x.s",    0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
- {"vmv.s.x",    0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
-@@ -2094,15 +1566,10 @@ const struct riscv_opcode riscv_opcodes[] =
- {"vrgather.vv",    0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
- {"vrgather.vx",    0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
- {"vrgather.vi",    0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
--{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
- 
- {"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
--
--{"vmv1r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
--{"vmv2r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
--{"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
--{"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
- /* END RVV */
-+
- /* Terminate the list.  */
- {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
- };
--- 
-2.33.0
-

+ 0 - 281
recipes-devtools/binutils/binutils/0006-Add-pseudo-instructions-for-B-extension.patch

@@ -1,281 +0,0 @@
-From 32134df31c001130ac0ad9b3975827aaa9c8f42c Mon Sep 17 00:00:00 2001
-From: LevyHsu <admin@levyhsu.com>
-Date: Tue, 8 Jun 2021 15:04:36 +0800
-Subject: [PATCH 06/28] Add pseudo-instructions for B extension
-
-rev[2/4/8/16].[p/n/b/w]
-[un]zip[2/4/8/16].[p/n/b/w]
-orc[2/4/8/16].[p/n/b/w]
----
- opcodes/riscv-opc.c | 246 +++++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 242 insertions(+), 4 deletions(-)
-
-diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
-index df6b1659f8..dc7c1fb428 100644
---- a/opcodes/riscv-opc.c
-+++ b/opcodes/riscv-opc.c
-@@ -25,9 +25,128 @@
- #include <stdio.h>
- 
- #define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
--#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
--#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
--#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_32     (0b11111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_64     (0b111111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_P_32   (0b00001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_P_64   (0b000001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_N_32   (0b00011 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_N_64   (0b000011 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_B_32   (0b00111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_B_64   (0b000111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_H_32   (0b01111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_H_64   (0b001111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV_W_64   (0b011111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_32    (0b11110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_64    (0b111110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_N_32  (0b00010 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_N_64  (0b000010 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_B_32  (0b00110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_B_64  (0b000110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_H_32  (0b01110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_H_64  (0b001110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV2_W_64  (0b011110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_32    (0b11100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_64    (0b111100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_B_32  (0b00100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_B_64  (0b000100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_H_32  (0b01100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_H_64  (0b001100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV4_W_64  (0b011100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_32    (0b11000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_64    (0b111000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_H_32  (0b01000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_H_64  (0b001000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV8_W_64  (0b011000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV16_32   (0b10000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV16_64   (0b110000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV16_W_64 (0b010000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_REV32_64   (0b100000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_32     (0b11110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_64     (0b111110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_N_32   (0b00010 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_N_64   (0b000010 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_B_32   (0b00110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_B_64   (0b000110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_H_32   (0b01110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_H_64   (0b001110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP_W_64   (0b011110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_32    (0b11100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_64    (0b111100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_B_32  (0b00100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_B_64  (0b000100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_H_32  (0b01100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_H_64  (0b001100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP2_W_64  (0b011100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP4_32    (0b11000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP4_64    (0b111000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP4_H_32  (0b01000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP4_H_64  (0b001000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP4_W_64  (0b011000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP8_32    (0b10000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP8_64    (0b110000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP8_W_64  (0b010000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ZIP16_64   (0b100000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_32     (0b11111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_64     (0b111111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_N_32   (0b00011 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_N_64   (0b000011 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_B_32   (0b00111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_B_64   (0b000111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_H_32   (0b01111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_H_64   (0b001111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP_W_64   (0b011111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_32    (0b11101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_64    (0b111101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_B_32  (0b00101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_B_64  (0b000101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_H_32  (0b01101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_H_64  (0b001101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP2_W_64  (0b011101 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP4_32    (0b11001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP4_64    (0b111001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP4_H_32  (0b01001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP4_H_64  (0b001001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP4_W_64  (0b011001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP8_32    (0b10001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP8_64    (0b110001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP8_W_64  (0b010001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_UNZIP16_64   (0b100001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_32     (0b11111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_64     (0b111111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_P_32   (0b00001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_P_64   (0b000001 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_N_32   (0b00011 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_N_64   (0b000011 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_B_32   (0b00111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_B_64   (0b000111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_H_32   (0b01111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_H_64   (0b001111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC_W_64   (0b011111 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_32    (0b11110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_64    (0b111110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_N_32  (0b00010 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_N_64  (0b000010 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_B_32  (0b00110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_B_64  (0b000110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_H_32  (0b01110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_H_64  (0b001110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC2_W_64  (0b011110 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_32    (0b11100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_64    (0b111100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_B_32  (0b00100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_B_64  (0b000100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_H_32  (0b01100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_H_64  (0b001100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC4_W_64  (0b011100 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC8_32    (0b11000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC8_64    (0b111000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC8_H_32  (0b01000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC8_H_64  (0b001000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC8_W_64  (0b011000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC16_32   (0b10000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC16_64   (0b110000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC16_W_64 (0b010000 << OP_SH_SHAMT)
-+#define MATCH_SHAMT_ORC32_64   (0b100000 << OP_SH_SHAMT)
- 
- /* Register names used by gas and objdump.  */
- 
-@@ -1207,9 +1326,128 @@ const struct riscv_opcode riscv_opcodes[] =
- {"rori",       0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, 0 },
- {"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,t",    MATCH_ROR, MASK_ROR, match_opcode, 0 },
- {"ror",        0, INSN_CLASS_ZBB_OR_ZBP,  "d,s,>",    MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
-+{"rev",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
- {"rev8",      32, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
- {"rev8",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
--{"orc.b",      0, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"rev8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"rev32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV32_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
-+{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
-+{"orc",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.b",     32, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.b",     64, INSN_CLASS_ZBB,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
-+{"orc32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC32_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
- {"clzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
- {"ctzw",      64, INSN_CLASS_ZBB,  "d,s",      MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
- {"cpopw",     64, INSN_CLASS_ZBB,  "d,s",      MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
--- 
-2.33.0
-

+ 321 - 0
recipes-devtools/binutils/binutils/0006-Merge-B-instruction-from-0p94-to-1.0.patch

@@ -0,0 +1,321 @@
+From 6065dbfb8d027463e65a5706f94a33995991db3e Mon Sep 17 00:00:00 2001
+From: "yilun.xie" <yilun.xie@starfivetech.com>
+Date: Fri, 22 Oct 2021 16:10:47 +0800
+Subject: [PATCH 06/11] Merge B instruction from 0p94 to 1.0
+
+---
+ bfd/elfxx-riscv.c      |   4 +-
+ gas/config/tc-riscv.c  |  44 ++---------
+ include/opcode/riscv.h |  11 ---
+ opcodes/riscv-opc.c    | 170 +----------------------------------------
+ 4 files changed, 11 insertions(+), 218 deletions(-)
+
+diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
+index 9999ec418a..24c045c46e 100644
+--- a/bfd/elfxx-riscv.c
++++ b/bfd/elfxx-riscv.c
+@@ -1077,8 +1077,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
+ 
+ static const char * const riscv_std_z_ext_strtab[] =
+ {
+-  "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause",
+-  "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt", "zvamo", "zvlsseg",NULL
++  "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg",
++  "zba", "zbb", "zbc",  "zbs", NULL
+ };
+ 
+ static const char * const riscv_std_s_ext_strtab[] =
+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
+index 3f6f7848b9..4aaba3c403 100644
+--- a/gas/config/tc-riscv.c
++++ b/gas/config/tc-riscv.c
+@@ -140,17 +140,11 @@ static const struct riscv_ext_version ext_version_table[] =
+ 
+   {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
+-  {"b",     ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbb",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zba",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbc",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbe",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbf",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbm",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbp",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbr",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbs",   ISA_SPEC_CLASS_DRAFT, 0, 94},
+-  {"zbt",   ISA_SPEC_CLASS_DRAFT, 0, 94},
++  {"b",     ISA_SPEC_CLASS_DRAFT, 1, 0},
++  {"zbb",   ISA_SPEC_CLASS_DRAFT, 1, 0},
++  {"zba",   ISA_SPEC_CLASS_DRAFT, 1, 0},
++  {"zbc",   ISA_SPEC_CLASS_DRAFT, 1, 0},
++  {"zbs",   ISA_SPEC_CLASS_DRAFT, 1, 0},
+ 
+   {"zvamo",   ISA_SPEC_CLASS_NONE, 1, 0},
+   {"zvlsseg", ISA_SPEC_CLASS_NONE, 1, 0},
+@@ -346,40 +340,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
+       return riscv_subset_supports ("zifencei");
+     case INSN_CLASS_ZIHINTPAUSE:
+       return riscv_subset_supports ("zihintpause");
+-
++    
+     case INSN_CLASS_ZBB:
+       return riscv_subset_supports ("zbb");
+-
+     case INSN_CLASS_ZBA:
+       return riscv_subset_supports ("zba");
+-
+     case INSN_CLASS_ZBC:
+       return riscv_subset_supports ("zbc");
+-
+-    case INSN_CLASS_ZBE:
+-      return riscv_subset_supports ("zbe");
+-    case INSN_CLASS_ZBF:
+-      return riscv_subset_supports ("zbf");
+-    case INSN_CLASS_ZBM:
+-      return riscv_subset_supports ("zbm");
+-    case INSN_CLASS_ZBP:
+-      return riscv_subset_supports ("zbp");
+-    case INSN_CLASS_ZBR:
+-      return riscv_subset_supports ("zbr");
+     case INSN_CLASS_ZBS:
+       return riscv_subset_supports ("zbs");
+-    case INSN_CLASS_ZBT:
+-      return riscv_subset_supports ("zbt");
+-    case INSN_CLASS_ZBB_OR_ZBP:
+-      return (riscv_subset_supports ("zbb") || riscv_subset_supports ("zbp"));
+-    case INSN_CLASS_ZBS_OR_ZBE:
+-      return (riscv_subset_supports ("zbs") || riscv_subset_supports ("zbe"));
+-    case INSN_CLASS_ZBP_OR_ZBM:
+-      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbm"));
+-    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF:
+-      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
+-    case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
+-      return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
++    
+     case INSN_CLASS_V: 
+       return riscv_subset_supports ("v");
+     case INSN_CLASS_V_AND_F:
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
+index a785cb1490..92b7ed18f9 100644
+--- a/include/opcode/riscv.h
++++ b/include/opcode/riscv.h
+@@ -388,18 +388,7 @@ enum riscv_insn_class
+   INSN_CLASS_ZBA,
+   INSN_CLASS_ZBB,
+   INSN_CLASS_ZBC,
+-  INSN_CLASS_ZBP,
+-  INSN_CLASS_ZBB_OR_ZBP,
+   INSN_CLASS_ZBS,
+-  INSN_CLASS_ZBE,
+-  INSN_CLASS_ZBS_OR_ZBE,
+-  INSN_CLASS_ZBF,
+-  INSN_CLASS_ZBM,
+-  INSN_CLASS_ZBP_OR_ZBM,
+-  INSN_CLASS_ZBR,
+-  INSN_CLASS_ZBT,
+-  INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
+-  INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
+   INSN_CLASS_V,
+   INSN_CLASS_V_AND_F,
+   INSN_CLASS_V_OR_ZVAMO,
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
+index 745c7a990b..98e7fa33f0 100644
+--- a/opcodes/riscv-opc.c
++++ b/opcodes/riscv-opc.c
+@@ -1257,7 +1257,7 @@ const struct riscv_opcode riscv_opcodes[] =
+ /* ZBS instructions */
+ {"bclr",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+ {"bclri",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
+-{"bext",       0, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
++{"bext",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+ {"bexti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
+ {"binv",       0, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINV, MASK_BINV, match_opcode, 0 },
+ {"binvi",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
+@@ -1265,155 +1265,10 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"bseti",      0, INSN_CLASS_ZBS,  "d,s,>",    MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
+ 
+ /* B instructions excluded from spec1.0 */
+-{"rev",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_P_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_N_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV2_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_B_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV4_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_H_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV8_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV16_W_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"rev32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GREVI|MATCH_SHAMT_REV32_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
+-{"zip",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_N_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.b",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.b",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_B_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP2_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_H_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP4_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP8_W_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"zip16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP16_64, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.n",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.n",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_N_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.b",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.b",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.h",   32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.h",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.b",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.b",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_B_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip2.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP2_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4.h",  32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4.h",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_H_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip4.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP4_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip8",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip8",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip8.w",  64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP8_W_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"unzip16",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_UNZIP16_64, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
+-{"orc",       32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc",       64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.p",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.p",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_P_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.n",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.n",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.h",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.h",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc.w",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.n",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.n",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_N_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc2.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC2_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4.b",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4.b",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_B_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc4.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC4_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc8",      32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc8",      64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc8.h",    32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc8.h",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_H_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc8.w",    64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC8_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc16",     32, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_32, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc16",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc16.w",   64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC16_W_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"orc32",     64, INSN_CLASS_ZBP,  "d,s",      MATCH_GORCI|MATCH_SHAMT_ORC32_64, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
+-{"pack",       0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
+-{"packu",      0, INSN_CLASS_ZBP_OR_ZBM,  "d,s,t",    MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
+-{"packh",      0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+-{"packw",     64, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,  "d,s,<",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+-{"packuw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
+-{"grev",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GREV, MASK_GREV, match_opcode, 0 },
+-{"grevi",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
+-{"grevw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
+-{"greviw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
+-{"gorc",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_GORC, MASK_GORC, match_opcode, 0 },
+-{"gorci",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
+-{"gorcw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
+-{"gorciw",    64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
+-{"shfl",       0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
+-{"shfli",      0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
+-{"shflw",     64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
+-{"unshfl",     0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
+-{"unshfli",    0, INSN_CLASS_ZBP,  "d,s,>",    MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
+-{"unshflw",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
+-{"xperm.n",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
+-{"xperm.b",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
+-{"xperm.h",    0, INSN_CLASS_ZBP,  "d,s,t",    MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
+-{"xperm.w",   64, INSN_CLASS_ZBP,  "d,s,<",    MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
+-{"bcompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BCOMPRESS, MASK_BCOMPRESS, match_opcode, 0 },
+-{"bdecompress",0, INSN_CLASS_ZBE,  "d,s,t",    MATCH_BDECOMPRESS, MASK_BDECOMPRESS, match_opcode, 0 },
+ {"bsetw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
+ {"bclrw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
+ {"binvw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
+-{"bextw",     64, INSN_CLASS_ZBS_OR_ZBE,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
+-{"bcompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BCOMPRESSW, MASK_BCOMPRESSW, match_opcode, 0 },
+-{"bdecompressw",64, INSN_CLASS_ZBE,  "d,s,<",    MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW, match_opcode, 0 },
++{"bextw",     64, INSN_CLASS_ZBS,  "d,s,t",    MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
+ {"bsetiw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
+ {"bclriw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
+ {"binviw",    64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
+@@ -1425,27 +1280,6 @@ const struct riscv_opcode riscv_opcodes[] =
+ {"srow",      64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROW, MASK_SROW, match_opcode, 0 },
+ {"sloiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
+ {"sroiw",     64, INSN_CLASS_ZBS,  "d,s,<",    MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
+-{"bfp",        0, INSN_CLASS_ZBF,  "d,s,t",    MATCH_BFP, MASK_BFP, match_opcode, 0 },
+-{"bfpw",      64, INSN_CLASS_ZBF,  "d,s,<",    MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
+-{"bmator",    64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
+-{"bmatxor",   64, INSN_CLASS_ZBM,  "d,s,t",    MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
+-{"bmatflip",  64, INSN_CLASS_ZBM,  "d,s",      MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
+-{"crc32.b",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
+-{"crc32.h",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
+-{"crc32.w",    0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
+-{"crc32c.b",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
+-{"crc32c.h",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
+-{"crc32c.w",   0, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
+-{"crc32.d",   64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
+-{"crc32c.d",  64, INSN_CLASS_ZBR,  "d,s",      MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
+-{"cmix",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
+-{"cmov",       0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
+-{"fsl",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSL, MASK_FSL, match_opcode, 0 },
+-{"fsr",        0, INSN_CLASS_ZBT,  "d,s,t,r",  MATCH_FSR, MASK_FSR, match_opcode, 0 },
+-{"fsri",       0, INSN_CLASS_ZBT,  "d,s,>,r",  MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
+-{"fslw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
+-{"fsrw",      64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
+-{"fsriw",     64, INSN_CLASS_ZBT,  "d,s,<,r",  MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+ 
+ /* RVV */
+ {"vsetvl",     0, INSN_CLASS_V,  "d,s,t",  MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
+-- 
+2.33.1
+

+ 37 - 0
recipes-devtools/binutils/binutils/0006-Only-generate-an-RPATH-entry-if-LD_RUN_PATH-is-not-e.patch

@@ -0,0 +1,37 @@
+From 29517900352336708495d41902b5b7e8cc9a401a Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Mon, 2 Mar 2015 01:27:17 +0000
+Subject: [PATCH] Only generate an RPATH entry if LD_RUN_PATH is not empty
+
+for cases where -rpath isn't specified. debian (#151024)
+
+Upstream-Status: Pending
+
+Signed-off-by: Chris Chimelis <chris@debian.org>
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ ld/ldelf.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/ld/ldelf.c b/ld/ldelf.c
+index d1615003ede..6a894285b11 100644
+--- a/ld/ldelf.c
++++ b/ld/ldelf.c
+@@ -1250,6 +1250,8 @@ ldelf_after_open (int use_libpath, int native, int is_linux, int is_freebsd,
+ 		  && command_line.rpath == NULL)
+ 		{
+ 		  path = (const char *) getenv ("LD_RUN_PATH");
++		  if ((path) && (strlen (path) == 0))
++		      path = NULL;
+ 		  if (path
+ 		      && ldelf_search_needed (path, &n, force,
+ 					      is_linux, elfsize))
+@@ -1610,6 +1612,8 @@ ldelf_before_allocation (char *audit, char *depaudit,
+   rpath = command_line.rpath;
+   if (rpath == NULL)
+     rpath = (const char *) getenv ("LD_RUN_PATH");
++  if ((rpath) && (strlen (rpath) == 0))
++    rpath = NULL;
+ 
+   for (abfd = link_info.input_bfds; abfd; abfd = abfd->link.next)
+     if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)

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