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@@ -0,0 +1,14220 @@
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+From 9c5cb77c2ba2d45a8f22fe9ac5e2819703f82f66 Mon Sep 17 00:00:00 2001
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+From: "max.ma" <max.ma@starfivetech.com>
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+Date: Thu, 30 Sep 2021 00:18:49 -0700
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+Subject: [PATCH 02/11] merge from dubhe-pr-06-30 to support vector1.0
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+
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+---
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+ gas/config/tc-riscv.c | 405 ++-
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+ gas/testsuite/gas/riscv/v-zero-imm.d | 17 +
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+ gas/testsuite/gas/riscv/v-zero-imm.s | 8 +
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+ .../gas/riscv/vector-insns-fail-arith-fixp.d | 3 +
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+ .../gas/riscv/vector-insns-fail-arith-fixp.l | 27 +
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+ .../gas/riscv/vector-insns-fail-arith-fixp.s | 81 +
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+ .../riscv/vector-insns-fail-arith-floatp.d | 3 +
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+ .../riscv/vector-insns-fail-arith-floatp.l | 49 +
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+ .../riscv/vector-insns-fail-arith-floatp.s | 157 ++
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+ .../gas/riscv/vector-insns-fail-arith-int.d | 3 +
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+ .../gas/riscv/vector-insns-fail-arith-int.l | 71 +
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+ .../gas/riscv/vector-insns-fail-arith-int.s | 213 ++
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+ .../riscv/vector-insns-fail-arith-narrow.d | 3 +
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+ .../riscv/vector-insns-fail-arith-narrow.l | 85 +
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+ .../riscv/vector-insns-fail-arith-narrow.s | 100 +
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+ .../gas/riscv/vector-insns-fail-arith-widen.d | 3 +
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+ .../gas/riscv/vector-insns-fail-arith-widen.l | 253 ++
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+ .../gas/riscv/vector-insns-fail-arith-widen.s | 297 +++
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+ .../gas/riscv/vector-insns-fail-load-store.d | 3 +
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+ .../gas/riscv/vector-insns-fail-load-store.l | 419 ++++
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+ .../gas/riscv/vector-insns-fail-load-store.s | 481 ++++
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+ .../gas/riscv/vector-insns-fail-mask.d | 3 +
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+ .../gas/riscv/vector-insns-fail-mask.l | 10 +
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+ .../gas/riscv/vector-insns-fail-mask.s | 23 +
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+ .../gas/riscv/vector-insns-fail-permutation.d | 3 +
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+ .../gas/riscv/vector-insns-fail-permutation.l | 31 +
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+ .../gas/riscv/vector-insns-fail-permutation.s | 56 +
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+ .../gas/riscv/vector-insns-fail-unsupport.d | 3 +
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+ .../gas/riscv/vector-insns-fail-unsupport.l | 1454 +++++++++++
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+ .../gas/riscv/vector-insns-fail-unsupport.s | 1663 +++++++++++++
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+ .../gas/riscv/vector-insns-fail-zvamo.d | 3 +
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+ .../gas/riscv/vector-insns-fail-zvamo.l | 109 +
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+ .../gas/riscv/vector-insns-fail-zvamo.s | 217 ++
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+ .../gas/riscv/vector-insns-vmsgtvx.d | 29 +
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+ .../gas/riscv/vector-insns-vmsgtvx.s | 9 +
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+ gas/testsuite/gas/riscv/vector-insns.d | 1944 +++++++++++++++
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+ gas/testsuite/gas/riscv/vector-insns.s | 2185 +++++++++++++++++
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+ include/opcode/riscv-opc.h | 1916 ++++++++++++++-
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+ include/opcode/riscv.h | 82 +-
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+ opcodes/riscv-dis.c | 90 +-
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+ opcodes/riscv-opc.c | 1125 ++++++++-
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+ 41 files changed, 13626 insertions(+), 10 deletions(-)
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+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.d
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+ create mode 100644 gas/testsuite/gas/riscv/v-zero-imm.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-mask.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.d
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+ create mode 100644 gas/testsuite/gas/riscv/vector-insns.s
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+
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+diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
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+index e5d8070b75..898ee89f96 100644
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+--- a/gas/config/tc-riscv.c
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++++ b/gas/config/tc-riscv.c
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+@@ -64,6 +64,7 @@ enum riscv_csr_class
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+ CSR_CLASS_I,
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+ CSR_CLASS_I_32, /* rv32 only */
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+ CSR_CLASS_F, /* f-ext only */
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++ CSR_CLASS_V,
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+ CSR_CLASS_DEBUG /* debug CSR */
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+ };
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+
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+@@ -367,6 +368,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
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+ return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
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+ case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
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+ return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
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++ case INSN_CLASS_V:
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++ return riscv_subset_supports ("v");
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++ case INSN_CLASS_V_AND_F:
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++ return riscv_subset_supports ("v") && riscv_subset_supports ("f");
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++ case INSN_CLASS_V_OR_ZVAMO:
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++ return (riscv_subset_supports ("a")
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++ && (riscv_subset_supports ("v")
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++ || riscv_subset_supports ("zvamo")));
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++ case INSN_CLASS_V_OR_ZVLSSEG:
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++ return riscv_subset_supports ("v") || riscv_subset_supports ("zvlsseg");
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+ default:
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+ as_fatal ("internal: unreachable");
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+ return false;
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+@@ -807,7 +818,8 @@ enum reg_class
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+ RCLASS_GPR,
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+ RCLASS_FPR,
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+ RCLASS_MAX,
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+-
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++ RCLASS_VECR,
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++ RCLASS_VECM,
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+ RCLASS_CSR
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+ };
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+
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+@@ -909,6 +921,12 @@ riscv_csr_address (const char *csr_name,
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+ result = riscv_subset_supports ("f");
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+ need_check_version = false;
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+ break;
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++ case CSR_CLASS_V:
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++ result = (riscv_subset_supports ("v")
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++ || riscv_subset_supports ("zvamo")
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++ || riscv_subset_supports ("zvlsseg"));
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++ need_check_version = false;
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++ break;
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+ case CSR_CLASS_DEBUG:
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+ need_check_version = false;
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+ break;
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+@@ -1171,6 +1189,33 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
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+ return false;
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+ }
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+ break;
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++
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++ case 'V': /* RVV */
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++ switch (c = *p++)
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++ {
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++ case 'd':
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++ case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
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++ case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
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++ case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
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++ case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
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++ case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
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++ USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
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++ case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
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++ USE_BITS (OP_MASK_VS1, OP_SH_VS1);
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++ USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
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++ case '0': break;
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++ case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break;
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++ case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
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++ case 'i':
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++ case 'j':
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++ case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
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++ case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
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++ default:
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++ as_bad (_("internal: bad RISC-V opcode (unknown operand type `V%c'): %s %s"),
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++ c, opc->name, opc->args);
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++ }
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++ break;
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++
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+ default:
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+ as_bad (_("internal: bad RISC-V opcode "
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+ "(unknown operand type `%c'): %s %s"),
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+@@ -1252,6 +1297,8 @@ md_begin (void)
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+ hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
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+ hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
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+ hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
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++ hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
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++ hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
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+ /* Add "fp" as an alias for "s0". */
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+ hash_reg_name (RCLASS_GPR, "fp", 8);
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+
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+@@ -1412,6 +1459,41 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
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+ break;
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+ case ',':
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+ continue;
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++
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++ case 'V': /* RVV */
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++ {
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++ switch (*fmt++)
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++ {
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++ case 'd':
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++ INSERT_OPERAND (VD, insn, va_arg (args, int));
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++ continue;
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++
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++ case 's':
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++ INSERT_OPERAND (VS1, insn, va_arg (args, int));
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++ continue;
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++
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++ case 't':
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++ INSERT_OPERAND (VS2, insn, va_arg (args, int));
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++ continue;
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++
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++ case 'm':
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++ {
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++ int reg = va_arg (args, int);
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++ if (reg == -1)
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++ {
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++ INSERT_OPERAND (VMASK, insn, 1);
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++ continue;
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++ }
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++ else if (reg == 0)
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++ {
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++ INSERT_OPERAND (VMASK, insn, 0);
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++ continue;
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++ }
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++ }
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++ /* fallthru */
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++ }
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++ }
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++
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+ default:
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+ as_fatal (_("internal: invalid macro"));
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+ }
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+@@ -1584,6 +1666,96 @@ load_const (int reg, expressionS *ep)
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+ }
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+ }
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+
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++/* Expand RISC-V Vector macros into one of more instructions. */
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++
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++static void
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++vector_macro (struct riscv_cl_insn *ip)
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++{
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++ int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
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++ int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
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++ int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
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++ int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
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++ int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
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++ int mask = ip->insn_mo->mask;
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++
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++ switch (mask)
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++ {
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++ case M_VMSGE:
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++ if (vm)
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++ {
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++ /* Unmasked. */
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++ macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
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++ macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
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++ break;
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++ }
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++ if (vtemp != 0)
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++ {
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++ /* Masked. Have vtemp to avoid overlap constraints. */
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++ if (vd == vm)
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++ {
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++ macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
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++ macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
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++ }
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++ else
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++ {
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++ /* Preserve the value of vd if not updating by vm. */
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++ macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
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++ macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
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++ macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
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++ macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
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++ }
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++ }
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++ else if (vd != vm)
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++ {
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++ /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
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++ macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
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++ macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
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++ }
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++ else
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++ as_bad (_("must provide temp if destination overlaps mask"));
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++ break;
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++
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++ case M_VMSGEU:
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++ if (vm)
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++ {
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++ /* Unmasked. */
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++ macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
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++ macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
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++ break;
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++ }
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++ if (vtemp != 0)
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++ {
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++ /* Masked. Have vtemp to avoid overlap constraints. */
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++ if (vd == vm)
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++ {
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++ macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
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++ macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
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++ }
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++ else
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++ {
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++ /* Preserve the value of vd if not updating by vm. */
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++ macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
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++ macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
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++ macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
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++ macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
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++ }
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++ }
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++ else if (vd != vm)
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++ {
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++ /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */
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++ macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
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++ macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
|
|
|
++ }
|
|
|
++ else
|
|
|
++ as_bad (_("must provide temp if destination overlaps mask"));
|
|
|
++ break;
|
|
|
++
|
|
|
++ default:
|
|
|
++ as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
|
|
|
++ break;
|
|
|
++ }
|
|
|
++}
|
|
|
++
|
|
|
+ /* Zero extend and sign extend byte/half-word/word. */
|
|
|
+
|
|
|
+ static void
|
|
|
+@@ -1739,6 +1911,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
|
|
|
+ riscv_ext (rd, rs1, xlen - 16, true);
|
|
|
+ break;
|
|
|
+
|
|
|
++ case M_VMSGE:
|
|
|
++ case M_VMSGEU:
|
|
|
++ vector_macro (ip);
|
|
|
++ break;
|
|
|
++
|
|
|
+ default:
|
|
|
+ as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
|
|
|
+ break;
|
|
|
+@@ -1892,6 +2069,66 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
|
|
|
+ return reloc_index;
|
|
|
+ }
|
|
|
+
|
|
|
++/* Parse string STR as a vsetvli operand. Store the expression in *EP.
|
|
|
++ On exit, EXPR_END points to the first character after the expression. */
|
|
|
++
|
|
|
++static void
|
|
|
++my_getVsetvliExpression (expressionS *ep, char *str)
|
|
|
++{
|
|
|
++ unsigned int vsew_value = 0, vlmul_value = 0;
|
|
|
++ unsigned int vta_value = 0, vma_value = 0;
|
|
|
++ bfd_boolean vsew_found = FALSE, vlmul_found = FALSE;
|
|
|
++ bfd_boolean vta_found = FALSE, vma_found = FALSE;
|
|
|
++
|
|
|
++ if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
|
|
|
++ {
|
|
|
++ if (*str == ',')
|
|
|
++ ++str;
|
|
|
++ if (vsew_found)
|
|
|
++ as_bad (_("multiple vsew constants"));
|
|
|
++ vsew_found = TRUE;
|
|
|
++ }
|
|
|
++ if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
|
|
|
++ {
|
|
|
++ if (*str == ',')
|
|
|
++ ++str;
|
|
|
++ if (vlmul_found)
|
|
|
++ as_bad (_("multiple vlmul constants"));
|
|
|
++ vlmul_found = TRUE;
|
|
|
++ }
|
|
|
++ if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
|
|
|
++ {
|
|
|
++ if (*str == ',')
|
|
|
++ ++str;
|
|
|
++ if (vta_found)
|
|
|
++ as_bad (_("multiple vta constants"));
|
|
|
++ vta_found = TRUE;
|
|
|
++ }
|
|
|
++ if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
|
|
|
++ {
|
|
|
++ if (*str == ',')
|
|
|
++ ++str;
|
|
|
++ if (vma_found)
|
|
|
++ as_bad (_("multiple vma constants"));
|
|
|
++ vma_found = TRUE;
|
|
|
++ }
|
|
|
++
|
|
|
++ if (vsew_found || vlmul_found || vta_found || vma_found)
|
|
|
++ {
|
|
|
++ ep->X_op = O_constant;
|
|
|
++ ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
|
|
|
++ | (vsew_value << OP_SH_VSEW)
|
|
|
++ | (vta_value << OP_SH_VTA)
|
|
|
++ | (vma_value << OP_SH_VMA);
|
|
|
++ expr_end = str;
|
|
|
++ }
|
|
|
++ else
|
|
|
++ {
|
|
|
++ my_getExpression (ep, str);
|
|
|
++ str = expr_end;
|
|
|
++ }
|
|
|
++}
|
|
|
++
|
|
|
+ /* Parse opcode name, could be an mnemonics or number. */
|
|
|
+
|
|
|
+ static size_t
|
|
|
+@@ -2755,6 +2992,170 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
|
|
+ imm_expr->X_op = O_absent;
|
|
|
+ continue;
|
|
|
+
|
|
|
++ case 'V': /* RVV */
|
|
|
++ switch (*++args)
|
|
|
++ {
|
|
|
++ case 'd': /* VD */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ break;
|
|
|
++ INSERT_OPERAND (VD, *ip, regno);
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'e': /* AMO VD */
|
|
|
++ if (reg_lookup (&s, RCLASS_GPR, ®no) && regno == 0)
|
|
|
++ INSERT_OPERAND (VWD, *ip, 0);
|
|
|
++ else if (reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ {
|
|
|
++ INSERT_OPERAND (VWD, *ip, 1);
|
|
|
++ INSERT_OPERAND (VD, *ip, regno);
|
|
|
++ }
|
|
|
++ else
|
|
|
++ break;
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'f': /* AMO VS3 */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ break;
|
|
|
++ if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
|
|
|
++ INSERT_OPERAND (VD, *ip, regno);
|
|
|
++ else
|
|
|
++ {
|
|
|
++ /* VS3 must match VD. */
|
|
|
++ if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
|
|
|
++ break;
|
|
|
++ }
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 's': /* VS1 */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ break;
|
|
|
++ INSERT_OPERAND (VS1, *ip, regno);
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 't': /* VS2 */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ break;
|
|
|
++ INSERT_OPERAND (VS2, *ip, regno);
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'u': /* VS1 == VS2 */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ break;
|
|
|
++ INSERT_OPERAND (VS1, *ip, regno);
|
|
|
++ INSERT_OPERAND (VS2, *ip, regno);
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'v': /* VD == VS1 == VS2 */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no))
|
|
|
++ break;
|
|
|
++ INSERT_OPERAND (VD, *ip, regno);
|
|
|
++ INSERT_OPERAND (VS1, *ip, regno);
|
|
|
++ INSERT_OPERAND (VS2, *ip, regno);
|
|
|
++ continue;
|
|
|
++
|
|
|
++ /* The `V0` is carry-in register for v[m]adc and v[m]sbc,
|
|
|
++ and is used to choose vs1/rs1/frs1/imm or vs2 for
|
|
|
++ v[f]merge. It use the same encoding as the vector mask
|
|
|
++ register. */
|
|
|
++ case '0':
|
|
|
++ if (reg_lookup (&s, RCLASS_VECR, ®no) && regno == 0)
|
|
|
++ continue;
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'b': /* vtypei for vsetivli */
|
|
|
++ my_getVsetvliExpression (imm_expr, s);
|
|
|
++ check_absolute_expr (ip, imm_expr, FALSE);
|
|
|
++ if (!VALID_RVV_VB_IMM (imm_expr->X_add_number))
|
|
|
++ as_bad (_("bad value for vsetivli immediate field, "
|
|
|
++ "value must be 0..1023"));
|
|
|
++ ip->insn_opcode
|
|
|
++ |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number);
|
|
|
++ imm_expr->X_op = O_absent;
|
|
|
++ s = expr_end;
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'c': /* vtypei for vsetvli */
|
|
|
++ my_getVsetvliExpression (imm_expr, s);
|
|
|
++ check_absolute_expr (ip, imm_expr, FALSE);
|
|
|
++ if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
|
|
|
++ as_bad (_("bad value for vsetvli immediate field, "
|
|
|
++ "value must be 0..2047"));
|
|
|
++ ip->insn_opcode
|
|
|
++ |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
|
|
|
++ imm_expr->X_op = O_absent;
|
|
|
++ s = expr_end;
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'i': /* vector arith signed immediate */
|
|
|
++ my_getExpression (imm_expr, s);
|
|
|
++ check_absolute_expr (ip, imm_expr, FALSE);
|
|
|
++ if (imm_expr->X_add_number > 15
|
|
|
++ || imm_expr->X_add_number < -16)
|
|
|
++ as_bad (_("bad value for vector immediate field, "
|
|
|
++ "value must be -16...15"));
|
|
|
++ INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
|
|
|
++ imm_expr->X_op = O_absent;
|
|
|
++ s = expr_end;
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'j': /* vector arith unsigned immediate */
|
|
|
++ my_getExpression (imm_expr, s);
|
|
|
++ check_absolute_expr (ip, imm_expr, FALSE);
|
|
|
++ if (imm_expr->X_add_number < 0
|
|
|
++ || imm_expr->X_add_number >= 32)
|
|
|
++ as_bad (_("bad value for vector immediate field, "
|
|
|
++ "value must be 0...31"));
|
|
|
++ INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
|
|
|
++ imm_expr->X_op = O_absent;
|
|
|
++ s = expr_end;
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'k': /* vector arith signed immediate, minus 1 */
|
|
|
++ my_getExpression (imm_expr, s);
|
|
|
++ check_absolute_expr (ip, imm_expr, FALSE);
|
|
|
++ if (imm_expr->X_add_number > 16
|
|
|
++ || imm_expr->X_add_number < -15)
|
|
|
++ as_bad (_("bad value for vector immediate field, "
|
|
|
++ "value must be -15...16"));
|
|
|
++ INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
|
|
|
++ imm_expr->X_op = O_absent;
|
|
|
++ s = expr_end;
|
|
|
++ continue;
|
|
|
++
|
|
|
++ case 'm': /* optional vector mask */
|
|
|
++ if (*s == '\0')
|
|
|
++ {
|
|
|
++ INSERT_OPERAND (VMASK, *ip, 1);
|
|
|
++ continue;
|
|
|
++ }
|
|
|
++ else if (*s == ',' && s++
|
|
|
++ && reg_lookup (&s, RCLASS_VECM, ®no)
|
|
|
++ && regno == 0)
|
|
|
++ {
|
|
|
++ INSERT_OPERAND (VMASK, *ip, 0);
|
|
|
++ continue;
|
|
|
++ }
|
|
|
++ break;
|
|
|
++
|
|
|
++ /* The following ones are only used in macros. */
|
|
|
++ case 'M': /* required vector mask */
|
|
|
++ if (reg_lookup (&s, RCLASS_VECM, ®no) && regno == 0)
|
|
|
++ {
|
|
|
++ INSERT_OPERAND (VMASK, *ip, 0);
|
|
|
++ continue;
|
|
|
++ }
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'T': /* vector macro temporary register */
|
|
|
++ if (!reg_lookup (&s, RCLASS_VECR, ®no) || regno == 0)
|
|
|
++ break;
|
|
|
++ /* Store it in the FUNCT6 field as we don't have anyplace
|
|
|
++ else to store it. */
|
|
|
++ INSERT_OPERAND (VFUNCT6, *ip, regno);
|
|
|
++ continue;
|
|
|
++ }
|
|
|
++ break;
|
|
|
++
|
|
|
+ default:
|
|
|
+ as_fatal (_("internal: unknown argument type `%c'"), *args);
|
|
|
+ }
|
|
|
+@@ -3940,4 +4341,4 @@ riscv_pop_insert (void)
|
|
|
+ extern void pop_insert (const pseudo_typeS *);
|
|
|
+
|
|
|
+ pop_insert (riscv_pseudo_table);
|
|
|
+-}
|
|
|
++}
|
|
|
+\ No newline at end of file
|
|
|
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.d b/gas/testsuite/gas/riscv/v-zero-imm.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..b95c068a17
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/v-zero-imm.d
|
|
|
+@@ -0,0 +1,17 @@
|
|
|
++#as: -march=rv32ifv0p10
|
|
|
++#objdump: -dr
|
|
|
++
|
|
|
++.*:[ ]+file format .*
|
|
|
++
|
|
|
++
|
|
|
++Disassembly of section .text:
|
|
|
++
|
|
|
++0+000 <.text>:
|
|
|
++[ ]+[0-9a-f]+:[ ]+768fb257[ ]+vmsle.vi[ ]+v4,v8,-1
|
|
|
++[ ]+[0-9a-f]+:[ ]+748fb257[ ]+vmsle.vi[ ]+v4,v8,-1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+66840257[ ]+vmsne.vv[ ]+v4,v8,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+64840257[ ]+vmsne.vv[ ]+v4,v8,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62840257[ ]+vmseq.vv[ ]+v4,v8,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+60840257[ ]+vmseq.vv[ ]+v4,v8,v8,v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/v-zero-imm.s b/gas/testsuite/gas/riscv/v-zero-imm.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..98b7063880
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/v-zero-imm.s
|
|
|
+@@ -0,0 +1,8 @@
|
|
|
++ vmslt.vi v4, v8, 0
|
|
|
++ vmslt.vi v4, v8, 0, v0.t
|
|
|
++ vmsltu.vi v4, v8, 0
|
|
|
++ vmsltu.vi v4, v8, 0, v0.t
|
|
|
++ vmsge.vi v4, v8, 0
|
|
|
++ vmsge.vi v4, v8, 0, v0.t
|
|
|
++ vmsgeu.vi v4, v8, 0
|
|
|
++ vmsgeu.vi v4, v8, 0, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..55cfd83301
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-arith-fixp.s
|
|
|
++#error_output: vector-insns-fail-arith-fixp.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..a3c126d8ec
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.l
|
|
|
+@@ -0,0 +1,27 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vsaddu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsaddu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vsaddu.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vsadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsadd.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vsadd.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vssubu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vssubu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vssub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vssub.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vaaddu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vaaddu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vaadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vaadd.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vasubu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vasubu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vasub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vasub.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vsmul.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsmul.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vssrl.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vssrl.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vssrl.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vssra.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vssra.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vssra.vi v0,v4,31,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..1fbcb601ea
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-fixp.s
|
|
|
+@@ -0,0 +1,81 @@
|
|
|
++# Vector Single-Width Saturating Add and Subtract
|
|
|
++
|
|
|
++ vsaddu.vv v4, v4, v8 # OK
|
|
|
++ vsaddu.vv v8, v4, v8 # OK
|
|
|
++ vsaddu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vsaddu.vx v4, v4, a1 # OK
|
|
|
++ vsaddu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vsaddu.vi v4, v4, 15 # OK
|
|
|
++ vsaddu.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vsadd.vv v4, v4, v8
|
|
|
++ vsadd.vv v8, v4, v8
|
|
|
++ vsadd.vv v0, v4, v8, v0.t
|
|
|
++ vsadd.vx v4, v4, a1
|
|
|
++ vsadd.vx v0, v4, a1, v0.t
|
|
|
++ vsadd.vi v4, v4, 15
|
|
|
++ vsadd.vi v0, v4, 15, v0.t
|
|
|
++
|
|
|
++ vssubu.vv v4, v4, v8 # OK
|
|
|
++ vssubu.vv v8, v4, v8 # OK
|
|
|
++ vssubu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vssubu.vx v4, v4, a1 # OK
|
|
|
++ vssubu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vssub.vv v4, v4, v8
|
|
|
++ vssub.vv v8, v4, v8
|
|
|
++ vssub.vv v0, v4, v8, v0.t
|
|
|
++ vssub.vx v4, v4, a1
|
|
|
++ vssub.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Averaging Add and Subtract
|
|
|
++
|
|
|
++ vaaddu.vv v4, v4, v8 # OK
|
|
|
++ vaaddu.vv v8, v4, v8 # OK
|
|
|
++ vaaddu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vaaddu.vx v4, v4, a1 # OK
|
|
|
++ vaaddu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vaadd.vv v4, v4, v8
|
|
|
++ vaadd.vv v8, v4, v8
|
|
|
++ vaadd.vv v0, v4, v8, v0.t
|
|
|
++ vaadd.vx v4, v4, a1
|
|
|
++ vaadd.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vasubu.vv v4, v4, v8
|
|
|
++ vasubu.vv v8, v4, v8
|
|
|
++ vasubu.vv v0, v4, v8, v0.t
|
|
|
++ vasubu.vx v4, v4, a1
|
|
|
++ vasubu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vasub.vv v4, v4, v8
|
|
|
++ vasub.vv v8, v4, v8
|
|
|
++ vasub.vv v0, v4, v8, v0.t
|
|
|
++ vasub.vx v4, v4, a1
|
|
|
++ vasub.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Fractional Multiply with Rounding and Saturation
|
|
|
++
|
|
|
++ vsmul.vv v4, v4, v8 # OK
|
|
|
++ vsmul.vv v8, v4, v8 # OK
|
|
|
++ vsmul.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vsmul.vx v4, v4, a1 # OK
|
|
|
++ vsmul.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Single-Width Scaling Shift Instructions
|
|
|
++
|
|
|
++ vssrl.vv v4, v4, v8 # OK
|
|
|
++ vssrl.vv v8, v4, v8 # OK
|
|
|
++ vssrl.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vssrl.vx v4, v4, a1 # OK
|
|
|
++ vssrl.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vssrl.vi v4, v4, 31 # OK
|
|
|
++ vssrl.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vssra.vv v4, v4, v8
|
|
|
++ vssra.vv v8, v4, v8
|
|
|
++ vssra.vv v0, v4, v8, v0.t
|
|
|
++ vssra.vx v4, v4, a1
|
|
|
++ vssra.vx v0, v4, a1, v0.t
|
|
|
++ vssra.vi v4, v4, 31
|
|
|
++ vssra.vi v0, v4, 31, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..d192761c06
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32ifv0p10
|
|
|
++#source: vector-insns-fail-arith-floatp.s
|
|
|
++#error_output: vector-insns-fail-arith-floatp.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..e4d365cfa5
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.l
|
|
|
+@@ -0,0 +1,49 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vfadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfadd.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsub.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfrsub.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfmul.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmul.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfdiv.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfdiv.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfrdiv.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfmacc.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmacc.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmacc.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmacc.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmsac.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmsac.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsac.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsac.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmadd.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmadd.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmsub.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfnmsub.vf v0,fa1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfsqrt.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfrece7.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfrsqrte7.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfclass.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfmin.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmin.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfmax.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfmax.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfneg.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfabs.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnj.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnj.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjn.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjn.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjx.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vfsgnjx.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfcvt.xu.f.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfcvt.x.f.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfcvt.rtz.xu.f.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfcvt.rtz.x.f.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfcvt.f.xu.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfcvt.f.x.v v0,v4,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..19ed26a95a
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-floatp.s
|
|
|
+@@ -0,0 +1,157 @@
|
|
|
++# Vector Single-Width Floating-Point Add/Subtract Instructions
|
|
|
++
|
|
|
++ vfadd.vv v4, v4, v8 # OK
|
|
|
++ vfadd.vv v8, v4, v8 # OK
|
|
|
++ vfadd.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfadd.vf v4, v4, fa1 # OK
|
|
|
++ vfadd.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfsub.vv v4, v4, v8
|
|
|
++ vfsub.vv v8, v4, v8
|
|
|
++ vfsub.vv v0, v4, v8, v0.t
|
|
|
++ vfsub.vf v4, v4, fa1
|
|
|
++ vfsub.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++ vfrsub.vf v4, v4, fa1 # OK
|
|
|
++ vfrsub.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Single-Width Floating-Point Multiply/Divide Instructions
|
|
|
++
|
|
|
++ vfmul.vv v4, v4, v8 # OK
|
|
|
++ vfmul.vv v8, v4, v8 # OK
|
|
|
++ vfmul.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfmul.vf v4, v4, fa1 # OK
|
|
|
++ vfmul.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfdiv.vv v4, v4, v8
|
|
|
++ vfdiv.vv v8, v4, v8
|
|
|
++ vfdiv.vv v0, v4, v8, v0.t
|
|
|
++ vfdiv.vf v4, v4, fa1
|
|
|
++ vfdiv.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++ vfrdiv.vf v4, v4, fa1 # OK
|
|
|
++ vfrdiv.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
|
|
|
++
|
|
|
++ vfmacc.vv v4, v4, v8 # OK
|
|
|
++ vfmacc.vv v8, v4, v8 # OK
|
|
|
++ vfmacc.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfmacc.vf v4, fa1, v4 # OK
|
|
|
++ vfmacc.vf v0, fa1, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfnmacc.vv v4, v4, v8
|
|
|
++ vfnmacc.vv v8, v4, v8
|
|
|
++ vfnmacc.vv v0, v4, v8, v0.t
|
|
|
++ vfnmacc.vf v4, fa1, v4
|
|
|
++ vfnmacc.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfmsac.vv v4, v4, v8
|
|
|
++ vfmsac.vv v8, v4, v8
|
|
|
++ vfmsac.vv v0, v4, v8, v0.t
|
|
|
++ vfmsac.vf v4, fa1, v4
|
|
|
++ vfmsac.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfnmsac.vv v4, v4, v8
|
|
|
++ vfnmsac.vv v8, v4, v8
|
|
|
++ vfnmsac.vv v0, v4, v8, v0.t
|
|
|
++ vfnmsac.vf v4, fa1, v4
|
|
|
++ vfnmsac.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfmadd.vv v4, v4, v8
|
|
|
++ vfmadd.vv v8, v4, v8
|
|
|
++ vfmadd.vv v0, v4, v8, v0.t
|
|
|
++ vfmadd.vf v4, fa1, v4
|
|
|
++ vfmadd.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfnmadd.vv v4, v4, v8
|
|
|
++ vfnmadd.vv v8, v4, v8
|
|
|
++ vfnmadd.vv v0, v4, v8, v0.t
|
|
|
++ vfnmadd.vf v4, fa1, v4
|
|
|
++ vfnmadd.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfmsub.vv v4, v4, v8
|
|
|
++ vfmsub.vv v8, v4, v8
|
|
|
++ vfmsub.vv v0, v4, v8, v0.t
|
|
|
++ vfmsub.vf v4, fa1, v4
|
|
|
++ vfmsub.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++ vfnmsub.vv v4, v4, v8
|
|
|
++ vfnmsub.vv v8, v4, v8
|
|
|
++ vfnmsub.vv v0, v4, v8, v0.t
|
|
|
++ vfnmsub.vf v4, fa1, v4
|
|
|
++ vfnmsub.vf v0, fa1, v4, v0.t
|
|
|
++
|
|
|
++# Vector Floating-Point Square-Root Instruction
|
|
|
++
|
|
|
++ vfsqrt.v v4, v4 # OK
|
|
|
++ vfsqrt.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Floating-Point Reciprocal Estimate Instruction
|
|
|
++
|
|
|
++ vfrece7.v v4, v4 # OK
|
|
|
++ vfrece7.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
|
|
|
++
|
|
|
++ vfrsqrte7.v v4, v4 # OK
|
|
|
++ vfrsqrte7.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Floating-Point Classify Instruction
|
|
|
++
|
|
|
++ vfclass.v v4, v4 # OK
|
|
|
++ vfclass.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Floating-Point MIN/MAX Instructions
|
|
|
++
|
|
|
++ vfmin.vv v4, v4, v8 # OK
|
|
|
++ vfmin.vv v8, v4, v8 # OK
|
|
|
++ vfmin.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfmin.vf v4, v4, fa1 # OK
|
|
|
++ vfmin.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfmax.vv v4, v4, v8
|
|
|
++ vfmax.vv v8, v4, v8
|
|
|
++ vfmax.vv v0, v4, v8, v0.t
|
|
|
++ vfmax.vf v4, v4, fa1
|
|
|
++ vfmax.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++# Vector Floating-Point Sign-Injection Instructions
|
|
|
++
|
|
|
++ vfneg.v v4, v4 # OK
|
|
|
++ vfneg.v v0, v4, v0.t # vd overlap vm
|
|
|
++ vfabs.v v4, v4 # OK
|
|
|
++ vfabs.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfsgnj.vv v4, v4, v8 # OK
|
|
|
++ vfsgnj.vv v8, v4, v8 # OK
|
|
|
++ vfsgnj.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vfsgnj.vf v4, v4, fa1 # OK
|
|
|
++ vfsgnj.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfsgnjn.vv v4, v4, v8
|
|
|
++ vfsgnjn.vv v8, v4, v8
|
|
|
++ vfsgnjn.vv v0, v4, v8, v0.t
|
|
|
++ vfsgnjn.vf v4, v4, fa1
|
|
|
++ vfsgnjn.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++ vfsgnjx.vv v4, v4, v8
|
|
|
++ vfsgnjx.vv v8, v4, v8
|
|
|
++ vfsgnjx.vv v0, v4, v8, v0.t
|
|
|
++ vfsgnjx.vf v4, v4, fa1
|
|
|
++ vfsgnjx.vf v0, v4, fa1, v0.t
|
|
|
++
|
|
|
++# Single-Width Floating-Point/Integer Type-Convert Instructions
|
|
|
++
|
|
|
++ vfcvt.xu.f.v v4, v4 # OK
|
|
|
++ vfcvt.xu.f.v v0, v4, v0.t # vd overlap vm
|
|
|
++ vfcvt.x.f.v v4, v4
|
|
|
++ vfcvt.x.f.v v0, v4, v0.t
|
|
|
++ vfcvt.rtz.xu.f.v v4, v4
|
|
|
++ vfcvt.rtz.xu.f.v v0, v4, v0.t
|
|
|
++ vfcvt.rtz.x.f.v v4, v4
|
|
|
++ vfcvt.rtz.x.f.v v0, v4, v0.t
|
|
|
++ vfcvt.f.xu.v v4, v4
|
|
|
++ vfcvt.f.xu.v v0, v4, v0.t
|
|
|
++ vfcvt.f.x.v v4, v4
|
|
|
++ vfcvt.f.x.v v0, v4, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..e26778a4e6
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-arith-int.s
|
|
|
++#error_output: vector-insns-fail-arith-int.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..e42096c1c4
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.l
|
|
|
+@@ -0,0 +1,71 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vneg.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vadd.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vadd.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsub.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrsub.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrsub.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vzext.vf2 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vsext.vf2 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vzext.vf4 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vsext.vf4 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vzext.vf8 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vsext.vf8 v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vadc.vvm v0,v4,v8,v0'
|
|
|
++.*Error: illegal operands `vadc.vxm v0,v4,a1,v0'
|
|
|
++.*Error: illegal operands `vadc.vim v0,v4,15,v0'
|
|
|
++.*Error: illegal operands `vsbc.vvm v0,v4,v8,v0'
|
|
|
++.*Error: illegal operands `vsbc.vxm v0,v4,a1,v0'
|
|
|
++.*Error: illegal operands `vnot.v v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vand.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vand.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vand.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vor.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vor.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vor.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vxor.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vxor.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vxor.vi v0,v4,15,v0.t'
|
|
|
++.*Error: illegal operands `vsll.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsll.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vsll.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vsrl.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsrl.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vsrl.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vsra.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vsra.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vsra.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vminu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vminu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmin.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmin.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmaxu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmaxu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmax.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmax.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmul.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmul.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmulh.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmulh.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmulhu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmulhu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmulhsu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmulhsu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vdivu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vdivu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vdiv.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vdiv.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vremu.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vremu.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrem.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vrem.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vmacc.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmacc.vx v0,a1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnmsac.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vnmsac.vx v0,a1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vmadd.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vmadd.vx v0,a1,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnmsub.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vnmsub.vx v0,a1,v4,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..6ce4e420c7
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-int.s
|
|
|
+@@ -0,0 +1,213 @@
|
|
|
++# Vector Single-Width Integer Add and Subtract
|
|
|
++
|
|
|
++ vneg.v v4, v4 # OK
|
|
|
++ vneg.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vadd.vv v4, v4, v8 # OK
|
|
|
++ vadd.vv v8, v4, v8 # OK
|
|
|
++ vadd.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vadd.vx v4, v4, a1 # OK
|
|
|
++ vadd.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vadd.vi v4, v4, 15 # OK
|
|
|
++ vadd.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vsub.vv v4, v4, v8 # OK
|
|
|
++ vsub.vv v8, v4, v8 # OK
|
|
|
++ vsub.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vsub.vx v4, v4, a1 # OK
|
|
|
++ vsub.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vrsub.vx v4, v4, a1 # OK
|
|
|
++ vrsub.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vrsub.vi v4, v4, 15 # OK
|
|
|
++ vrsub.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Integer Extension
|
|
|
++
|
|
|
++ vzext.vf2 v4, v4 # OK
|
|
|
++ vzext.vf2 v0, v4, v0.t # vd overlap vm
|
|
|
++ vsext.vf2 v4, v4
|
|
|
++ vsext.vf2 v0, v4, v0.t
|
|
|
++ vzext.vf4 v4, v4
|
|
|
++ vzext.vf4 v0, v4, v0.t
|
|
|
++ vsext.vf4 v4, v4
|
|
|
++ vsext.vf4 v0, v4, v0.t
|
|
|
++ vzext.vf8 v4, v4
|
|
|
++ vzext.vf8 v0, v4, v0.t
|
|
|
++ vsext.vf8 v4, v4
|
|
|
++ vsext.vf8 v0, v4, v0.t
|
|
|
++
|
|
|
++# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
|
|
|
++
|
|
|
++ vadc.vvm v4, v4, v8, v0 # OK
|
|
|
++ vadc.vvm v8, v4, v8, v0 # OK
|
|
|
++ vadc.vvm v0, v4, v8, v0 # vd overlap vm
|
|
|
++ vadc.vxm v4, v4, a1, v0 # OK
|
|
|
++ vadc.vxm v0, v4, a1, v0 # vd overlap vm
|
|
|
++ vadc.vim v4, v4, 15, v0 # OK
|
|
|
++ vadc.vim v0, v4, 15, v0 # vd overlap vm
|
|
|
++
|
|
|
++ vsbc.vvm v4, v4, v8, v0 # OK
|
|
|
++ vsbc.vvm v8, v4, v8, v0 # OK
|
|
|
++ vsbc.vvm v0, v4, v8, v0 # vd overlap vm
|
|
|
++ vsbc.vxm v4, v4, a1, v0 # OK
|
|
|
++ vsbc.vxm v0, v4, a1, v0 # vd overlap vm
|
|
|
++
|
|
|
++# Vector Bitwise Logical Instructions
|
|
|
++
|
|
|
++ vnot.v v4, v4 # OK
|
|
|
++ vnot.v v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vand.vv v4, v4, v8 # OK
|
|
|
++ vand.vv v8, v4, v8 # OK
|
|
|
++ vand.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vand.vx v4, v4, a1 # OK
|
|
|
++ vand.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vand.vi v4, v4, 15 # OK
|
|
|
++ vand.vi v0, v4, 15, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vor.vv v4, v4, v8
|
|
|
++ vor.vv v8, v4, v8
|
|
|
++ vor.vv v0, v4, v8, v0.t
|
|
|
++ vor.vx v4, v4, a1
|
|
|
++ vor.vx v0, v4, a1, v0.t
|
|
|
++ vor.vi v4, v4, 15
|
|
|
++ vor.vi v0, v4, 15, v0.t
|
|
|
++
|
|
|
++ vxor.vv v4, v4, v8
|
|
|
++ vxor.vv v8, v4, v8
|
|
|
++ vxor.vv v0, v4, v8, v0.t
|
|
|
++ vxor.vx v4, v4, a1
|
|
|
++ vxor.vx v0, v4, a1, v0.t
|
|
|
++ vxor.vi v4, v4, 15
|
|
|
++ vxor.vi v0, v4, 15, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Bit Shift Instructions
|
|
|
++
|
|
|
++ vsll.vv v4, v4, v8 # OK
|
|
|
++ vsll.vv v8, v4, v8 # OK
|
|
|
++ vsll.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vsll.vx v4, v4, a1 # OK
|
|
|
++ vsll.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vsll.vi v4, v4, 31 # OK
|
|
|
++ vsll.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vsrl.vv v4, v4, v8
|
|
|
++ vsrl.vv v8, v4, v8
|
|
|
++ vsrl.vv v0, v4, v8, v0.t
|
|
|
++ vsrl.vx v4, v4, a1
|
|
|
++ vsrl.vx v0, v4, a1, v0.t
|
|
|
++ vsrl.vi v4, v4, 31
|
|
|
++ vsrl.vi v0, v4, 31, v0.t
|
|
|
++
|
|
|
++ vsra.vv v4, v4, v8
|
|
|
++ vsra.vv v8, v4, v8
|
|
|
++ vsra.vv v0, v4, v8, v0.t
|
|
|
++ vsra.vx v4, v4, a1
|
|
|
++ vsra.vx v0, v4, a1, v0.t
|
|
|
++ vsra.vi v4, v4, 31
|
|
|
++ vsra.vi v0, v4, 31, v0.t
|
|
|
++
|
|
|
++# Vector Integer Min/Max Instructions
|
|
|
++
|
|
|
++ vminu.vv v4, v4, v8 # OK
|
|
|
++ vminu.vv v8, v4, v8 # OK
|
|
|
++ vminu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vminu.vx v4, v4, a1 # OK
|
|
|
++ vminu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vmin.vv v4, v4, v8
|
|
|
++ vmin.vv v8, v4, v8
|
|
|
++ vmin.vv v0, v4, v8, v0.t
|
|
|
++ vmin.vx v4, v4, a1
|
|
|
++ vmin.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmaxu.vv v4, v4, v8
|
|
|
++ vmaxu.vv v8, v4, v8
|
|
|
++ vmaxu.vv v0, v4, v8, v0.t
|
|
|
++ vmaxu.vx v4, v4, a1
|
|
|
++ vmaxu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmax.vv v4, v4, v8
|
|
|
++ vmax.vv v8, v4, v8
|
|
|
++ vmax.vv v0, v4, v8, v0.t
|
|
|
++ vmax.vx v4, v4, a1
|
|
|
++ vmax.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Integer Multiply Instructions
|
|
|
++
|
|
|
++ vmul.vv v4, v4, v8 # OK
|
|
|
++ vmul.vv v8, v4, v8 # OK
|
|
|
++ vmul.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vmul.vx v4, v4, a1 # OK
|
|
|
++ vmul.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vmulh.vv v4, v4, v8
|
|
|
++ vmulh.vv v8, v4, v8
|
|
|
++ vmulh.vv v0, v4, v8, v0.t
|
|
|
++ vmulh.vx v4, v4, a1
|
|
|
++ vmulh.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmulhu.vv v4, v4, v8
|
|
|
++ vmulhu.vv v8, v4, v8
|
|
|
++ vmulhu.vv v0, v4, v8, v0.t
|
|
|
++ vmulhu.vx v4, v4, a1
|
|
|
++ vmulhu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vmulhsu.vv v4, v4, v8
|
|
|
++ vmulhsu.vv v8, v4, v8
|
|
|
++ vmulhsu.vv v0, v4, v8, v0.t
|
|
|
++ vmulhsu.vx v4, v4, a1
|
|
|
++ vmulhsu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Integer Divide Instructions
|
|
|
++
|
|
|
++ vdivu.vv v4, v4, v8 # OK
|
|
|
++ vdivu.vv v8, v4, v8 # OK
|
|
|
++ vdivu.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vdivu.vx v4, v4, a1 # OK
|
|
|
++ vdivu.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vdiv.vv v4, v4, v8
|
|
|
++ vdiv.vv v8, v4, v8
|
|
|
++ vdiv.vv v0, v4, v8, v0.t
|
|
|
++ vdiv.vx v4, v4, a1
|
|
|
++ vdiv.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vremu.vv v4, v4, v8
|
|
|
++ vremu.vv v8, v4, v8
|
|
|
++ vremu.vv v0, v4, v8, v0.t
|
|
|
++ vremu.vx v4, v4, a1
|
|
|
++ vremu.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++ vrem.vv v4, v4, v8
|
|
|
++ vrem.vv v8, v4, v8
|
|
|
++ vrem.vv v0, v4, v8, v0.t
|
|
|
++ vrem.vx v4, v4, a1
|
|
|
++ vrem.vx v0, v4, a1, v0.t
|
|
|
++
|
|
|
++# Vector Single-Width Integer Multiply-Add Instructions
|
|
|
++
|
|
|
++ vmacc.vv v4, v4, v8 # OK
|
|
|
++ vmacc.vv v8, v4, v8 # OK
|
|
|
++ vmacc.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vmacc.vx v4, a1, v4 # OK
|
|
|
++ vmacc.vx v0, a1, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vnmsac.vv v4, v4, v8
|
|
|
++ vnmsac.vv v8, v4, v8
|
|
|
++ vnmsac.vv v0, v4, v8, v0.t
|
|
|
++ vnmsac.vx v4, a1, v4
|
|
|
++ vnmsac.vx v0, a1, v4, v0.t
|
|
|
++
|
|
|
++ vmadd.vv v4, v4, v8
|
|
|
++ vmadd.vv v8, v4, v8
|
|
|
++ vmadd.vv v0, v4, v8, v0.t
|
|
|
++ vmadd.vx v4, a1, v4
|
|
|
++ vmadd.vx v0, a1, v4, v0.t
|
|
|
++
|
|
|
++ vnmsub.vv v4, v4, v8
|
|
|
++ vnmsub.vv v8, v4, v8
|
|
|
++ vnmsub.vv v0, v4, v8, v0.t
|
|
|
++ vnmsub.vx v4, a1, v4
|
|
|
++ vnmsub.vx v0, a1, v4, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..5d38168a0b
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32ifv0p10
|
|
|
++#source: vector-insns-fail-arith-narrow.s
|
|
|
++#error_output: vector-insns-fail-arith-narrow.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..4bba63a6cd
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.l
|
|
|
+@@ -0,0 +1,85 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vncvt.x.x.w v2,v2'
|
|
|
++.*Error: illegal operands `vncvt.x.x.w v2,v3'
|
|
|
++.*Error: illegal operands `vncvt.x.x.w v3,v2'
|
|
|
++.*Error: illegal operands `vncvt.x.x.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vnsrl.wv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vnsrl.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vnsrl.wv v3,v2,v4'
|
|
|
++.*Error: illegal operands `vnsrl.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnsrl.wx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vnsrl.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vnsrl.wx v3,v2,a1'
|
|
|
++.*Error: illegal operands `vnsrl.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vnsrl.wi v2,v2,31'
|
|
|
++.*Error: illegal operands `vnsrl.wi v2,v3,31'
|
|
|
++.*Error: illegal operands `vnsrl.wi v3,v2,31'
|
|
|
++.*Error: illegal operands `vnsrl.wi v0,v2,31,v0.t'
|
|
|
++.*Error: illegal operands `vnsra.wv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vnsra.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vnsra.wv v3,v2,v4'
|
|
|
++.*Error: illegal operands `vnsra.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnsra.wx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vnsra.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vnsra.wx v3,v2,a1'
|
|
|
++.*Error: illegal operands `vnsra.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vnsra.wi v2,v2,31'
|
|
|
++.*Error: illegal operands `vnsra.wi v2,v3,31'
|
|
|
++.*Error: illegal operands `vnsra.wi v3,v2,31'
|
|
|
++.*Error: illegal operands `vnsra.wi v0,v2,31,v0.t'
|
|
|
++.*Error: illegal operands `vnclipu.wv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vnclipu.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vnclipu.wv v3,v2,v4'
|
|
|
++.*Error: illegal operands `vnclipu.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnclipu.wx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vnclipu.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vnclipu.wx v3,v2,a1'
|
|
|
++.*Error: illegal operands `vnclipu.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vnclipu.wi v2,v2,31'
|
|
|
++.*Error: illegal operands `vnclipu.wi v2,v3,31'
|
|
|
++.*Error: illegal operands `vnclipu.wi v3,v2,31'
|
|
|
++.*Error: illegal operands `vnclipu.wi v0,v2,31,v0.t'
|
|
|
++.*Error: illegal operands `vnclip.wv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vnclip.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vnclip.wv v3,v2,v4'
|
|
|
++.*Error: illegal operands `vnclip.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vnclip.wx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vnclip.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vnclip.wx v3,v2,a1'
|
|
|
++.*Error: illegal operands `vnclip.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vnclip.wi v2,v2,31'
|
|
|
++.*Error: illegal operands `vnclip.wi v2,v3,31'
|
|
|
++.*Error: illegal operands `vnclip.wi v3,v2,31'
|
|
|
++.*Error: illegal operands `vnclip.wi v0,v2,31,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.xu.f.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.xu.f.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.xu.f.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.xu.f.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.x.f.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.x.f.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.x.f.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.x.f.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.xu.f.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.x.f.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.x.f.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.rtz.x.f.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.f.xu.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.f.xu.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.f.xu.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.f.xu.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.f.x.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.f.x.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.f.x.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.f.x.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.f.f.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.f.f.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.f.f.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.f.f.w v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfncvt.rod.f.f.w v2,v2'
|
|
|
++.*Error: illegal operands `vfncvt.rod.f.f.w v2,v3'
|
|
|
++.*Error: illegal operands `vfncvt.rod.f.f.w v3,v2'
|
|
|
++.*Error: illegal operands `vfncvt.rod.f.f.w v0,v2,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..73b96ef800
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-narrow.s
|
|
|
+@@ -0,0 +1,100 @@
|
|
|
++# Vector Narrowing Integer Right Shift Instructions
|
|
|
++
|
|
|
++ # vncvt.x.x.w vd,vs,vm = vnsrl.wx vd,vs,x0,vm
|
|
|
++ vncvt.x.x.w v2, v2 # vd overlap vs2
|
|
|
++ vncvt.x.x.w v2, v3 # vs2 should be multiple of 2
|
|
|
++ vncvt.x.x.w v3, v2 # vd overlap vs2
|
|
|
++ vncvt.x.x.w v0, v2, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vnsrl.wv v2, v2, v4 # vd overlap vs2
|
|
|
++ vnsrl.wv v2, v3, v4 # vs2 should be multiple of 2
|
|
|
++ vnsrl.wv v3, v2, v4 # vd overlap vs2
|
|
|
++ vnsrl.wv v4, v2, v4 # OK
|
|
|
++ vnsrl.wv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vnsrl.wx v2, v2, a1 # vd overlap vs2
|
|
|
++ vnsrl.wx v2, v3, a1 # vs2 should be multiple of 2
|
|
|
++ vnsrl.wx v3, v2, a1 # vd overlap vs2
|
|
|
++ vnsrl.wx v0, v2, a1, v0.t # vd overlap vm
|
|
|
++ vnsrl.wi v2, v2, 31 # vd overlap vs2
|
|
|
++ vnsrl.wi v2, v3, 31 # vs2 should be multiple of 2
|
|
|
++ vnsrl.wi v3, v2, 31 # vd overlap vs2
|
|
|
++ vnsrl.wi v0, v2, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vnsra.wv v2, v2, v4
|
|
|
++ vnsra.wv v2, v3, v4
|
|
|
++ vnsra.wv v3, v2, v4
|
|
|
++ vnsra.wv v4, v2, v4
|
|
|
++ vnsra.wv v0, v2, v4, v0.t
|
|
|
++ vnsra.wx v2, v2, a1
|
|
|
++ vnsra.wx v2, v3, a1
|
|
|
++ vnsra.wx v3, v2, a1
|
|
|
++ vnsra.wx v0, v2, a1, v0.t
|
|
|
++ vnsra.wi v2, v2, 31
|
|
|
++ vnsra.wi v2, v3, 31
|
|
|
++ vnsra.wi v3, v2, 31
|
|
|
++ vnsra.wi v0, v2, 31, v0.t
|
|
|
++
|
|
|
++# Vector Narrowing Fixed-Point Clip Instructions
|
|
|
++
|
|
|
++ vnclipu.wv v2, v2, v4 # vd overlap vs2
|
|
|
++ vnclipu.wv v2, v3, v4 # vs2 should be multiple of 2
|
|
|
++ vnclipu.wv v3, v2, v4 # vd overlap vs2
|
|
|
++ vnclipu.wv v4, v2, v4 # OK
|
|
|
++ vnclipu.wv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vnclipu.wx v2, v2, a1 # vd overlap vs2
|
|
|
++ vnclipu.wx v2, v3, a1 # vs2 should be multiple of 2
|
|
|
++ vnclipu.wx v3, v2, a1 # vd overlap vs2
|
|
|
++ vnclipu.wx v0, v2, a1, v0.t # vd overlap vm
|
|
|
++ vnclipu.wi v2, v2, 31 # vd overlap vs2
|
|
|
++ vnclipu.wi v2, v3, 31 # vs2 should be multiple of 2
|
|
|
++ vnclipu.wi v3, v2, 31 # vd overlap vs2
|
|
|
++ vnclipu.wi v0, v2, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vnclip.wv v2, v2, v4
|
|
|
++ vnclip.wv v2, v3, v4
|
|
|
++ vnclip.wv v3, v2, v4
|
|
|
++ vnclip.wv v4, v2, v4
|
|
|
++ vnclip.wv v0, v2, v4, v0.t
|
|
|
++ vnclip.wx v2, v2, a1
|
|
|
++ vnclip.wx v2, v3, a1
|
|
|
++ vnclip.wx v3, v2, a1
|
|
|
++ vnclip.wx v0, v2, a1, v0.t
|
|
|
++ vnclip.wi v2, v2, 31
|
|
|
++ vnclip.wi v2, v3, 31
|
|
|
++ vnclip.wi v3, v2, 31
|
|
|
++ vnclip.wi v0, v2, 31, v0.t
|
|
|
++
|
|
|
++# Narrowing Floating-Point/Integer Type-Convert Instructions
|
|
|
++
|
|
|
++ vfncvt.xu.f.w v2, v2 # vd overlap vs2
|
|
|
++ vfncvt.xu.f.w v2, v3 # vs2 should be multiple of 2
|
|
|
++ vfncvt.xu.f.w v3, v2 # vd overlap vs2
|
|
|
++ vfncvt.xu.f.w v0, v2, v0.t # vd overlap vm
|
|
|
++ vfncvt.x.f.w v2, v2
|
|
|
++ vfncvt.x.f.w v2, v3
|
|
|
++ vfncvt.x.f.w v3, v2
|
|
|
++ vfncvt.x.f.w v0, v2, v0.t
|
|
|
++ vfncvt.rtz.xu.f.w v2, v2
|
|
|
++ vfncvt.rtz.xu.f.w v2, v3
|
|
|
++ vfncvt.rtz.xu.f.w v3, v2
|
|
|
++ vfncvt.rtz.xu.f.w v0, v2, v0.t
|
|
|
++ vfncvt.rtz.x.f.w v2, v2
|
|
|
++ vfncvt.rtz.x.f.w v2, v3
|
|
|
++ vfncvt.rtz.x.f.w v3, v2
|
|
|
++ vfncvt.rtz.x.f.w v0, v2, v0.t
|
|
|
++ vfncvt.f.xu.w v2, v2
|
|
|
++ vfncvt.f.xu.w v2, v3
|
|
|
++ vfncvt.f.xu.w v3, v2
|
|
|
++ vfncvt.f.xu.w v0, v2, v0.t
|
|
|
++ vfncvt.f.x.w v2, v2
|
|
|
++ vfncvt.f.x.w v2, v3
|
|
|
++ vfncvt.f.x.w v3, v2
|
|
|
++ vfncvt.f.x.w v0, v2, v0.t
|
|
|
++ vfncvt.f.f.w v2, v2
|
|
|
++ vfncvt.f.f.w v2, v3
|
|
|
++ vfncvt.f.f.w v3, v2
|
|
|
++ vfncvt.f.f.w v0, v2, v0.t
|
|
|
++ vfncvt.rod.f.f.w v2, v2
|
|
|
++ vfncvt.rod.f.f.w v2, v3
|
|
|
++ vfncvt.rod.f.f.w v3, v2
|
|
|
++ vfncvt.rod.f.f.w v0, v2, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..b3a61bbbb3
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32ifv0p10
|
|
|
++#source: vector-insns-fail-arith-widen.s
|
|
|
++#error_output: vector-insns-fail-arith-widen.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..5684601697
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.l
|
|
|
+@@ -0,0 +1,253 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vwcvtu.x.x.v v1,v2'
|
|
|
++.*Error: illegal operands `vwcvtu.x.x.v v2,v2'
|
|
|
++.*Error: illegal operands `vwcvtu.x.x.v v2,v3'
|
|
|
++.*Error: illegal operands `vwcvtu.x.x.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vwcvt.x.x.v v1,v2'
|
|
|
++.*Error: illegal operands `vwcvt.x.x.v v2,v2'
|
|
|
++.*Error: illegal operands `vwcvt.x.x.v v2,v3'
|
|
|
++.*Error: illegal operands `vwcvt.x.x.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vwaddu.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwaddu.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwaddu.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwaddu.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwaddu.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwaddu.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwaddu.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwaddu.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwaddu.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwaddu.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwaddu.wv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwaddu.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwaddu.wv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwaddu.wv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwaddu.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwaddu.wx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwaddu.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwaddu.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwsubu.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwsubu.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwsubu.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwsubu.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwsubu.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwsubu.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwsubu.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwsubu.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwsubu.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwsubu.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwsubu.wv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwsubu.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwsubu.wv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwsubu.wv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwsubu.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwsubu.wx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwsubu.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwsubu.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwadd.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwadd.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwadd.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwadd.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwadd.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwadd.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwadd.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwadd.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwadd.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwadd.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwadd.wv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwadd.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwadd.wv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwadd.wv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwadd.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwadd.wx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwadd.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwadd.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwsub.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwsub.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwsub.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwsub.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwsub.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwsub.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwsub.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwsub.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwsub.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwsub.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwsub.wv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwsub.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwsub.wv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwsub.wv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwsub.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwsub.wx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwsub.wx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwsub.wx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwmul.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwmul.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwmul.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwmul.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwmul.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwmul.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwmul.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwmul.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwmul.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwmul.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwmulu.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwmulu.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwmulu.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwmulu.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwmulu.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwmulu.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwmulu.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwmulu.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwmulu.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwmulu.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwmulsu.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwmulsu.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwmulsu.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwmulsu.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwmulsu.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwmulsu.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwmulsu.vx v1,v2,a1'
|
|
|
++.*Error: illegal operands `vwmulsu.vx v2,v2,a1'
|
|
|
++.*Error: illegal operands `vwmulsu.vx v2,v3,a1'
|
|
|
++.*Error: illegal operands `vwmulsu.vx v0,v2,a1,v0.t'
|
|
|
++.*Error: illegal operands `vwmaccu.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwmaccu.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwmaccu.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwmaccu.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwmaccu.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwmaccu.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwmaccu.vx v1,a1,v2'
|
|
|
++.*Error: illegal operands `vwmaccu.vx v2,a1,v2'
|
|
|
++.*Error: illegal operands `vwmaccu.vx v2,a1,v3'
|
|
|
++.*Error: illegal operands `vwmaccu.vx v0,a1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vwmacc.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwmacc.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwmacc.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwmacc.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwmacc.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwmacc.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwmacc.vx v1,a1,v2'
|
|
|
++.*Error: illegal operands `vwmacc.vx v2,a1,v2'
|
|
|
++.*Error: illegal operands `vwmacc.vx v2,a1,v3'
|
|
|
++.*Error: illegal operands `vwmacc.vx v0,a1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vwmaccsu.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vwmaccsu.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vwmaccsu.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vwmaccsu.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vwmaccsu.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vwmaccsu.vx v1,a1,v2'
|
|
|
++.*Error: illegal operands `vwmaccsu.vx v2,a1,v2'
|
|
|
++.*Error: illegal operands `vwmaccsu.vx v2,a1,v3'
|
|
|
++.*Error: illegal operands `vwmaccsu.vx v0,a1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vwmaccus.vx v1,a1,v2'
|
|
|
++.*Error: illegal operands `vwmaccus.vx v2,a1,v2'
|
|
|
++.*Error: illegal operands `vwmaccus.vx v2,a1,v3'
|
|
|
++.*Error: illegal operands `vwmaccus.vx v0,a1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwadd.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwadd.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwadd.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwadd.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwadd.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwadd.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwadd.vf v1,v2,fa1'
|
|
|
++.*Error: illegal operands `vfwadd.vf v2,v2,fa1'
|
|
|
++.*Error: illegal operands `vfwadd.vf v2,v3,fa1'
|
|
|
++.*Error: illegal operands `vfwadd.vf v0,v2,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfwadd.wv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwadd.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwadd.wv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwadd.wv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwadd.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwsub.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwsub.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwsub.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwsub.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwsub.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwsub.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
|
|
|
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
|
|
|
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
|
|
|
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfwsub.wv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwsub.wv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwsub.wv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwsub.wv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwsub.wv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwmul.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmul.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmul.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwmul.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmul.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwmul.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwsub.vf v1,v2,fa1'
|
|
|
++.*Error: illegal operands `vfwsub.vf v2,v2,fa1'
|
|
|
++.*Error: illegal operands `vfwsub.vf v2,v3,fa1'
|
|
|
++.*Error: illegal operands `vfwsub.vf v0,v2,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vfwmacc.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmacc.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmacc.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwmacc.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmacc.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwmacc.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwmacc.vf v1,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwmacc.vf v2,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwmacc.vf v2,fa1,v3'
|
|
|
++.*Error: illegal operands `vfwmacc.vf v0,fa1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwnmacc.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwnmacc.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwnmacc.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwnmacc.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwnmacc.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwnmacc.vf v1,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwnmacc.vf v2,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwnmacc.vf v2,fa1,v3'
|
|
|
++.*Error: illegal operands `vfwnmacc.vf v0,fa1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwmsac.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmsac.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmsac.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwmsac.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwmsac.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwmsac.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwmsac.vf v1,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwmsac.vf v2,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwmsac.vf v2,fa1,v3'
|
|
|
++.*Error: illegal operands `vfwmsac.vf v0,fa1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwnmsac.vv v1,v2,v4'
|
|
|
++.*Error: illegal operands `vfwnmsac.vv v2,v2,v4'
|
|
|
++.*Error: illegal operands `vfwnmsac.vv v2,v3,v4'
|
|
|
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v4'
|
|
|
++.*Error: illegal operands `vfwnmsac.vv v4,v2,v5'
|
|
|
++.*Error: illegal operands `vfwnmsac.vv v0,v2,v4,v0.t'
|
|
|
++.*Error: illegal operands `vfwnmsac.vf v1,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwnmsac.vf v2,fa1,v2'
|
|
|
++.*Error: illegal operands `vfwnmsac.vf v2,fa1,v3'
|
|
|
++.*Error: illegal operands `vfwnmsac.vf v0,fa1,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.xu.f.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.xu.f.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.xu.f.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.x.f.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.x.f.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.x.f.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.x.f.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.rtz.x.f.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.f.xu.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.f.xu.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.f.xu.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.f.x.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.f.x.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.f.x.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.f.x.v v0,v2,v0.t'
|
|
|
++.*Error: illegal operands `vfwcvt.f.f.v v1,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.f.f.v v2,v2'
|
|
|
++.*Error: illegal operands `vfwcvt.f.f.v v2,v3'
|
|
|
++.*Error: illegal operands `vfwcvt.f.f.v v0,v2,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..addedd4dc2
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-arith-widen.s
|
|
|
+@@ -0,0 +1,297 @@
|
|
|
++# Vector Widening Integer Add/Subtract
|
|
|
++
|
|
|
++ # vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
|
|
|
++ vwcvtu.x.x.v v1, v2 # vd should be multiple of 2
|
|
|
++ vwcvtu.x.x.v v2, v2 # vd overlap vs2
|
|
|
++ vwcvtu.x.x.v v2, v3 # vd overlap vs2
|
|
|
++ vwcvtu.x.x.v v0, v2, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ # vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
|
|
|
++ vwcvt.x.x.v v1, v2
|
|
|
++ vwcvt.x.x.v v2, v2
|
|
|
++ vwcvt.x.x.v v2, v3
|
|
|
++ vwcvt.x.x.v v0, v2, v0.t
|
|
|
++
|
|
|
++ vwaddu.vv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vwaddu.vv v2, v2, v4 # vd overlap vs2
|
|
|
++ vwaddu.vv v2, v3, v4 # vd overlap vs2
|
|
|
++ vwaddu.vv v4, v2, v4 # vd overlap vs1
|
|
|
++ vwaddu.vv v4, v2, v5 # vd overlap vs1
|
|
|
++ vwaddu.vv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vwaddu.vx v1, v2, a1 # vd should be multiple of 2
|
|
|
++ vwaddu.vx v2, v2, a1 # vd overlap vs2
|
|
|
++ vwaddu.vx v2, v3, a1 # vd overlap vs2
|
|
|
++ vwaddu.vx v0, v2, a1, v0.t # vd overlap vm
|
|
|
++ vwaddu.wv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vwaddu.wv v2, v2, v4 # OK
|
|
|
++ vwaddu.wv v2, v3, v4 # vs2 should be multiple of 2
|
|
|
++ vwaddu.wv v4, v2, v4 # vd overlap vs1
|
|
|
++ vwaddu.wv v4, v2, v5 # vd overlap vs1
|
|
|
++ vwaddu.wv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vwaddu.wx v1, v2, a1 # vd should be multiple of 2
|
|
|
++ vwaddu.wx v2, v2, a1 # OK
|
|
|
++ vwaddu.wx v2, v3, a1 # vs2 should be multiple of 2
|
|
|
++ vwaddu.wx v0, v2, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vwsubu.vv v1, v2, v4
|
|
|
++ vwsubu.vv v2, v2, v4
|
|
|
++ vwsubu.vv v2, v3, v4
|
|
|
++ vwsubu.vv v4, v2, v4
|
|
|
++ vwsubu.vv v4, v2, v5
|
|
|
++ vwsubu.vv v0, v2, v4, v0.t
|
|
|
++ vwsubu.vx v1, v2, a1
|
|
|
++ vwsubu.vx v2, v2, a1
|
|
|
++ vwsubu.vx v2, v3, a1
|
|
|
++ vwsubu.vx v0, v2, a1, v0.t
|
|
|
++ vwsubu.wv v1, v2, v4
|
|
|
++ vwsubu.wv v2, v2, v4
|
|
|
++ vwsubu.wv v2, v3, v4
|
|
|
++ vwsubu.wv v4, v2, v4
|
|
|
++ vwsubu.wv v4, v2, v5
|
|
|
++ vwsubu.wv v0, v2, v4, v0.t
|
|
|
++ vwsubu.wx v1, v2, a1
|
|
|
++ vwsubu.wx v2, v2, a1
|
|
|
++ vwsubu.wx v2, v3, a1
|
|
|
++ vwsubu.wx v0, v2, a1, v0.t
|
|
|
++
|
|
|
++ vwadd.vv v1, v2, v4
|
|
|
++ vwadd.vv v2, v2, v4
|
|
|
++ vwadd.vv v2, v3, v4
|
|
|
++ vwadd.vv v4, v2, v4
|
|
|
++ vwadd.vv v4, v2, v5
|
|
|
++ vwadd.vv v0, v2, v4, v0.t
|
|
|
++ vwadd.vx v1, v2, a1
|
|
|
++ vwadd.vx v2, v2, a1
|
|
|
++ vwadd.vx v2, v3, a1
|
|
|
++ vwadd.vx v0, v2, a1, v0.t
|
|
|
++ vwadd.wv v1, v2, v4
|
|
|
++ vwadd.wv v2, v2, v4
|
|
|
++ vwadd.wv v2, v3, v4
|
|
|
++ vwadd.wv v4, v2, v4
|
|
|
++ vwadd.wv v4, v2, v5
|
|
|
++ vwadd.wv v0, v2, v4, v0.t
|
|
|
++ vwadd.wx v1, v2, a1
|
|
|
++ vwadd.wx v2, v2, a1
|
|
|
++ vwadd.wx v2, v3, a1
|
|
|
++ vwadd.wx v0, v2, a1, v0.t
|
|
|
++
|
|
|
++ vwsub.vv v1, v2, v4
|
|
|
++ vwsub.vv v2, v2, v4
|
|
|
++ vwsub.vv v2, v3, v4
|
|
|
++ vwsub.vv v4, v2, v4
|
|
|
++ vwsub.vv v4, v2, v5
|
|
|
++ vwsub.vv v0, v2, v4, v0.t
|
|
|
++ vwsub.vx v1, v2, a1
|
|
|
++ vwsub.vx v2, v2, a1
|
|
|
++ vwsub.vx v2, v3, a1
|
|
|
++ vwsub.vx v0, v2, a1, v0.t
|
|
|
++ vwsub.wv v1, v2, v4
|
|
|
++ vwsub.wv v2, v2, v4
|
|
|
++ vwsub.wv v2, v3, v4
|
|
|
++ vwsub.wv v4, v2, v4
|
|
|
++ vwsub.wv v4, v2, v5
|
|
|
++ vwsub.wv v0, v2, v4, v0.t
|
|
|
++ vwsub.wx v1, v2, a1
|
|
|
++ vwsub.wx v2, v2, a1
|
|
|
++ vwsub.wx v2, v3, a1
|
|
|
++ vwsub.wx v0, v2, a1, v0.t
|
|
|
++
|
|
|
++# Vector Widening Integer Multiply Instructions
|
|
|
++
|
|
|
++ vwmul.vv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vwmul.vv v2, v2, v4 # vd overlap vs2
|
|
|
++ vwmul.vv v2, v3, v4 # vd overlap vs2
|
|
|
++ vwmul.vv v4, v2, v4 # vd overlap vs1
|
|
|
++ vwmul.vv v4, v2, v5 # vd overlap vs1
|
|
|
++ vwmul.vv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vwmul.vx v1, v2, a1 # vd should be multiple of 2
|
|
|
++ vwmul.vx v2, v2, a1 # vd overlap vs2
|
|
|
++ vwmul.vx v2, v3, a1 # vd overlap vs2
|
|
|
++ vwmul.vx v0, v2, a1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vwmulu.vv v1, v2, v4
|
|
|
++ vwmulu.vv v2, v2, v4
|
|
|
++ vwmulu.vv v2, v3, v4
|
|
|
++ vwmulu.vv v4, v2, v4
|
|
|
++ vwmulu.vv v4, v2, v5
|
|
|
++ vwmulu.vv v0, v2, v4, v0.t
|
|
|
++ vwmulu.vx v1, v2, a1
|
|
|
++ vwmulu.vx v2, v2, a1
|
|
|
++ vwmulu.vx v2, v3, a1
|
|
|
++ vwmulu.vx v0, v2, a1, v0.t
|
|
|
++
|
|
|
++ vwmulsu.vv v1, v2, v4
|
|
|
++ vwmulsu.vv v2, v2, v4
|
|
|
++ vwmulsu.vv v2, v3, v4
|
|
|
++ vwmulsu.vv v4, v2, v4
|
|
|
++ vwmulsu.vv v4, v2, v5
|
|
|
++ vwmulsu.vv v0, v2, v4, v0.t
|
|
|
++ vwmulsu.vx v1, v2, a1
|
|
|
++ vwmulsu.vx v2, v2, a1
|
|
|
++ vwmulsu.vx v2, v3, a1
|
|
|
++ vwmulsu.vx v0, v2, a1, v0.t
|
|
|
++
|
|
|
++# Vector Widening Integer Multiply-Add Instructions
|
|
|
++
|
|
|
++ vwmaccu.vv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vwmaccu.vv v2, v2, v4 # vd overlap vs1
|
|
|
++ vwmaccu.vv v2, v3, v4 # vd overlap vs1
|
|
|
++ vwmaccu.vv v4, v2, v4 # vd overlap vs2
|
|
|
++ vwmaccu.vv v4, v2, v5 # vd overlap vs2
|
|
|
++ vwmaccu.vv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vwmaccu.vx v1, a1, v2 # vd should be multiple of 2
|
|
|
++ vwmaccu.vx v2, a1, v2 # vd overlap vs2
|
|
|
++ vwmaccu.vx v2, a1, v3 # vd overlap vs2
|
|
|
++ vwmaccu.vx v0, a1, v2, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vwmacc.vv v1, v2, v4
|
|
|
++ vwmacc.vv v2, v2, v4
|
|
|
++ vwmacc.vv v2, v3, v4
|
|
|
++ vwmacc.vv v4, v2, v4
|
|
|
++ vwmacc.vv v4, v2, v5
|
|
|
++ vwmacc.vv v0, v2, v4, v0.t
|
|
|
++ vwmacc.vx v1, a1, v2
|
|
|
++ vwmacc.vx v2, a1, v2
|
|
|
++ vwmacc.vx v2, a1, v3
|
|
|
++ vwmacc.vx v0, a1, v2, v0.t
|
|
|
++
|
|
|
++ vwmaccsu.vv v1, v2, v4
|
|
|
++ vwmaccsu.vv v2, v2, v4
|
|
|
++ vwmaccsu.vv v2, v3, v4
|
|
|
++ vwmaccsu.vv v4, v2, v4
|
|
|
++ vwmaccsu.vv v4, v2, v5
|
|
|
++ vwmaccsu.vv v0, v2, v4, v0.t
|
|
|
++ vwmaccsu.vx v1, a1, v2
|
|
|
++ vwmaccsu.vx v2, a1, v2
|
|
|
++ vwmaccsu.vx v2, a1, v3
|
|
|
++ vwmaccsu.vx v0, a1, v2, v0.t
|
|
|
++
|
|
|
++ vwmaccus.vx v1, a1, v2 # vd should be multiple of 2
|
|
|
++ vwmaccus.vx v2, a1, v2 # vd overlap vs2
|
|
|
++ vwmaccus.vx v2, a1, v3 # vd overlap vs2
|
|
|
++ vwmaccus.vx v0, a1, v2, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Widening Floating-Point Add/Subtract Instructions
|
|
|
++
|
|
|
++ vfwadd.vv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vfwadd.vv v2, v2, v4 # vd overlap vs2
|
|
|
++ vfwadd.vv v2, v3, v4 # vd overlap vs2
|
|
|
++ vfwadd.vv v4, v2, v4 # vd overlap vs1
|
|
|
++ vfwadd.vv v4, v2, v5 # vd overlap vs1
|
|
|
++ vfwadd.vv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vfwadd.vf v1, v2, fa1 # vd should be multiple of 2
|
|
|
++ vfwadd.vf v2, v2, fa1 # vd overlap vs2
|
|
|
++ vfwadd.vf v2, v3, fa1 # vd overlap vs2
|
|
|
++ vfwadd.vf v0, v2, fa1, v0.t # vd overlap vm
|
|
|
++ vfwadd.wv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vfwadd.wv v2, v2, v4 # OK
|
|
|
++ vfwadd.wv v2, v3, v4 # vs2 should be multiple of 2
|
|
|
++ vfwadd.wv v4, v2, v4 # vd overlap vs1
|
|
|
++ vfwadd.wv v4, v2, v5 # vd overlap vs1
|
|
|
++ vfwadd.wv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfwsub.vv v1, v2, v4
|
|
|
++ vfwsub.vv v2, v2, v4
|
|
|
++ vfwsub.vv v2, v3, v4
|
|
|
++ vfwsub.vv v4, v2, v4
|
|
|
++ vfwsub.vv v4, v2, v5
|
|
|
++ vfwsub.vv v0, v2, v4, v0.t
|
|
|
++ vfwsub.vf v1, v2, fa1
|
|
|
++ vfwsub.vf v2, v2, fa1
|
|
|
++ vfwsub.vf v2, v3, fa1
|
|
|
++ vfwsub.vf v0, v2, fa1, v0.t
|
|
|
++ vfwsub.wv v1, v2, v4
|
|
|
++ vfwsub.wv v2, v2, v4
|
|
|
++ vfwsub.wv v2, v3, v4
|
|
|
++ vfwsub.wv v4, v2, v4
|
|
|
++ vfwsub.wv v4, v2, v5
|
|
|
++ vfwsub.wv v0, v2, v4, v0.t
|
|
|
++
|
|
|
++# Vector Widening Floating-Point Multiply
|
|
|
++
|
|
|
++ vfwmul.vv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vfwmul.vv v2, v2, v4 # vd overlap vs2
|
|
|
++ vfwmul.vv v2, v3, v4 # vd overlap vs2
|
|
|
++ vfwmul.vv v4, v2, v4 # vd overlap vs1
|
|
|
++ vfwmul.vv v4, v2, v5 # vd overlap vs1
|
|
|
++ vfwmul.vv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vfwsub.vf v1, v2, fa1 # vd should be multiple of 2
|
|
|
++ vfwsub.vf v2, v2, fa1 # vd overlap vs2
|
|
|
++ vfwsub.vf v2, v3, fa1 # vd overlap vs2
|
|
|
++ vfwsub.vf v0, v2, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Widening Floating-Point Fused Multiply-Add Instructions
|
|
|
++ vfwmacc.vv v1, v2, v4 # vd should be multiple of 2
|
|
|
++ vfwmacc.vv v2, v2, v4 # vd overlap vs1
|
|
|
++ vfwmacc.vv v2, v3, v4 # vd overlap vs1
|
|
|
++ vfwmacc.vv v4, v2, v4 # vd overlap vs2
|
|
|
++ vfwmacc.vv v4, v2, v5 # vd overlap vs2
|
|
|
++ vfwmacc.vv v0, v2, v4, v0.t # vd overlap vm
|
|
|
++ vfwmacc.vf v1, fa1, v2 # vd should be multiple of 2
|
|
|
++ vfwmacc.vf v2, fa1, v2 # vd overlap vs2
|
|
|
++ vfwmacc.vf v2, fa1, v3 # vd overlap vs2
|
|
|
++ vfwmacc.vf v0, fa1, v2, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vfwnmacc.vv v1, v2, v4
|
|
|
++ vfwnmacc.vv v2, v2, v4
|
|
|
++ vfwnmacc.vv v2, v3, v4
|
|
|
++ vfwnmacc.vv v4, v2, v4
|
|
|
++ vfwnmacc.vv v4, v2, v5
|
|
|
++ vfwnmacc.vv v0, v2, v4, v0.t
|
|
|
++ vfwnmacc.vf v1, fa1, v2
|
|
|
++ vfwnmacc.vf v2, fa1, v2
|
|
|
++ vfwnmacc.vf v2, fa1, v3
|
|
|
++ vfwnmacc.vf v0, fa1, v2, v0.t
|
|
|
++
|
|
|
++ vfwmsac.vv v1, v2, v4
|
|
|
++ vfwmsac.vv v2, v2, v4
|
|
|
++ vfwmsac.vv v2, v3, v4
|
|
|
++ vfwmsac.vv v4, v2, v4
|
|
|
++ vfwmsac.vv v4, v2, v5
|
|
|
++ vfwmsac.vv v0, v2, v4, v0.t
|
|
|
++ vfwmsac.vf v1, fa1, v2
|
|
|
++ vfwmsac.vf v2, fa1, v2
|
|
|
++ vfwmsac.vf v2, fa1, v3
|
|
|
++ vfwmsac.vf v0, fa1, v2, v0.t
|
|
|
++
|
|
|
++ vfwnmsac.vv v1, v2, v4
|
|
|
++ vfwnmsac.vv v2, v2, v4
|
|
|
++ vfwnmsac.vv v2, v3, v4
|
|
|
++ vfwnmsac.vv v4, v2, v4
|
|
|
++ vfwnmsac.vv v4, v2, v5
|
|
|
++ vfwnmsac.vv v0, v2, v4, v0.t
|
|
|
++ vfwnmsac.vf v1, fa1, v2
|
|
|
++ vfwnmsac.vf v2, fa1, v2
|
|
|
++ vfwnmsac.vf v2, fa1, v3
|
|
|
++ vfwnmsac.vf v0, fa1, v2, v0.t
|
|
|
++
|
|
|
++# Widening Floating-Point/Integer Type-Convert Instructions
|
|
|
++
|
|
|
++ vfwcvt.xu.f.v v1, v2 # vd should be multiple of 2
|
|
|
++ vfwcvt.xu.f.v v2, v2 # vd overlap vs2
|
|
|
++ vfwcvt.xu.f.v v2, v3 # vd overlap vs2
|
|
|
++ vfwcvt.xu.f.v v0, v2, v0.t # vd overlap vm
|
|
|
++ vfwcvt.x.f.v v1, v2
|
|
|
++ vfwcvt.x.f.v v2, v2
|
|
|
++ vfwcvt.x.f.v v2, v3
|
|
|
++ vfwcvt.x.f.v v0, v2, v0.t
|
|
|
++ vfwcvt.rtz.xu.f.v v1, v2
|
|
|
++ vfwcvt.rtz.xu.f.v v2, v2
|
|
|
++ vfwcvt.rtz.xu.f.v v2, v3
|
|
|
++ vfwcvt.rtz.xu.f.v v0, v2, v0.t
|
|
|
++ vfwcvt.rtz.x.f.v v1, v2
|
|
|
++ vfwcvt.rtz.x.f.v v2, v2
|
|
|
++ vfwcvt.rtz.x.f.v v2, v3
|
|
|
++ vfwcvt.rtz.x.f.v v0, v2, v0.t
|
|
|
++ vfwcvt.f.xu.v v1, v2
|
|
|
++ vfwcvt.f.xu.v v2, v2
|
|
|
++ vfwcvt.f.xu.v v2, v3
|
|
|
++ vfwcvt.f.xu.v v0, v2, v0.t
|
|
|
++ vfwcvt.f.x.v v1, v2
|
|
|
++ vfwcvt.f.x.v v2, v2
|
|
|
++ vfwcvt.f.x.v v2, v3
|
|
|
++ vfwcvt.f.x.v v0, v2, v0.t
|
|
|
++ vfwcvt.f.f.v v1, v2
|
|
|
++ vfwcvt.f.f.v v2, v2
|
|
|
++ vfwcvt.f.f.v v2, v3
|
|
|
++ vfwcvt.f.f.v v0, v2, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..1e4ac10260
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-load-store.s
|
|
|
++#error_output: vector-insns-fail-load-store.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..f2e682214c
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.l
|
|
|
+@@ -0,0 +1,419 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vle8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vle64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vse64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlse8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlse16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlse32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlse64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vsse64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vloxei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg2e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg3e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg4e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg5e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg6e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg7e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg8e8.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e8ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg2e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg3e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg4e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg5e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg6e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg7e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg8e16.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e16ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg2e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg3e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg4e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg5e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg6e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg7e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg8e32.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e32ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg2e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg2e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg3e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg3e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg4e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg4e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg5e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg5e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg6e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg6e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg7e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg7e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vsseg8e64.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlseg8e64ff.v v0,\(a0\),v0.t'
|
|
|
++.*Error: illegal operands `vlsseg2e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg2e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg3e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg3e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg4e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg4e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg5e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg5e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg6e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg6e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg7e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg7e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg8e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg8e8.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg2e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg2e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg3e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg3e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg4e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg4e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg5e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg5e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg6e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg6e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg7e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg7e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg8e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg8e16.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg2e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg2e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg3e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg3e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg4e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg4e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg5e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg5e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg6e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg6e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg7e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg7e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg8e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg8e32.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg2e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg2e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg3e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg3e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg4e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg4e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg5e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg5e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg6e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg6e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg7e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg7e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vlsseg8e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vssseg8e64.v v0,\(a0\),a1,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg2ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg2ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg2ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg2ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg3ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg3ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg3ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg3ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg4ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg4ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg4ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg4ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg5ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg5ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg5ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg5ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg6ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg6ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg6ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg6ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg7ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg7ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg7ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg7ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg8ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg8ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg8ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg8ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg2ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg2ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg2ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg2ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg3ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg3ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg3ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg3ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg4ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg4ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg4ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg4ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg5ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg5ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg5ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg5ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg6ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg6ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg6ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg6ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg7ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg7ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg7ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg7ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg8ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg8ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg8ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg8ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg2ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg2ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg2ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg2ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg3ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg3ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg3ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg3ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg4ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg4ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg4ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg4ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg5ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg5ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg5ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg5ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg6ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg6ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg6ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg6ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg7ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg7ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg7ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg7ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg8ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg8ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg8ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg8ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg2ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg2ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg2ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg2ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg3ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg3ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg3ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg3ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg4ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg4ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg4ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg4ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg5ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg5ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg5ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg5ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg6ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg6ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg6ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg6ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg7ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg7ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg7ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg7ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vloxseg8ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vloxseg8ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsoxseg8ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsoxseg8ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg2ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg2ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg2ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg2ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg3ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg3ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg3ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg3ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg4ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg4ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg4ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg4ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg5ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg5ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg5ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg5ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg6ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg6ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg6ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg6ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg7ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg7ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg7ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg7ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg8ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg8ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg8ei8.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg8ei8.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg2ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg2ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg2ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg2ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg3ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg3ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg3ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg3ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg4ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg4ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg4ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg4ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg5ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg5ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg5ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg5ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg6ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg6ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg6ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg6ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg7ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg7ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg7ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg7ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg8ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg8ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg8ei16.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg8ei16.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg2ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg2ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg2ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg2ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg3ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg3ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg3ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg3ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg4ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg4ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg4ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg4ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg5ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg5ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg5ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg5ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg6ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg6ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg6ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg6ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg7ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg7ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg7ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg7ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg8ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg8ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg8ei32.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg8ei32.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg2ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg2ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg2ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg2ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg3ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg3ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg3ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg3ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg4ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg4ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg4ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg4ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg5ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg5ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg5ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg5ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg6ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg6ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg6ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg6ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg7ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg7ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg7ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg7ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vluxseg8ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vluxseg8ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vsuxseg8ei64.v v4,\(a0\),v4'
|
|
|
++.*Error: illegal operands `vsuxseg8ei64.v v0,\(a0\),v4,v0.t'
|
|
|
++.*Error: illegal operands `vl2r.v v31,\(a0\)'
|
|
|
++.*Error: illegal operands `vl2re8.v v31,\(a0\)'
|
|
|
++.*Error: illegal operands `vl2re16.v v31,\(a0\)'
|
|
|
++.*Error: illegal operands `vl2re32.v v31,\(a0\)'
|
|
|
++.*Error: illegal operands `vl2re64.v v31,\(a0\)'
|
|
|
++.*Error: illegal operands `vl4r.v v30,\(a0\)'
|
|
|
++.*Error: illegal operands `vl4re8.v v30,\(a0\)'
|
|
|
++.*Error: illegal operands `vl4re16.v v30,\(a0\)'
|
|
|
++.*Error: illegal operands `vl4re32.v v30,\(a0\)'
|
|
|
++.*Error: illegal operands `vl4re64.v v30,\(a0\)'
|
|
|
++.*Error: illegal operands `vl8r.v v26,\(a0\)'
|
|
|
++.*Error: illegal operands `vl8re8.v v26,\(a0\)'
|
|
|
++.*Error: illegal operands `vl8re16.v v26,\(a0\)'
|
|
|
++.*Error: illegal operands `vl8re32.v v26,\(a0\)'
|
|
|
++.*Error: illegal operands `vl8re64.v v26,\(a0\)'
|
|
|
++.*Error: illegal operands `vs2r.v v31,\(a0\)'
|
|
|
++.*Error: illegal operands `vs4r.v v30,\(a0\)'
|
|
|
++.*Error: illegal operands `vs8r.v v26,\(a0\)'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..274d0b4226
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-load-store.s
|
|
|
+@@ -0,0 +1,481 @@
|
|
|
++# Vector Unit-Stride Loads and Stores
|
|
|
++
|
|
|
++ vle8.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vle8ff.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vle16.v v0, (a0), v0.t
|
|
|
++ vle16ff.v v0, (a0), v0.t
|
|
|
++ vle32.v v0, (a0), v0.t
|
|
|
++ vle32ff.v v0, (a0), v0.t
|
|
|
++ vle64.v v0, (a0), v0.t
|
|
|
++ vle64ff.v v0, (a0), v0.t
|
|
|
++
|
|
|
++ vse8.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vse16.v v0, (a0), v0.t
|
|
|
++ vse32.v v0, (a0), v0.t
|
|
|
++ vse64.v v0, (a0), v0.t
|
|
|
++
|
|
|
++# Vector Strided Loads and Stores
|
|
|
++
|
|
|
++ vlse8.v v0, (a0), a1, v0.t # vd overlap vm
|
|
|
++ vlse16.v v0, (a0), a1, v0.t
|
|
|
++ vlse32.v v0, (a0), a1, v0.t
|
|
|
++ vlse64.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vsse8.v v0, (a0), a1, v0.t
|
|
|
++ vsse16.v v0, (a0), a1, v0.t
|
|
|
++ vsse32.v v0, (a0), a1, v0.t
|
|
|
++ vsse64.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++# Vector Ordered Indexed Loads and Stores
|
|
|
++
|
|
|
++ vloxei8.v v4, (a0), v4 # OK
|
|
|
++ vloxei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vloxei16.v v4, (a0), v4
|
|
|
++ vloxei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxei32.v v4, (a0), v4
|
|
|
++ vloxei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxei64.v v4, (a0), v4
|
|
|
++ vloxei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vsoxei8.v v4, (a0), v4
|
|
|
++ vsoxei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxei16.v v4, (a0), v4
|
|
|
++ vsoxei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxei32.v v4, (a0), v4
|
|
|
++ vsoxei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxei64.v v4, (a0), v4
|
|
|
++ vsoxei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++# Vector Unordered Indexed Loads and Stores
|
|
|
++
|
|
|
++ vluxei8.v v4, (a0), v4 # OK
|
|
|
++ vluxei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vluxei16.v v4, (a0), v4
|
|
|
++ vluxei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxei32.v v4, (a0), v4
|
|
|
++ vluxei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxei64.v v4, (a0), v4
|
|
|
++ vluxei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vsuxei8.v v4, (a0), v4
|
|
|
++ vsuxei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxei16.v v4, (a0), v4
|
|
|
++ vsuxei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxei32.v v4, (a0), v4
|
|
|
++ vsuxei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxei64.v v4, (a0), v4
|
|
|
++ vsuxei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++# Vector Unit-Stride Segment Loads and Stores
|
|
|
++
|
|
|
++ vlseg2e8.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vsseg2e8.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vlseg2e8ff.v v0, (a0), v0.t # vd overlap vm
|
|
|
++ vlseg3e8.v v0, (a0), v0.t
|
|
|
++ vsseg3e8.v v0, (a0), v0.t
|
|
|
++ vlseg3e8ff.v v0, (a0), v0.t
|
|
|
++ vlseg4e8.v v0, (a0), v0.t
|
|
|
++ vsseg4e8.v v0, (a0), v0.t
|
|
|
++ vlseg4e8ff.v v0, (a0), v0.t
|
|
|
++ vlseg5e8.v v0, (a0), v0.t
|
|
|
++ vsseg5e8.v v0, (a0), v0.t
|
|
|
++ vlseg5e8ff.v v0, (a0), v0.t
|
|
|
++ vlseg6e8.v v0, (a0), v0.t
|
|
|
++ vsseg6e8.v v0, (a0), v0.t
|
|
|
++ vlseg6e8ff.v v0, (a0), v0.t
|
|
|
++ vlseg7e8.v v0, (a0), v0.t
|
|
|
++ vsseg7e8.v v0, (a0), v0.t
|
|
|
++ vlseg7e8ff.v v0, (a0), v0.t
|
|
|
++ vlseg8e8.v v0, (a0), v0.t
|
|
|
++ vsseg8e8.v v0, (a0), v0.t
|
|
|
++ vlseg8e8ff.v v0, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16.v v0, (a0), v0.t
|
|
|
++ vsseg2e16.v v0, (a0), v0.t
|
|
|
++ vlseg2e16ff.v v0, (a0), v0.t
|
|
|
++ vlseg3e16.v v0, (a0), v0.t
|
|
|
++ vsseg3e16.v v0, (a0), v0.t
|
|
|
++ vlseg3e16ff.v v0, (a0), v0.t
|
|
|
++ vlseg4e16.v v0, (a0), v0.t
|
|
|
++ vsseg4e16.v v0, (a0), v0.t
|
|
|
++ vlseg4e16ff.v v0, (a0), v0.t
|
|
|
++ vlseg5e16.v v0, (a0), v0.t
|
|
|
++ vsseg5e16.v v0, (a0), v0.t
|
|
|
++ vlseg5e16ff.v v0, (a0), v0.t
|
|
|
++ vlseg6e16.v v0, (a0), v0.t
|
|
|
++ vsseg6e16.v v0, (a0), v0.t
|
|
|
++ vlseg6e16ff.v v0, (a0), v0.t
|
|
|
++ vlseg7e16.v v0, (a0), v0.t
|
|
|
++ vsseg7e16.v v0, (a0), v0.t
|
|
|
++ vlseg7e16ff.v v0, (a0), v0.t
|
|
|
++ vlseg8e16.v v0, (a0), v0.t
|
|
|
++ vsseg8e16.v v0, (a0), v0.t
|
|
|
++ vlseg8e16ff.v v0, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e32.v v0, (a0), v0.t
|
|
|
++ vsseg2e32.v v0, (a0), v0.t
|
|
|
++ vlseg2e32ff.v v0, (a0), v0.t
|
|
|
++ vlseg3e32.v v0, (a0), v0.t
|
|
|
++ vsseg3e32.v v0, (a0), v0.t
|
|
|
++ vlseg3e32ff.v v0, (a0), v0.t
|
|
|
++ vlseg4e32.v v0, (a0), v0.t
|
|
|
++ vsseg4e32.v v0, (a0), v0.t
|
|
|
++ vlseg4e32ff.v v0, (a0), v0.t
|
|
|
++ vlseg5e32.v v0, (a0), v0.t
|
|
|
++ vsseg5e32.v v0, (a0), v0.t
|
|
|
++ vlseg5e32ff.v v0, (a0), v0.t
|
|
|
++ vlseg6e32.v v0, (a0), v0.t
|
|
|
++ vsseg6e32.v v0, (a0), v0.t
|
|
|
++ vlseg6e32ff.v v0, (a0), v0.t
|
|
|
++ vlseg7e32.v v0, (a0), v0.t
|
|
|
++ vsseg7e32.v v0, (a0), v0.t
|
|
|
++ vlseg7e32ff.v v0, (a0), v0.t
|
|
|
++ vlseg8e32.v v0, (a0), v0.t
|
|
|
++ vsseg8e32.v v0, (a0), v0.t
|
|
|
++ vlseg8e32ff.v v0, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e64.v v0, (a0), v0.t
|
|
|
++ vsseg2e64.v v0, (a0), v0.t
|
|
|
++ vlseg2e64ff.v v0, (a0), v0.t
|
|
|
++ vlseg3e64.v v0, (a0), v0.t
|
|
|
++ vsseg3e64.v v0, (a0), v0.t
|
|
|
++ vlseg3e64ff.v v0, (a0), v0.t
|
|
|
++ vlseg4e64.v v0, (a0), v0.t
|
|
|
++ vsseg4e64.v v0, (a0), v0.t
|
|
|
++ vlseg4e64ff.v v0, (a0), v0.t
|
|
|
++ vlseg5e64.v v0, (a0), v0.t
|
|
|
++ vsseg5e64.v v0, (a0), v0.t
|
|
|
++ vlseg5e64ff.v v0, (a0), v0.t
|
|
|
++ vlseg6e64.v v0, (a0), v0.t
|
|
|
++ vsseg6e64.v v0, (a0), v0.t
|
|
|
++ vlseg6e64ff.v v0, (a0), v0.t
|
|
|
++ vlseg7e64.v v0, (a0), v0.t
|
|
|
++ vsseg7e64.v v0, (a0), v0.t
|
|
|
++ vlseg7e64ff.v v0, (a0), v0.t
|
|
|
++ vlseg8e64.v v0, (a0), v0.t
|
|
|
++ vsseg8e64.v v0, (a0), v0.t
|
|
|
++ vlseg8e64ff.v v0, (a0), v0.t
|
|
|
++
|
|
|
++# Vector Strided Segment Loads and Stores
|
|
|
++
|
|
|
++ vlsseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
|
|
|
++ vssseg2e8.v v0, (a0), a1, v0.t # vd overlap vm
|
|
|
++ vlsseg3e8.v v0, (a0), a1, v0.t
|
|
|
++ vssseg3e8.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg4e8.v v0, (a0), a1, v0.t
|
|
|
++ vssseg4e8.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg5e8.v v0, (a0), a1, v0.t
|
|
|
++ vssseg5e8.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg6e8.v v0, (a0), a1, v0.t
|
|
|
++ vssseg6e8.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg7e8.v v0, (a0), a1, v0.t
|
|
|
++ vssseg7e8.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg8e8.v v0, (a0), a1, v0.t
|
|
|
++ vssseg8e8.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg2e16.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg3e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg3e16.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg4e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg4e16.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg5e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg5e16.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg6e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg6e16.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg7e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg7e16.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg8e16.v v0, (a0), a1, v0.t
|
|
|
++ vssseg8e16.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg2e32.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg3e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg3e32.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg4e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg4e32.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg5e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg5e32.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg6e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg6e32.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg7e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg7e32.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg8e32.v v0, (a0), a1, v0.t
|
|
|
++ vssseg8e32.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg2e64.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg3e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg3e64.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg4e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg4e64.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg5e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg5e64.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg6e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg6e64.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg7e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg7e64.v v0, (a0), a1, v0.t
|
|
|
++ vlsseg8e64.v v0, (a0), a1, v0.t
|
|
|
++ vssseg8e64.v v0, (a0), a1, v0.t
|
|
|
++
|
|
|
++# Vector Ordered Indexed Segment Loads and Stores
|
|
|
++
|
|
|
++ vloxseg2ei8.v v4, (a0), v4 # vd overlap vs2
|
|
|
++ vloxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vsoxseg2ei8.v v4, (a0), v4 # vd overlap vs2
|
|
|
++ vsoxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vloxseg3ei8.v v4, (a0), v4
|
|
|
++ vloxseg3ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg3ei8.v v4, (a0), v4
|
|
|
++ vsoxseg3ei8.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg4ei8.v v4, (a0), v4
|
|
|
++ vloxseg4ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg4ei8.v v4, (a0), v4
|
|
|
++ vsoxseg4ei8.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg5ei8.v v4, (a0), v4
|
|
|
++ vloxseg5ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg5ei8.v v4, (a0), v4
|
|
|
++ vsoxseg5ei8.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg6ei8.v v4, (a0), v4
|
|
|
++ vloxseg6ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg6ei8.v v4, (a0), v4
|
|
|
++ vsoxseg6ei8.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg7ei8.v v4, (a0), v4
|
|
|
++ vloxseg7ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg7ei8.v v4, (a0), v4
|
|
|
++ vsoxseg7ei8.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg8ei8.v v4, (a0), v4
|
|
|
++ vloxseg8ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg8ei8.v v4, (a0), v4
|
|
|
++ vsoxseg8ei8.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei16.v v4, (a0), v4
|
|
|
++ vloxseg2ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg2ei16.v v4, (a0), v4
|
|
|
++ vsoxseg2ei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg3ei16.v v4, (a0), v4
|
|
|
++ vloxseg3ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg3ei16.v v4, (a0), v4
|
|
|
++ vsoxseg3ei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg4ei16.v v4, (a0), v4
|
|
|
++ vloxseg4ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg4ei16.v v4, (a0), v4
|
|
|
++ vsoxseg4ei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg5ei16.v v4, (a0), v4
|
|
|
++ vloxseg5ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg5ei16.v v4, (a0), v4
|
|
|
++ vsoxseg5ei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg6ei16.v v4, (a0), v4
|
|
|
++ vloxseg6ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg6ei16.v v4, (a0), v4
|
|
|
++ vsoxseg6ei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg7ei16.v v4, (a0), v4
|
|
|
++ vloxseg7ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg7ei16.v v4, (a0), v4
|
|
|
++ vsoxseg7ei16.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg8ei16.v v4, (a0), v4
|
|
|
++ vloxseg8ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg8ei16.v v4, (a0), v4
|
|
|
++ vsoxseg8ei16.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei32.v v4, (a0), v4
|
|
|
++ vloxseg2ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg2ei32.v v4, (a0), v4
|
|
|
++ vsoxseg2ei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg3ei32.v v4, (a0), v4
|
|
|
++ vloxseg3ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg3ei32.v v4, (a0), v4
|
|
|
++ vsoxseg3ei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg4ei32.v v4, (a0), v4
|
|
|
++ vloxseg4ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg4ei32.v v4, (a0), v4
|
|
|
++ vsoxseg4ei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg5ei32.v v4, (a0), v4
|
|
|
++ vloxseg5ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg5ei32.v v4, (a0), v4
|
|
|
++ vsoxseg5ei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg6ei32.v v4, (a0), v4
|
|
|
++ vloxseg6ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg6ei32.v v4, (a0), v4
|
|
|
++ vsoxseg6ei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg7ei32.v v4, (a0), v4
|
|
|
++ vloxseg7ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg7ei32.v v4, (a0), v4
|
|
|
++ vsoxseg7ei32.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg8ei32.v v4, (a0), v4
|
|
|
++ vloxseg8ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg8ei32.v v4, (a0), v4
|
|
|
++ vsoxseg8ei32.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei64.v v4, (a0), v4
|
|
|
++ vloxseg2ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg2ei64.v v4, (a0), v4
|
|
|
++ vsoxseg2ei64.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg3ei64.v v4, (a0), v4
|
|
|
++ vloxseg3ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg3ei64.v v4, (a0), v4
|
|
|
++ vsoxseg3ei64.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg4ei64.v v4, (a0), v4
|
|
|
++ vloxseg4ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg4ei64.v v4, (a0), v4
|
|
|
++ vsoxseg4ei64.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg5ei64.v v4, (a0), v4
|
|
|
++ vloxseg5ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg5ei64.v v4, (a0), v4
|
|
|
++ vsoxseg5ei64.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg6ei64.v v4, (a0), v4
|
|
|
++ vloxseg6ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg6ei64.v v4, (a0), v4
|
|
|
++ vsoxseg6ei64.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg7ei64.v v4, (a0), v4
|
|
|
++ vloxseg7ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg7ei64.v v4, (a0), v4
|
|
|
++ vsoxseg7ei64.v v0, (a0), v4, v0.t
|
|
|
++ vloxseg8ei64.v v4, (a0), v4
|
|
|
++ vloxseg8ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsoxseg8ei64.v v4, (a0), v4
|
|
|
++ vsoxseg8ei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++# Vector Unordered Indexed Segment Loads and Stores
|
|
|
++
|
|
|
++ vluxseg2ei8.v v4, (a0), v4 # vd overlap vs2
|
|
|
++ vluxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vsuxseg2ei8.v v4, (a0), v4 # vd overlap vs2
|
|
|
++ vsuxseg2ei8.v v0, (a0), v4, v0.t # vd overlap vm
|
|
|
++ vluxseg3ei8.v v4, (a0), v4
|
|
|
++ vluxseg3ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg3ei8.v v4, (a0), v4
|
|
|
++ vsuxseg3ei8.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg4ei8.v v4, (a0), v4
|
|
|
++ vluxseg4ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg4ei8.v v4, (a0), v4
|
|
|
++ vsuxseg4ei8.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg5ei8.v v4, (a0), v4
|
|
|
++ vluxseg5ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg5ei8.v v4, (a0), v4
|
|
|
++ vsuxseg5ei8.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg6ei8.v v4, (a0), v4
|
|
|
++ vluxseg6ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg6ei8.v v4, (a0), v4
|
|
|
++ vsuxseg6ei8.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg7ei8.v v4, (a0), v4
|
|
|
++ vluxseg7ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg7ei8.v v4, (a0), v4
|
|
|
++ vsuxseg7ei8.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg8ei8.v v4, (a0), v4
|
|
|
++ vluxseg8ei8.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg8ei8.v v4, (a0), v4
|
|
|
++ vsuxseg8ei8.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei16.v v4, (a0), v4
|
|
|
++ vluxseg2ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg2ei16.v v4, (a0), v4
|
|
|
++ vsuxseg2ei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg3ei16.v v4, (a0), v4
|
|
|
++ vluxseg3ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg3ei16.v v4, (a0), v4
|
|
|
++ vsuxseg3ei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg4ei16.v v4, (a0), v4
|
|
|
++ vluxseg4ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg4ei16.v v4, (a0), v4
|
|
|
++ vsuxseg4ei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg5ei16.v v4, (a0), v4
|
|
|
++ vluxseg5ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg5ei16.v v4, (a0), v4
|
|
|
++ vsuxseg5ei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg6ei16.v v4, (a0), v4
|
|
|
++ vluxseg6ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg6ei16.v v4, (a0), v4
|
|
|
++ vsuxseg6ei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg7ei16.v v4, (a0), v4
|
|
|
++ vluxseg7ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg7ei16.v v4, (a0), v4
|
|
|
++ vsuxseg7ei16.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg8ei16.v v4, (a0), v4
|
|
|
++ vluxseg8ei16.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg8ei16.v v4, (a0), v4
|
|
|
++ vsuxseg8ei16.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei32.v v4, (a0), v4
|
|
|
++ vluxseg2ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg2ei32.v v4, (a0), v4
|
|
|
++ vsuxseg2ei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg3ei32.v v4, (a0), v4
|
|
|
++ vluxseg3ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg3ei32.v v4, (a0), v4
|
|
|
++ vsuxseg3ei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg4ei32.v v4, (a0), v4
|
|
|
++ vluxseg4ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg4ei32.v v4, (a0), v4
|
|
|
++ vsuxseg4ei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg5ei32.v v4, (a0), v4
|
|
|
++ vluxseg5ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg5ei32.v v4, (a0), v4
|
|
|
++ vsuxseg5ei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg6ei32.v v4, (a0), v4
|
|
|
++ vluxseg6ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg6ei32.v v4, (a0), v4
|
|
|
++ vsuxseg6ei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg7ei32.v v4, (a0), v4
|
|
|
++ vluxseg7ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg7ei32.v v4, (a0), v4
|
|
|
++ vsuxseg7ei32.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg8ei32.v v4, (a0), v4
|
|
|
++ vluxseg8ei32.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg8ei32.v v4, (a0), v4
|
|
|
++ vsuxseg8ei32.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei64.v v4, (a0), v4
|
|
|
++ vluxseg2ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg2ei64.v v4, (a0), v4
|
|
|
++ vsuxseg2ei64.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg3ei64.v v4, (a0), v4
|
|
|
++ vluxseg3ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg3ei64.v v4, (a0), v4
|
|
|
++ vsuxseg3ei64.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg4ei64.v v4, (a0), v4
|
|
|
++ vluxseg4ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg4ei64.v v4, (a0), v4
|
|
|
++ vsuxseg4ei64.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg5ei64.v v4, (a0), v4
|
|
|
++ vluxseg5ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg5ei64.v v4, (a0), v4
|
|
|
++ vsuxseg5ei64.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg6ei64.v v4, (a0), v4
|
|
|
++ vluxseg6ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg6ei64.v v4, (a0), v4
|
|
|
++ vsuxseg6ei64.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg7ei64.v v4, (a0), v4
|
|
|
++ vluxseg7ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg7ei64.v v4, (a0), v4
|
|
|
++ vsuxseg7ei64.v v0, (a0), v4, v0.t
|
|
|
++ vluxseg8ei64.v v4, (a0), v4
|
|
|
++ vluxseg8ei64.v v0, (a0), v4, v0.t
|
|
|
++ vsuxseg8ei64.v v4, (a0), v4
|
|
|
++ vsuxseg8ei64.v v0, (a0), v4, v0.t
|
|
|
++
|
|
|
++# Vector Load/Store Whole Register Instructions
|
|
|
++
|
|
|
++ vl1r.v v31, (a0) # OK
|
|
|
++
|
|
|
++ vl2r.v v31, (a0) # vd must be aligned to 2
|
|
|
++ vl2re8.v v31, (a0)
|
|
|
++ vl2re16.v v31, (a0)
|
|
|
++ vl2re32.v v31, (a0)
|
|
|
++ vl2re64.v v31, (a0)
|
|
|
++
|
|
|
++ vl4r.v v30, (a0) # vd must be aligned to 4
|
|
|
++ vl4re8.v v30, (a0)
|
|
|
++ vl4re16.v v30, (a0)
|
|
|
++ vl4re32.v v30, (a0)
|
|
|
++ vl4re64.v v30, (a0)
|
|
|
++
|
|
|
++ vl8r.v v26, (a0) # vd must be aligned to 8
|
|
|
++ vl8re8.v v26, (a0)
|
|
|
++ vl8re16.v v26, (a0)
|
|
|
++ vl8re32.v v26, (a0)
|
|
|
++ vl8re64.v v26, (a0)
|
|
|
++
|
|
|
++ vs2r.v v31, (a0) # vs3 must be aligned to 2
|
|
|
++ vs4r.v v30, (a0) # vs3 must be aligned to 4
|
|
|
++ vs8r.v v26, (a0) # vs3 must be aligned to 8
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.d b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..1d3aa8d7d3
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-mask.s
|
|
|
++#error_output: vector-insns-fail-mask.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..3b23becc16
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.l
|
|
|
+@@ -0,0 +1,10 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vmsbf.m v4,v4'
|
|
|
++.*Error: illegal operands `vmsbf.m v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vmsif.m v4,v4'
|
|
|
++.*Error: illegal operands `vmsif.m v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vmsof.m v4,v4'
|
|
|
++.*Error: illegal operands `vmsof.m v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `viota.m v4,v4'
|
|
|
++.*Error: illegal operands `viota.m v0,v4,v0.t'
|
|
|
++.*Error: illegal operands `vid.v v0,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..99b19f6bdd
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-mask.s
|
|
|
+@@ -0,0 +1,23 @@
|
|
|
++# Vector Set-before-first Mask Bit
|
|
|
++
|
|
|
++ vmsbf.m v4, v4 # vd overlap vs2
|
|
|
++ vmsbf.m v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Set-including-first Mask Bit
|
|
|
++
|
|
|
++ vmsif.m v4, v4 # vd overlap vs2
|
|
|
++ vmsif.m v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Set-only-first Mask Bit
|
|
|
++
|
|
|
++ vmsof.m v4, v4 # vd overlap vs2
|
|
|
++ vmsof.m v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Iota Instruction
|
|
|
++
|
|
|
++ viota.m v4, v4 # vd overlap vs2
|
|
|
++ viota.m v0, v4, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Element Index Instruction
|
|
|
++
|
|
|
++ vid.v v0, v0.t # vd overlap vm
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..ebdd2b1051
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32ifv0p10
|
|
|
++#source: vector-insns-fail-permutation.s
|
|
|
++#error_output: vector-insns-fail-permutation.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..c208f5710f
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.l
|
|
|
+@@ -0,0 +1,31 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vslideup.vx v4,v4,a1'
|
|
|
++.*Error: illegal operands `vslideup.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vslideup.vi v4,v4,31'
|
|
|
++.*Error: illegal operands `vslideup.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vslidedown.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vslidedown.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vslide1up.vx v4,v4,a1'
|
|
|
++.*Error: illegal operands `vslide1up.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vfslide1up.vf v4,v4,fa1'
|
|
|
++.*Error: illegal operands `vfslide1up.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vslide1down.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vfslide1down.vf v0,v4,fa1,v0.t'
|
|
|
++.*Error: illegal operands `vrgather.vv v4,v4,v8'
|
|
|
++.*Error: illegal operands `vrgather.vv v8,v4,v8'
|
|
|
++.*Error: illegal operands `vrgather.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vrgather.vx v4,v4,a1'
|
|
|
++.*Error: illegal operands `vrgather.vx v0,v4,a1,v0.t'
|
|
|
++.*Error: illegal operands `vrgather.vi v4,v4,31'
|
|
|
++.*Error: illegal operands `vrgather.vi v0,v4,31,v0.t'
|
|
|
++.*Error: illegal operands `vrgatherei16.vv v4,v4,v8'
|
|
|
++.*Error: illegal operands `vrgatherei16.vv v8,v4,v8'
|
|
|
++.*Error: illegal operands `vrgatherei16.vv v0,v4,v8,v0.t'
|
|
|
++.*Error: illegal operands `vcompress.vm v4,v4,v8'
|
|
|
++.*Error: illegal operands `vcompress.vm v8,v4,v8'
|
|
|
++.*Error: illegal operands `vmv2r.v v30,v31'
|
|
|
++.*Error: illegal operands `vmv2r.v v31,v30'
|
|
|
++.*Error: illegal operands `vmv4r.v v28,v30'
|
|
|
++.*Error: illegal operands `vmv4r.v v30,v28'
|
|
|
++.*Error: illegal operands `vmv8r.v v24,v26'
|
|
|
++.*Error: illegal operands `vmv8r.v v26,v24'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..85116457ff
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-permutation.s
|
|
|
+@@ -0,0 +1,56 @@
|
|
|
++# Vector Slideup Instructions
|
|
|
++
|
|
|
++ vslideup.vx v4, v4, a1 # vd overlap vs2
|
|
|
++ vslideup.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vslideup.vi v4, v4, 31 # vd overlap vs2
|
|
|
++ vslideup.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vslidedown.vx v4, v4, a1 # OK
|
|
|
++ vslidedown.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vslidedown.vi v4, v4, 31 # OK
|
|
|
++ vslidedown.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vslide1up.vx v4, v4, a1 # vd overlap vs2
|
|
|
++ vslide1up.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vfslide1up.vf v4, v4, fa1 # vd overlap vs2
|
|
|
++ vfslide1up.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vslide1down.vx v4, v4, a1 # OK
|
|
|
++ vslide1down.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vfslide1down.vf v4, v4, fa1 # OK
|
|
|
++ vfslide1down.vf v0, v4, fa1, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Register Gather Instructions
|
|
|
++
|
|
|
++ vrgather.vv v4, v4, v8 # vd overlap vs2
|
|
|
++ vrgather.vv v8, v4, v8 # vd overlap vs1
|
|
|
++ vrgather.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++ vrgather.vx v4, v4, a1 # vd overlap vs2
|
|
|
++ vrgather.vx v0, v4, a1, v0.t # vd overlap vm
|
|
|
++ vrgather.vi v4, v4, 31 # vd overlap vs2
|
|
|
++ vrgather.vi v0, v4, 31, v0.t # vd overlap vm
|
|
|
++
|
|
|
++ vrgatherei16.vv v4, v4, v8 # vd overlap vs2
|
|
|
++ vrgatherei16.vv v8, v4, v8 # vd overlap vs1
|
|
|
++ vrgatherei16.vv v0, v4, v8, v0.t # vd overlap vm
|
|
|
++
|
|
|
++# Vector Compress Instruction
|
|
|
++
|
|
|
++ vcompress.vm v4, v4, v8 # vd overlap vs2
|
|
|
++ vcompress.vm v8, v4, v8 # vd overlap vs1
|
|
|
++
|
|
|
++# Whole Vector Register Move
|
|
|
++
|
|
|
++ vmv1r.v v31, v31 # OK, HINT
|
|
|
++
|
|
|
++ vmv2r.v v30, v30 # OK, HINT
|
|
|
++ vmv2r.v v30, v31 # vs2 must be aligned to 2
|
|
|
++ vmv2r.v v31, v30 # vd must be aligned to 2
|
|
|
++
|
|
|
++ vmv4r.v v28, v28 # OK, HINT
|
|
|
++ vmv4r.v v28, v30 # vs2 must be aligned to 4
|
|
|
++ vmv4r.v v30, v28 # vd must be aligned to 4
|
|
|
++
|
|
|
++ vmv8r.v v24, v24 # OK, HINT
|
|
|
++ vmv8r.v v24, v26 # vs2 must be aligned to 8
|
|
|
++ vmv8r.v v26, v24 # vd must be aligned to 8
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..cca6928e7d
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#source: vector-insns-fail-unsupport.s
|
|
|
++#error_output: vector-insns-fail-unsupport.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..2b726b0268
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.l
|
|
|
+@@ -0,0 +1,1454 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,0x3ff'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e16,m2'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,m8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,m1'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e1024,mf2'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e512,mf4'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,mf8'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ma'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,mu'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,ma'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,ma'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,ta,mu'
|
|
|
++.*: Error: unrecognized opcode `vsetivli a0,0xb,e256,m2,tu,mu'
|
|
|
++.*: Error: unrecognized opcode `vle1.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle1.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vse1.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vse1.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e8.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e16.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e32.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e8.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e8.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e16.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e16.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e32.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e32.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1'
|
|
|
++.*: Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei8.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei16.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei32.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12'
|
|
|
++.*: Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e8ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e16ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e32ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t'
|
|
|
++.*: Error: unrecognized opcode `vl2r.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2r.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re8.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re8.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re16.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re16.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re32.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re32.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re64.v v2,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl2re64.v v2,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4r.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4r.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re8.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re8.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re16.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re16.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re32.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re32.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re64.v v4,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl4re64.v v4,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8r.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8r.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re8.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re8.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re16.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re16.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re32.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re32.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re64.v v8,\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vl8re64.v v8,0\(a0\)'
|
|
|
++.*: Error: unrecognized opcode `vs2r.v v2,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs2r.v v2,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs4r.v v4,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs4r.v v4,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs8r.v v8,\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vs8r.v v8,0\(a1\)'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei8.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei16.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei32.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoaddei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoswapei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoxorei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoandei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamoorei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamominuei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v v4,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vamomaxuei64.v x0,0\(a1\),v8,v4,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vwcvt.x.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwcvtu.x.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwaddu.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsubu.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwadd.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwsub.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vsll.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsll.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsrl.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vsra.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsra.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vncvt.x.x.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsrl.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnsra.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmul.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmulsu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccu.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmacc.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccsu.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8'
|
|
|
++.*: Error: unrecognized opcode `vwmaccus.vx v4,a1,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,15,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsaddu.vi v4,v8,-16,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,15,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsadd.vi v4,v8,-16,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssubu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssub.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaaddu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vaadd.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasubu.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vasub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vasub.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vsmul.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssrl.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vssra.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vssra.vi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclipu.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wx v4,v8,a1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,1,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vnclip.wi v4,v8,31,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.vf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.vf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwadd.wf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwsub.wf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmul.vf v4,v8,fa2,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmacc.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmacc.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwmsac.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vv v4,v12,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwnmsac.vf v4,fa2,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfsqrt.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrte7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrsqrt7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrece7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrece7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfrec7.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfrec7.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfclass.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfclass.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.rtz.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.xu.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfcvt.f.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.xu.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.rtz.x.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.xu.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.x.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwcvt.f.f.v v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.xu.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.x.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.xu.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rtz.x.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.xu.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.x.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.f.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfncvt.rod.f.f.w v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8'
|
|
|
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredmaxu.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredmax.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredminu.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredmin.vs v4,v8,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredand.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredor.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vredxor.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vwredsumu.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vwredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfredosum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredmax.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfredmin.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vfwredosum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vfwredsum.vs v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmsbf.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmsif.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmsof.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `viota.m v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmsbf.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmsif.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmsof.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `viota.m v4,v8,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12'
|
|
|
++.*: Error: unrecognized opcode `vrgatherei16.vv v4,v8,v12,v0.t'
|
|
|
++.*: Error: unrecognized opcode `vmv2r.v v2,v4'
|
|
|
++.*: Error: unrecognized opcode `vmv4r.v v4,v8'
|
|
|
++.*: Error: unrecognized opcode `vmv8r.v v0,v8'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..0112d0bce7
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-unsupport.s
|
|
|
+@@ -0,0 +1,1663 @@
|
|
|
++
|
|
|
++ vsetivli a0, 0xb, 0
|
|
|
++ vsetivli a0, 0xb, 0x3ff
|
|
|
++ vsetivli a0, 0xb, e16, m2
|
|
|
++ vsetivli a0, 0xb, e256, m8
|
|
|
++ vsetivli a0, 0xb, e512, m8
|
|
|
++ vsetivli a0, 0xb, e1024, m8
|
|
|
++ vsetivli a0, 0xb, e1024, m1
|
|
|
++ vsetivli a0, 0xb, e1024, mf2
|
|
|
++ vsetivli a0, 0xb, e512, mf4
|
|
|
++ vsetivli a0, 0xb, e256, mf8
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta
|
|
|
++ vsetivli a0, 0xb, e256, m2, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu
|
|
|
++ vsetivli a0, 0xb, e256, m2, mu
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta, mu
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu, mu
|
|
|
++
|
|
|
++ vle1.v v4, (a0)
|
|
|
++ vle1.v v4, 0(a0)
|
|
|
++ vse1.v v4, (a0)
|
|
|
++ vse1.v v4, 0(a0)
|
|
|
++
|
|
|
++
|
|
|
++ vluxei8.v v4, (a0), v12
|
|
|
++ vluxei8.v v4, 0(a0), v12
|
|
|
++ vluxei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei8.v v4, (a0), v12
|
|
|
++ vsuxei8.v v4, 0(a0), v12
|
|
|
++ vsuxei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++
|
|
|
++ vluxei16.v v4, (a0), v12
|
|
|
++ vluxei16.v v4, 0(a0), v12
|
|
|
++ vluxei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei16.v v4, (a0), v12
|
|
|
++ vsuxei16.v v4, 0(a0), v12
|
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++ vsuxei16.v v4, (a0), v12, v0.t
|
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++
|
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++
|
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++ vluxei32.v v4, (a0), v12
|
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++ vluxei32.v v4, 0(a0), v12
|
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++ vluxei32.v v4, (a0), v12, v0.t
|
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++ vsuxei32.v v4, (a0), v12
|
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++ vsuxei32.v v4, 0(a0), v12
|
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++ vsuxei32.v v4, (a0), v12, v0.t
|
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++
|
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++
|
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++ vluxei64.v v4, (a0), v12
|
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++ vluxei64.v v4, 0(a0), v12
|
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++ vluxei64.v v4, (a0), v12, v0.t
|
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++ vsuxei64.v v4, (a0), v12
|
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++ vsuxei64.v v4, 0(a0), v12
|
|
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++ vsuxei64.v v4, (a0), v12, v0.t
|
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++
|
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++ vle8ff.v v4, (a0)
|
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++ vle8ff.v v4, 0(a0)
|
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++ vle8ff.v v4, (a0), v0.t
|
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++
|
|
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++ vle16ff.v v4, (a0)
|
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++ vle16ff.v v4, 0(a0)
|
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++ vle16ff.v v4, (a0), v0.t
|
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++
|
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++ vle32ff.v v4, (a0)
|
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++ vle32ff.v v4, 0(a0)
|
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++ vle32ff.v v4, (a0), v0.t
|
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++
|
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++ vle64ff.v v4, (a0)
|
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++ vle64ff.v v4, 0(a0)
|
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++ vle64ff.v v4, (a0), v0.t
|
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++
|
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++ vlseg2e8.v v4, (a0)
|
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++ vlseg2e8.v v4, 0(a0)
|
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++ vlseg2e8.v v4, (a0), v0.t
|
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++ vsseg2e8.v v4, (a0)
|
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++ vsseg2e8.v v4, 0(a0)
|
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++ vsseg2e8.v v4, (a0), v0.t
|
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++
|
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++ vlseg3e8.v v4, (a0)
|
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++ vlseg3e8.v v4, 0(a0)
|
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++ vlseg3e8.v v4, (a0), v0.t
|
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++ vsseg3e8.v v4, (a0)
|
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++ vsseg3e8.v v4, 0(a0)
|
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++ vsseg3e8.v v4, (a0), v0.t
|
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++
|
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++ vlseg4e8.v v4, (a0)
|
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++ vlseg4e8.v v4, 0(a0)
|
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++ vlseg4e8.v v4, (a0), v0.t
|
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++ vsseg4e8.v v4, (a0)
|
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++ vsseg4e8.v v4, 0(a0)
|
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++ vsseg4e8.v v4, (a0), v0.t
|
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++
|
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++ vlseg5e8.v v4, (a0)
|
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++ vlseg5e8.v v4, 0(a0)
|
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++ vlseg5e8.v v4, (a0), v0.t
|
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++ vsseg5e8.v v4, (a0)
|
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++ vsseg5e8.v v4, 0(a0)
|
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++ vsseg5e8.v v4, (a0), v0.t
|
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++
|
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++ vlseg6e8.v v4, (a0)
|
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++ vlseg6e8.v v4, 0(a0)
|
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++ vlseg6e8.v v4, (a0), v0.t
|
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++ vsseg6e8.v v4, (a0)
|
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|
++ vsseg6e8.v v4, 0(a0)
|
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++ vsseg6e8.v v4, (a0), v0.t
|
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|
++
|
|
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++ vlseg7e8.v v4, (a0)
|
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++ vlseg7e8.v v4, 0(a0)
|
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++ vlseg7e8.v v4, (a0), v0.t
|
|
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++ vsseg7e8.v v4, (a0)
|
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++ vsseg7e8.v v4, 0(a0)
|
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|
++ vsseg7e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e8.v v4, (a0)
|
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++ vlseg8e8.v v4, 0(a0)
|
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|
++ vlseg8e8.v v4, (a0), v0.t
|
|
|
++ vsseg8e8.v v4, (a0)
|
|
|
++ vsseg8e8.v v4, 0(a0)
|
|
|
++ vsseg8e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16.v v4, (a0)
|
|
|
++ vlseg2e16.v v4, 0(a0)
|
|
|
++ vlseg2e16.v v4, (a0), v0.t
|
|
|
++ vsseg2e16.v v4, (a0)
|
|
|
++ vsseg2e16.v v4, 0(a0)
|
|
|
++ vsseg2e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e16.v v4, (a0)
|
|
|
++ vlseg3e16.v v4, 0(a0)
|
|
|
++ vlseg3e16.v v4, (a0), v0.t
|
|
|
++ vsseg3e16.v v4, (a0)
|
|
|
++ vsseg3e16.v v4, 0(a0)
|
|
|
++ vsseg3e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e16.v v4, (a0)
|
|
|
++ vlseg4e16.v v4, 0(a0)
|
|
|
++ vlseg4e16.v v4, (a0), v0.t
|
|
|
++ vsseg4e16.v v4, (a0)
|
|
|
++ vsseg4e16.v v4, 0(a0)
|
|
|
++ vsseg4e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e16.v v4, (a0)
|
|
|
++ vlseg5e16.v v4, 0(a0)
|
|
|
++ vlseg5e16.v v4, (a0), v0.t
|
|
|
++ vsseg5e16.v v4, (a0)
|
|
|
++ vsseg5e16.v v4, 0(a0)
|
|
|
++ vsseg5e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e16.v v4, (a0)
|
|
|
++ vlseg6e16.v v4, 0(a0)
|
|
|
++ vlseg6e16.v v4, (a0), v0.t
|
|
|
++ vsseg6e16.v v4, (a0)
|
|
|
++ vsseg6e16.v v4, 0(a0)
|
|
|
++ vsseg6e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e16.v v4, (a0)
|
|
|
++ vlseg7e16.v v4, 0(a0)
|
|
|
++ vlseg7e16.v v4, (a0), v0.t
|
|
|
++ vsseg7e16.v v4, (a0)
|
|
|
++ vsseg7e16.v v4, 0(a0)
|
|
|
++ vsseg7e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e16.v v4, (a0)
|
|
|
++ vlseg8e16.v v4, 0(a0)
|
|
|
++ vlseg8e16.v v4, (a0), v0.t
|
|
|
++ vsseg8e16.v v4, (a0)
|
|
|
++ vsseg8e16.v v4, 0(a0)
|
|
|
++ vsseg8e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e32.v v4, (a0)
|
|
|
++ vlseg2e32.v v4, 0(a0)
|
|
|
++ vlseg2e32.v v4, (a0), v0.t
|
|
|
++ vsseg2e32.v v4, (a0)
|
|
|
++ vsseg2e32.v v4, 0(a0)
|
|
|
++ vsseg2e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e32.v v4, (a0)
|
|
|
++ vlseg3e32.v v4, 0(a0)
|
|
|
++ vlseg3e32.v v4, (a0), v0.t
|
|
|
++ vsseg3e32.v v4, (a0)
|
|
|
++ vsseg3e32.v v4, 0(a0)
|
|
|
++ vsseg3e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e32.v v4, (a0)
|
|
|
++ vlseg4e32.v v4, 0(a0)
|
|
|
++ vlseg4e32.v v4, (a0), v0.t
|
|
|
++ vsseg4e32.v v4, (a0)
|
|
|
++ vsseg4e32.v v4, 0(a0)
|
|
|
++ vsseg4e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e32.v v4, (a0)
|
|
|
++ vlseg5e32.v v4, 0(a0)
|
|
|
++ vlseg5e32.v v4, (a0), v0.t
|
|
|
++ vsseg5e32.v v4, (a0)
|
|
|
++ vsseg5e32.v v4, 0(a0)
|
|
|
++ vsseg5e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e32.v v4, (a0)
|
|
|
++ vlseg6e32.v v4, 0(a0)
|
|
|
++ vlseg6e32.v v4, (a0), v0.t
|
|
|
++ vsseg6e32.v v4, (a0)
|
|
|
++ vsseg6e32.v v4, 0(a0)
|
|
|
++ vsseg6e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e32.v v4, (a0)
|
|
|
++ vlseg7e32.v v4, 0(a0)
|
|
|
++ vlseg7e32.v v4, (a0), v0.t
|
|
|
++ vsseg7e32.v v4, (a0)
|
|
|
++ vsseg7e32.v v4, 0(a0)
|
|
|
++ vsseg7e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e32.v v4, (a0)
|
|
|
++ vlseg8e32.v v4, 0(a0)
|
|
|
++ vlseg8e32.v v4, (a0), v0.t
|
|
|
++ vsseg8e32.v v4, (a0)
|
|
|
++ vsseg8e32.v v4, 0(a0)
|
|
|
++ vsseg8e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e64.v v4, (a0)
|
|
|
++ vlseg2e64.v v4, 0(a0)
|
|
|
++ vlseg2e64.v v4, (a0), v0.t
|
|
|
++ vsseg2e64.v v4, (a0)
|
|
|
++ vsseg2e64.v v4, 0(a0)
|
|
|
++ vsseg2e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e64.v v4, (a0)
|
|
|
++ vlseg3e64.v v4, 0(a0)
|
|
|
++ vlseg3e64.v v4, (a0), v0.t
|
|
|
++ vsseg3e64.v v4, (a0)
|
|
|
++ vsseg3e64.v v4, 0(a0)
|
|
|
++ vsseg3e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e64.v v4, (a0)
|
|
|
++ vlseg4e64.v v4, 0(a0)
|
|
|
++ vlseg4e64.v v4, (a0), v0.t
|
|
|
++ vsseg4e64.v v4, (a0)
|
|
|
++ vsseg4e64.v v4, 0(a0)
|
|
|
++ vsseg4e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e64.v v4, (a0)
|
|
|
++ vlseg5e64.v v4, 0(a0)
|
|
|
++ vlseg5e64.v v4, (a0), v0.t
|
|
|
++ vsseg5e64.v v4, (a0)
|
|
|
++ vsseg5e64.v v4, 0(a0)
|
|
|
++ vsseg5e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e64.v v4, (a0)
|
|
|
++ vlseg6e64.v v4, 0(a0)
|
|
|
++ vlseg6e64.v v4, (a0), v0.t
|
|
|
++ vsseg6e64.v v4, (a0)
|
|
|
++ vsseg6e64.v v4, 0(a0)
|
|
|
++ vsseg6e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e64.v v4, (a0)
|
|
|
++ vlseg7e64.v v4, 0(a0)
|
|
|
++ vlseg7e64.v v4, (a0), v0.t
|
|
|
++ vsseg7e64.v v4, (a0)
|
|
|
++ vsseg7e64.v v4, 0(a0)
|
|
|
++ vsseg7e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e64.v v4, (a0)
|
|
|
++ vlseg8e64.v v4, 0(a0)
|
|
|
++ vlseg8e64.v v4, (a0), v0.t
|
|
|
++ vsseg8e64.v v4, (a0)
|
|
|
++ vsseg8e64.v v4, 0(a0)
|
|
|
++ vsseg8e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlsseg2e8.v v4, (a0), a1
|
|
|
++ vlsseg2e8.v v4, 0(a0), a1
|
|
|
++ vlsseg2e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e8.v v4, (a0), a1
|
|
|
++ vssseg2e8.v v4, 0(a0), a1
|
|
|
++ vssseg2e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e8.v v4, (a0), a1
|
|
|
++ vlsseg3e8.v v4, 0(a0), a1
|
|
|
++ vlsseg3e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e8.v v4, (a0), a1
|
|
|
++ vssseg3e8.v v4, 0(a0), a1
|
|
|
++ vssseg3e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e8.v v4, (a0), a1
|
|
|
++ vlsseg4e8.v v4, 0(a0), a1
|
|
|
++ vlsseg4e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e8.v v4, (a0), a1
|
|
|
++ vssseg4e8.v v4, 0(a0), a1
|
|
|
++ vssseg4e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e8.v v4, (a0), a1
|
|
|
++ vlsseg5e8.v v4, 0(a0), a1
|
|
|
++ vlsseg5e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e8.v v4, (a0), a1
|
|
|
++ vssseg5e8.v v4, 0(a0), a1
|
|
|
++ vssseg5e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e8.v v4, (a0), a1
|
|
|
++ vlsseg6e8.v v4, 0(a0), a1
|
|
|
++ vlsseg6e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e8.v v4, (a0), a1
|
|
|
++ vssseg6e8.v v4, 0(a0), a1
|
|
|
++ vssseg6e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e8.v v4, (a0), a1
|
|
|
++ vlsseg7e8.v v4, 0(a0), a1
|
|
|
++ vlsseg7e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e8.v v4, (a0), a1
|
|
|
++ vssseg7e8.v v4, 0(a0), a1
|
|
|
++ vssseg7e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e8.v v4, (a0), a1
|
|
|
++ vlsseg8e8.v v4, 0(a0), a1
|
|
|
++ vlsseg8e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e8.v v4, (a0), a1
|
|
|
++ vssseg8e8.v v4, 0(a0), a1
|
|
|
++ vssseg8e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e16.v v4, (a0), a1
|
|
|
++ vlsseg2e16.v v4, 0(a0), a1
|
|
|
++ vlsseg2e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e16.v v4, (a0), a1
|
|
|
++ vssseg2e16.v v4, 0(a0), a1
|
|
|
++ vssseg2e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e16.v v4, (a0), a1
|
|
|
++ vlsseg3e16.v v4, 0(a0), a1
|
|
|
++ vlsseg3e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e16.v v4, (a0), a1
|
|
|
++ vssseg3e16.v v4, 0(a0), a1
|
|
|
++ vssseg3e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e16.v v4, (a0), a1
|
|
|
++ vlsseg4e16.v v4, 0(a0), a1
|
|
|
++ vlsseg4e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e16.v v4, (a0), a1
|
|
|
++ vssseg4e16.v v4, 0(a0), a1
|
|
|
++ vssseg4e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e16.v v4, (a0), a1
|
|
|
++ vlsseg5e16.v v4, 0(a0), a1
|
|
|
++ vlsseg5e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e16.v v4, (a0), a1
|
|
|
++ vssseg5e16.v v4, 0(a0), a1
|
|
|
++ vssseg5e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e16.v v4, (a0), a1
|
|
|
++ vlsseg6e16.v v4, 0(a0), a1
|
|
|
++ vlsseg6e16.v v4, (a0), a1, v0.t
|
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++ vssseg6e16.v v4, (a0), a1
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++ vssseg6e16.v v4, 0(a0), a1
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++ vssseg6e16.v v4, (a0), a1, v0.t
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++
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++ vlsseg7e16.v v4, (a0), a1
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++ vlsseg7e16.v v4, 0(a0), a1
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++ vlsseg7e16.v v4, (a0), a1, v0.t
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++ vssseg7e16.v v4, (a0), a1
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++ vssseg7e16.v v4, 0(a0), a1
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++ vssseg7e16.v v4, (a0), a1, v0.t
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++
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++ vlsseg8e16.v v4, (a0), a1
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++ vlsseg8e16.v v4, 0(a0), a1
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++ vlsseg8e16.v v4, (a0), a1, v0.t
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++ vssseg8e16.v v4, (a0), a1
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++ vssseg8e16.v v4, 0(a0), a1
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++ vssseg8e16.v v4, (a0), a1, v0.t
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++
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++ vlsseg2e32.v v4, (a0), a1
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++ vlsseg2e32.v v4, 0(a0), a1
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++ vlsseg2e32.v v4, (a0), a1, v0.t
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++ vssseg2e32.v v4, (a0), a1
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++ vssseg2e32.v v4, 0(a0), a1
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++ vssseg2e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg3e32.v v4, (a0), a1
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++ vlsseg3e32.v v4, 0(a0), a1
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++ vlsseg3e32.v v4, (a0), a1, v0.t
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++ vssseg3e32.v v4, (a0), a1
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++ vssseg3e32.v v4, 0(a0), a1
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++ vssseg3e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg4e32.v v4, (a0), a1
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++ vlsseg4e32.v v4, 0(a0), a1
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++ vlsseg4e32.v v4, (a0), a1, v0.t
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++ vssseg4e32.v v4, (a0), a1
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++ vssseg4e32.v v4, 0(a0), a1
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++ vssseg4e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg5e32.v v4, (a0), a1
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++ vlsseg5e32.v v4, 0(a0), a1
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++ vlsseg5e32.v v4, (a0), a1, v0.t
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++ vssseg5e32.v v4, (a0), a1
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++ vssseg5e32.v v4, 0(a0), a1
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++ vssseg5e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg6e32.v v4, (a0), a1
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++ vlsseg6e32.v v4, 0(a0), a1
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++ vlsseg6e32.v v4, (a0), a1, v0.t
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++ vssseg6e32.v v4, (a0), a1
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++ vssseg6e32.v v4, 0(a0), a1
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++ vssseg6e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg7e32.v v4, (a0), a1
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++ vlsseg7e32.v v4, 0(a0), a1
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++ vlsseg7e32.v v4, (a0), a1, v0.t
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++ vssseg7e32.v v4, (a0), a1
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++ vssseg7e32.v v4, 0(a0), a1
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++ vssseg7e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg8e32.v v4, (a0), a1
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++ vlsseg8e32.v v4, 0(a0), a1
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++ vlsseg8e32.v v4, (a0), a1, v0.t
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++ vssseg8e32.v v4, (a0), a1
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++ vssseg8e32.v v4, 0(a0), a1
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++ vssseg8e32.v v4, (a0), a1, v0.t
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++
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++ vlsseg2e64.v v4, (a0), a1
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++ vlsseg2e64.v v4, 0(a0), a1
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++ vlsseg2e64.v v4, (a0), a1, v0.t
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++ vssseg2e64.v v4, (a0), a1
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++ vssseg2e64.v v4, 0(a0), a1
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++ vssseg2e64.v v4, (a0), a1, v0.t
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++
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++ vlsseg3e64.v v4, (a0), a1
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++ vlsseg3e64.v v4, 0(a0), a1
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++ vlsseg3e64.v v4, (a0), a1, v0.t
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++ vssseg3e64.v v4, (a0), a1
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++ vssseg3e64.v v4, 0(a0), a1
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++ vssseg3e64.v v4, (a0), a1, v0.t
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++
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++ vlsseg4e64.v v4, (a0), a1
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++ vlsseg4e64.v v4, 0(a0), a1
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++ vlsseg4e64.v v4, (a0), a1, v0.t
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++ vssseg4e64.v v4, (a0), a1
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++ vssseg4e64.v v4, 0(a0), a1
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++ vssseg4e64.v v4, (a0), a1, v0.t
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++
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++ vlsseg5e64.v v4, (a0), a1
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++ vlsseg5e64.v v4, 0(a0), a1
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++ vlsseg5e64.v v4, (a0), a1, v0.t
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++ vssseg5e64.v v4, (a0), a1
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++ vssseg5e64.v v4, 0(a0), a1
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++ vssseg5e64.v v4, (a0), a1, v0.t
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++
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++ vlsseg6e64.v v4, (a0), a1
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++ vlsseg6e64.v v4, 0(a0), a1
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++ vlsseg6e64.v v4, (a0), a1, v0.t
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++ vssseg6e64.v v4, (a0), a1
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++ vssseg6e64.v v4, 0(a0), a1
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++ vssseg6e64.v v4, (a0), a1, v0.t
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++
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++ vlsseg7e64.v v4, (a0), a1
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++ vlsseg7e64.v v4, 0(a0), a1
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++ vlsseg7e64.v v4, (a0), a1, v0.t
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++ vssseg7e64.v v4, (a0), a1
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++ vssseg7e64.v v4, 0(a0), a1
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++ vssseg7e64.v v4, (a0), a1, v0.t
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++
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++ vlsseg8e64.v v4, (a0), a1
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++ vlsseg8e64.v v4, 0(a0), a1
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++ vlsseg8e64.v v4, (a0), a1, v0.t
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++ vssseg8e64.v v4, (a0), a1
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++ vssseg8e64.v v4, 0(a0), a1
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++ vssseg8e64.v v4, (a0), a1, v0.t
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++
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++ vloxseg2ei8.v v4, (a0), v12
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++ vloxseg2ei8.v v4, 0(a0), v12
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++ vloxseg2ei8.v v4, (a0), v12, v0.t
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++ vsoxseg2ei8.v v4, (a0), v12
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++ vsoxseg2ei8.v v4, 0(a0), v12
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++ vsoxseg2ei8.v v4, (a0), v12, v0.t
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++
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++ vloxseg3ei8.v v4, (a0), v12
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++ vloxseg3ei8.v v4, 0(a0), v12
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++ vloxseg3ei8.v v4, (a0), v12, v0.t
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++ vsoxseg3ei8.v v4, (a0), v12
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++ vsoxseg3ei8.v v4, 0(a0), v12
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++ vsoxseg3ei8.v v4, (a0), v12, v0.t
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++
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++ vloxseg4ei8.v v4, (a0), v12
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++ vloxseg4ei8.v v4, 0(a0), v12
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++ vloxseg4ei8.v v4, (a0), v12, v0.t
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++ vsoxseg4ei8.v v4, (a0), v12
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++ vsoxseg4ei8.v v4, 0(a0), v12
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++ vsoxseg4ei8.v v4, (a0), v12, v0.t
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++
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++ vloxseg5ei8.v v4, (a0), v12
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++ vloxseg5ei8.v v4, 0(a0), v12
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++ vloxseg5ei8.v v4, (a0), v12, v0.t
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++ vsoxseg5ei8.v v4, (a0), v12
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++ vsoxseg5ei8.v v4, 0(a0), v12
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++ vsoxseg5ei8.v v4, (a0), v12, v0.t
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++
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++ vloxseg6ei8.v v4, (a0), v12
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++ vloxseg6ei8.v v4, 0(a0), v12
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++ vloxseg6ei8.v v4, (a0), v12, v0.t
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++ vsoxseg6ei8.v v4, (a0), v12
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++ vsoxseg6ei8.v v4, 0(a0), v12
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++ vsoxseg6ei8.v v4, (a0), v12, v0.t
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++
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++ vloxseg7ei8.v v4, (a0), v12
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++ vloxseg7ei8.v v4, 0(a0), v12
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++ vloxseg7ei8.v v4, (a0), v12, v0.t
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++ vsoxseg7ei8.v v4, (a0), v12
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++ vsoxseg7ei8.v v4, 0(a0), v12
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++ vsoxseg7ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg8ei8.v v4, (a0), v12
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++ vloxseg8ei8.v v4, 0(a0), v12
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++ vloxseg8ei8.v v4, (a0), v12, v0.t
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++ vsoxseg8ei8.v v4, (a0), v12
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++ vsoxseg8ei8.v v4, 0(a0), v12
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++ vsoxseg8ei8.v v4, (a0), v12, v0.t
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++
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++ vloxseg2ei16.v v4, (a0), v12
|
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++ vloxseg2ei16.v v4, 0(a0), v12
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++ vloxseg2ei16.v v4, (a0), v12, v0.t
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++ vsoxseg2ei16.v v4, (a0), v12
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++ vsoxseg2ei16.v v4, 0(a0), v12
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++ vsoxseg2ei16.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg3ei16.v v4, (a0), v12
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++ vloxseg3ei16.v v4, 0(a0), v12
|
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++ vloxseg3ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg3ei16.v v4, (a0), v12
|
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++ vsoxseg3ei16.v v4, 0(a0), v12
|
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++ vsoxseg3ei16.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg4ei16.v v4, (a0), v12
|
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++ vloxseg4ei16.v v4, 0(a0), v12
|
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++ vloxseg4ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei16.v v4, (a0), v12
|
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++ vsoxseg4ei16.v v4, 0(a0), v12
|
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++ vsoxseg4ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg5ei16.v v4, (a0), v12
|
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++ vloxseg5ei16.v v4, 0(a0), v12
|
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++ vloxseg5ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg5ei16.v v4, (a0), v12
|
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++ vsoxseg5ei16.v v4, 0(a0), v12
|
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++ vsoxseg5ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg6ei16.v v4, (a0), v12
|
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++ vloxseg6ei16.v v4, 0(a0), v12
|
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++ vloxseg6ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg6ei16.v v4, (a0), v12
|
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++ vsoxseg6ei16.v v4, 0(a0), v12
|
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++ vsoxseg6ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg7ei16.v v4, (a0), v12
|
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++ vloxseg7ei16.v v4, 0(a0), v12
|
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++ vloxseg7ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg7ei16.v v4, (a0), v12
|
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++ vsoxseg7ei16.v v4, 0(a0), v12
|
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++ vsoxseg7ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg8ei16.v v4, (a0), v12
|
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++ vloxseg8ei16.v v4, 0(a0), v12
|
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++ vloxseg8ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg8ei16.v v4, (a0), v12
|
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++ vsoxseg8ei16.v v4, 0(a0), v12
|
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++ vsoxseg8ei16.v v4, (a0), v12, v0.t
|
|
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++
|
|
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++ vloxseg2ei32.v v4, (a0), v12
|
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++ vloxseg2ei32.v v4, 0(a0), v12
|
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++ vloxseg2ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg2ei32.v v4, (a0), v12
|
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++ vsoxseg2ei32.v v4, 0(a0), v12
|
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++ vsoxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg3ei32.v v4, (a0), v12
|
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++ vloxseg3ei32.v v4, 0(a0), v12
|
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++ vloxseg3ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg3ei32.v v4, (a0), v12
|
|
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++ vsoxseg3ei32.v v4, 0(a0), v12
|
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++ vsoxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
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++ vloxseg4ei32.v v4, (a0), v12
|
|
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++ vloxseg4ei32.v v4, 0(a0), v12
|
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++ vloxseg4ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei32.v v4, (a0), v12
|
|
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++ vsoxseg4ei32.v v4, 0(a0), v12
|
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++ vsoxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
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++ vloxseg5ei32.v v4, (a0), v12
|
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++ vloxseg5ei32.v v4, 0(a0), v12
|
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++ vloxseg5ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg5ei32.v v4, (a0), v12
|
|
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++ vsoxseg5ei32.v v4, 0(a0), v12
|
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++ vsoxseg5ei32.v v4, (a0), v12, v0.t
|
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|
++
|
|
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++ vloxseg6ei32.v v4, (a0), v12
|
|
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++ vloxseg6ei32.v v4, 0(a0), v12
|
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++ vloxseg6ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg6ei32.v v4, (a0), v12
|
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|
++ vsoxseg6ei32.v v4, 0(a0), v12
|
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++ vsoxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg7ei32.v v4, (a0), v12
|
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++ vloxseg7ei32.v v4, 0(a0), v12
|
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++ vloxseg7ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg7ei32.v v4, (a0), v12
|
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++ vsoxseg7ei32.v v4, 0(a0), v12
|
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++ vsoxseg7ei32.v v4, (a0), v12, v0.t
|
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|
++
|
|
|
++ vloxseg8ei32.v v4, (a0), v12
|
|
|
++ vloxseg8ei32.v v4, 0(a0), v12
|
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++ vloxseg8ei32.v v4, (a0), v12, v0.t
|
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|
++ vsoxseg8ei32.v v4, (a0), v12
|
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++ vsoxseg8ei32.v v4, 0(a0), v12
|
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++ vsoxseg8ei32.v v4, (a0), v12, v0.t
|
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|
++
|
|
|
++ vloxseg2ei64.v v4, (a0), v12
|
|
|
++ vloxseg2ei64.v v4, 0(a0), v12
|
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++ vloxseg2ei64.v v4, (a0), v12, v0.t
|
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++ vsoxseg2ei64.v v4, (a0), v12
|
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++ vsoxseg2ei64.v v4, 0(a0), v12
|
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++ vsoxseg2ei64.v v4, (a0), v12, v0.t
|
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|
++
|
|
|
++ vloxseg3ei64.v v4, (a0), v12
|
|
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++ vloxseg3ei64.v v4, 0(a0), v12
|
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++ vloxseg3ei64.v v4, (a0), v12, v0.t
|
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|
++ vsoxseg3ei64.v v4, (a0), v12
|
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++ vsoxseg3ei64.v v4, 0(a0), v12
|
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|
++ vsoxseg3ei64.v v4, (a0), v12, v0.t
|
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|
++
|
|
|
++ vloxseg4ei64.v v4, (a0), v12
|
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|
++ vloxseg4ei64.v v4, 0(a0), v12
|
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++ vloxseg4ei64.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei64.v v4, (a0), v12
|
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|
++ vsoxseg4ei64.v v4, 0(a0), v12
|
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++ vsoxseg4ei64.v v4, (a0), v12, v0.t
|
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++
|
|
|
++ vloxseg5ei64.v v4, (a0), v12
|
|
|
++ vloxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg5ei64.v v4, (a0), v12
|
|
|
++ vsoxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg6ei64.v v4, (a0), v12
|
|
|
++ vloxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg6ei64.v v4, (a0), v12
|
|
|
++ vsoxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg7ei64.v v4, (a0), v12
|
|
|
++ vloxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg7ei64.v v4, (a0), v12
|
|
|
++ vsoxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg8ei64.v v4, (a0), v12
|
|
|
++ vloxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg8ei64.v v4, (a0), v12
|
|
|
++ vsoxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei8.v v4, (a0), v12
|
|
|
++ vluxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei8.v v4, (a0), v12
|
|
|
++ vsuxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei8.v v4, (a0), v12
|
|
|
++ vluxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei8.v v4, (a0), v12
|
|
|
++ vsuxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei8.v v4, (a0), v12
|
|
|
++ vluxseg4ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei8.v v4, (a0), v12
|
|
|
++ vsuxseg4ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei8.v v4, (a0), v12
|
|
|
++ vluxseg5ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei8.v v4, (a0), v12
|
|
|
++ vsuxseg5ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei8.v v4, (a0), v12
|
|
|
++ vluxseg6ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei8.v v4, (a0), v12
|
|
|
++ vsuxseg6ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei8.v v4, (a0), v12
|
|
|
++ vluxseg7ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei8.v v4, (a0), v12
|
|
|
++ vsuxseg7ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei8.v v4, (a0), v12
|
|
|
++ vluxseg8ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei8.v v4, (a0), v12
|
|
|
++ vsuxseg8ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei16.v v4, (a0), v12
|
|
|
++ vluxseg2ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei16.v v4, (a0), v12
|
|
|
++ vsuxseg2ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei16.v v4, (a0), v12
|
|
|
++ vluxseg3ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei16.v v4, (a0), v12
|
|
|
++ vsuxseg3ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei16.v v4, (a0), v12
|
|
|
++ vluxseg4ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei16.v v4, (a0), v12
|
|
|
++ vsuxseg4ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei16.v v4, (a0), v12
|
|
|
++ vluxseg5ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei16.v v4, (a0), v12
|
|
|
++ vsuxseg5ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei16.v v4, (a0), v12
|
|
|
++ vluxseg6ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei16.v v4, (a0), v12
|
|
|
++ vsuxseg6ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei16.v v4, (a0), v12
|
|
|
++ vluxseg7ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei16.v v4, (a0), v12
|
|
|
++ vsuxseg7ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei16.v v4, (a0), v12
|
|
|
++ vluxseg8ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei16.v v4, (a0), v12
|
|
|
++ vsuxseg8ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei32.v v4, (a0), v12
|
|
|
++ vluxseg2ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei32.v v4, (a0), v12
|
|
|
++ vsuxseg2ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei32.v v4, (a0), v12
|
|
|
++ vluxseg3ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei32.v v4, (a0), v12
|
|
|
++ vsuxseg3ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei32.v v4, (a0), v12
|
|
|
++ vluxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei32.v v4, (a0), v12
|
|
|
++ vsuxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei32.v v4, (a0), v12
|
|
|
++ vluxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei32.v v4, (a0), v12
|
|
|
++ vsuxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei32.v v4, (a0), v12
|
|
|
++ vluxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei32.v v4, (a0), v12
|
|
|
++ vsuxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei32.v v4, (a0), v12
|
|
|
++ vluxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei32.v v4, (a0), v12
|
|
|
++ vsuxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei32.v v4, (a0), v12
|
|
|
++ vluxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei32.v v4, (a0), v12
|
|
|
++ vsuxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei64.v v4, (a0), v12
|
|
|
++ vluxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei64.v v4, (a0), v12
|
|
|
++ vsuxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei64.v v4, (a0), v12
|
|
|
++ vluxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei64.v v4, (a0), v12
|
|
|
++ vsuxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei64.v v4, (a0), v12
|
|
|
++ vluxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei64.v v4, (a0), v12
|
|
|
++ vsuxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei64.v v4, (a0), v12
|
|
|
++ vluxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei64.v v4, (a0), v12
|
|
|
++ vsuxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei64.v v4, (a0), v12
|
|
|
++ vluxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei64.v v4, (a0), v12
|
|
|
++ vsuxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei64.v v4, (a0), v12
|
|
|
++ vluxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei64.v v4, (a0), v12
|
|
|
++ vsuxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei64.v v4, (a0), v12
|
|
|
++ vluxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei64.v v4, (a0), v12
|
|
|
++ vsuxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vlseg2e8ff.v v4, (a0)
|
|
|
++ vlseg2e8ff.v v4, 0(a0)
|
|
|
++ vlseg2e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e8ff.v v4, (a0)
|
|
|
++ vlseg3e8ff.v v4, 0(a0)
|
|
|
++ vlseg3e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e8ff.v v4, (a0)
|
|
|
++ vlseg4e8ff.v v4, 0(a0)
|
|
|
++ vlseg4e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e8ff.v v4, (a0)
|
|
|
++ vlseg5e8ff.v v4, 0(a0)
|
|
|
++ vlseg5e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e8ff.v v4, (a0)
|
|
|
++ vlseg6e8ff.v v4, 0(a0)
|
|
|
++ vlseg6e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e8ff.v v4, (a0)
|
|
|
++ vlseg7e8ff.v v4, 0(a0)
|
|
|
++ vlseg7e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e8ff.v v4, (a0)
|
|
|
++ vlseg8e8ff.v v4, 0(a0)
|
|
|
++ vlseg8e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16ff.v v4, (a0)
|
|
|
++ vlseg2e16ff.v v4, 0(a0)
|
|
|
++ vlseg2e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e16ff.v v4, (a0)
|
|
|
++ vlseg3e16ff.v v4, 0(a0)
|
|
|
++ vlseg3e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e16ff.v v4, (a0)
|
|
|
++ vlseg4e16ff.v v4, 0(a0)
|
|
|
++ vlseg4e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e16ff.v v4, (a0)
|
|
|
++ vlseg5e16ff.v v4, 0(a0)
|
|
|
++ vlseg5e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e16ff.v v4, (a0)
|
|
|
++ vlseg6e16ff.v v4, 0(a0)
|
|
|
++ vlseg6e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e16ff.v v4, (a0)
|
|
|
++ vlseg7e16ff.v v4, 0(a0)
|
|
|
++ vlseg7e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e16ff.v v4, (a0)
|
|
|
++ vlseg8e16ff.v v4, 0(a0)
|
|
|
++ vlseg8e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e32ff.v v4, (a0)
|
|
|
++ vlseg2e32ff.v v4, 0(a0)
|
|
|
++ vlseg2e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e32ff.v v4, (a0)
|
|
|
++ vlseg3e32ff.v v4, 0(a0)
|
|
|
++ vlseg3e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e32ff.v v4, (a0)
|
|
|
++ vlseg4e32ff.v v4, 0(a0)
|
|
|
++ vlseg4e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e32ff.v v4, (a0)
|
|
|
++ vlseg5e32ff.v v4, 0(a0)
|
|
|
++ vlseg5e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e32ff.v v4, (a0)
|
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++ vlseg6e32ff.v v4, 0(a0)
|
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++ vlseg6e32ff.v v4, (a0), v0.t
|
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++
|
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++ vlseg7e32ff.v v4, (a0)
|
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++ vlseg7e32ff.v v4, 0(a0)
|
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++ vlseg7e32ff.v v4, (a0), v0.t
|
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++
|
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++ vlseg8e32ff.v v4, (a0)
|
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|
++ vlseg8e32ff.v v4, 0(a0)
|
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++ vlseg8e32ff.v v4, (a0), v0.t
|
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|
++
|
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++ vlseg2e64ff.v v4, (a0)
|
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++ vlseg2e64ff.v v4, 0(a0)
|
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++ vlseg2e64ff.v v4, (a0), v0.t
|
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|
++
|
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++ vlseg3e64ff.v v4, (a0)
|
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++ vlseg3e64ff.v v4, 0(a0)
|
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++ vlseg3e64ff.v v4, (a0), v0.t
|
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|
++
|
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|
++ vlseg4e64ff.v v4, (a0)
|
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++ vlseg4e64ff.v v4, 0(a0)
|
|
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++ vlseg4e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e64ff.v v4, (a0)
|
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|
++ vlseg5e64ff.v v4, 0(a0)
|
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|
++ vlseg5e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e64ff.v v4, (a0)
|
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++ vlseg6e64ff.v v4, 0(a0)
|
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|
++ vlseg6e64ff.v v4, (a0), v0.t
|
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|
++
|
|
|
++ vlseg7e64ff.v v4, (a0)
|
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++ vlseg7e64ff.v v4, 0(a0)
|
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|
++ vlseg7e64ff.v v4, (a0), v0.t
|
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|
++
|
|
|
++ vlseg8e64ff.v v4, (a0)
|
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++ vlseg8e64ff.v v4, 0(a0)
|
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|
++ vlseg8e64ff.v v4, (a0), v0.t
|
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|
++
|
|
|
++ vl2r.v v2, (a0)
|
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|
++ vl2r.v v2, 0(a0)
|
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|
++ vl2re8.v v2, (a0)
|
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|
++ vl2re8.v v2, 0(a0)
|
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|
++ vl2re16.v v2, (a0)
|
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|
++ vl2re16.v v2, 0(a0)
|
|
|
++ vl2re32.v v2, (a0)
|
|
|
++ vl2re32.v v2, 0(a0)
|
|
|
++ vl2re64.v v2, (a0)
|
|
|
++ vl2re64.v v2, 0(a0)
|
|
|
++
|
|
|
++ vl4r.v v4, (a0)
|
|
|
++ vl4r.v v4, 0(a0)
|
|
|
++ vl4re8.v v4, (a0)
|
|
|
++ vl4re8.v v4, 0(a0)
|
|
|
++ vl4re16.v v4, (a0)
|
|
|
++ vl4re16.v v4, 0(a0)
|
|
|
++ vl4re32.v v4, (a0)
|
|
|
++ vl4re32.v v4, 0(a0)
|
|
|
++ vl4re64.v v4, (a0)
|
|
|
++ vl4re64.v v4, 0(a0)
|
|
|
++
|
|
|
++ vl8r.v v8, (a0)
|
|
|
++ vl8r.v v8, 0(a0)
|
|
|
++ vl8re8.v v8, (a0)
|
|
|
++ vl8re8.v v8, 0(a0)
|
|
|
++ vl8re16.v v8, (a0)
|
|
|
++ vl8re16.v v8, 0(a0)
|
|
|
++ vl8re32.v v8, (a0)
|
|
|
++ vl8re32.v v8, 0(a0)
|
|
|
++ vl8re64.v v8, (a0)
|
|
|
++ vl8re64.v v8, 0(a0)
|
|
|
++
|
|
|
++ vs2r.v v2, (a1)
|
|
|
++ vs2r.v v2, 0(a1)
|
|
|
++ vs4r.v v4, (a1)
|
|
|
++ vs4r.v v4, 0(a1)
|
|
|
++ vs8r.v v8, (a1)
|
|
|
++ vs8r.v v8, 0(a1)
|
|
|
++
|
|
|
++ vamoaddei8.v v4, (a1), v8, v4
|
|
|
++ vamoaddei8.v x0, (a1), v8, v4
|
|
|
++ vamoaddei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v v4, (a1), v8, v4
|
|
|
++ vamoswapei8.v x0, (a1), v8, v4
|
|
|
++ vamoswapei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v4, (a1), v8, v4
|
|
|
++ vamoxorei8.v x0, (a1), v8, v4
|
|
|
++ vamoxorei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v v4, (a1), v8, v4
|
|
|
++ vamoandei8.v x0, (a1), v8, v4
|
|
|
++ vamoandei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v v4, (a1), v8, v4
|
|
|
++ vamoorei8.v x0, (a1), v8, v4
|
|
|
++ vamoorei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v4, (a1), v8, v4
|
|
|
++ vamominei8.v x0, (a1), v8, v4
|
|
|
++ vamominei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v v4, (a1), v8, v4
|
|
|
++ vamomaxei8.v x0, (a1), v8, v4
|
|
|
++ vamomaxei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v v4, (a1), v8, v4
|
|
|
++ vamominuei8.v x0, (a1), v8, v4
|
|
|
++ vamominuei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei8.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v4, 0(a1), v8, v4
|
|
|
++ vamominei8.v x0, 0(a1), v8, v4
|
|
|
++ vamominei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei8.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei8.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei8.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v4, (a1), v8, v4
|
|
|
++ vamoaddei16.v x0, (a1), v8, v4
|
|
|
++ vamoaddei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v v4, (a1), v8, v4
|
|
|
++ vamoswapei16.v x0, (a1), v8, v4
|
|
|
++ vamoswapei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v4, (a1), v8, v4
|
|
|
++ vamoxorei16.v x0, (a1), v8, v4
|
|
|
++ vamoxorei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v v4, (a1), v8, v4
|
|
|
++ vamoandei16.v x0, (a1), v8, v4
|
|
|
++ vamoandei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v v4, (a1), v8, v4
|
|
|
++ vamoorei16.v x0, (a1), v8, v4
|
|
|
++ vamoorei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v4, (a1), v8, v4
|
|
|
++ vamominei16.v x0, (a1), v8, v4
|
|
|
++ vamominei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v v4, (a1), v8, v4
|
|
|
++ vamomaxei16.v x0, (a1), v8, v4
|
|
|
++ vamomaxei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v v4, (a1), v8, v4
|
|
|
++ vamominuei16.v x0, (a1), v8, v4
|
|
|
++ vamominuei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei16.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v4, 0(a1), v8, v4
|
|
|
++ vamominei16.v x0, 0(a1), v8, v4
|
|
|
++ vamominei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei16.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei16.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei16.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v4, (a1), v8, v4
|
|
|
++ vamoaddei32.v x0, (a1), v8, v4
|
|
|
++ vamoaddei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v v4, (a1), v8, v4
|
|
|
++ vamoswapei32.v x0, (a1), v8, v4
|
|
|
++ vamoswapei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v4, (a1), v8, v4
|
|
|
++ vamoxorei32.v x0, (a1), v8, v4
|
|
|
++ vamoxorei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v v4, (a1), v8, v4
|
|
|
++ vamoandei32.v x0, (a1), v8, v4
|
|
|
++ vamoandei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v v4, (a1), v8, v4
|
|
|
++ vamoorei32.v x0, (a1), v8, v4
|
|
|
++ vamoorei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v4, (a1), v8, v4
|
|
|
++ vamominei32.v x0, (a1), v8, v4
|
|
|
++ vamominei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v v4, (a1), v8, v4
|
|
|
++ vamomaxei32.v x0, (a1), v8, v4
|
|
|
++ vamomaxei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v v4, (a1), v8, v4
|
|
|
++ vamominuei32.v x0, (a1), v8, v4
|
|
|
++ vamominuei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei32.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v4, 0(a1), v8, v4
|
|
|
++ vamominei32.v x0, 0(a1), v8, v4
|
|
|
++ vamominei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei32.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei32.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei32.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v4, (a1), v8, v4
|
|
|
++ vamoaddei64.v x0, (a1), v8, v4
|
|
|
++ vamoaddei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v v4, (a1), v8, v4
|
|
|
++ vamoswapei64.v x0, (a1), v8, v4
|
|
|
++ vamoswapei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v4, (a1), v8, v4
|
|
|
++ vamoxorei64.v x0, (a1), v8, v4
|
|
|
++ vamoxorei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v v4, (a1), v8, v4
|
|
|
++ vamoandei64.v x0, (a1), v8, v4
|
|
|
++ vamoandei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v v4, (a1), v8, v4
|
|
|
++ vamoorei64.v x0, (a1), v8, v4
|
|
|
++ vamoorei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v4, (a1), v8, v4
|
|
|
++ vamominei64.v x0, (a1), v8, v4
|
|
|
++ vamominei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v v4, (a1), v8, v4
|
|
|
++ vamomaxei64.v x0, (a1), v8, v4
|
|
|
++ vamomaxei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v v4, (a1), v8, v4
|
|
|
++ vamominuei64.v x0, (a1), v8, v4
|
|
|
++ vamominuei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei64.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v4, 0(a1), v8, v4
|
|
|
++ vamominei64.v x0, 0(a1), v8, v4
|
|
|
++ vamominei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei64.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei64.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei64.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ # Aliases
|
|
|
++ vwcvt.x.x.v v4, v8
|
|
|
++ vwcvtu.x.x.v v4, v8
|
|
|
++ vwcvt.x.x.v v4, v8, v0.t
|
|
|
++ vwcvtu.x.x.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vwaddu.vv v4, v8, v12
|
|
|
++ vwaddu.vx v4, v8, a1
|
|
|
++ vwaddu.vv v4, v8, v12, v0.t
|
|
|
++ vwaddu.vx v4, v8, a1, v0.t
|
|
|
++ vwsubu.vv v4, v8, v12
|
|
|
++ vwsubu.vx v4, v8, a1
|
|
|
++ vwsubu.vv v4, v8, v12, v0.t
|
|
|
++ vwsubu.vx v4, v8, a1, v0.t
|
|
|
++ vwadd.vv v4, v8, v12
|
|
|
++ vwadd.vx v4, v8, a1
|
|
|
++ vwadd.vv v4, v8, v12, v0.t
|
|
|
++ vwadd.vx v4, v8, a1, v0.t
|
|
|
++ vwsub.vv v4, v8, v12
|
|
|
++ vwsub.vx v4, v8, a1
|
|
|
++ vwsub.vv v4, v8, v12, v0.t
|
|
|
++ vwsub.vx v4, v8, a1, v0.t
|
|
|
++ vwaddu.wv v4, v8, v12
|
|
|
++ vwaddu.wx v4, v8, a1
|
|
|
++ vwaddu.wv v4, v8, v12, v0.t
|
|
|
++ vwaddu.wx v4, v8, a1, v0.t
|
|
|
++ vwsubu.wv v4, v8, v12
|
|
|
++ vwsubu.wx v4, v8, a1
|
|
|
++ vwsubu.wv v4, v8, v12, v0.t
|
|
|
++ vwsubu.wx v4, v8, a1, v0.t
|
|
|
++ vwadd.wv v4, v8, v12
|
|
|
++ vwadd.wx v4, v8, a1
|
|
|
++ vwadd.wv v4, v8, v12, v0.t
|
|
|
++ vwadd.wx v4, v8, a1, v0.t
|
|
|
++ vwsub.wv v4, v8, v12
|
|
|
++ vwsub.wx v4, v8, a1
|
|
|
++ vwsub.wv v4, v8, v12, v0.t
|
|
|
++ vwsub.wx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vsll.vv v4, v8, v12
|
|
|
++ vsll.vx v4, v8, a1
|
|
|
++ vsll.vi v4, v8, 1
|
|
|
++ vsll.vi v4, v8, 31
|
|
|
++ vsll.vv v4, v8, v12, v0.t
|
|
|
++ vsll.vx v4, v8, a1, v0.t
|
|
|
++ vsll.vi v4, v8, 1, v0.t
|
|
|
++ vsll.vi v4, v8, 31, v0.t
|
|
|
++ vsrl.vv v4, v8, v12
|
|
|
++ vsrl.vx v4, v8, a1
|
|
|
++ vsrl.vi v4, v8, 1
|
|
|
++ vsrl.vi v4, v8, 31
|
|
|
++ vsrl.vv v4, v8, v12, v0.t
|
|
|
++ vsrl.vx v4, v8, a1, v0.t
|
|
|
++ vsrl.vi v4, v8, 1, v0.t
|
|
|
++ vsrl.vi v4, v8, 31, v0.t
|
|
|
++ vsra.vv v4, v8, v12
|
|
|
++ vsra.vx v4, v8, a1
|
|
|
++ vsra.vi v4, v8, 1
|
|
|
++ vsra.vi v4, v8, 31
|
|
|
++ vsra.vv v4, v8, v12, v0.t
|
|
|
++ vsra.vx v4, v8, a1, v0.t
|
|
|
++ vsra.vi v4, v8, 1, v0.t
|
|
|
++ vsra.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vncvt.x.x.w v4, v8
|
|
|
++ vncvt.x.x.w v4, v8, v0.t
|
|
|
++
|
|
|
++ vnsrl.wv v4, v8, v12
|
|
|
++ vnsrl.wx v4, v8, a1
|
|
|
++ vnsrl.wi v4, v8, 1
|
|
|
++ vnsrl.wi v4, v8, 31
|
|
|
++ vnsrl.wv v4, v8, v12, v0.t
|
|
|
++ vnsrl.wx v4, v8, a1, v0.t
|
|
|
++ vnsrl.wi v4, v8, 1, v0.t
|
|
|
++ vnsrl.wi v4, v8, 31, v0.t
|
|
|
++ vnsra.wv v4, v8, v12
|
|
|
++ vnsra.wx v4, v8, a1
|
|
|
++ vnsra.wi v4, v8, 1
|
|
|
++ vnsra.wi v4, v8, 31
|
|
|
++ vnsra.wv v4, v8, v12, v0.t
|
|
|
++ vnsra.wx v4, v8, a1, v0.t
|
|
|
++ vnsra.wi v4, v8, 1, v0.t
|
|
|
++ vnsra.wi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vwmul.vv v4, v8, v12
|
|
|
++ vwmul.vx v4, v8, a1
|
|
|
++ vwmul.vv v4, v8, v12, v0.t
|
|
|
++ vwmul.vx v4, v8, a1, v0.t
|
|
|
++ vwmulu.vv v4, v8, v12
|
|
|
++ vwmulu.vx v4, v8, a1
|
|
|
++ vwmulu.vv v4, v8, v12, v0.t
|
|
|
++ vwmulu.vx v4, v8, a1, v0.t
|
|
|
++ vwmulsu.vv v4, v8, v12
|
|
|
++ vwmulsu.vx v4, v8, a1
|
|
|
++ vwmulsu.vv v4, v8, v12, v0.t
|
|
|
++ vwmulsu.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vwmaccu.vv v4, v12, v8
|
|
|
++ vwmaccu.vx v4, a1, v8
|
|
|
++ vwmaccu.vv v4, v12, v8, v0.t
|
|
|
++ vwmaccu.vx v4, a1, v8, v0.t
|
|
|
++ vwmacc.vv v4, v12, v8
|
|
|
++ vwmacc.vx v4, a1, v8
|
|
|
++ vwmacc.vv v4, v12, v8, v0.t
|
|
|
++ vwmacc.vx v4, a1, v8, v0.t
|
|
|
++ vwmaccsu.vv v4, v12, v8
|
|
|
++ vwmaccsu.vx v4, a1, v8
|
|
|
++ vwmaccsu.vv v4, v12, v8, v0.t
|
|
|
++ vwmaccsu.vx v4, a1, v8, v0.t
|
|
|
++ vwmaccus.vx v4, a1, v8
|
|
|
++ vwmaccus.vx v4, a1, v8, v0.t
|
|
|
++
|
|
|
++ vsaddu.vv v4, v8, v12
|
|
|
++ vsaddu.vx v4, v8, a1
|
|
|
++ vsaddu.vi v4, v8, 15
|
|
|
++ vsaddu.vi v4, v8, -16
|
|
|
++ vsaddu.vv v4, v8, v12, v0.t
|
|
|
++ vsaddu.vx v4, v8, a1, v0.t
|
|
|
++ vsaddu.vi v4, v8, 15, v0.t
|
|
|
++ vsaddu.vi v4, v8, -16, v0.t
|
|
|
++ vsadd.vv v4, v8, v12
|
|
|
++ vsadd.vx v4, v8, a1
|
|
|
++ vsadd.vi v4, v8, 15
|
|
|
++ vsadd.vi v4, v8, -16
|
|
|
++ vsadd.vv v4, v8, v12, v0.t
|
|
|
++ vsadd.vx v4, v8, a1, v0.t
|
|
|
++ vsadd.vi v4, v8, 15, v0.t
|
|
|
++ vsadd.vi v4, v8, -16, v0.t
|
|
|
++ vssubu.vv v4, v8, v12
|
|
|
++ vssubu.vx v4, v8, a1
|
|
|
++ vssubu.vv v4, v8, v12, v0.t
|
|
|
++ vssubu.vx v4, v8, a1, v0.t
|
|
|
++ vssub.vv v4, v8, v12
|
|
|
++ vssub.vx v4, v8, a1
|
|
|
++ vssub.vv v4, v8, v12, v0.t
|
|
|
++ vssub.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vaaddu.vv v4, v8, v12
|
|
|
++ vaaddu.vx v4, v8, a1
|
|
|
++ vaaddu.vv v4, v8, v12, v0.t
|
|
|
++ vaaddu.vx v4, v8, a1, v0.t
|
|
|
++ vaadd.vv v4, v8, v12
|
|
|
++ vaadd.vx v4, v8, a1
|
|
|
++ vaadd.vv v4, v8, v12, v0.t
|
|
|
++ vaadd.vx v4, v8, a1, v0.t
|
|
|
++ vasubu.vv v4, v8, v12
|
|
|
++ vasubu.vx v4, v8, a1
|
|
|
++ vasubu.vv v4, v8, v12, v0.t
|
|
|
++ vasubu.vx v4, v8, a1, v0.t
|
|
|
++ vasub.vv v4, v8, v12
|
|
|
++ vasub.vx v4, v8, a1
|
|
|
++ vasub.vv v4, v8, v12, v0.t
|
|
|
++ vasub.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vsmul.vv v4, v8, v12
|
|
|
++ vsmul.vx v4, v8, a1
|
|
|
++ vsmul.vv v4, v8, v12, v0.t
|
|
|
++ vsmul.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vssrl.vv v4, v8, v12
|
|
|
++ vssrl.vx v4, v8, a1
|
|
|
++ vssrl.vi v4, v8, 1
|
|
|
++ vssrl.vi v4, v8, 31
|
|
|
++ vssrl.vv v4, v8, v12, v0.t
|
|
|
++ vssrl.vx v4, v8, a1, v0.t
|
|
|
++ vssrl.vi v4, v8, 1, v0.t
|
|
|
++ vssrl.vi v4, v8, 31, v0.t
|
|
|
++ vssra.vv v4, v8, v12
|
|
|
++ vssra.vx v4, v8, a1
|
|
|
++ vssra.vi v4, v8, 1
|
|
|
++ vssra.vi v4, v8, 31
|
|
|
++ vssra.vv v4, v8, v12, v0.t
|
|
|
++ vssra.vx v4, v8, a1, v0.t
|
|
|
++ vssra.vi v4, v8, 1, v0.t
|
|
|
++ vssra.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vnclipu.wv v4, v8, v12
|
|
|
++ vnclipu.wx v4, v8, a1
|
|
|
++ vnclipu.wi v4, v8, 1
|
|
|
++ vnclipu.wi v4, v8, 31
|
|
|
++ vnclipu.wv v4, v8, v12, v0.t
|
|
|
++ vnclipu.wx v4, v8, a1, v0.t
|
|
|
++ vnclipu.wi v4, v8, 1, v0.t
|
|
|
++ vnclipu.wi v4, v8, 31, v0.t
|
|
|
++ vnclip.wv v4, v8, v12
|
|
|
++ vnclip.wx v4, v8, a1
|
|
|
++ vnclip.wi v4, v8, 1
|
|
|
++ vnclip.wi v4, v8, 31
|
|
|
++ vnclip.wv v4, v8, v12, v0.t
|
|
|
++ vnclip.wx v4, v8, a1, v0.t
|
|
|
++ vnclip.wi v4, v8, 1, v0.t
|
|
|
++ vnclip.wi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vfwadd.vv v4, v8, v12
|
|
|
++ vfwadd.vf v4, v8, fa2
|
|
|
++ vfwadd.vv v4, v8, v12, v0.t
|
|
|
++ vfwadd.vf v4, v8, fa2, v0.t
|
|
|
++ vfwsub.vv v4, v8, v12
|
|
|
++ vfwsub.vf v4, v8, fa2
|
|
|
++ vfwsub.vv v4, v8, v12, v0.t
|
|
|
++ vfwsub.vf v4, v8, fa2, v0.t
|
|
|
++ vfwadd.wv v4, v8, v12
|
|
|
++ vfwadd.wf v4, v8, fa2
|
|
|
++ vfwadd.wv v4, v8, v12, v0.t
|
|
|
++ vfwadd.wf v4, v8, fa2, v0.t
|
|
|
++ vfwsub.wv v4, v8, v12
|
|
|
++ vfwsub.wf v4, v8, fa2
|
|
|
++ vfwsub.wv v4, v8, v12, v0.t
|
|
|
++ vfwsub.wf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfwmul.vv v4, v8, v12
|
|
|
++ vfwmul.vf v4, v8, fa2
|
|
|
++ vfwmul.vv v4, v8, v12, v0.t
|
|
|
++ vfwmul.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfwmacc.vv v4, v12, v8
|
|
|
++ vfwmacc.vf v4, fa2, v8
|
|
|
++ vfwnmacc.vv v4, v12, v8
|
|
|
++ vfwnmacc.vf v4, fa2, v8
|
|
|
++ vfwmsac.vv v4, v12, v8
|
|
|
++ vfwmsac.vf v4, fa2, v8
|
|
|
++ vfwnmsac.vv v4, v12, v8
|
|
|
++ vfwnmsac.vf v4, fa2, v8
|
|
|
++ vfwmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfwmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfwnmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfwnmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfwmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfwmsac.vf v4, fa2, v8, v0.t
|
|
|
++ vfwnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfwnmsac.vf v4, fa2, v8, v0.t
|
|
|
++
|
|
|
++ vfsqrt.v v4, v8
|
|
|
++ vfsqrt.v v4, v8, v0.t
|
|
|
++ vfrsqrte7.v v4, v8
|
|
|
++ vfrsqrte7.v v4, v8, v0.t
|
|
|
++ vfrsqrt7.v v4, v8
|
|
|
++ vfrsqrt7.v v4, v8, v0.t
|
|
|
++ vfrece7.v v4, v8
|
|
|
++ vfrece7.v v4, v8, v0.t
|
|
|
++ vfrec7.v v4, v8
|
|
|
++ vfrec7.v v4, v8, v0.t
|
|
|
++ vfclass.v v4, v8
|
|
|
++ vfclass.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfcvt.xu.f.v v4, v8
|
|
|
++ vfcvt.x.f.v v4, v8
|
|
|
++ vfcvt.rtz.xu.f.v v4, v8
|
|
|
++ vfcvt.rtz.x.f.v v4, v8
|
|
|
++ vfcvt.f.xu.v v4, v8
|
|
|
++ vfcvt.f.x.v v4, v8
|
|
|
++ vfcvt.xu.f.v v4, v8, v0.t
|
|
|
++ vfcvt.x.f.v v4, v8, v0.t
|
|
|
++ vfcvt.rtz.xu.f.v v4, v8, v0.t
|
|
|
++ vfcvt.rtz.x.f.v v4, v8, v0.t
|
|
|
++ vfcvt.f.xu.v v4, v8, v0.t
|
|
|
++ vfcvt.f.x.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfwcvt.xu.f.v v4, v8
|
|
|
++ vfwcvt.x.f.v v4, v8
|
|
|
++ vfwcvt.rtz.xu.f.v v4, v8
|
|
|
++ vfwcvt.rtz.x.f.v v4, v8
|
|
|
++ vfwcvt.f.xu.v v4, v8
|
|
|
++ vfwcvt.f.x.v v4, v8
|
|
|
++ vfwcvt.f.f.v v4, v8
|
|
|
++ vfwcvt.xu.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.x.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.rtz.xu.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.rtz.x.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.xu.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.x.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.f.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfncvt.xu.f.w v4, v8
|
|
|
++ vfncvt.x.f.w v4, v8
|
|
|
++ vfncvt.rtz.xu.f.w v4, v8
|
|
|
++ vfncvt.rtz.x.f.w v4, v8
|
|
|
++ vfncvt.f.xu.w v4, v8
|
|
|
++ vfncvt.f.x.w v4, v8
|
|
|
++ vfncvt.f.f.w v4, v8
|
|
|
++ vfncvt.rod.f.f.w v4, v8
|
|
|
++ vfncvt.xu.f.w v4, v8, v0.t
|
|
|
++ vfncvt.x.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rtz.xu.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rtz.x.f.w v4, v8, v0.t
|
|
|
++ vfncvt.f.xu.w v4, v8, v0.t
|
|
|
++ vfncvt.f.x.w v4, v8, v0.t
|
|
|
++ vfncvt.f.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rod.f.f.w v4, v8, v0.t
|
|
|
++
|
|
|
++ vredsum.vs v4, v8, v12
|
|
|
++ vredmaxu.vs v4, v8, v8
|
|
|
++ vredmax.vs v4, v8, v8
|
|
|
++ vredminu.vs v4, v8, v8
|
|
|
++ vredmin.vs v4, v8, v8
|
|
|
++ vredand.vs v4, v8, v12
|
|
|
++ vredor.vs v4, v8, v12
|
|
|
++ vredxor.vs v4, v8, v12
|
|
|
++ vredsum.vs v4, v8, v12, v0.t
|
|
|
++ vredmaxu.vs v4, v8, v8, v0.t
|
|
|
++ vredmax.vs v4, v8, v8, v0.t
|
|
|
++ vredminu.vs v4, v8, v8, v0.t
|
|
|
++ vredmin.vs v4, v8, v8, v0.t
|
|
|
++ vredand.vs v4, v8, v12, v0.t
|
|
|
++ vredor.vs v4, v8, v12, v0.t
|
|
|
++ vredxor.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vwredsumu.vs v4, v8, v12
|
|
|
++ vwredsum.vs v4, v8, v12
|
|
|
++ vwredsumu.vs v4, v8, v12, v0.t
|
|
|
++ vwredsum.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vfredosum.vs v4, v8, v12
|
|
|
++ vfredsum.vs v4, v8, v12
|
|
|
++ vfredmax.vs v4, v8, v12
|
|
|
++ vfredmin.vs v4, v8, v12
|
|
|
++ vfredosum.vs v4, v8, v12, v0.t
|
|
|
++ vfredsum.vs v4, v8, v12, v0.t
|
|
|
++ vfredmax.vs v4, v8, v12, v0.t
|
|
|
++ vfredmin.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vfwredosum.vs v4, v8, v12
|
|
|
++ vfwredsum.vs v4, v8, v12
|
|
|
++ vfwredosum.vs v4, v8, v12, v0.t
|
|
|
++ vfwredsum.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vmsbf.m v4, v8
|
|
|
++ vmsif.m v4, v8
|
|
|
++ vmsof.m v4, v8
|
|
|
++ viota.m v4, v8
|
|
|
++
|
|
|
++ vmsbf.m v4, v8, v0.t
|
|
|
++ vmsif.m v4, v8, v0.t
|
|
|
++ vmsof.m v4, v8, v0.t
|
|
|
++ viota.m v4, v8, v0.t
|
|
|
++
|
|
|
++ vrgatherei16.vv v4, v8, v12
|
|
|
++ vrgatherei16.vv v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vmv2r.v v2, v4
|
|
|
++ vmv4r.v v4, v8
|
|
|
++ vmv8r.v v0, v8
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..4f2b611f53
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.d
|
|
|
+@@ -0,0 +1,3 @@
|
|
|
++#as: -march=rv32iav0p10
|
|
|
++#source: vector-insns-fail-zvamo.s
|
|
|
++#error_output: vector-insns-fail-zvamo.l
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..6207fb2fee
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.l
|
|
|
+@@ -0,0 +1,109 @@
|
|
|
++.*: Assembler messages:
|
|
|
++.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
|
|
|
++.*Error: illegal operands `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
|
|
|
++.*Error: illegal operands `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..0fd3c26a58
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvamo.s
|
|
|
+@@ -0,0 +1,217 @@
|
|
|
++# Vector AMO Operations
|
|
|
++
|
|
|
++ vamoaddei8.v v0, (a1), v4, v0 # OK
|
|
|
++ vamoaddei8.v v4, (a1), v4, v0 # vd must match vs3
|
|
|
++ vamoaddei8.v v0, (a1), v4, v0, v0.t # vd overlap vm
|
|
|
++ vamoaddei8.v x0, (a1), v4, v0 # OK
|
|
|
++ vamoaddei8.v x0, (a1), v4, v0, v0.t # vs3 overlap vm
|
|
|
++
|
|
|
++ vamoswapei8.v v0, (a1), v4, v0
|
|
|
++ vamoswapei8.v v4, (a1), v4, v0
|
|
|
++ vamoswapei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoswapei8.v x0, (a1), v4, v0
|
|
|
++ vamoswapei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v0, (a1), v4, v0
|
|
|
++ vamoxorei8.v v4, (a1), v4, v0
|
|
|
++ vamoxorei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoxorei8.v x0, (a1), v4, v0
|
|
|
++ vamoxorei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoandei8.v v0, (a1), v4, v0
|
|
|
++ vamoandei8.v v4, (a1), v4, v0
|
|
|
++ vamoandei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoandei8.v x0, (a1), v4, v0
|
|
|
++ vamoandei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoorei8.v v0, (a1), v4, v0
|
|
|
++ vamoorei8.v v4, (a1), v4, v0
|
|
|
++ vamoorei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoorei8.v x0, (a1), v4, v0
|
|
|
++ vamoorei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v0, (a1), v4, v0
|
|
|
++ vamominei8.v v4, (a1), v4, v0
|
|
|
++ vamominei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominei8.v x0, (a1), v4, v0
|
|
|
++ vamominei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxei8.v v0, (a1), v4, v0
|
|
|
++ vamomaxei8.v v4, (a1), v4, v0
|
|
|
++ vamomaxei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxei8.v x0, (a1), v4, v0
|
|
|
++ vamomaxei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominuei8.v v0, (a1), v4, v0
|
|
|
++ vamominuei8.v v4, (a1), v4, v0
|
|
|
++ vamominuei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominuei8.v x0, (a1), v4, v0
|
|
|
++ vamominuei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxuei8.v v0, (a1), v4, v0
|
|
|
++ vamomaxuei8.v v4, (a1), v4, v0
|
|
|
++ vamomaxuei8.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxuei8.v x0, (a1), v4, v0
|
|
|
++ vamomaxuei8.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v0, (a1), v4, v0
|
|
|
++ vamoaddei16.v v4, (a1), v4, v0
|
|
|
++ vamoaddei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoaddei16.v x0, (a1), v4, v0
|
|
|
++ vamoaddei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoswapei16.v v0, (a1), v4, v0
|
|
|
++ vamoswapei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoswapei16.v v4, (a1), v4, v0
|
|
|
++ vamoswapei16.v x0, (a1), v4, v0
|
|
|
++ vamoswapei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v0, (a1), v4, v0
|
|
|
++ vamoxorei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoxorei16.v v4, (a1), v4, v0
|
|
|
++ vamoxorei16.v x0, (a1), v4, v0
|
|
|
++ vamoxorei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoandei16.v v0, (a1), v4, v0
|
|
|
++ vamoandei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoandei16.v v4, (a1), v4, v0
|
|
|
++ vamoandei16.v x0, (a1), v4, v0
|
|
|
++ vamoandei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoorei16.v v0, (a1), v4, v0
|
|
|
++ vamoorei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoorei16.v v4, (a1), v4, v0
|
|
|
++ vamoorei16.v x0, (a1), v4, v0
|
|
|
++ vamoorei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v0, (a1), v4, v0
|
|
|
++ vamominei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominei16.v v4, (a1), v4, v0
|
|
|
++ vamominei16.v x0, (a1), v4, v0
|
|
|
++ vamominei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxei16.v v0, (a1), v4, v0
|
|
|
++ vamomaxei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxei16.v v4, (a1), v4, v0
|
|
|
++ vamomaxei16.v x0, (a1), v4, v0
|
|
|
++ vamomaxei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominuei16.v v0, (a1), v4, v0
|
|
|
++ vamominuei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominuei16.v v4, (a1), v4, v0
|
|
|
++ vamominuei16.v x0, (a1), v4, v0
|
|
|
++ vamominuei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxuei16.v v0, (a1), v4, v0
|
|
|
++ vamomaxuei16.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxuei16.v v4, (a1), v4, v0
|
|
|
++ vamomaxuei16.v x0, (a1), v4, v0
|
|
|
++ vamomaxuei16.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v0, (a1), v4, v0
|
|
|
++ vamoaddei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoaddei32.v v4, (a1), v4, v0
|
|
|
++ vamoaddei32.v x0, (a1), v4, v0
|
|
|
++ vamoaddei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoswapei32.v v0, (a1), v4, v0
|
|
|
++ vamoswapei32.v v4, (a1), v4, v0
|
|
|
++ vamoswapei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoswapei32.v x0, (a1), v4, v0
|
|
|
++ vamoswapei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v0, (a1), v4, v0
|
|
|
++ vamoxorei32.v v4, (a1), v4, v0
|
|
|
++ vamoxorei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoxorei32.v x0, (a1), v4, v0
|
|
|
++ vamoxorei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoandei32.v v0, (a1), v4, v0
|
|
|
++ vamoandei32.v v4, (a1), v4, v0
|
|
|
++ vamoandei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoandei32.v x0, (a1), v4, v0
|
|
|
++ vamoandei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoorei32.v v0, (a1), v4, v0
|
|
|
++ vamoorei32.v v4, (a1), v4, v0
|
|
|
++ vamoorei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoorei32.v x0, (a1), v4, v0
|
|
|
++ vamoorei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v0, (a1), v4, v0
|
|
|
++ vamominei32.v v4, (a1), v4, v0
|
|
|
++ vamominei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominei32.v x0, (a1), v4, v0
|
|
|
++ vamominei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxei32.v v0, (a1), v4, v0
|
|
|
++ vamomaxei32.v v4, (a1), v4, v0
|
|
|
++ vamomaxei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxei32.v x0, (a1), v4, v0
|
|
|
++ vamomaxei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominuei32.v v0, (a1), v4, v0
|
|
|
++ vamominuei32.v v4, (a1), v4, v0
|
|
|
++ vamominuei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominuei32.v x0, (a1), v4, v0
|
|
|
++ vamominuei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxuei32.v v0, (a1), v4, v0
|
|
|
++ vamomaxuei32.v v4, (a1), v4, v0
|
|
|
++ vamomaxuei32.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxuei32.v x0, (a1), v4, v0
|
|
|
++ vamomaxuei32.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v0, (a1), v4, v0
|
|
|
++ vamoaddei64.v v4, (a1), v4, v0
|
|
|
++ vamoaddei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoaddei64.v x0, (a1), v4, v0
|
|
|
++ vamoaddei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoswapei64.v v0, (a1), v4, v0
|
|
|
++ vamoswapei64.v v4, (a1), v4, v0
|
|
|
++ vamoswapei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoswapei64.v x0, (a1), v4, v0
|
|
|
++ vamoswapei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v0, (a1), v4, v0
|
|
|
++ vamoxorei64.v v4, (a1), v4, v0
|
|
|
++ vamoxorei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoxorei64.v x0, (a1), v4, v0
|
|
|
++ vamoxorei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoandei64.v v0, (a1), v4, v0
|
|
|
++ vamoandei64.v v4, (a1), v4, v0
|
|
|
++ vamoandei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoandei64.v x0, (a1), v4, v0
|
|
|
++ vamoandei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamoorei64.v v0, (a1), v4, v0
|
|
|
++ vamoorei64.v v4, (a1), v4, v0
|
|
|
++ vamoorei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamoorei64.v x0, (a1), v4, v0
|
|
|
++ vamoorei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v0, (a1), v4, v0
|
|
|
++ vamominei64.v v4, (a1), v4, v0
|
|
|
++ vamominei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominei64.v x0, (a1), v4, v0
|
|
|
++ vamominei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxei64.v v0, (a1), v4, v0
|
|
|
++ vamomaxei64.v v4, (a1), v4, v0
|
|
|
++ vamomaxei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxei64.v x0, (a1), v4, v0
|
|
|
++ vamomaxei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamominuei64.v v0, (a1), v4, v0
|
|
|
++ vamominuei64.v v4, (a1), v4, v0
|
|
|
++ vamominuei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamominuei64.v x0, (a1), v4, v0
|
|
|
++ vamominuei64.v x0, (a1), v4, v0, v0.t
|
|
|
++
|
|
|
++ vamomaxuei64.v v0, (a1), v4, v0
|
|
|
++ vamomaxuei64.v v4, (a1), v4, v0
|
|
|
++ vamomaxuei64.v v0, (a1), v4, v0, v0.t
|
|
|
++ vamomaxuei64.v x0, (a1), v4, v0
|
|
|
++ vamomaxuei64.v x0, (a1), v4, v0, v0.t
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..207a410c28
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d
|
|
|
+@@ -0,0 +1,29 @@
|
|
|
++#as: -march=rv32iv0p10
|
|
|
++#objdump: -dr
|
|
|
++
|
|
|
++.*:[ ]+file format .*
|
|
|
++
|
|
|
++
|
|
|
++Disassembly of section .text:
|
|
|
++
|
|
|
++0+000 <.text>:
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandnot.mm[ ]+v0,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandnot.mm[ ]+v12,v0,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandnot.mm[ ]+v4,v4,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..afbb7ccb36
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s
|
|
|
+@@ -0,0 +1,9 @@
|
|
|
++ vmsge.vx v4, v8, a1 # unmasked va >= x
|
|
|
++ vmsge.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
|
|
|
++ vmsge.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
|
|
|
++ vmsge.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
|
|
|
++
|
|
|
++ vmsgeu.vx v4, v8, a1 # unmasked va >= x
|
|
|
++ vmsgeu.vx v8, v12, a2, v0.t # masked va >= x, vd != v0
|
|
|
++ vmsgeu.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0
|
|
|
++ vmsgeu.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..0556a22a7b
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns.d
|
|
|
+@@ -0,0 +1,1944 @@
|
|
|
++#as: -march=rv32iafv0p10
|
|
|
++#objdump: -dr
|
|
|
++
|
|
|
++.*:[ ]+file format .*
|
|
|
++
|
|
|
++
|
|
|
++Disassembly of section .text:
|
|
|
++
|
|
|
++0+000 <.text>:
|
|
|
++[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
|
|
|
++[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
|
|
|
++[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,ta,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+c095f557[ ]+vsetivli[ ]+a0,11,e16,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c2b5f557[ ]+vsetivli[ ]+a0,11,e256,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c335f557[ ]+vsetivli[ ]+a0,11,e512,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c3b5f557[ ]+vsetivli[ ]+a0,11,e1024,m8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c385f557[ ]+vsetivli[ ]+a0,11,e1024,m1,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c3f5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c365f557[ ]+vsetivli[ ]+a0,11,e512,mf4,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c2d5f557[ ]+vsetivli[ ]+a0,11,e256,mf8,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+ce95f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma
|
|
|
++[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
|
|
|
++[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vle1.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vle1.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vse1.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02b50227[ ]+vse1.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050207[ ]+vle8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00050207[ ]+vle8.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02050227[ ]+vse8.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00050227[ ]+vse8.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055207[ ]+vle16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00055207[ ]+vle16.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02055227[ ]+vse16.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00055227[ ]+vse16.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056207[ ]+vle32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00056207[ ]+vle32.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02056227[ ]+vse32.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00056227[ ]+vse32.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057207[ ]+vle64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00057207[ ]+vle64.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+02057227[ ]+vse64.v[ ]+v4,\(a0\)
|
|
|
++[ ]+[0-9a-f]+:[ ]+00057227[ ]+vse64.v[ ]+v4,\(a0\),v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+vlse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50207[ ]+vlse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b50207[ ]+vlse8.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+vsse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab50227[ ]+vsse8.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b50227[ ]+vsse8.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+vlse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55207[ ]+vlse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b55207[ ]+vlse16.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+vsse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab55227[ ]+vsse16.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b55227[ ]+vsse16.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+vlse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56207[ ]+vlse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b56207[ ]+vlse32.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+vsse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab56227[ ]+vsse32.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b56227[ ]+vsse32.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+vlse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57207[ ]+vlse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b57207[ ]+vlse64.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+vsse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ab57227[ ]+vsse64.v[ ]+v4,\(a0\),a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+08b57227[ ]+vsse64.v[ ]+v4,\(a0\),a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc50207[ ]+vloxei8.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0cc50227[ ]+vsoxei8.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+06c50207[ ]+vluxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+06c50207[ ]+vluxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+04c50207[ ]+vluxei8.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+06c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+06c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+04c50227[ ]+vsuxei8.v[ ]+v4,\(a0\),v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0ec55207[ ]+vloxei16.v[ ]+v4,\(a0\),v12
|
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|
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|
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|
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|
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++[ ]+[0-9a-f]+:[ ]+6085822f[ ]+vamoandei8.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+4685822f[ ]+vamoorei8.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4285822f[ ]+vamoorei8.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485822f[ ]+vamoorei8.v[ ]+v4,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+4085822f[ ]+vamoorei8.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+8685822f[ ]+vamominei8.v[ ]+v4,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+8285822f[ ]+vamominei8.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485822f[ ]+vamominei8.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085822f[ ]+vamominei8.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+a685822f[ ]+vamomaxei8.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285822f[ ]+vamomaxei8.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485822f[ ]+vamomaxei8.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a085822f[ ]+vamomaxei8.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+c685822f[ ]+vamominuei8.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c285822f[ ]+vamominuei8.v[ ]+zero,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+c485822f[ ]+vamominuei8.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c085822f[ ]+vamominuei8.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+e685822f[ ]+vamomaxuei8.v[ ]+v4,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+e285822f[ ]+vamomaxuei8.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e485822f[ ]+vamomaxuei8.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e085822f[ ]+vamomaxuei8.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+0685d22f[ ]+vamoaddei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0285d22f[ ]+vamoaddei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0485d22f[ ]+vamoaddei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0085d22f[ ]+vamoaddei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e85d22f[ ]+vamoswapei16.v[ ]+v4,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+0a85d22f[ ]+vamoswapei16.v[ ]+zero,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+0c85d22f[ ]+vamoswapei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0885d22f[ ]+vamoswapei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685d22f[ ]+vamoxorei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2285d22f[ ]+vamoxorei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485d22f[ ]+vamoxorei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2085d22f[ ]+vamoxorei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+6685d22f[ ]+vamoandei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285d22f[ ]+vamoandei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485d22f[ ]+vamoandei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+6085d22f[ ]+vamoandei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+4685d22f[ ]+vamoorei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4285d22f[ ]+vamoorei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485d22f[ ]+vamoorei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+4085d22f[ ]+vamoorei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+8685d22f[ ]+vamominei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285d22f[ ]+vamominei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485d22f[ ]+vamominei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085d22f[ ]+vamominei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+a685d22f[ ]+vamomaxei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285d22f[ ]+vamomaxei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485d22f[ ]+vamomaxei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a085d22f[ ]+vamomaxei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+c685d22f[ ]+vamominuei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c285d22f[ ]+vamominuei16.v[ ]+zero,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+c485d22f[ ]+vamominuei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c085d22f[ ]+vamominuei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+e685d22f[ ]+vamomaxuei16.v[ ]+v4,\(a1\),v8,v4
|
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|
++[ ]+[0-9a-f]+:[ ]+e285d22f[ ]+vamomaxuei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e485d22f[ ]+vamomaxuei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e085d22f[ ]+vamomaxuei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+0685d22f[ ]+vamoaddei16.v[ ]+v4,\(a1\),v8,v4
|
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++[ ]+[0-9a-f]+:[ ]+0285d22f[ ]+vamoaddei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0485d22f[ ]+vamoaddei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0085d22f[ ]+vamoaddei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+0e85d22f[ ]+vamoswapei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a85d22f[ ]+vamoswapei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c85d22f[ ]+vamoswapei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0885d22f[ ]+vamoswapei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685d22f[ ]+vamoxorei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2285d22f[ ]+vamoxorei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485d22f[ ]+vamoxorei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2085d22f[ ]+vamoxorei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6685d22f[ ]+vamoandei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285d22f[ ]+vamoandei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485d22f[ ]+vamoandei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6085d22f[ ]+vamoandei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+4685d22f[ ]+vamoorei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4285d22f[ ]+vamoorei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485d22f[ ]+vamoorei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4085d22f[ ]+vamoorei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+8685d22f[ ]+vamominei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285d22f[ ]+vamominei16.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485d22f[ ]+vamominei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
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|
++[ ]+[0-9a-f]+:[ ]+8085d22f[ ]+vamominei16.v[ ]+zero,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+a685d22f[ ]+vamomaxei16.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285d22f[ ]+vamomaxei16.v[ ]+zero,\(a1\),v8,v4
|
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++[ ]+[0-9a-f]+:[ ]+a485d22f[ ]+vamomaxei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+a085d22f[ ]+vamomaxei16.v[ ]+zero,\(a1\),v8,v4,v0.t
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++[ ]+[0-9a-f]+:[ ]+c685d22f[ ]+vamominuei16.v[ ]+v4,\(a1\),v8,v4
|
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|
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++[ ]+[0-9a-f]+:[ ]+c485d22f[ ]+vamominuei16.v[ ]+v4,\(a1\),v8,v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+c085d22f[ ]+vamominuei16.v[ ]+zero,\(a1\),v8,v4,v0.t
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|
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|
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++[ ]+[0-9a-f]+:[ ]+e085d22f[ ]+vamomaxuei16.v[ ]+zero,\(a1\),v8,v4,v0.t
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++[ ]+[0-9a-f]+:[ ]+0885e22f[ ]+vamoswapei32.v[ ]+zero,\(a1\),v8,v4,v0.t
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++[ ]+[0-9a-f]+:[ ]+2685e22f[ ]+vamoxorei32.v[ ]+v4,\(a1\),v8,v4
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|
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++[ ]+[0-9a-f]+:[ ]+2085e22f[ ]+vamoxorei32.v[ ]+zero,\(a1\),v8,v4,v0.t
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
|
++[ ]+[0-9a-f]+:[ ]+0885e22f[ ]+vamoswapei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685e22f[ ]+vamoxorei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2285e22f[ ]+vamoxorei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485e22f[ ]+vamoxorei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2085e22f[ ]+vamoxorei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6685e22f[ ]+vamoandei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285e22f[ ]+vamoandei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485e22f[ ]+vamoandei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6085e22f[ ]+vamoandei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4685e22f[ ]+vamoorei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4285e22f[ ]+vamoorei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485e22f[ ]+vamoorei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4085e22f[ ]+vamoorei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8685e22f[ ]+vamominei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285e22f[ ]+vamominei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485e22f[ ]+vamominei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085e22f[ ]+vamominei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a685e22f[ ]+vamomaxei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285e22f[ ]+vamomaxei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485e22f[ ]+vamomaxei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a085e22f[ ]+vamomaxei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c685e22f[ ]+vamominuei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c285e22f[ ]+vamominuei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c485e22f[ ]+vamominuei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c085e22f[ ]+vamominuei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e685e22f[ ]+vamomaxuei32.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e285e22f[ ]+vamomaxuei32.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e485e22f[ ]+vamomaxuei32.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e085e22f[ ]+vamomaxuei32.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0685f22f[ ]+vamoaddei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0285f22f[ ]+vamoaddei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0485f22f[ ]+vamoaddei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0085f22f[ ]+vamoaddei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e85f22f[ ]+vamoswapei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a85f22f[ ]+vamoswapei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c85f22f[ ]+vamoswapei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0885f22f[ ]+vamoswapei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685f22f[ ]+vamoxorei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2285f22f[ ]+vamoxorei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485f22f[ ]+vamoxorei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2085f22f[ ]+vamoxorei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6685f22f[ ]+vamoandei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285f22f[ ]+vamoandei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485f22f[ ]+vamoandei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6085f22f[ ]+vamoandei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4685f22f[ ]+vamoorei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4285f22f[ ]+vamoorei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485f22f[ ]+vamoorei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4085f22f[ ]+vamoorei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8685f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a685f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a085f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c685f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c285f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c485f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c085f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e685f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e285f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e485f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e085f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0685f22f[ ]+vamoaddei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0285f22f[ ]+vamoaddei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0485f22f[ ]+vamoaddei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0085f22f[ ]+vamoaddei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e85f22f[ ]+vamoswapei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a85f22f[ ]+vamoswapei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c85f22f[ ]+vamoswapei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0885f22f[ ]+vamoswapei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685f22f[ ]+vamoxorei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2285f22f[ ]+vamoxorei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485f22f[ ]+vamoxorei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2085f22f[ ]+vamoxorei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6685f22f[ ]+vamoandei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285f22f[ ]+vamoandei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485f22f[ ]+vamoandei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6085f22f[ ]+vamoandei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4685f22f[ ]+vamoorei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4285f22f[ ]+vamoorei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485f22f[ ]+vamoorei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4085f22f[ ]+vamoorei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8685f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485f22f[ ]+vamominei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085f22f[ ]+vamominei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a685f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485f22f[ ]+vamomaxei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a085f22f[ ]+vamomaxei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c685f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c285f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+c485f22f[ ]+vamominuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c085f22f[ ]+vamominuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e685f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e285f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+e485f22f[ ]+vamomaxuei64.v[ ]+v4,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e085f22f[ ]+vamomaxuei64.v[ ]+zero,\(a1\),v8,v4,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e804257[ ]+vneg.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c804257[ ]+vneg.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02860257[ ]+vadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0285c257[ ]+vadd.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0287b257[ ]+vadd.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+02883257[ ]+vadd.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+00860257[ ]+vadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0085c257[ ]+vadd.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0087b257[ ]+vadd.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+00883257[ ]+vadd.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a860257[ ]+vsub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a85c257[ ]+vsub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e85c257[ ]+vrsub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e87b257[ ]+vrsub.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+0e883257[ ]+vrsub.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+08860257[ ]+vsub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0885c257[ ]+vsub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c85c257[ ]+vrsub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c87b257[ ]+vrsub.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0c883257[ ]+vrsub.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c6806257[ ]+vwcvt.x.x.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+c2806257[ ]+vwcvtu.x.x.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+c4806257[ ]+vwcvt.x.x.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c0806257[ ]+vwcvtu.x.x.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c2862257[ ]+vwaddu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+c285e257[ ]+vwaddu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+c0862257[ ]+vwaddu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c085e257[ ]+vwaddu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ca862257[ ]+vwsubu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ca85e257[ ]+vwsubu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+c8862257[ ]+vwsubu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c885e257[ ]+vwsubu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c6862257[ ]+vwadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+c685e257[ ]+vwadd.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+c4862257[ ]+vwadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c485e257[ ]+vwadd.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ce862257[ ]+vwsub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ce85e257[ ]+vwsub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+cc862257[ ]+vwsub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+cc85e257[ ]+vwsub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d2862257[ ]+vwaddu.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+d285e257[ ]+vwaddu.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+d0862257[ ]+vwaddu.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d085e257[ ]+vwaddu.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+da862257[ ]+vwsubu.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+da85e257[ ]+vwsubu.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+d8862257[ ]+vwsubu.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d885e257[ ]+vwsubu.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d6862257[ ]+vwadd.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+d685e257[ ]+vwadd.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+d4862257[ ]+vwadd.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d485e257[ ]+vwadd.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+de862257[ ]+vwsub.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+de85e257[ ]+vwsub.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+dc862257[ ]+vwsub.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+dc85e257[ ]+vwsub.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a832257[ ]+vzext.vf2[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+48832257[ ]+vzext.vf2[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a83a257[ ]+vsext.vf2[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4883a257[ ]+vsext.vf2[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a822257[ ]+vzext.vf4[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+48822257[ ]+vzext.vf4[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a82a257[ ]+vsext.vf4[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4882a257[ ]+vsext.vf4[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a812257[ ]+vzext.vf8[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+48812257[ ]+vzext.vf8[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4a81a257[ ]+vsext.vf8[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4881a257[ ]+vsext.vf8[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+40860257[ ]+vadc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4085c257[ ]+vadc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4087b257[ ]+vadc.vim[ ]+v4,v8,15,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+40883257[ ]+vadc.vim[ ]+v4,v8,-16,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+44860257[ ]+vmadc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4485c257[ ]+vmadc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4487b257[ ]+vmadc.vim[ ]+v4,v8,15,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+44883257[ ]+vmadc.vim[ ]+v4,v8,-16,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+46860257[ ]+vmadc.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+4685c257[ ]+vmadc.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+4687b257[ ]+vmadc.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+46883257[ ]+vmadc.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+48860257[ ]+vsbc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4885c257[ ]+vsbc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c860257[ ]+vmsbc.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c85c257[ ]+vmsbc.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e860257[ ]+vmsbc.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e85c257[ ]+vmsbc.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e8fb257[ ]+vnot.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c8fb257[ ]+vnot.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+26860257[ ]+vand.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685c257[ ]+vand.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2687b257[ ]+vand.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+26883257[ ]+vand.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+24860257[ ]+vand.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485c257[ ]+vand.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2487b257[ ]+vand.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+24883257[ ]+vand.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a860257[ ]+vor.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a85c257[ ]+vor.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a87b257[ ]+vor.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a883257[ ]+vor.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+28860257[ ]+vor.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2885c257[ ]+vor.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2887b257[ ]+vor.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+28883257[ ]+vor.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e860257[ ]+vxor.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e85c257[ ]+vxor.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e87b257[ ]+vxor.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e883257[ ]+vxor.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c860257[ ]+vxor.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c85c257[ ]+vxor.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c87b257[ ]+vxor.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c883257[ ]+vxor.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+96860257[ ]+vsll.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9685c257[ ]+vsll.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+9680b257[ ]+vsll.vi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+968fb257[ ]+vsll.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+94860257[ ]+vsll.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9485c257[ ]+vsll.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9480b257[ ]+vsll.vi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+948fb257[ ]+vsll.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a2860257[ ]+vsrl.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+a285c257[ ]+vsrl.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+a280b257[ ]+vsrl.vi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+a28fb257[ ]+vsrl.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+a0860257[ ]+vsrl.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a085c257[ ]+vsrl.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a080b257[ ]+vsrl.vi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a08fb257[ ]+vsrl.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a6860257[ ]+vsra.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+a685c257[ ]+vsra.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+a680b257[ ]+vsra.vi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+a68fb257[ ]+vsra.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+a4860257[ ]+vsra.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485c257[ ]+vsra.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a480b257[ ]+vsra.vi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a48fb257[ ]+vsra.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b2804257[ ]+vncvt.x.x.w[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b0804257[ ]+vncvt.x.x.w[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b2860257[ ]+vnsrl.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+b285c257[ ]+vnsrl.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+b280b257[ ]+vnsrl.wi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+b28fb257[ ]+vnsrl.wi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+b0860257[ ]+vnsrl.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b085c257[ ]+vnsrl.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b080b257[ ]+vnsrl.wi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b08fb257[ ]+vnsrl.wi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b6860257[ ]+vnsra.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+b685c257[ ]+vnsra.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+b680b257[ ]+vnsra.wi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+b68fb257[ ]+vnsra.wi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+b4860257[ ]+vnsra.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b485c257[ ]+vnsra.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b480b257[ ]+vnsra.wi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b48fb257[ ]+vnsra.wi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ec40257[ ]+vmslt.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+6ac40257[ ]+vmsltu.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+76c40257[ ]+vmsle.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+72c40257[ ]+vmsleu.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+6cc40257[ ]+vmslt.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+68c40257[ ]+vmsltu.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74c40257[ ]+vmsle.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70c40257[ ]+vmsleu.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7687b257[ ]+vmsle.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+76883257[ ]+vmsle.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7287b257[ ]+vmsleu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+72883257[ ]+vmsleu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+vmsgt.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e883257[ ]+vmsgt.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+vmsgtu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a883257[ ]+vmsgtu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7487b257[ ]+vmsle.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74883257[ ]+vmsle.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7087b257[ ]+vmsleu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70883257[ ]+vmsleu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+vmsgt.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c883257[ ]+vmsgt.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7887b257[ ]+vmsgtu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+78883257[ ]+vmsgtu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+62860257[ ]+vmseq.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6285c257[ ]+vmseq.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+6287b257[ ]+vmseq.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+62883257[ ]+vmseq.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+60860257[ ]+vmseq.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6085c257[ ]+vmseq.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6087b257[ ]+vmseq.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+60883257[ ]+vmseq.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+66860257[ ]+vmsne.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6685c257[ ]+vmsne.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+6687b257[ ]+vmsne.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+66883257[ ]+vmsne.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+64860257[ ]+vmsne.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6485c257[ ]+vmsne.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6487b257[ ]+vmsne.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+64883257[ ]+vmsne.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a860257[ ]+vmsltu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+68860257[ ]+vmsltu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6885c257[ ]+vmsltu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e860257[ ]+vmslt.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c860257[ ]+vmslt.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+6c85c257[ ]+vmslt.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+72860257[ ]+vmsleu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+7285c257[ ]+vmsleu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7287b257[ ]+vmsleu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+72883257[ ]+vmsleu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+70860257[ ]+vmsleu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7085c257[ ]+vmsleu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7087b257[ ]+vmsleu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+70883257[ ]+vmsleu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+76860257[ ]+vmsle.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+7685c257[ ]+vmsle.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7687b257[ ]+vmsle.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+76883257[ ]+vmsle.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+74860257[ ]+vmsle.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7485c257[ ]+vmsle.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7487b257[ ]+vmsle.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+74883257[ ]+vmsle.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a85c257[ ]+vmsgtu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+vmsgtu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7a883257[ ]+vmsgtu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7885c257[ ]+vmsgtu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7887b257[ ]+vmsgtu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+78883257[ ]+vmsgtu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e85c257[ ]+vmsgt.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+vmsgt.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+7e883257[ ]+vmsgt.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c85c257[ ]+vmsgt.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+vmsgt.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+7c883257[ ]+vmsgt.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+12860257[ ]+vminu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1285c257[ ]+vminu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+10860257[ ]+vminu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1085c257[ ]+vminu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+16860257[ ]+vmin.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1685c257[ ]+vmin.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+14860257[ ]+vmin.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1485c257[ ]+vmin.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a860257[ ]+vmaxu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a85c257[ ]+vmaxu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+18860257[ ]+vmaxu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1885c257[ ]+vmaxu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1e860257[ ]+vmax.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1e85c257[ ]+vmax.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+1c860257[ ]+vmax.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+1c85c257[ ]+vmax.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+96862257[ ]+vmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9685e257[ ]+vmul.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+94862257[ ]+vmul.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9485e257[ ]+vmul.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e862257[ ]+vmulh.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e85e257[ ]+vmulh.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c862257[ ]+vmulh.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c85e257[ ]+vmulh.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+92862257[ ]+vmulhu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9285e257[ ]+vmulhu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+90862257[ ]+vmulhu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9085e257[ ]+vmulhu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9a862257[ ]+vmulhsu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9a85e257[ ]+vmulhsu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+98862257[ ]+vmulhsu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9885e257[ ]+vmulhsu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ee862257[ ]+vwmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ee85e257[ ]+vwmul.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+ec862257[ ]+vwmul.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ec85e257[ ]+vwmul.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e2862257[ ]+vwmulu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+e285e257[ ]+vwmulu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+e0862257[ ]+vwmulu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e085e257[ ]+vwmulu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ea862257[ ]+vwmulsu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ea85e257[ ]+vwmulsu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+e8862257[ ]+vwmulsu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e885e257[ ]+vwmulsu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b6862257[ ]+vmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b685e257[ ]+vmacc.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b4862257[ ]+vmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b485e257[ ]+vmacc.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+be862257[ ]+vnmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+be85e257[ ]+vnmsac.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc862257[ ]+vnmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc85e257[ ]+vnmsac.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a6862257[ ]+vmadd.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a685e257[ ]+vmadd.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a4862257[ ]+vmadd.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a485e257[ ]+vmadd.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae862257[ ]+vnmsub.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae85e257[ ]+vnmsub.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac862257[ ]+vnmsub.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac85e257[ ]+vnmsub.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f2862257[ ]+vwmaccu.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f285e257[ ]+vwmaccu.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f0862257[ ]+vwmaccu.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f085e257[ ]+vwmaccu.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f6862257[ ]+vwmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f685e257[ ]+vwmacc.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f4862257[ ]+vwmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f485e257[ ]+vwmacc.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+fe862257[ ]+vwmaccsu.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+fe85e257[ ]+vwmaccsu.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+fc862257[ ]+vwmaccsu.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+fc85e257[ ]+vwmaccsu.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+fa85e257[ ]+vwmaccus.vx[ ]+v4,a1,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f885e257[ ]+vwmaccus.vx[ ]+v4,a1,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+82862257[ ]+vdivu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285e257[ ]+vdivu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+80862257[ ]+vdivu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085e257[ ]+vdivu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+86862257[ ]+vdiv.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8685e257[ ]+vdiv.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+84862257[ ]+vdiv.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485e257[ ]+vdiv.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8a862257[ ]+vremu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8a85e257[ ]+vremu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+88862257[ ]+vremu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8885e257[ ]+vremu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8e862257[ ]+vrem.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8e85e257[ ]+vrem.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+8c862257[ ]+vrem.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8c85e257[ ]+vrem.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c860257[ ]+vmerge.vvm[ ]+v4,v8,v12,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c85c257[ ]+vmerge.vxm[ ]+v4,v8,a1,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c87b257[ ]+vmerge.vim[ ]+v4,v8,15,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5c883257[ ]+vmerge.vim[ ]+v4,v8,-16,v0
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e060457[ ]+vmv.v.v[ ]+v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e05c457[ ]+vmv.v.x[ ]+v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e07b457[ ]+vmv.v.i[ ]+v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e083457[ ]+vmv.v.i[ ]+v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+82860257[ ]+vsaddu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8285c257[ ]+vsaddu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+8287b257[ ]+vsaddu.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+82883257[ ]+vsaddu.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+80860257[ ]+vsaddu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8085c257[ ]+vsaddu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8087b257[ ]+vsaddu.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+80883257[ ]+vsaddu.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+86860257[ ]+vsadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8685c257[ ]+vsadd.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+8687b257[ ]+vsadd.vi[ ]+v4,v8,15
|
|
|
++[ ]+[0-9a-f]+:[ ]+86883257[ ]+vsadd.vi[ ]+v4,v8,-16
|
|
|
++[ ]+[0-9a-f]+:[ ]+84860257[ ]+vsadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8485c257[ ]+vsadd.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8487b257[ ]+vsadd.vi[ ]+v4,v8,15,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+84883257[ ]+vsadd.vi[ ]+v4,v8,-16,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8a860257[ ]+vssubu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8a85c257[ ]+vssubu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+88860257[ ]+vssubu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8885c257[ ]+vssubu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8e860257[ ]+vssub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+8e85c257[ ]+vssub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+8c860257[ ]+vssub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+8c85c257[ ]+vssub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+22862257[ ]+vaaddu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2285e257[ ]+vaaddu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+20862257[ ]+vaaddu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2085e257[ ]+vaaddu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+26862257[ ]+vaadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2685e257[ ]+vaadd.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+24862257[ ]+vaadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2485e257[ ]+vaadd.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a862257[ ]+vasubu.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a85e257[ ]+vasubu.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+28862257[ ]+vasubu.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2885e257[ ]+vasubu.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e862257[ ]+vasub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2e85e257[ ]+vasub.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c862257[ ]+vasub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2c85e257[ ]+vasub.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e860257[ ]+vsmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e85c257[ ]+vsmul.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c860257[ ]+vsmul.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c85c257[ ]+vsmul.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa860257[ ]+vssrl.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa85c257[ ]+vssrl.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa80b257[ ]+vssrl.vi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa8fb257[ ]+vssrl.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+a8860257[ ]+vssrl.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a885c257[ ]+vssrl.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a880b257[ ]+vssrl.vi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a88fb257[ ]+vssrl.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae860257[ ]+vssra.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae85c257[ ]+vssra.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae80b257[ ]+vssra.vi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae8fb257[ ]+vssra.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac860257[ ]+vssra.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac85c257[ ]+vssra.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac80b257[ ]+vssra.vi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac8fb257[ ]+vssra.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba860257[ ]+vnclipu.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba85c257[ ]+vnclipu.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba80b257[ ]+vnclipu.wi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba8fb257[ ]+vnclipu.wi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+b8860257[ ]+vnclipu.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b885c257[ ]+vnclipu.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b880b257[ ]+vnclipu.wi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b88fb257[ ]+vnclipu.wi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+be860257[ ]+vnclip.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+be85c257[ ]+vnclip.wx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+be80b257[ ]+vnclip.wi[ ]+v4,v8,1
|
|
|
++[ ]+[0-9a-f]+:[ ]+be8fb257[ ]+vnclip.wi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc860257[ ]+vnclip.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc85c257[ ]+vnclip.wx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc80b257[ ]+vnclip.wi[ ]+v4,v8,1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+vnclip.wi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+02861257[ ]+vfadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+02865257[ ]+vfadd.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+00861257[ ]+vfadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+00865257[ ]+vfadd.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a861257[ ]+vfsub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+0a865257[ ]+vfsub.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+08861257[ ]+vfsub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+08865257[ ]+vfsub.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e865257[ ]+vfrsub.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+9c865257[ ]+vfrsub.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c2861257[ ]+vfwadd.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+c2865257[ ]+vfwadd.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+c0861257[ ]+vfwadd.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c0865257[ ]+vfwadd.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ca861257[ ]+vfwsub.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+ca865257[ ]+vfwsub.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+c8861257[ ]+vfwsub.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+c8865257[ ]+vfwsub.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d2861257[ ]+vfwadd.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+d2865257[ ]+vfwadd.wf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+d0861257[ ]+vfwadd.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d0865257[ ]+vfwadd.wf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+da861257[ ]+vfwsub.wv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+da865257[ ]+vfwsub.wf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+d8861257[ ]+vfwsub.wv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+d8865257[ ]+vfwsub.wf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+92861257[ ]+vfmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+92865257[ ]+vfmul.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+90861257[ ]+vfmul.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+90865257[ ]+vfmul.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+82861257[ ]+vfdiv.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+82865257[ ]+vfdiv.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+80861257[ ]+vfdiv.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+80865257[ ]+vfdiv.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+86865257[ ]+vfrdiv.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+84865257[ ]+vfrdiv.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e2861257[ ]+vfwmul.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+e2865257[ ]+vfwmul.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+e0861257[ ]+vfwmul.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+e0865257[ ]+vfwmul.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a2861257[ ]+vfmadd.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a2865257[ ]+vfmadd.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a6861257[ ]+vfnmadd.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a6865257[ ]+vfnmadd.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa861257[ ]+vfmsub.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+aa865257[ ]+vfmsub.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae861257[ ]+vfnmsub.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ae865257[ ]+vfnmsub.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+a0861257[ ]+vfmadd.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a0865257[ ]+vfmadd.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a4861257[ ]+vfnmadd.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a4865257[ ]+vfnmadd.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a8861257[ ]+vfmsub.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+a8865257[ ]+vfmsub.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac861257[ ]+vfnmsub.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+ac865257[ ]+vfnmsub.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b2861257[ ]+vfmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b2865257[ ]+vfmacc.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b6861257[ ]+vfnmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b6865257[ ]+vfnmacc.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba861257[ ]+vfmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+ba865257[ ]+vfmsac.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+be861257[ ]+vfnmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+be865257[ ]+vfnmsac.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+b0861257[ ]+vfmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b0865257[ ]+vfmacc.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b4861257[ ]+vfnmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b4865257[ ]+vfnmacc.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b8861257[ ]+vfmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+b8865257[ ]+vfmsac.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc861257[ ]+vfnmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+bc865257[ ]+vfnmsac.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f2861257[ ]+vfwmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f2865257[ ]+vfwmacc.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f6861257[ ]+vfwnmacc.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f6865257[ ]+vfwnmacc.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+fa861257[ ]+vfwmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+fa865257[ ]+vfwmsac.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+fe861257[ ]+vfwnmsac.vv[ ]+v4,v12,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+fe865257[ ]+vfwnmsac.vf[ ]+v4,fa2,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+f0861257[ ]+vfwmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f0865257[ ]+vfwmacc.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f4861257[ ]+vfwnmacc.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f4865257[ ]+vfwnmacc.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f8861257[ ]+vfwmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+f8865257[ ]+vfwmsac.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+fc861257[ ]+vfwnmsac.vv[ ]+v4,v12,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+fc865257[ ]+vfwnmsac.vf[ ]+v4,fa2,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e801257[ ]+vfsqrt.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c801257[ ]+vfsqrt.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e821257[ ]+vfrsqrt7.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c821257[ ]+vfrsqrt7.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e821257[ ]+vfrsqrt7.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c821257[ ]+vfrsqrt7.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e829257[ ]+vfrec7.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c829257[ ]+vfrec7.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e829257[ ]+vfrec7.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c829257[ ]+vfrec7.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+4e881257[ ]+vfclass.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+4c881257[ ]+vfclass.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+12861257[ ]+vfmin.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+12865257[ ]+vfmin.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a861257[ ]+vfmax.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+1a865257[ ]+vfmax.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+10861257[ ]+vfmin.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+10865257[ ]+vfmin.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+18861257[ ]+vfmax.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+18865257[ ]+vfmax.vf[ ]+v4,v8,fa2,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+26841257[ ]+vfneg.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+24841257[ ]+vfneg.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a841257[ ]+vfabs.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+28841257[ ]+vfabs.v[ ]+v4,v8,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+22861257[ ]+vfsgnj.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+22865257[ ]+vfsgnj.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+26861257[ ]+vfsgnjn.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+26865257[ ]+vfsgnjn.vf[ ]+v4,v8,fa2
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a861257[ ]+vfsgnjx.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+2a865257[ ]+vfsgnjx.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+20861257[ ]+vfsgnj.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+20865257[ ]+vfsgnj.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+24861257[ ]+vfsgnjn.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+24865257[ ]+vfsgnjn.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+28861257[ ]+vfsgnjx.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+28865257[ ]+vfsgnjx.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+6ec41257[ ]+vmflt.vv[ ]+v4,v12,v8
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++[ ]+[0-9a-f]+:[ ]+66c41257[ ]+vmfle.vv[ ]+v4,v12,v8
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++[ ]+[0-9a-f]+:[ ]+6cc41257[ ]+vmflt.vv[ ]+v4,v12,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+64c41257[ ]+vmfle.vv[ ]+v4,v12,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+62861257[ ]+vmfeq.vv[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+62865257[ ]+vmfeq.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+72861257[ ]+vmfne.vv[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+72865257[ ]+vmfne.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+6e861257[ ]+vmflt.vv[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+6e865257[ ]+vmflt.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+66861257[ ]+vmfle.vv[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+66865257[ ]+vmfle.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+76865257[ ]+vmfgt.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+7e865257[ ]+vmfge.vf[ ]+v4,v8,fa2
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++[ ]+[0-9a-f]+:[ ]+60861257[ ]+vmfeq.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+60865257[ ]+vmfeq.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+70861257[ ]+vmfne.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+70865257[ ]+vmfne.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+6c861257[ ]+vmflt.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+6c865257[ ]+vmflt.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+64861257[ ]+vmfle.vv[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+64865257[ ]+vmfle.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+74865257[ ]+vmfgt.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+7c865257[ ]+vmfge.vf[ ]+v4,v8,fa2,v0.t
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++[ ]+[0-9a-f]+:[ ]+5c865257[ ]+vfmerge.vfm[ ]+v4,v8,fa2,v0
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++[ ]+[0-9a-f]+:[ ]+5e05d257[ ]+vfmv.v.f[ ]+v4,fa1
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++[ ]+[0-9a-f]+:[ ]+4a801257[ ]+vfcvt.xu.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a809257[ ]+vfcvt.x.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a839257[ ]+vfcvt.rtz.x.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+48801257[ ]+vfcvt.xu.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48809257[ ]+vfcvt.x.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48831257[ ]+vfcvt.rtz.xu.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48839257[ ]+vfcvt.rtz.x.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48811257[ ]+vfcvt.f.xu.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48819257[ ]+vfcvt.f.x.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+4a841257[ ]+vfwcvt.xu.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a849257[ ]+vfwcvt.x.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a871257[ ]+vfwcvt.rtz.xu.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a879257[ ]+vfwcvt.rtz.x.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a851257[ ]+vfwcvt.f.xu.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a859257[ ]+vfwcvt.f.x.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a861257[ ]+vfwcvt.f.f.v[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+48841257[ ]+vfwcvt.xu.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48849257[ ]+vfwcvt.x.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48871257[ ]+vfwcvt.rtz.xu.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48879257[ ]+vfwcvt.rtz.x.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48851257[ ]+vfwcvt.f.xu.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48859257[ ]+vfwcvt.f.x.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48861257[ ]+vfwcvt.f.f.v[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+4a881257[ ]+vfncvt.xu.f.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a889257[ ]+vfncvt.x.f.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a8b1257[ ]+vfncvt.rtz.xu.f.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a8b9257[ ]+vfncvt.rtz.x.f.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a891257[ ]+vfncvt.f.xu.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a899257[ ]+vfncvt.f.x.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a8a1257[ ]+vfncvt.f.f.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+4a8a9257[ ]+vfncvt.rod.f.f.w[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+48881257[ ]+vfncvt.xu.f.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48889257[ ]+vfncvt.x.f.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+488b1257[ ]+vfncvt.rtz.xu.f.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+488b9257[ ]+vfncvt.rtz.x.f.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48891257[ ]+vfncvt.f.xu.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+48899257[ ]+vfncvt.f.x.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+488a1257[ ]+vfncvt.f.f.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+488a9257[ ]+vfncvt.rod.f.f.w[ ]+v4,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+02862257[ ]+vredsum.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+1a842257[ ]+vredmaxu.vs[ ]+v4,v8,v8
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++[ ]+[0-9a-f]+:[ ]+1e842257[ ]+vredmax.vs[ ]+v4,v8,v8
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++[ ]+[0-9a-f]+:[ ]+12842257[ ]+vredminu.vs[ ]+v4,v8,v8
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++[ ]+[0-9a-f]+:[ ]+16842257[ ]+vredmin.vs[ ]+v4,v8,v8
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++[ ]+[0-9a-f]+:[ ]+06862257[ ]+vredand.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+0a862257[ ]+vredor.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+0e862257[ ]+vredxor.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+00862257[ ]+vredsum.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+18842257[ ]+vredmaxu.vs[ ]+v4,v8,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+1c842257[ ]+vredmax.vs[ ]+v4,v8,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+10842257[ ]+vredminu.vs[ ]+v4,v8,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+14842257[ ]+vredmin.vs[ ]+v4,v8,v8,v0.t
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++[ ]+[0-9a-f]+:[ ]+04862257[ ]+vredand.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+08862257[ ]+vredor.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+0c862257[ ]+vredxor.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+c2860257[ ]+vwredsumu.vs[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+c6860257[ ]+vwredsum.vs[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+c0860257[ ]+vwredsumu.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+c4860257[ ]+vwredsum.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+0e861257[ ]+vfredosum.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+06861257[ ]+vfredusum.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+1e861257[ ]+vfredmax.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+16861257[ ]+vfredmin.vs[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+0c861257[ ]+vfredosum.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+04861257[ ]+vfredusum.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+1c861257[ ]+vfredmax.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+14861257[ ]+vfredmin.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+ce861257[ ]+vfwredosum.vs[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+c6861257[ ]+vfwredusum.vs[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+cc861257[ ]+vfwredosum.vs[ ]+v4,v8,v12,v0.t
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++[ ]+[0-9a-f]+:[ ]+c4861257[ ]+vfwredusum.vs[ ]+v4,v8,v12,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8
|
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++[ ]+[0-9a-f]+:[ ]+66842257[ ]+vmmv.m[ ]+v4,v8
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++[ ]+[0-9a-f]+:[ ]+6e422257[ ]+vmclr.m[ ]+v4
|
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++[ ]+[0-9a-f]+:[ ]+7e422257[ ]+vmset.m[ ]+v4
|
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++[ ]+[0-9a-f]+:[ ]+76842257[ ]+vmnot.m[ ]+v4,v8
|
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++[ ]+[0-9a-f]+:[ ]+66862257[ ]+vmand.mm[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+76862257[ ]+vmnand.mm[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+62862257[ ]+vmandnot.mm[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+6e862257[ ]+vmxor.mm[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+6a862257[ ]+vmor.mm[ ]+v4,v8,v12
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++[ ]+[0-9a-f]+:[ ]+7a862257[ ]+vmnor.mm[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+72862257[ ]+vmornot.mm[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+7e862257[ ]+vmxnor.mm[ ]+v4,v8,v12
|
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++[ ]+[0-9a-f]+:[ ]+42c82557[ ]+vpopc.m[ ]+a0,v12
|
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++[ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12
|
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++[ ]+[0-9a-f]+:[ ]+5280a257[ ]+vmsbf.m[ ]+v4,v8
|
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++[ ]+[0-9a-f]+:[ ]+5281a257[ ]+vmsif.m[ ]+v4,v8
|
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++[ ]+[0-9a-f]+:[ ]+52812257[ ]+vmsof.m[ ]+v4,v8
|
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++[ ]+[0-9a-f]+:[ ]+52882257[ ]+viota.m[ ]+v4,v8
|
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++[ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4
|
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++[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vpopc.m[ ]+a0,v12,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+5080a257[ ]+vmsbf.m[ ]+v4,v8,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+5081a257[ ]+vmsif.m[ ]+v4,v8,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+50812257[ ]+vmsof.m[ ]+v4,v8,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+50882257[ ]+viota.m[ ]+v4,v8,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+5008a257[ ]+vid.v[ ]+v4,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+42c02557[ ]+vmv.x.s[ ]+a0,v12
|
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++[ ]+[0-9a-f]+:[ ]+42056257[ ]+vmv.s.x[ ]+v4,a0
|
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++[ ]+[0-9a-f]+:[ ]+42801557[ ]+vfmv.f.s[ ]+fa0,v8
|
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++[ ]+[0-9a-f]+:[ ]+4205d257[ ]+vfmv.s.f[ ]+v4,fa1
|
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++[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+vslideup.vx[ ]+v4,v8,a1
|
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++[ ]+[0-9a-f]+:[ ]+3a803257[ ]+vslideup.vi[ ]+v4,v8,0
|
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++[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+vslideup.vi[ ]+v4,v8,31
|
|
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++[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+vslidedown.vx[ ]+v4,v8,a1
|
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++[ ]+[0-9a-f]+:[ ]+3e803257[ ]+vslidedown.vi[ ]+v4,v8,0
|
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++[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+vslidedown.vi[ ]+v4,v8,31
|
|
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++[ ]+[0-9a-f]+:[ ]+3885c257[ ]+vslideup.vx[ ]+v4,v8,a1,v0.t
|
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++[ ]+[0-9a-f]+:[ ]+38803257[ ]+vslideup.vi[ ]+v4,v8,0,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+388fb257[ ]+vslideup.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+vslidedown.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c803257[ ]+vslidedown.vi[ ]+v4,v8,0,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+vslidedown.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+vslide1up.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+vslide1down.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3885e257[ ]+vslide1up.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+vslide1down.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a85d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3e85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1
|
|
|
++[ ]+[0-9a-f]+:[ ]+3885d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3c85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1,v0.t
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|
|
++[ ]+[0-9a-f]+:[ ]+32860257[ ]+vrgather.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+3285c257[ ]+vrgather.vx[ ]+v4,v8,a1
|
|
|
++[ ]+[0-9a-f]+:[ ]+32803257[ ]+vrgather.vi[ ]+v4,v8,0
|
|
|
++[ ]+[0-9a-f]+:[ ]+328fb257[ ]+vrgather.vi[ ]+v4,v8,31
|
|
|
++[ ]+[0-9a-f]+:[ ]+30860257[ ]+vrgather.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3085c257[ ]+vrgather.vx[ ]+v4,v8,a1,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+3a860257[ ]+vrgatherei16.vv[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+38860257[ ]+vrgatherei16.vv[ ]+v4,v8,v12,v0.t
|
|
|
++[ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e40b157[ ]+vmv2r.v[ ]+v2,v4
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e81b257[ ]+vmv4r.v[ ]+v4,v8
|
|
|
++[ ]+[0-9a-f]+:[ ]+9e83b057[ ]+vmv8r.v[ ]+v0,v8
|
|
|
+diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
|
|
|
+new file mode 100644
|
|
|
+index 0000000000..380e0441c9
|
|
|
+--- /dev/null
|
|
|
++++ b/gas/testsuite/gas/riscv/vector-insns.s
|
|
|
+@@ -0,0 +1,2185 @@
|
|
|
++ vsetvl a0, a1, a2
|
|
|
++ vsetvli a0, a1, 0
|
|
|
++ vsetvli a0, a1, 0x7ff
|
|
|
++ vsetvli a0, a1, e16, m2
|
|
|
++ vsetvli a0, a1, e256, m8
|
|
|
++ vsetvli a0, a1, e512, m8
|
|
|
++ vsetvli a0, a1, e1024, m8
|
|
|
++ vsetvli a0, a1, e1024, m1
|
|
|
++ vsetvli a0, a1, e1024, mf2
|
|
|
++ vsetvli a0, a1, e512, mf4
|
|
|
++ vsetvli a0, a1, e256, mf8
|
|
|
++ vsetvli a0, a1, e256, m2, ta
|
|
|
++ vsetvli a0, a1, e256, m2, ma
|
|
|
++ vsetvli a0, a1, e256, m2, tu
|
|
|
++ vsetvli a0, a1, e256, m2, mu
|
|
|
++ vsetvli a0, a1, e256, m2, ta, ma
|
|
|
++ vsetvli a0, a1, e256, m2, tu, ma
|
|
|
++ vsetvli a0, a1, e256, m2, ta, mu
|
|
|
++ vsetvli a0, a1, e256, m2, tu, mu
|
|
|
++ vsetivli a0, 0xb, 0
|
|
|
++ vsetivli a0, 0xb, 0x3ff
|
|
|
++ vsetivli a0, 0xb, e16, m2
|
|
|
++ vsetivli a0, 0xb, e256, m8
|
|
|
++ vsetivli a0, 0xb, e512, m8
|
|
|
++ vsetivli a0, 0xb, e1024, m8
|
|
|
++ vsetivli a0, 0xb, e1024, m1
|
|
|
++ vsetivli a0, 0xb, e1024, mf2
|
|
|
++ vsetivli a0, 0xb, e512, mf4
|
|
|
++ vsetivli a0, 0xb, e256, mf8
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta
|
|
|
++ vsetivli a0, 0xb, e256, m2, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu
|
|
|
++ vsetivli a0, 0xb, e256, m2, mu
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu, ma
|
|
|
++ vsetivli a0, 0xb, e256, m2, ta, mu
|
|
|
++ vsetivli a0, 0xb, e256, m2, tu, mu
|
|
|
++
|
|
|
++ vle1.v v4, (a0)
|
|
|
++ vle1.v v4, 0(a0)
|
|
|
++ vse1.v v4, (a0)
|
|
|
++ vse1.v v4, 0(a0)
|
|
|
++
|
|
|
++ vle8.v v4, (a0)
|
|
|
++ vle8.v v4, 0(a0)
|
|
|
++ vle8.v v4, (a0), v0.t
|
|
|
++ vse8.v v4, (a0)
|
|
|
++ vse8.v v4, 0(a0)
|
|
|
++ vse8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle16.v v4, (a0)
|
|
|
++ vle16.v v4, 0(a0)
|
|
|
++ vle16.v v4, (a0), v0.t
|
|
|
++ vse16.v v4, (a0)
|
|
|
++ vse16.v v4, 0(a0)
|
|
|
++ vse16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle32.v v4, (a0)
|
|
|
++ vle32.v v4, 0(a0)
|
|
|
++ vle32.v v4, (a0), v0.t
|
|
|
++ vse32.v v4, (a0)
|
|
|
++ vse32.v v4, 0(a0)
|
|
|
++ vse32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle64.v v4, (a0)
|
|
|
++ vle64.v v4, 0(a0)
|
|
|
++ vle64.v v4, (a0), v0.t
|
|
|
++ vse64.v v4, (a0)
|
|
|
++ vse64.v v4, 0(a0)
|
|
|
++ vse64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlse8.v v4, (a0), a1
|
|
|
++ vlse8.v v4, 0(a0), a1
|
|
|
++ vlse8.v v4, (a0), a1, v0.t
|
|
|
++ vsse8.v v4, (a0), a1
|
|
|
++ vsse8.v v4, 0(a0), a1
|
|
|
++ vsse8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlse16.v v4, (a0), a1
|
|
|
++ vlse16.v v4, 0(a0), a1
|
|
|
++ vlse16.v v4, (a0), a1, v0.t
|
|
|
++ vsse16.v v4, (a0), a1
|
|
|
++ vsse16.v v4, 0(a0), a1
|
|
|
++ vsse16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlse32.v v4, (a0), a1
|
|
|
++ vlse32.v v4, 0(a0), a1
|
|
|
++ vlse32.v v4, (a0), a1, v0.t
|
|
|
++ vsse32.v v4, (a0), a1
|
|
|
++ vsse32.v v4, 0(a0), a1
|
|
|
++ vsse32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlse64.v v4, (a0), a1
|
|
|
++ vlse64.v v4, 0(a0), a1
|
|
|
++ vlse64.v v4, (a0), a1, v0.t
|
|
|
++ vsse64.v v4, (a0), a1
|
|
|
++ vsse64.v v4, 0(a0), a1
|
|
|
++ vsse64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vloxei8.v v4, (a0), v12
|
|
|
++ vloxei8.v v4, 0(a0), v12
|
|
|
++ vloxei8.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei8.v v4, (a0), v12
|
|
|
++ vsoxei8.v v4, 0(a0), v12
|
|
|
++ vsoxei8.v v4, (a0), v12, v0.t
|
|
|
++ vluxei8.v v4, (a0), v12
|
|
|
++ vluxei8.v v4, 0(a0), v12
|
|
|
++ vluxei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei8.v v4, (a0), v12
|
|
|
++ vsuxei8.v v4, 0(a0), v12
|
|
|
++ vsuxei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxei16.v v4, (a0), v12
|
|
|
++ vloxei16.v v4, 0(a0), v12
|
|
|
++ vloxei16.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei16.v v4, (a0), v12
|
|
|
++ vsoxei16.v v4, 0(a0), v12
|
|
|
++ vsoxei16.v v4, (a0), v12, v0.t
|
|
|
++ vluxei16.v v4, (a0), v12
|
|
|
++ vluxei16.v v4, 0(a0), v12
|
|
|
++ vluxei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei16.v v4, (a0), v12
|
|
|
++ vsuxei16.v v4, 0(a0), v12
|
|
|
++ vsuxei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxei32.v v4, (a0), v12
|
|
|
++ vloxei32.v v4, 0(a0), v12
|
|
|
++ vloxei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei32.v v4, (a0), v12
|
|
|
++ vsoxei32.v v4, 0(a0), v12
|
|
|
++ vsoxei32.v v4, (a0), v12, v0.t
|
|
|
++ vluxei32.v v4, (a0), v12
|
|
|
++ vluxei32.v v4, 0(a0), v12
|
|
|
++ vluxei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei32.v v4, (a0), v12
|
|
|
++ vsuxei32.v v4, 0(a0), v12
|
|
|
++ vsuxei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxei64.v v4, (a0), v12
|
|
|
++ vloxei64.v v4, 0(a0), v12
|
|
|
++ vloxei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxei64.v v4, (a0), v12
|
|
|
++ vsoxei64.v v4, 0(a0), v12
|
|
|
++ vsoxei64.v v4, (a0), v12, v0.t
|
|
|
++ vluxei64.v v4, (a0), v12
|
|
|
++ vluxei64.v v4, 0(a0), v12
|
|
|
++ vluxei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxei64.v v4, (a0), v12
|
|
|
++ vsuxei64.v v4, 0(a0), v12
|
|
|
++ vsuxei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vle8ff.v v4, (a0)
|
|
|
++ vle8ff.v v4, 0(a0)
|
|
|
++ vle8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle16ff.v v4, (a0)
|
|
|
++ vle16ff.v v4, 0(a0)
|
|
|
++ vle16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle32ff.v v4, (a0)
|
|
|
++ vle32ff.v v4, 0(a0)
|
|
|
++ vle32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vle64ff.v v4, (a0)
|
|
|
++ vle64ff.v v4, 0(a0)
|
|
|
++ vle64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e8.v v4, (a0)
|
|
|
++ vlseg2e8.v v4, 0(a0)
|
|
|
++ vlseg2e8.v v4, (a0), v0.t
|
|
|
++ vsseg2e8.v v4, (a0)
|
|
|
++ vsseg2e8.v v4, 0(a0)
|
|
|
++ vsseg2e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e8.v v4, (a0)
|
|
|
++ vlseg3e8.v v4, 0(a0)
|
|
|
++ vlseg3e8.v v4, (a0), v0.t
|
|
|
++ vsseg3e8.v v4, (a0)
|
|
|
++ vsseg3e8.v v4, 0(a0)
|
|
|
++ vsseg3e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e8.v v4, (a0)
|
|
|
++ vlseg4e8.v v4, 0(a0)
|
|
|
++ vlseg4e8.v v4, (a0), v0.t
|
|
|
++ vsseg4e8.v v4, (a0)
|
|
|
++ vsseg4e8.v v4, 0(a0)
|
|
|
++ vsseg4e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e8.v v4, (a0)
|
|
|
++ vlseg5e8.v v4, 0(a0)
|
|
|
++ vlseg5e8.v v4, (a0), v0.t
|
|
|
++ vsseg5e8.v v4, (a0)
|
|
|
++ vsseg5e8.v v4, 0(a0)
|
|
|
++ vsseg5e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e8.v v4, (a0)
|
|
|
++ vlseg6e8.v v4, 0(a0)
|
|
|
++ vlseg6e8.v v4, (a0), v0.t
|
|
|
++ vsseg6e8.v v4, (a0)
|
|
|
++ vsseg6e8.v v4, 0(a0)
|
|
|
++ vsseg6e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e8.v v4, (a0)
|
|
|
++ vlseg7e8.v v4, 0(a0)
|
|
|
++ vlseg7e8.v v4, (a0), v0.t
|
|
|
++ vsseg7e8.v v4, (a0)
|
|
|
++ vsseg7e8.v v4, 0(a0)
|
|
|
++ vsseg7e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e8.v v4, (a0)
|
|
|
++ vlseg8e8.v v4, 0(a0)
|
|
|
++ vlseg8e8.v v4, (a0), v0.t
|
|
|
++ vsseg8e8.v v4, (a0)
|
|
|
++ vsseg8e8.v v4, 0(a0)
|
|
|
++ vsseg8e8.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16.v v4, (a0)
|
|
|
++ vlseg2e16.v v4, 0(a0)
|
|
|
++ vlseg2e16.v v4, (a0), v0.t
|
|
|
++ vsseg2e16.v v4, (a0)
|
|
|
++ vsseg2e16.v v4, 0(a0)
|
|
|
++ vsseg2e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e16.v v4, (a0)
|
|
|
++ vlseg3e16.v v4, 0(a0)
|
|
|
++ vlseg3e16.v v4, (a0), v0.t
|
|
|
++ vsseg3e16.v v4, (a0)
|
|
|
++ vsseg3e16.v v4, 0(a0)
|
|
|
++ vsseg3e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e16.v v4, (a0)
|
|
|
++ vlseg4e16.v v4, 0(a0)
|
|
|
++ vlseg4e16.v v4, (a0), v0.t
|
|
|
++ vsseg4e16.v v4, (a0)
|
|
|
++ vsseg4e16.v v4, 0(a0)
|
|
|
++ vsseg4e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e16.v v4, (a0)
|
|
|
++ vlseg5e16.v v4, 0(a0)
|
|
|
++ vlseg5e16.v v4, (a0), v0.t
|
|
|
++ vsseg5e16.v v4, (a0)
|
|
|
++ vsseg5e16.v v4, 0(a0)
|
|
|
++ vsseg5e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e16.v v4, (a0)
|
|
|
++ vlseg6e16.v v4, 0(a0)
|
|
|
++ vlseg6e16.v v4, (a0), v0.t
|
|
|
++ vsseg6e16.v v4, (a0)
|
|
|
++ vsseg6e16.v v4, 0(a0)
|
|
|
++ vsseg6e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e16.v v4, (a0)
|
|
|
++ vlseg7e16.v v4, 0(a0)
|
|
|
++ vlseg7e16.v v4, (a0), v0.t
|
|
|
++ vsseg7e16.v v4, (a0)
|
|
|
++ vsseg7e16.v v4, 0(a0)
|
|
|
++ vsseg7e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e16.v v4, (a0)
|
|
|
++ vlseg8e16.v v4, 0(a0)
|
|
|
++ vlseg8e16.v v4, (a0), v0.t
|
|
|
++ vsseg8e16.v v4, (a0)
|
|
|
++ vsseg8e16.v v4, 0(a0)
|
|
|
++ vsseg8e16.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e32.v v4, (a0)
|
|
|
++ vlseg2e32.v v4, 0(a0)
|
|
|
++ vlseg2e32.v v4, (a0), v0.t
|
|
|
++ vsseg2e32.v v4, (a0)
|
|
|
++ vsseg2e32.v v4, 0(a0)
|
|
|
++ vsseg2e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e32.v v4, (a0)
|
|
|
++ vlseg3e32.v v4, 0(a0)
|
|
|
++ vlseg3e32.v v4, (a0), v0.t
|
|
|
++ vsseg3e32.v v4, (a0)
|
|
|
++ vsseg3e32.v v4, 0(a0)
|
|
|
++ vsseg3e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e32.v v4, (a0)
|
|
|
++ vlseg4e32.v v4, 0(a0)
|
|
|
++ vlseg4e32.v v4, (a0), v0.t
|
|
|
++ vsseg4e32.v v4, (a0)
|
|
|
++ vsseg4e32.v v4, 0(a0)
|
|
|
++ vsseg4e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e32.v v4, (a0)
|
|
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++ vlseg5e32.v v4, 0(a0)
|
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|
++ vlseg5e32.v v4, (a0), v0.t
|
|
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++ vsseg5e32.v v4, (a0)
|
|
|
++ vsseg5e32.v v4, 0(a0)
|
|
|
++ vsseg5e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e32.v v4, (a0)
|
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++ vlseg6e32.v v4, 0(a0)
|
|
|
++ vlseg6e32.v v4, (a0), v0.t
|
|
|
++ vsseg6e32.v v4, (a0)
|
|
|
++ vsseg6e32.v v4, 0(a0)
|
|
|
++ vsseg6e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e32.v v4, (a0)
|
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++ vlseg7e32.v v4, 0(a0)
|
|
|
++ vlseg7e32.v v4, (a0), v0.t
|
|
|
++ vsseg7e32.v v4, (a0)
|
|
|
++ vsseg7e32.v v4, 0(a0)
|
|
|
++ vsseg7e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e32.v v4, (a0)
|
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++ vlseg8e32.v v4, 0(a0)
|
|
|
++ vlseg8e32.v v4, (a0), v0.t
|
|
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++ vsseg8e32.v v4, (a0)
|
|
|
++ vsseg8e32.v v4, 0(a0)
|
|
|
++ vsseg8e32.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e64.v v4, (a0)
|
|
|
++ vlseg2e64.v v4, 0(a0)
|
|
|
++ vlseg2e64.v v4, (a0), v0.t
|
|
|
++ vsseg2e64.v v4, (a0)
|
|
|
++ vsseg2e64.v v4, 0(a0)
|
|
|
++ vsseg2e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e64.v v4, (a0)
|
|
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++ vlseg3e64.v v4, 0(a0)
|
|
|
++ vlseg3e64.v v4, (a0), v0.t
|
|
|
++ vsseg3e64.v v4, (a0)
|
|
|
++ vsseg3e64.v v4, 0(a0)
|
|
|
++ vsseg3e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e64.v v4, (a0)
|
|
|
++ vlseg4e64.v v4, 0(a0)
|
|
|
++ vlseg4e64.v v4, (a0), v0.t
|
|
|
++ vsseg4e64.v v4, (a0)
|
|
|
++ vsseg4e64.v v4, 0(a0)
|
|
|
++ vsseg4e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e64.v v4, (a0)
|
|
|
++ vlseg5e64.v v4, 0(a0)
|
|
|
++ vlseg5e64.v v4, (a0), v0.t
|
|
|
++ vsseg5e64.v v4, (a0)
|
|
|
++ vsseg5e64.v v4, 0(a0)
|
|
|
++ vsseg5e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e64.v v4, (a0)
|
|
|
++ vlseg6e64.v v4, 0(a0)
|
|
|
++ vlseg6e64.v v4, (a0), v0.t
|
|
|
++ vsseg6e64.v v4, (a0)
|
|
|
++ vsseg6e64.v v4, 0(a0)
|
|
|
++ vsseg6e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e64.v v4, (a0)
|
|
|
++ vlseg7e64.v v4, 0(a0)
|
|
|
++ vlseg7e64.v v4, (a0), v0.t
|
|
|
++ vsseg7e64.v v4, (a0)
|
|
|
++ vsseg7e64.v v4, 0(a0)
|
|
|
++ vsseg7e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e64.v v4, (a0)
|
|
|
++ vlseg8e64.v v4, 0(a0)
|
|
|
++ vlseg8e64.v v4, (a0), v0.t
|
|
|
++ vsseg8e64.v v4, (a0)
|
|
|
++ vsseg8e64.v v4, 0(a0)
|
|
|
++ vsseg8e64.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlsseg2e8.v v4, (a0), a1
|
|
|
++ vlsseg2e8.v v4, 0(a0), a1
|
|
|
++ vlsseg2e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e8.v v4, (a0), a1
|
|
|
++ vssseg2e8.v v4, 0(a0), a1
|
|
|
++ vssseg2e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e8.v v4, (a0), a1
|
|
|
++ vlsseg3e8.v v4, 0(a0), a1
|
|
|
++ vlsseg3e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e8.v v4, (a0), a1
|
|
|
++ vssseg3e8.v v4, 0(a0), a1
|
|
|
++ vssseg3e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e8.v v4, (a0), a1
|
|
|
++ vlsseg4e8.v v4, 0(a0), a1
|
|
|
++ vlsseg4e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e8.v v4, (a0), a1
|
|
|
++ vssseg4e8.v v4, 0(a0), a1
|
|
|
++ vssseg4e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e8.v v4, (a0), a1
|
|
|
++ vlsseg5e8.v v4, 0(a0), a1
|
|
|
++ vlsseg5e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e8.v v4, (a0), a1
|
|
|
++ vssseg5e8.v v4, 0(a0), a1
|
|
|
++ vssseg5e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e8.v v4, (a0), a1
|
|
|
++ vlsseg6e8.v v4, 0(a0), a1
|
|
|
++ vlsseg6e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e8.v v4, (a0), a1
|
|
|
++ vssseg6e8.v v4, 0(a0), a1
|
|
|
++ vssseg6e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e8.v v4, (a0), a1
|
|
|
++ vlsseg7e8.v v4, 0(a0), a1
|
|
|
++ vlsseg7e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e8.v v4, (a0), a1
|
|
|
++ vssseg7e8.v v4, 0(a0), a1
|
|
|
++ vssseg7e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e8.v v4, (a0), a1
|
|
|
++ vlsseg8e8.v v4, 0(a0), a1
|
|
|
++ vlsseg8e8.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e8.v v4, (a0), a1
|
|
|
++ vssseg8e8.v v4, 0(a0), a1
|
|
|
++ vssseg8e8.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e16.v v4, (a0), a1
|
|
|
++ vlsseg2e16.v v4, 0(a0), a1
|
|
|
++ vlsseg2e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e16.v v4, (a0), a1
|
|
|
++ vssseg2e16.v v4, 0(a0), a1
|
|
|
++ vssseg2e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e16.v v4, (a0), a1
|
|
|
++ vlsseg3e16.v v4, 0(a0), a1
|
|
|
++ vlsseg3e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e16.v v4, (a0), a1
|
|
|
++ vssseg3e16.v v4, 0(a0), a1
|
|
|
++ vssseg3e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e16.v v4, (a0), a1
|
|
|
++ vlsseg4e16.v v4, 0(a0), a1
|
|
|
++ vlsseg4e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e16.v v4, (a0), a1
|
|
|
++ vssseg4e16.v v4, 0(a0), a1
|
|
|
++ vssseg4e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e16.v v4, (a0), a1
|
|
|
++ vlsseg5e16.v v4, 0(a0), a1
|
|
|
++ vlsseg5e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e16.v v4, (a0), a1
|
|
|
++ vssseg5e16.v v4, 0(a0), a1
|
|
|
++ vssseg5e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e16.v v4, (a0), a1
|
|
|
++ vlsseg6e16.v v4, 0(a0), a1
|
|
|
++ vlsseg6e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e16.v v4, (a0), a1
|
|
|
++ vssseg6e16.v v4, 0(a0), a1
|
|
|
++ vssseg6e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e16.v v4, (a0), a1
|
|
|
++ vlsseg7e16.v v4, 0(a0), a1
|
|
|
++ vlsseg7e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e16.v v4, (a0), a1
|
|
|
++ vssseg7e16.v v4, 0(a0), a1
|
|
|
++ vssseg7e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e16.v v4, (a0), a1
|
|
|
++ vlsseg8e16.v v4, 0(a0), a1
|
|
|
++ vlsseg8e16.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e16.v v4, (a0), a1
|
|
|
++ vssseg8e16.v v4, 0(a0), a1
|
|
|
++ vssseg8e16.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e32.v v4, (a0), a1
|
|
|
++ vlsseg2e32.v v4, 0(a0), a1
|
|
|
++ vlsseg2e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e32.v v4, (a0), a1
|
|
|
++ vssseg2e32.v v4, 0(a0), a1
|
|
|
++ vssseg2e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e32.v v4, (a0), a1
|
|
|
++ vlsseg3e32.v v4, 0(a0), a1
|
|
|
++ vlsseg3e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e32.v v4, (a0), a1
|
|
|
++ vssseg3e32.v v4, 0(a0), a1
|
|
|
++ vssseg3e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e32.v v4, (a0), a1
|
|
|
++ vlsseg4e32.v v4, 0(a0), a1
|
|
|
++ vlsseg4e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e32.v v4, (a0), a1
|
|
|
++ vssseg4e32.v v4, 0(a0), a1
|
|
|
++ vssseg4e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e32.v v4, (a0), a1
|
|
|
++ vlsseg5e32.v v4, 0(a0), a1
|
|
|
++ vlsseg5e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e32.v v4, (a0), a1
|
|
|
++ vssseg5e32.v v4, 0(a0), a1
|
|
|
++ vssseg5e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e32.v v4, (a0), a1
|
|
|
++ vlsseg6e32.v v4, 0(a0), a1
|
|
|
++ vlsseg6e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e32.v v4, (a0), a1
|
|
|
++ vssseg6e32.v v4, 0(a0), a1
|
|
|
++ vssseg6e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e32.v v4, (a0), a1
|
|
|
++ vlsseg7e32.v v4, 0(a0), a1
|
|
|
++ vlsseg7e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e32.v v4, (a0), a1
|
|
|
++ vssseg7e32.v v4, 0(a0), a1
|
|
|
++ vssseg7e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e32.v v4, (a0), a1
|
|
|
++ vlsseg8e32.v v4, 0(a0), a1
|
|
|
++ vlsseg8e32.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e32.v v4, (a0), a1
|
|
|
++ vssseg8e32.v v4, 0(a0), a1
|
|
|
++ vssseg8e32.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg2e64.v v4, (a0), a1
|
|
|
++ vlsseg2e64.v v4, 0(a0), a1
|
|
|
++ vlsseg2e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg2e64.v v4, (a0), a1
|
|
|
++ vssseg2e64.v v4, 0(a0), a1
|
|
|
++ vssseg2e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg3e64.v v4, (a0), a1
|
|
|
++ vlsseg3e64.v v4, 0(a0), a1
|
|
|
++ vlsseg3e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg3e64.v v4, (a0), a1
|
|
|
++ vssseg3e64.v v4, 0(a0), a1
|
|
|
++ vssseg3e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg4e64.v v4, (a0), a1
|
|
|
++ vlsseg4e64.v v4, 0(a0), a1
|
|
|
++ vlsseg4e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg4e64.v v4, (a0), a1
|
|
|
++ vssseg4e64.v v4, 0(a0), a1
|
|
|
++ vssseg4e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg5e64.v v4, (a0), a1
|
|
|
++ vlsseg5e64.v v4, 0(a0), a1
|
|
|
++ vlsseg5e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg5e64.v v4, (a0), a1
|
|
|
++ vssseg5e64.v v4, 0(a0), a1
|
|
|
++ vssseg5e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg6e64.v v4, (a0), a1
|
|
|
++ vlsseg6e64.v v4, 0(a0), a1
|
|
|
++ vlsseg6e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg6e64.v v4, (a0), a1
|
|
|
++ vssseg6e64.v v4, 0(a0), a1
|
|
|
++ vssseg6e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg7e64.v v4, (a0), a1
|
|
|
++ vlsseg7e64.v v4, 0(a0), a1
|
|
|
++ vlsseg7e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg7e64.v v4, (a0), a1
|
|
|
++ vssseg7e64.v v4, 0(a0), a1
|
|
|
++ vssseg7e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vlsseg8e64.v v4, (a0), a1
|
|
|
++ vlsseg8e64.v v4, 0(a0), a1
|
|
|
++ vlsseg8e64.v v4, (a0), a1, v0.t
|
|
|
++ vssseg8e64.v v4, (a0), a1
|
|
|
++ vssseg8e64.v v4, 0(a0), a1
|
|
|
++ vssseg8e64.v v4, (a0), a1, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei8.v v4, (a0), v12
|
|
|
++ vloxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vloxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg2ei8.v v4, (a0), v12
|
|
|
++ vsoxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vsoxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg3ei8.v v4, (a0), v12
|
|
|
++ vloxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vloxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg3ei8.v v4, (a0), v12
|
|
|
++ vsoxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vsoxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg4ei8.v v4, (a0), v12
|
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++ vloxseg4ei8.v v4, 0(a0), v12
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++ vloxseg4ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei8.v v4, (a0), v12
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++ vsoxseg4ei8.v v4, 0(a0), v12
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++ vsoxseg4ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg5ei8.v v4, (a0), v12
|
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++ vloxseg5ei8.v v4, 0(a0), v12
|
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++ vloxseg5ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg5ei8.v v4, (a0), v12
|
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++ vsoxseg5ei8.v v4, 0(a0), v12
|
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++ vsoxseg5ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg6ei8.v v4, (a0), v12
|
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++ vloxseg6ei8.v v4, 0(a0), v12
|
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++ vloxseg6ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg6ei8.v v4, (a0), v12
|
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++ vsoxseg6ei8.v v4, 0(a0), v12
|
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++ vsoxseg6ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg7ei8.v v4, (a0), v12
|
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++ vloxseg7ei8.v v4, 0(a0), v12
|
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++ vloxseg7ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg7ei8.v v4, (a0), v12
|
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++ vsoxseg7ei8.v v4, 0(a0), v12
|
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++ vsoxseg7ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg8ei8.v v4, (a0), v12
|
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++ vloxseg8ei8.v v4, 0(a0), v12
|
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++ vloxseg8ei8.v v4, (a0), v12, v0.t
|
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++ vsoxseg8ei8.v v4, (a0), v12
|
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++ vsoxseg8ei8.v v4, 0(a0), v12
|
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++ vsoxseg8ei8.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg2ei16.v v4, (a0), v12
|
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++ vloxseg2ei16.v v4, 0(a0), v12
|
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++ vloxseg2ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg2ei16.v v4, (a0), v12
|
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++ vsoxseg2ei16.v v4, 0(a0), v12
|
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++ vsoxseg2ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg3ei16.v v4, (a0), v12
|
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++ vloxseg3ei16.v v4, 0(a0), v12
|
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++ vloxseg3ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg3ei16.v v4, (a0), v12
|
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++ vsoxseg3ei16.v v4, 0(a0), v12
|
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++ vsoxseg3ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg4ei16.v v4, (a0), v12
|
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++ vloxseg4ei16.v v4, 0(a0), v12
|
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++ vloxseg4ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg4ei16.v v4, (a0), v12
|
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++ vsoxseg4ei16.v v4, 0(a0), v12
|
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++ vsoxseg4ei16.v v4, (a0), v12, v0.t
|
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++
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++ vloxseg5ei16.v v4, (a0), v12
|
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++ vloxseg5ei16.v v4, 0(a0), v12
|
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++ vloxseg5ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg5ei16.v v4, (a0), v12
|
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++ vsoxseg5ei16.v v4, 0(a0), v12
|
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++ vsoxseg5ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg6ei16.v v4, (a0), v12
|
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++ vloxseg6ei16.v v4, 0(a0), v12
|
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++ vloxseg6ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg6ei16.v v4, (a0), v12
|
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++ vsoxseg6ei16.v v4, 0(a0), v12
|
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++ vsoxseg6ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg7ei16.v v4, (a0), v12
|
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++ vloxseg7ei16.v v4, 0(a0), v12
|
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++ vloxseg7ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg7ei16.v v4, (a0), v12
|
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++ vsoxseg7ei16.v v4, 0(a0), v12
|
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++ vsoxseg7ei16.v v4, (a0), v12, v0.t
|
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++
|
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++ vloxseg8ei16.v v4, (a0), v12
|
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++ vloxseg8ei16.v v4, 0(a0), v12
|
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++ vloxseg8ei16.v v4, (a0), v12, v0.t
|
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++ vsoxseg8ei16.v v4, (a0), v12
|
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++ vsoxseg8ei16.v v4, 0(a0), v12
|
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++ vsoxseg8ei16.v v4, (a0), v12, v0.t
|
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|
++
|
|
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++ vloxseg2ei32.v v4, (a0), v12
|
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++ vloxseg2ei32.v v4, 0(a0), v12
|
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++ vloxseg2ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg2ei32.v v4, (a0), v12
|
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++ vsoxseg2ei32.v v4, 0(a0), v12
|
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|
++ vsoxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg3ei32.v v4, (a0), v12
|
|
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++ vloxseg3ei32.v v4, 0(a0), v12
|
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++ vloxseg3ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg3ei32.v v4, (a0), v12
|
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|
++ vsoxseg3ei32.v v4, 0(a0), v12
|
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|
++ vsoxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg4ei32.v v4, (a0), v12
|
|
|
++ vloxseg4ei32.v v4, 0(a0), v12
|
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|
++ vloxseg4ei32.v v4, (a0), v12, v0.t
|
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|
++ vsoxseg4ei32.v v4, (a0), v12
|
|
|
++ vsoxseg4ei32.v v4, 0(a0), v12
|
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|
++ vsoxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg5ei32.v v4, (a0), v12
|
|
|
++ vloxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg5ei32.v v4, (a0), v12, v0.t
|
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|
++ vsoxseg5ei32.v v4, (a0), v12
|
|
|
++ vsoxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vsoxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg6ei32.v v4, (a0), v12
|
|
|
++ vloxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vloxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg6ei32.v v4, (a0), v12
|
|
|
++ vsoxseg6ei32.v v4, 0(a0), v12
|
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|
++ vsoxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg7ei32.v v4, (a0), v12
|
|
|
++ vloxseg7ei32.v v4, 0(a0), v12
|
|
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++ vloxseg7ei32.v v4, (a0), v12, v0.t
|
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|
++ vsoxseg7ei32.v v4, (a0), v12
|
|
|
++ vsoxseg7ei32.v v4, 0(a0), v12
|
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++ vsoxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
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++ vloxseg8ei32.v v4, (a0), v12
|
|
|
++ vloxseg8ei32.v v4, 0(a0), v12
|
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++ vloxseg8ei32.v v4, (a0), v12, v0.t
|
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++ vsoxseg8ei32.v v4, (a0), v12
|
|
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++ vsoxseg8ei32.v v4, 0(a0), v12
|
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|
++ vsoxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg2ei64.v v4, (a0), v12
|
|
|
++ vloxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg2ei64.v v4, (a0), v12
|
|
|
++ vsoxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg3ei64.v v4, (a0), v12
|
|
|
++ vloxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg3ei64.v v4, (a0), v12
|
|
|
++ vsoxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg4ei64.v v4, (a0), v12
|
|
|
++ vloxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg4ei64.v v4, (a0), v12
|
|
|
++ vsoxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg5ei64.v v4, (a0), v12
|
|
|
++ vloxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg5ei64.v v4, (a0), v12
|
|
|
++ vsoxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg6ei64.v v4, (a0), v12
|
|
|
++ vloxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg6ei64.v v4, (a0), v12
|
|
|
++ vsoxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg7ei64.v v4, (a0), v12
|
|
|
++ vloxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg7ei64.v v4, (a0), v12
|
|
|
++ vsoxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vloxseg8ei64.v v4, (a0), v12
|
|
|
++ vloxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vloxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsoxseg8ei64.v v4, (a0), v12
|
|
|
++ vsoxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vsoxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei8.v v4, (a0), v12
|
|
|
++ vluxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei8.v v4, (a0), v12
|
|
|
++ vsuxseg2ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei8.v v4, (a0), v12
|
|
|
++ vluxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei8.v v4, (a0), v12
|
|
|
++ vsuxseg3ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei8.v v4, (a0), v12
|
|
|
++ vluxseg4ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei8.v v4, (a0), v12
|
|
|
++ vsuxseg4ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei8.v v4, (a0), v12
|
|
|
++ vluxseg5ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei8.v v4, (a0), v12
|
|
|
++ vsuxseg5ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei8.v v4, (a0), v12
|
|
|
++ vluxseg6ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei8.v v4, (a0), v12
|
|
|
++ vsuxseg6ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei8.v v4, (a0), v12
|
|
|
++ vluxseg7ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei8.v v4, (a0), v12
|
|
|
++ vsuxseg7ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei8.v v4, (a0), v12
|
|
|
++ vluxseg8ei8.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei8.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei8.v v4, (a0), v12
|
|
|
++ vsuxseg8ei8.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei8.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei16.v v4, (a0), v12
|
|
|
++ vluxseg2ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei16.v v4, (a0), v12
|
|
|
++ vsuxseg2ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei16.v v4, (a0), v12
|
|
|
++ vluxseg3ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei16.v v4, (a0), v12
|
|
|
++ vsuxseg3ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei16.v v4, (a0), v12
|
|
|
++ vluxseg4ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei16.v v4, (a0), v12
|
|
|
++ vsuxseg4ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei16.v v4, (a0), v12
|
|
|
++ vluxseg5ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei16.v v4, (a0), v12
|
|
|
++ vsuxseg5ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei16.v v4, (a0), v12
|
|
|
++ vluxseg6ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei16.v v4, (a0), v12
|
|
|
++ vsuxseg6ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei16.v v4, (a0), v12
|
|
|
++ vluxseg7ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei16.v v4, (a0), v12
|
|
|
++ vsuxseg7ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei16.v v4, (a0), v12
|
|
|
++ vluxseg8ei16.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei16.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei16.v v4, (a0), v12
|
|
|
++ vsuxseg8ei16.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei16.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei32.v v4, (a0), v12
|
|
|
++ vluxseg2ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei32.v v4, (a0), v12
|
|
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++ vsuxseg2ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei32.v v4, (a0), v12
|
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++ vluxseg3ei32.v v4, 0(a0), v12
|
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|
++ vluxseg3ei32.v v4, (a0), v12, v0.t
|
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++ vsuxseg3ei32.v v4, (a0), v12
|
|
|
++ vsuxseg3ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei32.v v4, (a0), v12
|
|
|
++ vluxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei32.v v4, (a0), v12
|
|
|
++ vsuxseg4ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei32.v v4, (a0), v12
|
|
|
++ vluxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei32.v v4, (a0), v12
|
|
|
++ vsuxseg5ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei32.v v4, (a0), v12
|
|
|
++ vluxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei32.v v4, (a0), v12
|
|
|
++ vsuxseg6ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei32.v v4, (a0), v12
|
|
|
++ vluxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei32.v v4, (a0), v12
|
|
|
++ vsuxseg7ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei32.v v4, (a0), v12
|
|
|
++ vluxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei32.v v4, (a0), v12
|
|
|
++ vsuxseg8ei32.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei32.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg2ei64.v v4, (a0), v12
|
|
|
++ vluxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg2ei64.v v4, (a0), v12
|
|
|
++ vsuxseg2ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg2ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg3ei64.v v4, (a0), v12
|
|
|
++ vluxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg3ei64.v v4, (a0), v12
|
|
|
++ vsuxseg3ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg3ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg4ei64.v v4, (a0), v12
|
|
|
++ vluxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg4ei64.v v4, (a0), v12
|
|
|
++ vsuxseg4ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg4ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg5ei64.v v4, (a0), v12
|
|
|
++ vluxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg5ei64.v v4, (a0), v12
|
|
|
++ vsuxseg5ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg5ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg6ei64.v v4, (a0), v12
|
|
|
++ vluxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg6ei64.v v4, (a0), v12
|
|
|
++ vsuxseg6ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg6ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg7ei64.v v4, (a0), v12
|
|
|
++ vluxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg7ei64.v v4, (a0), v12
|
|
|
++ vsuxseg7ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg7ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vluxseg8ei64.v v4, (a0), v12
|
|
|
++ vluxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vluxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++ vsuxseg8ei64.v v4, (a0), v12
|
|
|
++ vsuxseg8ei64.v v4, 0(a0), v12
|
|
|
++ vsuxseg8ei64.v v4, (a0), v12, v0.t
|
|
|
++
|
|
|
++ vlseg2e8ff.v v4, (a0)
|
|
|
++ vlseg2e8ff.v v4, 0(a0)
|
|
|
++ vlseg2e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e8ff.v v4, (a0)
|
|
|
++ vlseg3e8ff.v v4, 0(a0)
|
|
|
++ vlseg3e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e8ff.v v4, (a0)
|
|
|
++ vlseg4e8ff.v v4, 0(a0)
|
|
|
++ vlseg4e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e8ff.v v4, (a0)
|
|
|
++ vlseg5e8ff.v v4, 0(a0)
|
|
|
++ vlseg5e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e8ff.v v4, (a0)
|
|
|
++ vlseg6e8ff.v v4, 0(a0)
|
|
|
++ vlseg6e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e8ff.v v4, (a0)
|
|
|
++ vlseg7e8ff.v v4, 0(a0)
|
|
|
++ vlseg7e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e8ff.v v4, (a0)
|
|
|
++ vlseg8e8ff.v v4, 0(a0)
|
|
|
++ vlseg8e8ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e16ff.v v4, (a0)
|
|
|
++ vlseg2e16ff.v v4, 0(a0)
|
|
|
++ vlseg2e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e16ff.v v4, (a0)
|
|
|
++ vlseg3e16ff.v v4, 0(a0)
|
|
|
++ vlseg3e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e16ff.v v4, (a0)
|
|
|
++ vlseg4e16ff.v v4, 0(a0)
|
|
|
++ vlseg4e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e16ff.v v4, (a0)
|
|
|
++ vlseg5e16ff.v v4, 0(a0)
|
|
|
++ vlseg5e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e16ff.v v4, (a0)
|
|
|
++ vlseg6e16ff.v v4, 0(a0)
|
|
|
++ vlseg6e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e16ff.v v4, (a0)
|
|
|
++ vlseg7e16ff.v v4, 0(a0)
|
|
|
++ vlseg7e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e16ff.v v4, (a0)
|
|
|
++ vlseg8e16ff.v v4, 0(a0)
|
|
|
++ vlseg8e16ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e32ff.v v4, (a0)
|
|
|
++ vlseg2e32ff.v v4, 0(a0)
|
|
|
++ vlseg2e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e32ff.v v4, (a0)
|
|
|
++ vlseg3e32ff.v v4, 0(a0)
|
|
|
++ vlseg3e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e32ff.v v4, (a0)
|
|
|
++ vlseg4e32ff.v v4, 0(a0)
|
|
|
++ vlseg4e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e32ff.v v4, (a0)
|
|
|
++ vlseg5e32ff.v v4, 0(a0)
|
|
|
++ vlseg5e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e32ff.v v4, (a0)
|
|
|
++ vlseg6e32ff.v v4, 0(a0)
|
|
|
++ vlseg6e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e32ff.v v4, (a0)
|
|
|
++ vlseg7e32ff.v v4, 0(a0)
|
|
|
++ vlseg7e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e32ff.v v4, (a0)
|
|
|
++ vlseg8e32ff.v v4, 0(a0)
|
|
|
++ vlseg8e32ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg2e64ff.v v4, (a0)
|
|
|
++ vlseg2e64ff.v v4, 0(a0)
|
|
|
++ vlseg2e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg3e64ff.v v4, (a0)
|
|
|
++ vlseg3e64ff.v v4, 0(a0)
|
|
|
++ vlseg3e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg4e64ff.v v4, (a0)
|
|
|
++ vlseg4e64ff.v v4, 0(a0)
|
|
|
++ vlseg4e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg5e64ff.v v4, (a0)
|
|
|
++ vlseg5e64ff.v v4, 0(a0)
|
|
|
++ vlseg5e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg6e64ff.v v4, (a0)
|
|
|
++ vlseg6e64ff.v v4, 0(a0)
|
|
|
++ vlseg6e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg7e64ff.v v4, (a0)
|
|
|
++ vlseg7e64ff.v v4, 0(a0)
|
|
|
++ vlseg7e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vlseg8e64ff.v v4, (a0)
|
|
|
++ vlseg8e64ff.v v4, 0(a0)
|
|
|
++ vlseg8e64ff.v v4, (a0), v0.t
|
|
|
++
|
|
|
++ vl1r.v v3, (a0)
|
|
|
++ vl1r.v v3, 0(a0)
|
|
|
++ vl1re8.v v3, (a0)
|
|
|
++ vl1re8.v v3, 0(a0)
|
|
|
++ vl1re16.v v3, (a0)
|
|
|
++ vl1re16.v v3, 0(a0)
|
|
|
++ vl1re32.v v3, (a0)
|
|
|
++ vl1re32.v v3, 0(a0)
|
|
|
++ vl1re64.v v3, (a0)
|
|
|
++ vl1re64.v v3, 0(a0)
|
|
|
++
|
|
|
++ vl2r.v v2, (a0)
|
|
|
++ vl2r.v v2, 0(a0)
|
|
|
++ vl2re8.v v2, (a0)
|
|
|
++ vl2re8.v v2, 0(a0)
|
|
|
++ vl2re16.v v2, (a0)
|
|
|
++ vl2re16.v v2, 0(a0)
|
|
|
++ vl2re32.v v2, (a0)
|
|
|
++ vl2re32.v v2, 0(a0)
|
|
|
++ vl2re64.v v2, (a0)
|
|
|
++ vl2re64.v v2, 0(a0)
|
|
|
++
|
|
|
++ vl4r.v v4, (a0)
|
|
|
++ vl4r.v v4, 0(a0)
|
|
|
++ vl4re8.v v4, (a0)
|
|
|
++ vl4re8.v v4, 0(a0)
|
|
|
++ vl4re16.v v4, (a0)
|
|
|
++ vl4re16.v v4, 0(a0)
|
|
|
++ vl4re32.v v4, (a0)
|
|
|
++ vl4re32.v v4, 0(a0)
|
|
|
++ vl4re64.v v4, (a0)
|
|
|
++ vl4re64.v v4, 0(a0)
|
|
|
++
|
|
|
++ vl8r.v v8, (a0)
|
|
|
++ vl8r.v v8, 0(a0)
|
|
|
++ vl8re8.v v8, (a0)
|
|
|
++ vl8re8.v v8, 0(a0)
|
|
|
++ vl8re16.v v8, (a0)
|
|
|
++ vl8re16.v v8, 0(a0)
|
|
|
++ vl8re32.v v8, (a0)
|
|
|
++ vl8re32.v v8, 0(a0)
|
|
|
++ vl8re64.v v8, (a0)
|
|
|
++ vl8re64.v v8, 0(a0)
|
|
|
++
|
|
|
++ vs1r.v v3, (a1)
|
|
|
++ vs1r.v v3, 0(a1)
|
|
|
++ vs2r.v v2, (a1)
|
|
|
++ vs2r.v v2, 0(a1)
|
|
|
++ vs4r.v v4, (a1)
|
|
|
++ vs4r.v v4, 0(a1)
|
|
|
++ vs8r.v v8, (a1)
|
|
|
++ vs8r.v v8, 0(a1)
|
|
|
++
|
|
|
++ vamoaddei8.v v4, (a1), v8, v4
|
|
|
++ vamoaddei8.v x0, (a1), v8, v4
|
|
|
++ vamoaddei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v v4, (a1), v8, v4
|
|
|
++ vamoswapei8.v x0, (a1), v8, v4
|
|
|
++ vamoswapei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v4, (a1), v8, v4
|
|
|
++ vamoxorei8.v x0, (a1), v8, v4
|
|
|
++ vamoxorei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v v4, (a1), v8, v4
|
|
|
++ vamoandei8.v x0, (a1), v8, v4
|
|
|
++ vamoandei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v v4, (a1), v8, v4
|
|
|
++ vamoorei8.v x0, (a1), v8, v4
|
|
|
++ vamoorei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v4, (a1), v8, v4
|
|
|
++ vamominei8.v x0, (a1), v8, v4
|
|
|
++ vamominei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v v4, (a1), v8, v4
|
|
|
++ vamomaxei8.v x0, (a1), v8, v4
|
|
|
++ vamomaxei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v v4, (a1), v8, v4
|
|
|
++ vamominuei8.v x0, (a1), v8, v4
|
|
|
++ vamominuei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei8.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei8.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei8.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei8.v v4, 0(a1), v8, v4
|
|
|
++ vamominei8.v x0, 0(a1), v8, v4
|
|
|
++ vamominei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei8.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei8.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei8.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v4, (a1), v8, v4
|
|
|
++ vamoaddei16.v x0, (a1), v8, v4
|
|
|
++ vamoaddei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v v4, (a1), v8, v4
|
|
|
++ vamoswapei16.v x0, (a1), v8, v4
|
|
|
++ vamoswapei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v4, (a1), v8, v4
|
|
|
++ vamoxorei16.v x0, (a1), v8, v4
|
|
|
++ vamoxorei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v v4, (a1), v8, v4
|
|
|
++ vamoandei16.v x0, (a1), v8, v4
|
|
|
++ vamoandei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v v4, (a1), v8, v4
|
|
|
++ vamoorei16.v x0, (a1), v8, v4
|
|
|
++ vamoorei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v4, (a1), v8, v4
|
|
|
++ vamominei16.v x0, (a1), v8, v4
|
|
|
++ vamominei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v v4, (a1), v8, v4
|
|
|
++ vamomaxei16.v x0, (a1), v8, v4
|
|
|
++ vamomaxei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v v4, (a1), v8, v4
|
|
|
++ vamominuei16.v x0, (a1), v8, v4
|
|
|
++ vamominuei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei16.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei16.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei16.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei16.v v4, 0(a1), v8, v4
|
|
|
++ vamominei16.v x0, 0(a1), v8, v4
|
|
|
++ vamominei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei16.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei16.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei16.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v4, (a1), v8, v4
|
|
|
++ vamoaddei32.v x0, (a1), v8, v4
|
|
|
++ vamoaddei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v v4, (a1), v8, v4
|
|
|
++ vamoswapei32.v x0, (a1), v8, v4
|
|
|
++ vamoswapei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v4, (a1), v8, v4
|
|
|
++ vamoxorei32.v x0, (a1), v8, v4
|
|
|
++ vamoxorei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v v4, (a1), v8, v4
|
|
|
++ vamoandei32.v x0, (a1), v8, v4
|
|
|
++ vamoandei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v v4, (a1), v8, v4
|
|
|
++ vamoorei32.v x0, (a1), v8, v4
|
|
|
++ vamoorei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v4, (a1), v8, v4
|
|
|
++ vamominei32.v x0, (a1), v8, v4
|
|
|
++ vamominei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v v4, (a1), v8, v4
|
|
|
++ vamomaxei32.v x0, (a1), v8, v4
|
|
|
++ vamomaxei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v v4, (a1), v8, v4
|
|
|
++ vamominuei32.v x0, (a1), v8, v4
|
|
|
++ vamominuei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei32.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei32.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei32.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei32.v v4, 0(a1), v8, v4
|
|
|
++ vamominei32.v x0, 0(a1), v8, v4
|
|
|
++ vamominei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei32.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei32.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei32.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v4, (a1), v8, v4
|
|
|
++ vamoaddei64.v x0, (a1), v8, v4
|
|
|
++ vamoaddei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoaddei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v v4, (a1), v8, v4
|
|
|
++ vamoswapei64.v x0, (a1), v8, v4
|
|
|
++ vamoswapei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v4, (a1), v8, v4
|
|
|
++ vamoxorei64.v x0, (a1), v8, v4
|
|
|
++ vamoxorei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoxorei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v v4, (a1), v8, v4
|
|
|
++ vamoandei64.v x0, (a1), v8, v4
|
|
|
++ vamoandei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v v4, (a1), v8, v4
|
|
|
++ vamoorei64.v x0, (a1), v8, v4
|
|
|
++ vamoorei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v4, (a1), v8, v4
|
|
|
++ vamominei64.v x0, (a1), v8, v4
|
|
|
++ vamominei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v v4, (a1), v8, v4
|
|
|
++ vamomaxei64.v x0, (a1), v8, v4
|
|
|
++ vamomaxei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v v4, (a1), v8, v4
|
|
|
++ vamominuei64.v x0, (a1), v8, v4
|
|
|
++ vamominuei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v x0, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v v4, (a1), v8, v4
|
|
|
++ vamomaxuei64.v x0, (a1), v8, v4
|
|
|
++ vamomaxuei64.v v4, (a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v x0, (a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoaddei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoaddei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoaddei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoaddei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoswapei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoswapei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoswapei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamoxorei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoxorei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoxorei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoxorei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoandei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoandei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoandei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v v4, 0(a1), v8, v4
|
|
|
++ vamoorei64.v x0, 0(a1), v8, v4
|
|
|
++ vamoorei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamoorei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vamominei64.v v4, 0(a1), v8, v4
|
|
|
++ vamominei64.v x0, 0(a1), v8, v4
|
|
|
++ vamominei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxei64.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v v4, 0(a1), v8, v4
|
|
|
++ vamominuei64.v x0, 0(a1), v8, v4
|
|
|
++ vamominuei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamominuei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v v4, 0(a1), v8, v4
|
|
|
++ vamomaxuei64.v x0, 0(a1), v8, v4
|
|
|
++ vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
|
|
|
++ vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
|
|
|
++
|
|
|
++ vneg.v v4, v8
|
|
|
++ vneg.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vadd.vv v4, v8, v12
|
|
|
++ vadd.vx v4, v8, a1
|
|
|
++ vadd.vi v4, v8, 15
|
|
|
++ vadd.vi v4, v8, -16
|
|
|
++ vadd.vv v4, v8, v12, v0.t
|
|
|
++ vadd.vx v4, v8, a1, v0.t
|
|
|
++ vadd.vi v4, v8, 15, v0.t
|
|
|
++ vadd.vi v4, v8, -16, v0.t
|
|
|
++ vsub.vv v4, v8, v12
|
|
|
++ vsub.vx v4, v8, a1
|
|
|
++ vrsub.vx v4, v8, a1
|
|
|
++ vrsub.vi v4, v8, 15
|
|
|
++ vrsub.vi v4, v8, -16
|
|
|
++ vsub.vv v4, v8, v12, v0.t
|
|
|
++ vsub.vx v4, v8, a1, v0.t
|
|
|
++ vrsub.vx v4, v8, a1, v0.t
|
|
|
++ vrsub.vi v4, v8, 15, v0.t
|
|
|
++ vrsub.vi v4, v8, -16, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vwcvt.x.x.v v4, v8
|
|
|
++ vwcvtu.x.x.v v4, v8
|
|
|
++ vwcvt.x.x.v v4, v8, v0.t
|
|
|
++ vwcvtu.x.x.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vwaddu.vv v4, v8, v12
|
|
|
++ vwaddu.vx v4, v8, a1
|
|
|
++ vwaddu.vv v4, v8, v12, v0.t
|
|
|
++ vwaddu.vx v4, v8, a1, v0.t
|
|
|
++ vwsubu.vv v4, v8, v12
|
|
|
++ vwsubu.vx v4, v8, a1
|
|
|
++ vwsubu.vv v4, v8, v12, v0.t
|
|
|
++ vwsubu.vx v4, v8, a1, v0.t
|
|
|
++ vwadd.vv v4, v8, v12
|
|
|
++ vwadd.vx v4, v8, a1
|
|
|
++ vwadd.vv v4, v8, v12, v0.t
|
|
|
++ vwadd.vx v4, v8, a1, v0.t
|
|
|
++ vwsub.vv v4, v8, v12
|
|
|
++ vwsub.vx v4, v8, a1
|
|
|
++ vwsub.vv v4, v8, v12, v0.t
|
|
|
++ vwsub.vx v4, v8, a1, v0.t
|
|
|
++ vwaddu.wv v4, v8, v12
|
|
|
++ vwaddu.wx v4, v8, a1
|
|
|
++ vwaddu.wv v4, v8, v12, v0.t
|
|
|
++ vwaddu.wx v4, v8, a1, v0.t
|
|
|
++ vwsubu.wv v4, v8, v12
|
|
|
++ vwsubu.wx v4, v8, a1
|
|
|
++ vwsubu.wv v4, v8, v12, v0.t
|
|
|
++ vwsubu.wx v4, v8, a1, v0.t
|
|
|
++ vwadd.wv v4, v8, v12
|
|
|
++ vwadd.wx v4, v8, a1
|
|
|
++ vwadd.wv v4, v8, v12, v0.t
|
|
|
++ vwadd.wx v4, v8, a1, v0.t
|
|
|
++ vwsub.wv v4, v8, v12
|
|
|
++ vwsub.wx v4, v8, a1
|
|
|
++ vwsub.wv v4, v8, v12, v0.t
|
|
|
++ vwsub.wx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vzext.vf2 v4, v8
|
|
|
++ vzext.vf2 v4, v8, v0.t
|
|
|
++ vsext.vf2 v4, v8
|
|
|
++ vsext.vf2 v4, v8, v0.t
|
|
|
++ vzext.vf4 v4, v8
|
|
|
++ vzext.vf4 v4, v8, v0.t
|
|
|
++ vsext.vf4 v4, v8
|
|
|
++ vsext.vf4 v4, v8, v0.t
|
|
|
++ vzext.vf8 v4, v8
|
|
|
++ vzext.vf8 v4, v8, v0.t
|
|
|
++ vsext.vf8 v4, v8
|
|
|
++ vsext.vf8 v4, v8, v0.t
|
|
|
++
|
|
|
++ vadc.vvm v4, v8, v12, v0
|
|
|
++ vadc.vxm v4, v8, a1, v0
|
|
|
++ vadc.vim v4, v8, 15, v0
|
|
|
++ vadc.vim v4, v8, -16, v0
|
|
|
++ vmadc.vvm v4, v8, v12, v0
|
|
|
++ vmadc.vxm v4, v8, a1, v0
|
|
|
++ vmadc.vim v4, v8, 15, v0
|
|
|
++ vmadc.vim v4, v8, -16, v0
|
|
|
++ vmadc.vv v4, v8, v12
|
|
|
++ vmadc.vx v4, v8, a1
|
|
|
++ vmadc.vi v4, v8, 15
|
|
|
++ vmadc.vi v4, v8, -16
|
|
|
++ vsbc.vvm v4, v8, v12, v0
|
|
|
++ vsbc.vxm v4, v8, a1, v0
|
|
|
++ vmsbc.vvm v4, v8, v12, v0
|
|
|
++ vmsbc.vxm v4, v8, a1, v0
|
|
|
++ vmsbc.vv v4, v8, v12
|
|
|
++ vmsbc.vx v4, v8, a1
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vnot.v v4, v8
|
|
|
++ vnot.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vand.vv v4, v8, v12
|
|
|
++ vand.vx v4, v8, a1
|
|
|
++ vand.vi v4, v8, 15
|
|
|
++ vand.vi v4, v8, -16
|
|
|
++ vand.vv v4, v8, v12, v0.t
|
|
|
++ vand.vx v4, v8, a1, v0.t
|
|
|
++ vand.vi v4, v8, 15, v0.t
|
|
|
++ vand.vi v4, v8, -16, v0.t
|
|
|
++ vor.vv v4, v8, v12
|
|
|
++ vor.vx v4, v8, a1
|
|
|
++ vor.vi v4, v8, 15
|
|
|
++ vor.vi v4, v8, -16
|
|
|
++ vor.vv v4, v8, v12, v0.t
|
|
|
++ vor.vx v4, v8, a1, v0.t
|
|
|
++ vor.vi v4, v8, 15, v0.t
|
|
|
++ vor.vi v4, v8, -16, v0.t
|
|
|
++ vxor.vv v4, v8, v12
|
|
|
++ vxor.vx v4, v8, a1
|
|
|
++ vxor.vi v4, v8, 15
|
|
|
++ vxor.vi v4, v8, -16
|
|
|
++ vxor.vv v4, v8, v12, v0.t
|
|
|
++ vxor.vx v4, v8, a1, v0.t
|
|
|
++ vxor.vi v4, v8, 15, v0.t
|
|
|
++ vxor.vi v4, v8, -16, v0.t
|
|
|
++
|
|
|
++ vsll.vv v4, v8, v12
|
|
|
++ vsll.vx v4, v8, a1
|
|
|
++ vsll.vi v4, v8, 1
|
|
|
++ vsll.vi v4, v8, 31
|
|
|
++ vsll.vv v4, v8, v12, v0.t
|
|
|
++ vsll.vx v4, v8, a1, v0.t
|
|
|
++ vsll.vi v4, v8, 1, v0.t
|
|
|
++ vsll.vi v4, v8, 31, v0.t
|
|
|
++ vsrl.vv v4, v8, v12
|
|
|
++ vsrl.vx v4, v8, a1
|
|
|
++ vsrl.vi v4, v8, 1
|
|
|
++ vsrl.vi v4, v8, 31
|
|
|
++ vsrl.vv v4, v8, v12, v0.t
|
|
|
++ vsrl.vx v4, v8, a1, v0.t
|
|
|
++ vsrl.vi v4, v8, 1, v0.t
|
|
|
++ vsrl.vi v4, v8, 31, v0.t
|
|
|
++ vsra.vv v4, v8, v12
|
|
|
++ vsra.vx v4, v8, a1
|
|
|
++ vsra.vi v4, v8, 1
|
|
|
++ vsra.vi v4, v8, 31
|
|
|
++ vsra.vv v4, v8, v12, v0.t
|
|
|
++ vsra.vx v4, v8, a1, v0.t
|
|
|
++ vsra.vi v4, v8, 1, v0.t
|
|
|
++ vsra.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vncvt.x.x.w v4, v8
|
|
|
++ vncvt.x.x.w v4, v8, v0.t
|
|
|
++
|
|
|
++ vnsrl.wv v4, v8, v12
|
|
|
++ vnsrl.wx v4, v8, a1
|
|
|
++ vnsrl.wi v4, v8, 1
|
|
|
++ vnsrl.wi v4, v8, 31
|
|
|
++ vnsrl.wv v4, v8, v12, v0.t
|
|
|
++ vnsrl.wx v4, v8, a1, v0.t
|
|
|
++ vnsrl.wi v4, v8, 1, v0.t
|
|
|
++ vnsrl.wi v4, v8, 31, v0.t
|
|
|
++ vnsra.wv v4, v8, v12
|
|
|
++ vnsra.wx v4, v8, a1
|
|
|
++ vnsra.wi v4, v8, 1
|
|
|
++ vnsra.wi v4, v8, 31
|
|
|
++ vnsra.wv v4, v8, v12, v0.t
|
|
|
++ vnsra.wx v4, v8, a1, v0.t
|
|
|
++ vnsra.wi v4, v8, 1, v0.t
|
|
|
++ vnsra.wi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vmsgt.vv v4, v8, v12
|
|
|
++ vmsgtu.vv v4, v8, v12
|
|
|
++ vmsge.vv v4, v8, v12
|
|
|
++ vmsgeu.vv v4, v8, v12
|
|
|
++ vmsgt.vv v4, v8, v12, v0.t
|
|
|
++ vmsgtu.vv v4, v8, v12, v0.t
|
|
|
++ vmsge.vv v4, v8, v12, v0.t
|
|
|
++ vmsgeu.vv v4, v8, v12, v0.t
|
|
|
++ vmslt.vi v4, v8, 16
|
|
|
++ vmslt.vi v4, v8, -15
|
|
|
++ vmsltu.vi v4, v8, 16
|
|
|
++ vmsltu.vi v4, v8, -15
|
|
|
++ vmsge.vi v4, v8, 16
|
|
|
++ vmsge.vi v4, v8, -15
|
|
|
++ vmsgeu.vi v4, v8, 16
|
|
|
++ vmsgeu.vi v4, v8, -15
|
|
|
++ vmslt.vi v4, v8, 16, v0.t
|
|
|
++ vmslt.vi v4, v8, -15, v0.t
|
|
|
++ vmsltu.vi v4, v8, 16, v0.t
|
|
|
++ vmsltu.vi v4, v8, -15, v0.t
|
|
|
++ vmsge.vi v4, v8, 16, v0.t
|
|
|
++ vmsge.vi v4, v8, -15, v0.t
|
|
|
++ vmsgeu.vi v4, v8, 16, v0.t
|
|
|
++ vmsgeu.vi v4, v8, -15, v0.t
|
|
|
++
|
|
|
++ vmseq.vv v4, v8, v12
|
|
|
++ vmseq.vx v4, v8, a1
|
|
|
++ vmseq.vi v4, v8, 15
|
|
|
++ vmseq.vi v4, v8, -16
|
|
|
++ vmseq.vv v4, v8, v12, v0.t
|
|
|
++ vmseq.vx v4, v8, a1, v0.t
|
|
|
++ vmseq.vi v4, v8, 15, v0.t
|
|
|
++ vmseq.vi v4, v8, -16, v0.t
|
|
|
++ vmsne.vv v4, v8, v12
|
|
|
++ vmsne.vx v4, v8, a1
|
|
|
++ vmsne.vi v4, v8, 15
|
|
|
++ vmsne.vi v4, v8, -16
|
|
|
++ vmsne.vv v4, v8, v12, v0.t
|
|
|
++ vmsne.vx v4, v8, a1, v0.t
|
|
|
++ vmsne.vi v4, v8, 15, v0.t
|
|
|
++ vmsne.vi v4, v8, -16, v0.t
|
|
|
++ vmsltu.vv v4, v8, v12
|
|
|
++ vmsltu.vx v4, v8, a1
|
|
|
++ vmsltu.vv v4, v8, v12, v0.t
|
|
|
++ vmsltu.vx v4, v8, a1, v0.t
|
|
|
++ vmslt.vv v4, v8, v12
|
|
|
++ vmslt.vx v4, v8, a1
|
|
|
++ vmslt.vv v4, v8, v12, v0.t
|
|
|
++ vmslt.vx v4, v8, a1, v0.t
|
|
|
++ vmsleu.vv v4, v8, v12
|
|
|
++ vmsleu.vx v4, v8, a1
|
|
|
++ vmsleu.vi v4, v8, 15
|
|
|
++ vmsleu.vi v4, v8, -16
|
|
|
++ vmsleu.vv v4, v8, v12, v0.t
|
|
|
++ vmsleu.vx v4, v8, a1, v0.t
|
|
|
++ vmsleu.vi v4, v8, 15, v0.t
|
|
|
++ vmsleu.vi v4, v8, -16, v0.t
|
|
|
++ vmsle.vv v4, v8, v12
|
|
|
++ vmsle.vx v4, v8, a1
|
|
|
++ vmsle.vi v4, v8, 15
|
|
|
++ vmsle.vi v4, v8, -16
|
|
|
++ vmsle.vv v4, v8, v12, v0.t
|
|
|
++ vmsle.vx v4, v8, a1, v0.t
|
|
|
++ vmsle.vi v4, v8, 15, v0.t
|
|
|
++ vmsle.vi v4, v8, -16, v0.t
|
|
|
++ vmsgtu.vx v4, v8, a1
|
|
|
++ vmsgtu.vi v4, v8, 15
|
|
|
++ vmsgtu.vi v4, v8, -16
|
|
|
++ vmsgtu.vx v4, v8, a1, v0.t
|
|
|
++ vmsgtu.vi v4, v8, 15, v0.t
|
|
|
++ vmsgtu.vi v4, v8, -16, v0.t
|
|
|
++ vmsgt.vx v4, v8, a1
|
|
|
++ vmsgt.vi v4, v8, 15
|
|
|
++ vmsgt.vi v4, v8, -16
|
|
|
++ vmsgt.vx v4, v8, a1, v0.t
|
|
|
++ vmsgt.vi v4, v8, 15, v0.t
|
|
|
++ vmsgt.vi v4, v8, -16, v0.t
|
|
|
++
|
|
|
++ vminu.vv v4, v8, v12
|
|
|
++ vminu.vx v4, v8, a1
|
|
|
++ vminu.vv v4, v8, v12, v0.t
|
|
|
++ vminu.vx v4, v8, a1, v0.t
|
|
|
++ vmin.vv v4, v8, v12
|
|
|
++ vmin.vx v4, v8, a1
|
|
|
++ vmin.vv v4, v8, v12, v0.t
|
|
|
++ vmin.vx v4, v8, a1, v0.t
|
|
|
++ vmaxu.vv v4, v8, v12
|
|
|
++ vmaxu.vx v4, v8, a1
|
|
|
++ vmaxu.vv v4, v8, v12, v0.t
|
|
|
++ vmaxu.vx v4, v8, a1, v0.t
|
|
|
++ vmax.vv v4, v8, v12
|
|
|
++ vmax.vx v4, v8, a1
|
|
|
++ vmax.vv v4, v8, v12, v0.t
|
|
|
++ vmax.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vmul.vv v4, v8, v12
|
|
|
++ vmul.vx v4, v8, a1
|
|
|
++ vmul.vv v4, v8, v12, v0.t
|
|
|
++ vmul.vx v4, v8, a1, v0.t
|
|
|
++ vmulh.vv v4, v8, v12
|
|
|
++ vmulh.vx v4, v8, a1
|
|
|
++ vmulh.vv v4, v8, v12, v0.t
|
|
|
++ vmulh.vx v4, v8, a1, v0.t
|
|
|
++ vmulhu.vv v4, v8, v12
|
|
|
++ vmulhu.vx v4, v8, a1
|
|
|
++ vmulhu.vv v4, v8, v12, v0.t
|
|
|
++ vmulhu.vx v4, v8, a1, v0.t
|
|
|
++ vmulhsu.vv v4, v8, v12
|
|
|
++ vmulhsu.vx v4, v8, a1
|
|
|
++ vmulhsu.vv v4, v8, v12, v0.t
|
|
|
++ vmulhsu.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vwmul.vv v4, v8, v12
|
|
|
++ vwmul.vx v4, v8, a1
|
|
|
++ vwmul.vv v4, v8, v12, v0.t
|
|
|
++ vwmul.vx v4, v8, a1, v0.t
|
|
|
++ vwmulu.vv v4, v8, v12
|
|
|
++ vwmulu.vx v4, v8, a1
|
|
|
++ vwmulu.vv v4, v8, v12, v0.t
|
|
|
++ vwmulu.vx v4, v8, a1, v0.t
|
|
|
++ vwmulsu.vv v4, v8, v12
|
|
|
++ vwmulsu.vx v4, v8, a1
|
|
|
++ vwmulsu.vv v4, v8, v12, v0.t
|
|
|
++ vwmulsu.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vmacc.vv v4, v12, v8
|
|
|
++ vmacc.vx v4, a1, v8
|
|
|
++ vmacc.vv v4, v12, v8, v0.t
|
|
|
++ vmacc.vx v4, a1, v8, v0.t
|
|
|
++ vnmsac.vv v4, v12, v8
|
|
|
++ vnmsac.vx v4, a1, v8
|
|
|
++ vnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vnmsac.vx v4, a1, v8, v0.t
|
|
|
++ vmadd.vv v4, v12, v8
|
|
|
++ vmadd.vx v4, a1, v8
|
|
|
++ vmadd.vv v4, v12, v8, v0.t
|
|
|
++ vmadd.vx v4, a1, v8, v0.t
|
|
|
++ vnmsub.vv v4, v12, v8
|
|
|
++ vnmsub.vx v4, a1, v8
|
|
|
++ vnmsub.vv v4, v12, v8, v0.t
|
|
|
++ vnmsub.vx v4, a1, v8, v0.t
|
|
|
++
|
|
|
++ vwmaccu.vv v4, v12, v8
|
|
|
++ vwmaccu.vx v4, a1, v8
|
|
|
++ vwmaccu.vv v4, v12, v8, v0.t
|
|
|
++ vwmaccu.vx v4, a1, v8, v0.t
|
|
|
++ vwmacc.vv v4, v12, v8
|
|
|
++ vwmacc.vx v4, a1, v8
|
|
|
++ vwmacc.vv v4, v12, v8, v0.t
|
|
|
++ vwmacc.vx v4, a1, v8, v0.t
|
|
|
++ vwmaccsu.vv v4, v12, v8
|
|
|
++ vwmaccsu.vx v4, a1, v8
|
|
|
++ vwmaccsu.vv v4, v12, v8, v0.t
|
|
|
++ vwmaccsu.vx v4, a1, v8, v0.t
|
|
|
++ vwmaccus.vx v4, a1, v8
|
|
|
++ vwmaccus.vx v4, a1, v8, v0.t
|
|
|
++
|
|
|
++ vdivu.vv v4, v8, v12
|
|
|
++ vdivu.vx v4, v8, a1
|
|
|
++ vdivu.vv v4, v8, v12, v0.t
|
|
|
++ vdivu.vx v4, v8, a1, v0.t
|
|
|
++ vdiv.vv v4, v8, v12
|
|
|
++ vdiv.vx v4, v8, a1
|
|
|
++ vdiv.vv v4, v8, v12, v0.t
|
|
|
++ vdiv.vx v4, v8, a1, v0.t
|
|
|
++ vremu.vv v4, v8, v12
|
|
|
++ vremu.vx v4, v8, a1
|
|
|
++ vremu.vv v4, v8, v12, v0.t
|
|
|
++ vremu.vx v4, v8, a1, v0.t
|
|
|
++ vrem.vv v4, v8, v12
|
|
|
++ vrem.vx v4, v8, a1
|
|
|
++ vrem.vv v4, v8, v12, v0.t
|
|
|
++ vrem.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vmerge.vvm v4, v8, v12, v0
|
|
|
++ vmerge.vxm v4, v8, a1, v0
|
|
|
++ vmerge.vim v4, v8, 15, v0
|
|
|
++ vmerge.vim v4, v8, -16, v0
|
|
|
++
|
|
|
++ vmv.v.v v8, v12
|
|
|
++ vmv.v.x v8, a1
|
|
|
++ vmv.v.i v8, 15
|
|
|
++ vmv.v.i v8, -16
|
|
|
++
|
|
|
++ vsaddu.vv v4, v8, v12
|
|
|
++ vsaddu.vx v4, v8, a1
|
|
|
++ vsaddu.vi v4, v8, 15
|
|
|
++ vsaddu.vi v4, v8, -16
|
|
|
++ vsaddu.vv v4, v8, v12, v0.t
|
|
|
++ vsaddu.vx v4, v8, a1, v0.t
|
|
|
++ vsaddu.vi v4, v8, 15, v0.t
|
|
|
++ vsaddu.vi v4, v8, -16, v0.t
|
|
|
++ vsadd.vv v4, v8, v12
|
|
|
++ vsadd.vx v4, v8, a1
|
|
|
++ vsadd.vi v4, v8, 15
|
|
|
++ vsadd.vi v4, v8, -16
|
|
|
++ vsadd.vv v4, v8, v12, v0.t
|
|
|
++ vsadd.vx v4, v8, a1, v0.t
|
|
|
++ vsadd.vi v4, v8, 15, v0.t
|
|
|
++ vsadd.vi v4, v8, -16, v0.t
|
|
|
++ vssubu.vv v4, v8, v12
|
|
|
++ vssubu.vx v4, v8, a1
|
|
|
++ vssubu.vv v4, v8, v12, v0.t
|
|
|
++ vssubu.vx v4, v8, a1, v0.t
|
|
|
++ vssub.vv v4, v8, v12
|
|
|
++ vssub.vx v4, v8, a1
|
|
|
++ vssub.vv v4, v8, v12, v0.t
|
|
|
++ vssub.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vaaddu.vv v4, v8, v12
|
|
|
++ vaaddu.vx v4, v8, a1
|
|
|
++ vaaddu.vv v4, v8, v12, v0.t
|
|
|
++ vaaddu.vx v4, v8, a1, v0.t
|
|
|
++ vaadd.vv v4, v8, v12
|
|
|
++ vaadd.vx v4, v8, a1
|
|
|
++ vaadd.vv v4, v8, v12, v0.t
|
|
|
++ vaadd.vx v4, v8, a1, v0.t
|
|
|
++ vasubu.vv v4, v8, v12
|
|
|
++ vasubu.vx v4, v8, a1
|
|
|
++ vasubu.vv v4, v8, v12, v0.t
|
|
|
++ vasubu.vx v4, v8, a1, v0.t
|
|
|
++ vasub.vv v4, v8, v12
|
|
|
++ vasub.vx v4, v8, a1
|
|
|
++ vasub.vv v4, v8, v12, v0.t
|
|
|
++ vasub.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vsmul.vv v4, v8, v12
|
|
|
++ vsmul.vx v4, v8, a1
|
|
|
++ vsmul.vv v4, v8, v12, v0.t
|
|
|
++ vsmul.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vssrl.vv v4, v8, v12
|
|
|
++ vssrl.vx v4, v8, a1
|
|
|
++ vssrl.vi v4, v8, 1
|
|
|
++ vssrl.vi v4, v8, 31
|
|
|
++ vssrl.vv v4, v8, v12, v0.t
|
|
|
++ vssrl.vx v4, v8, a1, v0.t
|
|
|
++ vssrl.vi v4, v8, 1, v0.t
|
|
|
++ vssrl.vi v4, v8, 31, v0.t
|
|
|
++ vssra.vv v4, v8, v12
|
|
|
++ vssra.vx v4, v8, a1
|
|
|
++ vssra.vi v4, v8, 1
|
|
|
++ vssra.vi v4, v8, 31
|
|
|
++ vssra.vv v4, v8, v12, v0.t
|
|
|
++ vssra.vx v4, v8, a1, v0.t
|
|
|
++ vssra.vi v4, v8, 1, v0.t
|
|
|
++ vssra.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vnclipu.wv v4, v8, v12
|
|
|
++ vnclipu.wx v4, v8, a1
|
|
|
++ vnclipu.wi v4, v8, 1
|
|
|
++ vnclipu.wi v4, v8, 31
|
|
|
++ vnclipu.wv v4, v8, v12, v0.t
|
|
|
++ vnclipu.wx v4, v8, a1, v0.t
|
|
|
++ vnclipu.wi v4, v8, 1, v0.t
|
|
|
++ vnclipu.wi v4, v8, 31, v0.t
|
|
|
++ vnclip.wv v4, v8, v12
|
|
|
++ vnclip.wx v4, v8, a1
|
|
|
++ vnclip.wi v4, v8, 1
|
|
|
++ vnclip.wi v4, v8, 31
|
|
|
++ vnclip.wv v4, v8, v12, v0.t
|
|
|
++ vnclip.wx v4, v8, a1, v0.t
|
|
|
++ vnclip.wi v4, v8, 1, v0.t
|
|
|
++ vnclip.wi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vfadd.vv v4, v8, v12
|
|
|
++ vfadd.vf v4, v8, fa2
|
|
|
++ vfadd.vv v4, v8, v12, v0.t
|
|
|
++ vfadd.vf v4, v8, fa2, v0.t
|
|
|
++ vfsub.vv v4, v8, v12
|
|
|
++ vfsub.vf v4, v8, fa2
|
|
|
++ vfsub.vv v4, v8, v12, v0.t
|
|
|
++ vfsub.vf v4, v8, fa2, v0.t
|
|
|
++ vfrsub.vf v4, v8, fa2
|
|
|
++ vfrsub.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfwadd.vv v4, v8, v12
|
|
|
++ vfwadd.vf v4, v8, fa2
|
|
|
++ vfwadd.vv v4, v8, v12, v0.t
|
|
|
++ vfwadd.vf v4, v8, fa2, v0.t
|
|
|
++ vfwsub.vv v4, v8, v12
|
|
|
++ vfwsub.vf v4, v8, fa2
|
|
|
++ vfwsub.vv v4, v8, v12, v0.t
|
|
|
++ vfwsub.vf v4, v8, fa2, v0.t
|
|
|
++ vfwadd.wv v4, v8, v12
|
|
|
++ vfwadd.wf v4, v8, fa2
|
|
|
++ vfwadd.wv v4, v8, v12, v0.t
|
|
|
++ vfwadd.wf v4, v8, fa2, v0.t
|
|
|
++ vfwsub.wv v4, v8, v12
|
|
|
++ vfwsub.wf v4, v8, fa2
|
|
|
++ vfwsub.wv v4, v8, v12, v0.t
|
|
|
++ vfwsub.wf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfmul.vv v4, v8, v12
|
|
|
++ vfmul.vf v4, v8, fa2
|
|
|
++ vfmul.vv v4, v8, v12, v0.t
|
|
|
++ vfmul.vf v4, v8, fa2, v0.t
|
|
|
++ vfdiv.vv v4, v8, v12
|
|
|
++ vfdiv.vf v4, v8, fa2
|
|
|
++ vfdiv.vv v4, v8, v12, v0.t
|
|
|
++ vfdiv.vf v4, v8, fa2, v0.t
|
|
|
++ vfrdiv.vf v4, v8, fa2
|
|
|
++ vfrdiv.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfwmul.vv v4, v8, v12
|
|
|
++ vfwmul.vf v4, v8, fa2
|
|
|
++ vfwmul.vv v4, v8, v12, v0.t
|
|
|
++ vfwmul.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfmadd.vv v4, v12, v8
|
|
|
++ vfmadd.vf v4, fa2, v8
|
|
|
++ vfnmadd.vv v4, v12, v8
|
|
|
++ vfnmadd.vf v4, fa2, v8
|
|
|
++ vfmsub.vv v4, v12, v8
|
|
|
++ vfmsub.vf v4, fa2, v8
|
|
|
++ vfnmsub.vv v4, v12, v8
|
|
|
++ vfnmsub.vf v4, fa2, v8
|
|
|
++ vfmadd.vv v4, v12, v8, v0.t
|
|
|
++ vfmadd.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmadd.vv v4, v12, v8, v0.t
|
|
|
++ vfnmadd.vf v4, fa2, v8, v0.t
|
|
|
++ vfmsub.vv v4, v12, v8, v0.t
|
|
|
++ vfmsub.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmsub.vv v4, v12, v8, v0.t
|
|
|
++ vfnmsub.vf v4, fa2, v8, v0.t
|
|
|
++ vfmacc.vv v4, v12, v8
|
|
|
++ vfmacc.vf v4, fa2, v8
|
|
|
++ vfnmacc.vv v4, v12, v8
|
|
|
++ vfnmacc.vf v4, fa2, v8
|
|
|
++ vfmsac.vv v4, v12, v8
|
|
|
++ vfmsac.vf v4, fa2, v8
|
|
|
++ vfnmsac.vv v4, v12, v8
|
|
|
++ vfnmsac.vf v4, fa2, v8
|
|
|
++ vfmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfnmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfmsac.vf v4, fa2, v8, v0.t
|
|
|
++ vfnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfnmsac.vf v4, fa2, v8, v0.t
|
|
|
++
|
|
|
++ vfwmacc.vv v4, v12, v8
|
|
|
++ vfwmacc.vf v4, fa2, v8
|
|
|
++ vfwnmacc.vv v4, v12, v8
|
|
|
++ vfwnmacc.vf v4, fa2, v8
|
|
|
++ vfwmsac.vv v4, v12, v8
|
|
|
++ vfwmsac.vf v4, fa2, v8
|
|
|
++ vfwnmsac.vv v4, v12, v8
|
|
|
++ vfwnmsac.vf v4, fa2, v8
|
|
|
++ vfwmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfwmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfwnmacc.vv v4, v12, v8, v0.t
|
|
|
++ vfwnmacc.vf v4, fa2, v8, v0.t
|
|
|
++ vfwmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfwmsac.vf v4, fa2, v8, v0.t
|
|
|
++ vfwnmsac.vv v4, v12, v8, v0.t
|
|
|
++ vfwnmsac.vf v4, fa2, v8, v0.t
|
|
|
++
|
|
|
++ vfsqrt.v v4, v8
|
|
|
++ vfsqrt.v v4, v8, v0.t
|
|
|
++ vfrsqrte7.v v4, v8
|
|
|
++ vfrsqrte7.v v4, v8, v0.t
|
|
|
++ vfrsqrt7.v v4, v8
|
|
|
++ vfrsqrt7.v v4, v8, v0.t
|
|
|
++ vfrece7.v v4, v8
|
|
|
++ vfrece7.v v4, v8, v0.t
|
|
|
++ vfrec7.v v4, v8
|
|
|
++ vfrec7.v v4, v8, v0.t
|
|
|
++ vfclass.v v4, v8
|
|
|
++ vfclass.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfmin.vv v4, v8, v12
|
|
|
++ vfmin.vf v4, v8, fa2
|
|
|
++ vfmax.vv v4, v8, v12
|
|
|
++ vfmax.vf v4, v8, fa2
|
|
|
++ vfmin.vv v4, v8, v12, v0.t
|
|
|
++ vfmin.vf v4, v8, fa2, v0.t
|
|
|
++ vfmax.vv v4, v8, v12, v0.t
|
|
|
++ vfmax.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfneg.v v4, v8
|
|
|
++ vfneg.v v4, v8, v0.t
|
|
|
++ vfabs.v v4, v8
|
|
|
++ vfabs.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfsgnj.vv v4, v8, v12
|
|
|
++ vfsgnj.vf v4, v8, fa2
|
|
|
++ vfsgnjn.vv v4, v8, v12
|
|
|
++ vfsgnjn.vf v4, v8, fa2
|
|
|
++ vfsgnjx.vv v4, v8, v12
|
|
|
++ vfsgnjx.vf v4, v8, fa2
|
|
|
++ vfsgnj.vv v4, v8, v12, v0.t
|
|
|
++ vfsgnj.vf v4, v8, fa2, v0.t
|
|
|
++ vfsgnjn.vv v4, v8, v12, v0.t
|
|
|
++ vfsgnjn.vf v4, v8, fa2, v0.t
|
|
|
++ vfsgnjx.vv v4, v8, v12, v0.t
|
|
|
++ vfsgnjx.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vmfgt.vv v4, v8, v12
|
|
|
++ vmfge.vv v4, v8, v12
|
|
|
++ vmfgt.vv v4, v8, v12, v0.t
|
|
|
++ vmfge.vv v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vmfeq.vv v4, v8, v12
|
|
|
++ vmfeq.vf v4, v8, fa2
|
|
|
++ vmfne.vv v4, v8, v12
|
|
|
++ vmfne.vf v4, v8, fa2
|
|
|
++ vmflt.vv v4, v8, v12
|
|
|
++ vmflt.vf v4, v8, fa2
|
|
|
++ vmfle.vv v4, v8, v12
|
|
|
++ vmfle.vf v4, v8, fa2
|
|
|
++ vmfgt.vf v4, v8, fa2
|
|
|
++ vmfge.vf v4, v8, fa2
|
|
|
++ vmfeq.vv v4, v8, v12, v0.t
|
|
|
++ vmfeq.vf v4, v8, fa2, v0.t
|
|
|
++ vmfne.vv v4, v8, v12, v0.t
|
|
|
++ vmfne.vf v4, v8, fa2, v0.t
|
|
|
++ vmflt.vv v4, v8, v12, v0.t
|
|
|
++ vmflt.vf v4, v8, fa2, v0.t
|
|
|
++ vmfle.vv v4, v8, v12, v0.t
|
|
|
++ vmfle.vf v4, v8, fa2, v0.t
|
|
|
++ vmfgt.vf v4, v8, fa2, v0.t
|
|
|
++ vmfge.vf v4, v8, fa2, v0.t
|
|
|
++
|
|
|
++ vfmerge.vfm v4, v8, fa2, v0
|
|
|
++ vfmv.v.f v4, fa1
|
|
|
++
|
|
|
++ vfcvt.xu.f.v v4, v8
|
|
|
++ vfcvt.x.f.v v4, v8
|
|
|
++ vfcvt.rtz.xu.f.v v4, v8
|
|
|
++ vfcvt.rtz.x.f.v v4, v8
|
|
|
++ vfcvt.f.xu.v v4, v8
|
|
|
++ vfcvt.f.x.v v4, v8
|
|
|
++ vfcvt.xu.f.v v4, v8, v0.t
|
|
|
++ vfcvt.x.f.v v4, v8, v0.t
|
|
|
++ vfcvt.rtz.xu.f.v v4, v8, v0.t
|
|
|
++ vfcvt.rtz.x.f.v v4, v8, v0.t
|
|
|
++ vfcvt.f.xu.v v4, v8, v0.t
|
|
|
++ vfcvt.f.x.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfwcvt.xu.f.v v4, v8
|
|
|
++ vfwcvt.x.f.v v4, v8
|
|
|
++ vfwcvt.rtz.xu.f.v v4, v8
|
|
|
++ vfwcvt.rtz.x.f.v v4, v8
|
|
|
++ vfwcvt.f.xu.v v4, v8
|
|
|
++ vfwcvt.f.x.v v4, v8
|
|
|
++ vfwcvt.f.f.v v4, v8
|
|
|
++ vfwcvt.xu.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.x.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.rtz.xu.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.rtz.x.f.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.xu.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.x.v v4, v8, v0.t
|
|
|
++ vfwcvt.f.f.v v4, v8, v0.t
|
|
|
++
|
|
|
++ vfncvt.xu.f.w v4, v8
|
|
|
++ vfncvt.x.f.w v4, v8
|
|
|
++ vfncvt.rtz.xu.f.w v4, v8
|
|
|
++ vfncvt.rtz.x.f.w v4, v8
|
|
|
++ vfncvt.f.xu.w v4, v8
|
|
|
++ vfncvt.f.x.w v4, v8
|
|
|
++ vfncvt.f.f.w v4, v8
|
|
|
++ vfncvt.rod.f.f.w v4, v8
|
|
|
++ vfncvt.xu.f.w v4, v8, v0.t
|
|
|
++ vfncvt.x.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rtz.xu.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rtz.x.f.w v4, v8, v0.t
|
|
|
++ vfncvt.f.xu.w v4, v8, v0.t
|
|
|
++ vfncvt.f.x.w v4, v8, v0.t
|
|
|
++ vfncvt.f.f.w v4, v8, v0.t
|
|
|
++ vfncvt.rod.f.f.w v4, v8, v0.t
|
|
|
++
|
|
|
++ vredsum.vs v4, v8, v12
|
|
|
++ vredmaxu.vs v4, v8, v8
|
|
|
++ vredmax.vs v4, v8, v8
|
|
|
++ vredminu.vs v4, v8, v8
|
|
|
++ vredmin.vs v4, v8, v8
|
|
|
++ vredand.vs v4, v8, v12
|
|
|
++ vredor.vs v4, v8, v12
|
|
|
++ vredxor.vs v4, v8, v12
|
|
|
++ vredsum.vs v4, v8, v12, v0.t
|
|
|
++ vredmaxu.vs v4, v8, v8, v0.t
|
|
|
++ vredmax.vs v4, v8, v8, v0.t
|
|
|
++ vredminu.vs v4, v8, v8, v0.t
|
|
|
++ vredmin.vs v4, v8, v8, v0.t
|
|
|
++ vredand.vs v4, v8, v12, v0.t
|
|
|
++ vredor.vs v4, v8, v12, v0.t
|
|
|
++ vredxor.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vwredsumu.vs v4, v8, v12
|
|
|
++ vwredsum.vs v4, v8, v12
|
|
|
++ vwredsumu.vs v4, v8, v12, v0.t
|
|
|
++ vwredsum.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vfredosum.vs v4, v8, v12
|
|
|
++ vfredsum.vs v4, v8, v12
|
|
|
++ vfredmax.vs v4, v8, v12
|
|
|
++ vfredmin.vs v4, v8, v12
|
|
|
++ vfredosum.vs v4, v8, v12, v0.t
|
|
|
++ vfredsum.vs v4, v8, v12, v0.t
|
|
|
++ vfredmax.vs v4, v8, v12, v0.t
|
|
|
++ vfredmin.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vfwredosum.vs v4, v8, v12
|
|
|
++ vfwredsum.vs v4, v8, v12
|
|
|
++ vfwredosum.vs v4, v8, v12, v0.t
|
|
|
++ vfwredsum.vs v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ # Aliases
|
|
|
++ vmcpy.m v4, v8
|
|
|
++ vmmv.m v4, v8
|
|
|
++ vmclr.m v4
|
|
|
++ vmset.m v4
|
|
|
++ vmnot.m v4, v8
|
|
|
++
|
|
|
++ vmand.mm v4, v8, v12
|
|
|
++ vmnand.mm v4, v8, v12
|
|
|
++ vmandnot.mm v4, v8, v12
|
|
|
++ vmxor.mm v4, v8, v12
|
|
|
++ vmor.mm v4, v8, v12
|
|
|
++ vmnor.mm v4, v8, v12
|
|
|
++ vmornot.mm v4, v8, v12
|
|
|
++ vmxnor.mm v4, v8, v12
|
|
|
++
|
|
|
++ vpopc.m a0, v12
|
|
|
++ vfirst.m a0, v12
|
|
|
++ vmsbf.m v4, v8
|
|
|
++ vmsif.m v4, v8
|
|
|
++ vmsof.m v4, v8
|
|
|
++ viota.m v4, v8
|
|
|
++ vid.v v4
|
|
|
++ vpopc.m a0, v12, v0.t
|
|
|
++ vfirst.m a0, v12, v0.t
|
|
|
++ vmsbf.m v4, v8, v0.t
|
|
|
++ vmsif.m v4, v8, v0.t
|
|
|
++ vmsof.m v4, v8, v0.t
|
|
|
++ viota.m v4, v8, v0.t
|
|
|
++ vid.v v4, v0.t
|
|
|
++
|
|
|
++ vmv.x.s a0, v12
|
|
|
++ vmv.s.x v4, a0
|
|
|
++
|
|
|
++ vfmv.f.s fa0, v8
|
|
|
++ vfmv.s.f v4, fa1
|
|
|
++
|
|
|
++ vslideup.vx v4, v8, a1
|
|
|
++ vslideup.vi v4, v8, 0
|
|
|
++ vslideup.vi v4, v8, 31
|
|
|
++ vslidedown.vx v4, v8, a1
|
|
|
++ vslidedown.vi v4, v8, 0
|
|
|
++ vslidedown.vi v4, v8, 31
|
|
|
++ vslideup.vx v4, v8, a1, v0.t
|
|
|
++ vslideup.vi v4, v8, 0, v0.t
|
|
|
++ vslideup.vi v4, v8, 31, v0.t
|
|
|
++ vslidedown.vx v4, v8, a1, v0.t
|
|
|
++ vslidedown.vi v4, v8, 0, v0.t
|
|
|
++ vslidedown.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vslide1up.vx v4, v8, a1
|
|
|
++ vslide1down.vx v4, v8, a1
|
|
|
++ vslide1up.vx v4, v8, a1, v0.t
|
|
|
++ vslide1down.vx v4, v8, a1, v0.t
|
|
|
++
|
|
|
++ vfslide1up.vf v4, v8, fa1
|
|
|
++ vfslide1down.vf v4, v8, fa1
|
|
|
++ vfslide1up.vf v4, v8, fa1, v0.t
|
|
|
++ vfslide1down.vf v4, v8, fa1, v0.t
|
|
|
++
|
|
|
++ vrgather.vv v4, v8, v12
|
|
|
++ vrgather.vx v4, v8, a1
|
|
|
++ vrgather.vi v4, v8, 0
|
|
|
++ vrgather.vi v4, v8, 31
|
|
|
++ vrgather.vv v4, v8, v12, v0.t
|
|
|
++ vrgather.vx v4, v8, a1, v0.t
|
|
|
++ vrgather.vi v4, v8, 0, v0.t
|
|
|
++ vrgather.vi v4, v8, 31, v0.t
|
|
|
++
|
|
|
++ vrgatherei16.vv v4, v8, v12
|
|
|
++ vrgatherei16.vv v4, v8, v12, v0.t
|
|
|
++
|
|
|
++ vcompress.vm v4, v8, v12
|
|
|
++
|
|
|
++ vmv1r.v v1, v2
|
|
|
++ vmv2r.v v2, v4
|
|
|
++ vmv4r.v v4, v8
|
|
|
++ vmv8r.v v0, v8
|
|
|
+diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
|
|
|
+index 1a80dbf87d..a62eada16a 100644
|
|
|
+--- a/include/opcode/riscv-opc.h
|
|
|
++++ b/include/opcode/riscv-opc.h
|
|
|
+@@ -755,7 +755,1903 @@
|
|
|
+ #define MASK_C_LDSP 0xe003
|
|
|
+ #define MATCH_C_SDSP 0xe002
|
|
|
+ #define MASK_C_SDSP 0xe003
|
|
|
+-/* Privileged CSR addresses. */
|
|
|
++
|
|
|
++/* RVV */
|
|
|
++/* Version 1.0-draft-20210130. */
|
|
|
++
|
|
|
++/* Temporary configuration-setting encoding info
|
|
|
++
|
|
|
++`-` means zimm
|
|
|
++
|
|
|
++31 30 zimm RS2 RS1/uimm funct3 RD opcode
|
|
|
++1 0 00000 xxxxx xxxxx 111 xxxxx 1010111 vsetvl
|
|
|
++1 1 ----- ----- xxxxx 111 xxxxx 1010111 vsetivli
|
|
|
++0 - ----- ----- xxxxx 111 xxxxx 1010111 vsetvli
|
|
|
++*/
|
|
|
++
|
|
|
++#define MATCH_VSETVL 0x80007057
|
|
|
++#define MASK_VSETVL 0xfe00707f
|
|
|
++#define MATCH_VSETIVLI 0xc0007057
|
|
|
++#define MASK_VSETIVLI 0xc000707f
|
|
|
++#define MATCH_VSETVLI 0x00007057
|
|
|
++#define MASK_VSETVLI 0x8000707f
|
|
|
++
|
|
|
++/* Temporary Load/store encoding info
|
|
|
++
|
|
|
++MOP load
|
|
|
++00 unit-stride LE<EEW>, VLE<EEW>FF, VL<nf>RE<EEW> (nf = 1, 2, 4, 8)
|
|
|
++01 indexed-unordered VLUXEI<EEW>
|
|
|
++10 strided VLSE<EEW>
|
|
|
++11 indexed-ordered VLOXEI<EEW>
|
|
|
++
|
|
|
++MOP store
|
|
|
++00 unit-stride VSE<EEW>, VS<nf>R (nf = 1, 2, 4, 8)
|
|
|
++01 indexed-unordered VSUXEI<EEW>
|
|
|
++10 strided VSSE<EEW>
|
|
|
++11 indexed-ordered VSOXEI<EEW>
|
|
|
++
|
|
|
++VM 0 masked
|
|
|
++VM 1 unmasked
|
|
|
++
|
|
|
++LUMOP
|
|
|
++00000 unit-stride load
|
|
|
++01000 unit-stride, whole registers load
|
|
|
++01011 unit-stride, mask load, EEW = 1
|
|
|
++10000 unit-stride first-fault
|
|
|
++xxxxx other encodings reserved, x != 0
|
|
|
++
|
|
|
++SUMOP
|
|
|
++00000 unit-stride store
|
|
|
++01000 unit-stride, whole registers store
|
|
|
++01011 unit-stride, mask store, EEW = 1
|
|
|
++0xxxx other encodings reserved, x != 0
|
|
|
++
|
|
|
++`-` means EEW =
|
|
|
++MEW WIDTH
|
|
|
++x 001 FLH/FSH
|
|
|
++x 010 FLW/FSW
|
|
|
++x 011 FLD/FSW
|
|
|
++x 100 FLQ/FSQ
|
|
|
++0 000 VLxE8/VSxE8, VLxEI8/VSxEI8, VL<nf>RE8, VS<nf>R
|
|
|
++0 101 VLxE16/VSxE16, VLxEI16/VSxEI16, VL<nf>RE16
|
|
|
++0 110 VLxE32/VSxE32, VLxEI32/VSxEI32, VL<nf>RE32
|
|
|
++0 111 VLxE64/VSxE64, VLxEI64/VSxEI64, VL<nf>RE64
|
|
|
++1 000 Reserved (VLxE128/VSxE128, VL<nf>RE128)
|
|
|
++1 101 Reserved (VLxE256/VSxE256, VL<nf>RE256)
|
|
|
++1 110 Reserved (VLxE512/VSxE512, VL<nf>RE512)
|
|
|
++1 111 Reserved (VLxE1024/VSxE1024, VL<nf>RE1024)
|
|
|
++
|
|
|
++NF MEW MOP VM LUMOP/RS2 RS1 WIDTH VD opcode
|
|
|
++000 - 00 x 00000 xxxxx --- xxxxx 0000111 VLE<EEW>
|
|
|
++000 - 00 x 00000 xxxxx --- xxxxx 0100111 VSE<EEW>
|
|
|
++000 - 00 1 01011 xxxxx --- xxxxx 0000111 VLE, EEW = 1
|
|
|
++000 - 00 1 01011 xxxxx --- xxxxx 0100111 VSE, EEW = 1
|
|
|
++000 - 10 x xxxxx xxxxx --- xxxxx 0000111 VLSE<EEW>
|
|
|
++000 - 10 x xxxxx xxxxx --- xxxxx 0100111 VSSE<EEW>
|
|
|
++000 0 11 x xxxxx xxxxx --- xxxxx 0000111 VLOXE<EEW>I
|
|
|
++000 0 11 x xxxxx xxxxx --- xxxxx 0100111 VSOXE<EEW>I
|
|
|
++000 0 01 x xxxxx xxxxx --- xxxxx 0000111 VLUXE<EEW>I
|
|
|
++000 0 01 x xxxxx xxxxx --- xxxxx 0100111 VSUXE<EEW>I
|
|
|
++000 - 00 x 10000 xxxxx --- xxxxx 0000111 VLE<EEW>FF
|
|
|
++xxx - 00 1 01000 xxxxx --- xxxxx 0000111 VL<nf>RE<EEW>, nf = 1,2,4,8
|
|
|
++xxx 0 00 1 01000 xxxxx 000 xxxxx 0100111 VS<nf>R, nf = 1,2,4,8
|
|
|
++
|
|
|
++xxx - 00 x 00000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>
|
|
|
++xxx - 00 x 00000 xxxxx --- xxxxx 0100111 VSSEG<nf>E<EEW>
|
|
|
++xxx - 10 x 00000 xxxxx --- xxxxx 0000111 VLSSEG<nf>E<EEW>
|
|
|
++xxx - 10 x 00000 xxxxx --- xxxxx 0100111 VSSSEG<nf>E<EEW>
|
|
|
++xxx - 11 x 00000 xxxxx --- xxxxx 0000111 VLOXSEG<nf>E<EEW>I
|
|
|
++xxx - 11 x 00000 xxxxx --- xxxxx 0100111 VSOXSEG<nf>E<EEW>I
|
|
|
++xxx - 01 x 00000 xxxxx --- xxxxx 0000111 VLUXSEG<nf>E<EEW>I
|
|
|
++xxx - 01 x 00000 xxxxx --- xxxxx 0100111 VSUXSEG<nf>E<EEW>I
|
|
|
++xxx - 00 x 10000 xxxxx --- xxxxx 0000111 VLSEG<nf>E<EEW>FF
|
|
|
++*/
|
|
|
++
|
|
|
++#define MATCH_VLE1V 0x02b00007
|
|
|
++#define MASK_VLE1V 0xfff0707f
|
|
|
++#define MATCH_VSE1V 0x02b00027
|
|
|
++#define MASK_VSE1V 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VLE8V 0x00000007
|
|
|
++#define MASK_VLE8V 0xfdf0707f
|
|
|
++#define MATCH_VLE16V 0x00005007
|
|
|
++#define MASK_VLE16V 0xfdf0707f
|
|
|
++#define MATCH_VLE32V 0x00006007
|
|
|
++#define MASK_VLE32V 0xfdf0707f
|
|
|
++#define MATCH_VLE64V 0x00007007
|
|
|
++#define MASK_VLE64V 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VSE8V 0x00000027
|
|
|
++#define MASK_VSE8V 0xfdf0707f
|
|
|
++#define MATCH_VSE16V 0x00005027
|
|
|
++#define MASK_VSE16V 0xfdf0707f
|
|
|
++#define MATCH_VSE32V 0x00006027
|
|
|
++#define MASK_VSE32V 0xfdf0707f
|
|
|
++#define MATCH_VSE64V 0x00007027
|
|
|
++#define MASK_VSE64V 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSE8V 0x08000007
|
|
|
++#define MASK_VLSE8V 0xfc00707f
|
|
|
++#define MATCH_VLSE16V 0x08005007
|
|
|
++#define MASK_VLSE16V 0xfc00707f
|
|
|
++#define MATCH_VLSE32V 0x08006007
|
|
|
++#define MASK_VLSE32V 0xfc00707f
|
|
|
++#define MATCH_VLSE64V 0x08007007
|
|
|
++#define MASK_VLSE64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSSE8V 0x08000027
|
|
|
++#define MASK_VSSE8V 0xfc00707f
|
|
|
++#define MATCH_VSSE16V 0x08005027
|
|
|
++#define MASK_VSSE16V 0xfc00707f
|
|
|
++#define MATCH_VSSE32V 0x08006027
|
|
|
++#define MASK_VSSE32V 0xfc00707f
|
|
|
++#define MATCH_VSSE64V 0x08007027
|
|
|
++#define MASK_VSSE64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLOXEI8V 0x0c000007
|
|
|
++#define MASK_VLOXEI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXEI16V 0x0c005007
|
|
|
++#define MASK_VLOXEI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXEI32V 0x0c006007
|
|
|
++#define MASK_VLOXEI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXEI64V 0x0c007007
|
|
|
++#define MASK_VLOXEI64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSOXEI8V 0x0c000027
|
|
|
++#define MASK_VSOXEI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXEI16V 0x0c005027
|
|
|
++#define MASK_VSOXEI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXEI32V 0x0c006027
|
|
|
++#define MASK_VSOXEI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXEI64V 0x0c007027
|
|
|
++#define MASK_VSOXEI64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLUXEI8V 0x04000007
|
|
|
++#define MASK_VLUXEI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXEI16V 0x04005007
|
|
|
++#define MASK_VLUXEI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXEI32V 0x04006007
|
|
|
++#define MASK_VLUXEI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXEI64V 0x04007007
|
|
|
++#define MASK_VLUXEI64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSUXEI8V 0x04000027
|
|
|
++#define MASK_VSUXEI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXEI16V 0x04005027
|
|
|
++#define MASK_VSUXEI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXEI32V 0x04006027
|
|
|
++#define MASK_VSUXEI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXEI64V 0x04007027
|
|
|
++#define MASK_VSUXEI64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLE8FFV 0x01000007
|
|
|
++#define MASK_VLE8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLE16FFV 0x01005007
|
|
|
++#define MASK_VLE16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLE32FFV 0x01006007
|
|
|
++#define MASK_VLE32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLE64FFV 0x01007007
|
|
|
++#define MASK_VLE64FFV 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E8V 0x20000007
|
|
|
++#define MASK_VLSEG2E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG2E8V 0x20000027
|
|
|
++#define MASK_VSSEG2E8V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E8V 0x40000007
|
|
|
++#define MASK_VLSEG3E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG3E8V 0x40000027
|
|
|
++#define MASK_VSSEG3E8V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E8V 0x60000007
|
|
|
++#define MASK_VLSEG4E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG4E8V 0x60000027
|
|
|
++#define MASK_VSSEG4E8V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E8V 0x80000007
|
|
|
++#define MASK_VLSEG5E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG5E8V 0x80000027
|
|
|
++#define MASK_VSSEG5E8V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E8V 0xa0000007
|
|
|
++#define MASK_VLSEG6E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG6E8V 0xa0000027
|
|
|
++#define MASK_VSSEG6E8V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E8V 0xc0000007
|
|
|
++#define MASK_VLSEG7E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG7E8V 0xc0000027
|
|
|
++#define MASK_VSSEG7E8V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E8V 0xe0000007
|
|
|
++#define MASK_VLSEG8E8V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG8E8V 0xe0000027
|
|
|
++#define MASK_VSSEG8E8V 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E16V 0x20005007
|
|
|
++#define MASK_VLSEG2E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG2E16V 0x20005027
|
|
|
++#define MASK_VSSEG2E16V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E16V 0x40005007
|
|
|
++#define MASK_VLSEG3E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG3E16V 0x40005027
|
|
|
++#define MASK_VSSEG3E16V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E16V 0x60005007
|
|
|
++#define MASK_VLSEG4E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG4E16V 0x60005027
|
|
|
++#define MASK_VSSEG4E16V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E16V 0x80005007
|
|
|
++#define MASK_VLSEG5E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG5E16V 0x80005027
|
|
|
++#define MASK_VSSEG5E16V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E16V 0xa0005007
|
|
|
++#define MASK_VLSEG6E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG6E16V 0xa0005027
|
|
|
++#define MASK_VSSEG6E16V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E16V 0xc0005007
|
|
|
++#define MASK_VLSEG7E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG7E16V 0xc0005027
|
|
|
++#define MASK_VSSEG7E16V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E16V 0xe0005007
|
|
|
++#define MASK_VLSEG8E16V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG8E16V 0xe0005027
|
|
|
++#define MASK_VSSEG8E16V 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E32V 0x20006007
|
|
|
++#define MASK_VLSEG2E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG2E32V 0x20006027
|
|
|
++#define MASK_VSSEG2E32V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E32V 0x40006007
|
|
|
++#define MASK_VLSEG3E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG3E32V 0x40006027
|
|
|
++#define MASK_VSSEG3E32V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E32V 0x60006007
|
|
|
++#define MASK_VLSEG4E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG4E32V 0x60006027
|
|
|
++#define MASK_VSSEG4E32V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E32V 0x80006007
|
|
|
++#define MASK_VLSEG5E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG5E32V 0x80006027
|
|
|
++#define MASK_VSSEG5E32V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E32V 0xa0006007
|
|
|
++#define MASK_VLSEG6E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG6E32V 0xa0006027
|
|
|
++#define MASK_VSSEG6E32V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E32V 0xc0006007
|
|
|
++#define MASK_VLSEG7E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG7E32V 0xc0006027
|
|
|
++#define MASK_VSSEG7E32V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E32V 0xe0006007
|
|
|
++#define MASK_VLSEG8E32V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG8E32V 0xe0006027
|
|
|
++#define MASK_VSSEG8E32V 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E64V 0x20007007
|
|
|
++#define MASK_VLSEG2E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG2E64V 0x20007027
|
|
|
++#define MASK_VSSEG2E64V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E64V 0x40007007
|
|
|
++#define MASK_VLSEG3E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG3E64V 0x40007027
|
|
|
++#define MASK_VSSEG3E64V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E64V 0x60007007
|
|
|
++#define MASK_VLSEG4E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG4E64V 0x60007027
|
|
|
++#define MASK_VSSEG4E64V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E64V 0x80007007
|
|
|
++#define MASK_VLSEG5E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG5E64V 0x80007027
|
|
|
++#define MASK_VSSEG5E64V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E64V 0xa0007007
|
|
|
++#define MASK_VLSEG6E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG6E64V 0xa0007027
|
|
|
++#define MASK_VSSEG6E64V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E64V 0xc0007007
|
|
|
++#define MASK_VLSEG7E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG7E64V 0xc0007027
|
|
|
++#define MASK_VSSEG7E64V 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E64V 0xe0007007
|
|
|
++#define MASK_VLSEG8E64V 0xfdf0707f
|
|
|
++#define MATCH_VSSEG8E64V 0xe0007027
|
|
|
++#define MASK_VSSEG8E64V 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSSEG2E8V 0x28000007
|
|
|
++#define MASK_VLSSEG2E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG2E8V 0x28000027
|
|
|
++#define MASK_VSSSEG2E8V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG3E8V 0x48000007
|
|
|
++#define MASK_VLSSEG3E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG3E8V 0x48000027
|
|
|
++#define MASK_VSSSEG3E8V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG4E8V 0x68000007
|
|
|
++#define MASK_VLSSEG4E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG4E8V 0x68000027
|
|
|
++#define MASK_VSSSEG4E8V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG5E8V 0x88000007
|
|
|
++#define MASK_VLSSEG5E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG5E8V 0x88000027
|
|
|
++#define MASK_VSSSEG5E8V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG6E8V 0xa8000007
|
|
|
++#define MASK_VLSSEG6E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG6E8V 0xa8000027
|
|
|
++#define MASK_VSSSEG6E8V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG7E8V 0xc8000007
|
|
|
++#define MASK_VLSSEG7E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG7E8V 0xc8000027
|
|
|
++#define MASK_VSSSEG7E8V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG8E8V 0xe8000007
|
|
|
++#define MASK_VLSSEG8E8V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG8E8V 0xe8000027
|
|
|
++#define MASK_VSSSEG8E8V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLSSEG2E16V 0x28005007
|
|
|
++#define MASK_VLSSEG2E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG2E16V 0x28005027
|
|
|
++#define MASK_VSSSEG2E16V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG3E16V 0x48005007
|
|
|
++#define MASK_VLSSEG3E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG3E16V 0x48005027
|
|
|
++#define MASK_VSSSEG3E16V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG4E16V 0x68005007
|
|
|
++#define MASK_VLSSEG4E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG4E16V 0x68005027
|
|
|
++#define MASK_VSSSEG4E16V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG5E16V 0x88005007
|
|
|
++#define MASK_VLSSEG5E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG5E16V 0x88005027
|
|
|
++#define MASK_VSSSEG5E16V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG6E16V 0xa8005007
|
|
|
++#define MASK_VLSSEG6E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG6E16V 0xa8005027
|
|
|
++#define MASK_VSSSEG6E16V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG7E16V 0xc8005007
|
|
|
++#define MASK_VLSSEG7E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG7E16V 0xc8005027
|
|
|
++#define MASK_VSSSEG7E16V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG8E16V 0xe8005007
|
|
|
++#define MASK_VLSSEG8E16V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG8E16V 0xe8005027
|
|
|
++#define MASK_VSSSEG8E16V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLSSEG2E32V 0x28006007
|
|
|
++#define MASK_VLSSEG2E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG2E32V 0x28006027
|
|
|
++#define MASK_VSSSEG2E32V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG3E32V 0x48006007
|
|
|
++#define MASK_VLSSEG3E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG3E32V 0x48006027
|
|
|
++#define MASK_VSSSEG3E32V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG4E32V 0x68006007
|
|
|
++#define MASK_VLSSEG4E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG4E32V 0x68006027
|
|
|
++#define MASK_VSSSEG4E32V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG5E32V 0x88006007
|
|
|
++#define MASK_VLSSEG5E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG5E32V 0x88006027
|
|
|
++#define MASK_VSSSEG5E32V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG6E32V 0xa8006007
|
|
|
++#define MASK_VLSSEG6E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG6E32V 0xa8006027
|
|
|
++#define MASK_VSSSEG6E32V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG7E32V 0xc8006007
|
|
|
++#define MASK_VLSSEG7E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG7E32V 0xc8006027
|
|
|
++#define MASK_VSSSEG7E32V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG8E32V 0xe8006007
|
|
|
++#define MASK_VLSSEG8E32V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG8E32V 0xe8006027
|
|
|
++#define MASK_VSSSEG8E32V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLSSEG2E64V 0x28007007
|
|
|
++#define MASK_VLSSEG2E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG2E64V 0x28007027
|
|
|
++#define MASK_VSSSEG2E64V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG3E64V 0x48007007
|
|
|
++#define MASK_VLSSEG3E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG3E64V 0x48007027
|
|
|
++#define MASK_VSSSEG3E64V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG4E64V 0x68007007
|
|
|
++#define MASK_VLSSEG4E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG4E64V 0x68007027
|
|
|
++#define MASK_VSSSEG4E64V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG5E64V 0x88007007
|
|
|
++#define MASK_VLSSEG5E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG5E64V 0x88007027
|
|
|
++#define MASK_VSSSEG5E64V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG6E64V 0xa8007007
|
|
|
++#define MASK_VLSSEG6E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG6E64V 0xa8007027
|
|
|
++#define MASK_VSSSEG6E64V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG7E64V 0xc8007007
|
|
|
++#define MASK_VLSSEG7E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG7E64V 0xc8007027
|
|
|
++#define MASK_VSSSEG7E64V 0xfc00707f
|
|
|
++#define MATCH_VLSSEG8E64V 0xe8007007
|
|
|
++#define MASK_VLSSEG8E64V 0xfc00707f
|
|
|
++#define MATCH_VSSSEG8E64V 0xe8007027
|
|
|
++#define MASK_VSSSEG8E64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLOXSEG2EI8V 0x2c000007
|
|
|
++#define MASK_VLOXSEG2EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG2EI8V 0x2c000027
|
|
|
++#define MASK_VSOXSEG2EI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG3EI8V 0x4c000007
|
|
|
++#define MASK_VLOXSEG3EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG3EI8V 0x4c000027
|
|
|
++#define MASK_VSOXSEG3EI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG4EI8V 0x6c000007
|
|
|
++#define MASK_VLOXSEG4EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG4EI8V 0x6c000027
|
|
|
++#define MASK_VSOXSEG4EI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG5EI8V 0x8c000007
|
|
|
++#define MASK_VLOXSEG5EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG5EI8V 0x8c000027
|
|
|
++#define MASK_VSOXSEG5EI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG6EI8V 0xac000007
|
|
|
++#define MASK_VLOXSEG6EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG6EI8V 0xac000027
|
|
|
++#define MASK_VSOXSEG6EI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG7EI8V 0xcc000007
|
|
|
++#define MASK_VLOXSEG7EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG7EI8V 0xcc000027
|
|
|
++#define MASK_VSOXSEG7EI8V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG8EI8V 0xec000007
|
|
|
++#define MASK_VLOXSEG8EI8V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG8EI8V 0xec000027
|
|
|
++#define MASK_VSOXSEG8EI8V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLUXSEG2EI8V 0x24000007
|
|
|
++#define MASK_VLUXSEG2EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG2EI8V 0x24000027
|
|
|
++#define MASK_VSUXSEG2EI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG3EI8V 0x44000007
|
|
|
++#define MASK_VLUXSEG3EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG3EI8V 0x44000027
|
|
|
++#define MASK_VSUXSEG3EI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG4EI8V 0x64000007
|
|
|
++#define MASK_VLUXSEG4EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG4EI8V 0x64000027
|
|
|
++#define MASK_VSUXSEG4EI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG5EI8V 0x84000007
|
|
|
++#define MASK_VLUXSEG5EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG5EI8V 0x84000027
|
|
|
++#define MASK_VSUXSEG5EI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG6EI8V 0xa4000007
|
|
|
++#define MASK_VLUXSEG6EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG6EI8V 0xa4000027
|
|
|
++#define MASK_VSUXSEG6EI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG7EI8V 0xc4000007
|
|
|
++#define MASK_VLUXSEG7EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG7EI8V 0xc4000027
|
|
|
++#define MASK_VSUXSEG7EI8V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG8EI8V 0xe4000007
|
|
|
++#define MASK_VLUXSEG8EI8V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG8EI8V 0xe4000027
|
|
|
++#define MASK_VSUXSEG8EI8V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLOXSEG2EI16V 0x2c005007
|
|
|
++#define MASK_VLOXSEG2EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG2EI16V 0x2c005027
|
|
|
++#define MASK_VSOXSEG2EI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG3EI16V 0x4c005007
|
|
|
++#define MASK_VLOXSEG3EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG3EI16V 0x4c005027
|
|
|
++#define MASK_VSOXSEG3EI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG4EI16V 0x6c005007
|
|
|
++#define MASK_VLOXSEG4EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG4EI16V 0x6c005027
|
|
|
++#define MASK_VSOXSEG4EI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG5EI16V 0x8c005007
|
|
|
++#define MASK_VLOXSEG5EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG5EI16V 0x8c005027
|
|
|
++#define MASK_VSOXSEG5EI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG6EI16V 0xac005007
|
|
|
++#define MASK_VLOXSEG6EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG6EI16V 0xac005027
|
|
|
++#define MASK_VSOXSEG6EI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG7EI16V 0xcc005007
|
|
|
++#define MASK_VLOXSEG7EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG7EI16V 0xcc005027
|
|
|
++#define MASK_VSOXSEG7EI16V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG8EI16V 0xec005007
|
|
|
++#define MASK_VLOXSEG8EI16V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG8EI16V 0xec005027
|
|
|
++#define MASK_VSOXSEG8EI16V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLUXSEG2EI16V 0x24005007
|
|
|
++#define MASK_VLUXSEG2EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG2EI16V 0x24005027
|
|
|
++#define MASK_VSUXSEG2EI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG3EI16V 0x44005007
|
|
|
++#define MASK_VLUXSEG3EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG3EI16V 0x44005027
|
|
|
++#define MASK_VSUXSEG3EI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG4EI16V 0x64005007
|
|
|
++#define MASK_VLUXSEG4EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG4EI16V 0x64005027
|
|
|
++#define MASK_VSUXSEG4EI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG5EI16V 0x84005007
|
|
|
++#define MASK_VLUXSEG5EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG5EI16V 0x84005027
|
|
|
++#define MASK_VSUXSEG5EI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG6EI16V 0xa4005007
|
|
|
++#define MASK_VLUXSEG6EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG6EI16V 0xa4005027
|
|
|
++#define MASK_VSUXSEG6EI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG7EI16V 0xc4005007
|
|
|
++#define MASK_VLUXSEG7EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG7EI16V 0xc4005027
|
|
|
++#define MASK_VSUXSEG7EI16V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG8EI16V 0xe4005007
|
|
|
++#define MASK_VLUXSEG8EI16V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG8EI16V 0xe4005027
|
|
|
++#define MASK_VSUXSEG8EI16V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLOXSEG2EI32V 0x2c006007
|
|
|
++#define MASK_VLOXSEG2EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG2EI32V 0x2c006027
|
|
|
++#define MASK_VSOXSEG2EI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG3EI32V 0x4c006007
|
|
|
++#define MASK_VLOXSEG3EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG3EI32V 0x4c006027
|
|
|
++#define MASK_VSOXSEG3EI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG4EI32V 0x6c006007
|
|
|
++#define MASK_VLOXSEG4EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG4EI32V 0x6c006027
|
|
|
++#define MASK_VSOXSEG4EI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG5EI32V 0x8c006007
|
|
|
++#define MASK_VLOXSEG5EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG5EI32V 0x8c006027
|
|
|
++#define MASK_VSOXSEG5EI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG6EI32V 0xac006007
|
|
|
++#define MASK_VLOXSEG6EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG6EI32V 0xac006027
|
|
|
++#define MASK_VSOXSEG6EI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG7EI32V 0xcc006007
|
|
|
++#define MASK_VLOXSEG7EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG7EI32V 0xcc006027
|
|
|
++#define MASK_VSOXSEG7EI32V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG8EI32V 0xec006007
|
|
|
++#define MASK_VLOXSEG8EI32V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG8EI32V 0xec006027
|
|
|
++#define MASK_VSOXSEG8EI32V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLUXSEG2EI32V 0x24006007
|
|
|
++#define MASK_VLUXSEG2EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG2EI32V 0x24006027
|
|
|
++#define MASK_VSUXSEG2EI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG3EI32V 0x44006007
|
|
|
++#define MASK_VLUXSEG3EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG3EI32V 0x44006027
|
|
|
++#define MASK_VSUXSEG3EI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG4EI32V 0x64006007
|
|
|
++#define MASK_VLUXSEG4EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG4EI32V 0x64006027
|
|
|
++#define MASK_VSUXSEG4EI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG5EI32V 0x84006007
|
|
|
++#define MASK_VLUXSEG5EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG5EI32V 0x84006027
|
|
|
++#define MASK_VSUXSEG5EI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG6EI32V 0xa4006007
|
|
|
++#define MASK_VLUXSEG6EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG6EI32V 0xa4006027
|
|
|
++#define MASK_VSUXSEG6EI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG7EI32V 0xc4006007
|
|
|
++#define MASK_VLUXSEG7EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG7EI32V 0xc4006027
|
|
|
++#define MASK_VSUXSEG7EI32V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG8EI32V 0xe4006007
|
|
|
++#define MASK_VLUXSEG8EI32V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG8EI32V 0xe4006027
|
|
|
++#define MASK_VSUXSEG8EI32V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLOXSEG2EI64V 0x2c007007
|
|
|
++#define MASK_VLOXSEG2EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG2EI64V 0x2c007027
|
|
|
++#define MASK_VSOXSEG2EI64V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG3EI64V 0x4c007007
|
|
|
++#define MASK_VLOXSEG3EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG3EI64V 0x4c007027
|
|
|
++#define MASK_VSOXSEG3EI64V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG4EI64V 0x6c007007
|
|
|
++#define MASK_VLOXSEG4EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG4EI64V 0x6c007027
|
|
|
++#define MASK_VSOXSEG4EI64V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG5EI64V 0x8c007007
|
|
|
++#define MASK_VLOXSEG5EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG5EI64V 0x8c007027
|
|
|
++#define MASK_VSOXSEG5EI64V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG6EI64V 0xac007007
|
|
|
++#define MASK_VLOXSEG6EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG6EI64V 0xac007027
|
|
|
++#define MASK_VSOXSEG6EI64V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG7EI64V 0xcc007007
|
|
|
++#define MASK_VLOXSEG7EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG7EI64V 0xcc007027
|
|
|
++#define MASK_VSOXSEG7EI64V 0xfc00707f
|
|
|
++#define MATCH_VLOXSEG8EI64V 0xec007007
|
|
|
++#define MASK_VLOXSEG8EI64V 0xfc00707f
|
|
|
++#define MATCH_VSOXSEG8EI64V 0xec007027
|
|
|
++#define MASK_VSOXSEG8EI64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLUXSEG2EI64V 0x24007007
|
|
|
++#define MASK_VLUXSEG2EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG2EI64V 0x24007027
|
|
|
++#define MASK_VSUXSEG2EI64V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG3EI64V 0x44007007
|
|
|
++#define MASK_VLUXSEG3EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG3EI64V 0x44007027
|
|
|
++#define MASK_VSUXSEG3EI64V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG4EI64V 0x64007007
|
|
|
++#define MASK_VLUXSEG4EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG4EI64V 0x64007027
|
|
|
++#define MASK_VSUXSEG4EI64V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG5EI64V 0x84007007
|
|
|
++#define MASK_VLUXSEG5EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG5EI64V 0x84007027
|
|
|
++#define MASK_VSUXSEG5EI64V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG6EI64V 0xa4007007
|
|
|
++#define MASK_VLUXSEG6EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG6EI64V 0xa4007027
|
|
|
++#define MASK_VSUXSEG6EI64V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG7EI64V 0xc4007007
|
|
|
++#define MASK_VLUXSEG7EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG7EI64V 0xc4007027
|
|
|
++#define MASK_VSUXSEG7EI64V 0xfc00707f
|
|
|
++#define MATCH_VLUXSEG8EI64V 0xe4007007
|
|
|
++#define MASK_VLUXSEG8EI64V 0xfc00707f
|
|
|
++#define MATCH_VSUXSEG8EI64V 0xe4007027
|
|
|
++#define MASK_VSUXSEG8EI64V 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E8FFV 0x21000007
|
|
|
++#define MASK_VLSEG2E8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E8FFV 0x41000007
|
|
|
++#define MASK_VLSEG3E8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E8FFV 0x61000007
|
|
|
++#define MASK_VLSEG4E8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E8FFV 0x81000007
|
|
|
++#define MASK_VLSEG5E8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E8FFV 0xa1000007
|
|
|
++#define MASK_VLSEG6E8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E8FFV 0xc1000007
|
|
|
++#define MASK_VLSEG7E8FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E8FFV 0xe1000007
|
|
|
++#define MASK_VLSEG8E8FFV 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E16FFV 0x21005007
|
|
|
++#define MASK_VLSEG2E16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E16FFV 0x41005007
|
|
|
++#define MASK_VLSEG3E16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E16FFV 0x61005007
|
|
|
++#define MASK_VLSEG4E16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E16FFV 0x81005007
|
|
|
++#define MASK_VLSEG5E16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E16FFV 0xa1005007
|
|
|
++#define MASK_VLSEG6E16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E16FFV 0xc1005007
|
|
|
++#define MASK_VLSEG7E16FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E16FFV 0xe1005007
|
|
|
++#define MASK_VLSEG8E16FFV 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E32FFV 0x21006007
|
|
|
++#define MASK_VLSEG2E32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E32FFV 0x41006007
|
|
|
++#define MASK_VLSEG3E32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E32FFV 0x61006007
|
|
|
++#define MASK_VLSEG4E32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E32FFV 0x81006007
|
|
|
++#define MASK_VLSEG5E32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E32FFV 0xa1006007
|
|
|
++#define MASK_VLSEG6E32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E32FFV 0xc1006007
|
|
|
++#define MASK_VLSEG7E32FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E32FFV 0xe1006007
|
|
|
++#define MASK_VLSEG8E32FFV 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VLSEG2E64FFV 0x21007007
|
|
|
++#define MASK_VLSEG2E64FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG3E64FFV 0x41007007
|
|
|
++#define MASK_VLSEG3E64FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG4E64FFV 0x61007007
|
|
|
++#define MASK_VLSEG4E64FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG5E64FFV 0x81007007
|
|
|
++#define MASK_VLSEG5E64FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG6E64FFV 0xa1007007
|
|
|
++#define MASK_VLSEG6E64FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG7E64FFV 0xc1007007
|
|
|
++#define MASK_VLSEG7E64FFV 0xfdf0707f
|
|
|
++#define MATCH_VLSEG8E64FFV 0xe1007007
|
|
|
++#define MASK_VLSEG8E64FFV 0xfdf0707f
|
|
|
++
|
|
|
++#define MATCH_VL1RE8V 0x02800007
|
|
|
++#define MASK_VL1RE8V 0xfff0707f
|
|
|
++#define MATCH_VL1RE16V 0x02805007
|
|
|
++#define MASK_VL1RE16V 0xfff0707f
|
|
|
++#define MATCH_VL1RE32V 0x02806007
|
|
|
++#define MASK_VL1RE32V 0xfff0707f
|
|
|
++#define MATCH_VL1RE64V 0x02807007
|
|
|
++#define MASK_VL1RE64V 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VL2RE8V 0x22800007
|
|
|
++#define MASK_VL2RE8V 0xfff0707f
|
|
|
++#define MATCH_VL2RE16V 0x22805007
|
|
|
++#define MASK_VL2RE16V 0xfff0707f
|
|
|
++#define MATCH_VL2RE32V 0x22806007
|
|
|
++#define MASK_VL2RE32V 0xfff0707f
|
|
|
++#define MATCH_VL2RE64V 0x22807007
|
|
|
++#define MASK_VL2RE64V 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VL4RE8V 0x62800007
|
|
|
++#define MASK_VL4RE8V 0xfff0707f
|
|
|
++#define MATCH_VL4RE16V 0x62805007
|
|
|
++#define MASK_VL4RE16V 0xfff0707f
|
|
|
++#define MATCH_VL4RE32V 0x62806007
|
|
|
++#define MASK_VL4RE32V 0xfff0707f
|
|
|
++#define MATCH_VL4RE64V 0x62807007
|
|
|
++#define MASK_VL4RE64V 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VL8RE8V 0xe2800007
|
|
|
++#define MASK_VL8RE8V 0xfff0707f
|
|
|
++#define MATCH_VL8RE16V 0xe2805007
|
|
|
++#define MASK_VL8RE16V 0xfff0707f
|
|
|
++#define MATCH_VL8RE32V 0xe2806007
|
|
|
++#define MASK_VL8RE32V 0xfff0707f
|
|
|
++#define MATCH_VL8RE64V 0xe2807007
|
|
|
++#define MASK_VL8RE64V 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VS1RV 0x02800027
|
|
|
++#define MASK_VS1RV 0xfff0707f
|
|
|
++#define MATCH_VS2RV 0x22800027
|
|
|
++#define MASK_VS2RV 0xfff0707f
|
|
|
++#define MATCH_VS4RV 0x62800027
|
|
|
++#define MASK_VS4RV 0xfff0707f
|
|
|
++#define MATCH_VS8RV 0xe2800027
|
|
|
++#define MASK_VS8RV 0xfff0707f
|
|
|
++
|
|
|
++/* Temporary AMO encoding info
|
|
|
++
|
|
|
++width
|
|
|
++010 AMO*.W
|
|
|
++011 AMO*.D
|
|
|
++100 AMO*.Q
|
|
|
++000 VAMO*EI8.V
|
|
|
++101 VAMO*EI16.V
|
|
|
++110 VAMO*EI32.V
|
|
|
++111 VAMO*EI64.V
|
|
|
++
|
|
|
++amoop
|
|
|
++00001 vamoswap
|
|
|
++00000 vamoadd
|
|
|
++00100 vamoxor
|
|
|
++01100 vamoand
|
|
|
++01000 vamoor
|
|
|
++10000 vamomin
|
|
|
++10100 vamomax
|
|
|
++11000 vamominu
|
|
|
++11100 vamomaxu
|
|
|
++
|
|
|
++ 31-27 26 25 24-20 19-15 14-12 11-7 6-0
|
|
|
++ amoop wd vm vs2 rs1 width vs3/vd opcode
|
|
|
++ 00001 x 1 xxxxx xxxxx 110 xxxxx 0101111
|
|
|
++ 0000 1x1x xxxx xxxx x110 xxxx x010 1111
|
|
|
++ 1111 1010 0000 0000 0111 0000 0111 1111 */
|
|
|
++
|
|
|
++#define MATCH_VAMOADDEI8V 0x0000002f
|
|
|
++#define MASK_VAMOADDEI8V 0xf800707f
|
|
|
++#define MATCH_VAMOSWAPEI8V 0x0800002f
|
|
|
++#define MASK_VAMOSWAPEI8V 0xf800707f
|
|
|
++#define MATCH_VAMOXOREI8V 0x2000002f
|
|
|
++#define MASK_VAMOXOREI8V 0xf800707f
|
|
|
++#define MATCH_VAMOANDEI8V 0x6000002f
|
|
|
++#define MASK_VAMOANDEI8V 0xf800707f
|
|
|
++#define MATCH_VAMOOREI8V 0x4000002f
|
|
|
++#define MASK_VAMOOREI8V 0xf800707f
|
|
|
++#define MATCH_VAMOMINEI8V 0x8000002f
|
|
|
++#define MASK_VAMOMINEI8V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXEI8V 0xa000002f
|
|
|
++#define MASK_VAMOMAXEI8V 0xf800707f
|
|
|
++#define MATCH_VAMOMINUEI8V 0xc000002f
|
|
|
++#define MASK_VAMOMINUEI8V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXUEI8V 0xe000002f
|
|
|
++#define MASK_VAMOMAXUEI8V 0xf800707f
|
|
|
++
|
|
|
++#define MATCH_VAMOADDEI16V 0x0000502f
|
|
|
++#define MASK_VAMOADDEI16V 0xf800707f
|
|
|
++#define MATCH_VAMOSWAPEI16V 0x0800502f
|
|
|
++#define MASK_VAMOSWAPEI16V 0xf800707f
|
|
|
++#define MATCH_VAMOXOREI16V 0x2000502f
|
|
|
++#define MASK_VAMOXOREI16V 0xf800707f
|
|
|
++#define MATCH_VAMOANDEI16V 0x6000502f
|
|
|
++#define MASK_VAMOANDEI16V 0xf800707f
|
|
|
++#define MATCH_VAMOOREI16V 0x4000502f
|
|
|
++#define MASK_VAMOOREI16V 0xf800707f
|
|
|
++#define MATCH_VAMOMINEI16V 0x8000502f
|
|
|
++#define MASK_VAMOMINEI16V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXEI16V 0xa000502f
|
|
|
++#define MASK_VAMOMAXEI16V 0xf800707f
|
|
|
++#define MATCH_VAMOMINUEI16V 0xc000502f
|
|
|
++#define MASK_VAMOMINUEI16V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXUEI16V 0xe000502f
|
|
|
++#define MASK_VAMOMAXUEI16V 0xf800707f
|
|
|
++
|
|
|
++#define MATCH_VAMOADDEI32V 0x0000602f
|
|
|
++#define MASK_VAMOADDEI32V 0xf800707f
|
|
|
++#define MATCH_VAMOSWAPEI32V 0x0800602f
|
|
|
++#define MASK_VAMOSWAPEI32V 0xf800707f
|
|
|
++#define MATCH_VAMOXOREI32V 0x2000602f
|
|
|
++#define MASK_VAMOXOREI32V 0xf800707f
|
|
|
++#define MATCH_VAMOANDEI32V 0x6000602f
|
|
|
++#define MASK_VAMOANDEI32V 0xf800707f
|
|
|
++#define MATCH_VAMOOREI32V 0x4000602f
|
|
|
++#define MASK_VAMOOREI32V 0xf800707f
|
|
|
++#define MATCH_VAMOMINEI32V 0x8000602f
|
|
|
++#define MASK_VAMOMINEI32V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXEI32V 0xa000602f
|
|
|
++#define MASK_VAMOMAXEI32V 0xf800707f
|
|
|
++#define MATCH_VAMOMINUEI32V 0xc000602f
|
|
|
++#define MASK_VAMOMINUEI32V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXUEI32V 0xe000602f
|
|
|
++#define MASK_VAMOMAXUEI32V 0xf800707f
|
|
|
++
|
|
|
++#define MATCH_VAMOADDEI64V 0x0000702f
|
|
|
++#define MASK_VAMOADDEI64V 0xf800707f
|
|
|
++#define MATCH_VAMOSWAPEI64V 0x0800702f
|
|
|
++#define MASK_VAMOSWAPEI64V 0xf800707f
|
|
|
++#define MATCH_VAMOXOREI64V 0x2000702f
|
|
|
++#define MASK_VAMOXOREI64V 0xf800707f
|
|
|
++#define MATCH_VAMOANDEI64V 0x6000702f
|
|
|
++#define MASK_VAMOANDEI64V 0xf800707f
|
|
|
++#define MATCH_VAMOOREI64V 0x4000702f
|
|
|
++#define MASK_VAMOOREI64V 0xf800707f
|
|
|
++#define MATCH_VAMOMINEI64V 0x8000702f
|
|
|
++#define MASK_VAMOMINEI64V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXEI64V 0xa000702f
|
|
|
++#define MASK_VAMOMAXEI64V 0xf800707f
|
|
|
++#define MATCH_VAMOMINUEI64V 0xc000702f
|
|
|
++#define MASK_VAMOMINUEI64V 0xf800707f
|
|
|
++#define MATCH_VAMOMAXUEI64V 0xe000702f
|
|
|
++#define MASK_VAMOMAXUEI64V 0xf800707f
|
|
|
++
|
|
|
++/* Temporary ALU encoding info
|
|
|
++
|
|
|
++funct3
|
|
|
++000 OPIVV vv
|
|
|
++001 OPFVV vv
|
|
|
++010 OPMVV vv
|
|
|
++011 OPIVI vi simm[4:0]
|
|
|
++100 OPIVX vx GPR x-reg rs1
|
|
|
++101 OPFVF vf FP f-reg rs1
|
|
|
++110 OPMVX vx GPR x-reg rs1
|
|
|
++111 OPCFG si GPR x-reg rs1 & rs2/imm
|
|
|
++
|
|
|
++INT OPI
|
|
|
++funct6
|
|
|
++000000 vadd
|
|
|
++000001
|
|
|
++000010 vsub
|
|
|
++000011 vrsub
|
|
|
++000100 vminu
|
|
|
++000101 vmin
|
|
|
++000110 vmaxu
|
|
|
++000111 vmax
|
|
|
++001000
|
|
|
++001001 vand
|
|
|
++001010 vor
|
|
|
++001011 vxor
|
|
|
++001100 vrgather
|
|
|
++001101
|
|
|
++001110 vslideup, vrgatherei16
|
|
|
++001111 vslidedown
|
|
|
++010000 vadc
|
|
|
++010001 vmadc
|
|
|
++010010 vsbc
|
|
|
++010011 vmsbc
|
|
|
++010100
|
|
|
++010101
|
|
|
++010110
|
|
|
++010111 vmerge/vmv
|
|
|
++011000 vmseq
|
|
|
++011001 vmsne
|
|
|
++011010 vmsltu
|
|
|
++011011 vmslt
|
|
|
++011100 vmsleu
|
|
|
++011101 vmsle
|
|
|
++011110 vmsgtu
|
|
|
++011111 vmsgt
|
|
|
++100000 vsaddu
|
|
|
++100001 vsadd
|
|
|
++100010 vssubu
|
|
|
++100011 vssub
|
|
|
++100100
|
|
|
++100101 vsll
|
|
|
++100110
|
|
|
++100111 vmv<nf>r (nf = 1, 2, 4, 8)
|
|
|
++101000 vsrl
|
|
|
++101001 vsra
|
|
|
++101010 vssrl
|
|
|
++101011 vssra
|
|
|
++101100 vnsrl
|
|
|
++101101 vnsra
|
|
|
++101110 vnclipu
|
|
|
++101111 vnclip
|
|
|
++110000 vwredsumu
|
|
|
++110001 vwredsum
|
|
|
++110010
|
|
|
++110011
|
|
|
++110100
|
|
|
++110101
|
|
|
++110110
|
|
|
++110111
|
|
|
++111000 vdotu **
|
|
|
++111001 vdot **
|
|
|
++111010
|
|
|
++111011
|
|
|
++111100 vqmaccu
|
|
|
++111101 vqmacc
|
|
|
++111110 vqmaccus
|
|
|
++111111 vqmaccsu
|
|
|
++
|
|
|
++INT OPM
|
|
|
++funct6
|
|
|
++000000 vredsum
|
|
|
++000001 vredand
|
|
|
++000010 vredor
|
|
|
++000011 vredxor
|
|
|
++000100 vredminu
|
|
|
++000101 vredmin
|
|
|
++000110 vredmaxu
|
|
|
++000111 vredmax
|
|
|
++001000 vaaddu
|
|
|
++001001 vaadd
|
|
|
++001010 vasubu
|
|
|
++001011 vasub
|
|
|
++001100
|
|
|
++001101
|
|
|
++001110 vslide1up
|
|
|
++001111 vslide1down
|
|
|
++010000 VRXUNARY0/VWXUNARY0
|
|
|
++010001
|
|
|
++010010 VXUNARY0
|
|
|
++010011
|
|
|
++010100 VMUNARY0
|
|
|
++010101
|
|
|
++010110
|
|
|
++010111 vcompress
|
|
|
++011000 vmandnot
|
|
|
++011001 vmand
|
|
|
++011010 vmor
|
|
|
++011011 vmxor
|
|
|
++011100 vmornot
|
|
|
++011101 vmnand
|
|
|
++011110 vmnor
|
|
|
++011111 vmxnor
|
|
|
++100000 vdivu
|
|
|
++100001 vdiv
|
|
|
++100010 vremu
|
|
|
++100011 vrem
|
|
|
++100100 vmulhu
|
|
|
++100101 vmul
|
|
|
++100110 vmulhsu
|
|
|
++100111 vmulh
|
|
|
++101000
|
|
|
++101001 vmadd
|
|
|
++101010
|
|
|
++101011 vnmsub
|
|
|
++101100
|
|
|
++101101 vmacc
|
|
|
++101110
|
|
|
++101111 vnmsac
|
|
|
++110000 vwaddu
|
|
|
++110001 vwadd
|
|
|
++110010 vwsubu
|
|
|
++110011 vwsub
|
|
|
++110100 vwaddu.w
|
|
|
++110101 vwadd.w
|
|
|
++110110 vwsubu.w
|
|
|
++110111 vwsub.w
|
|
|
++111000 vwmulu
|
|
|
++111001
|
|
|
++111010 vwmulsu
|
|
|
++111011 vwmul
|
|
|
++111100 vwmaccu
|
|
|
++111101 vwmacc
|
|
|
++111110 vwmaccus
|
|
|
++111111 vwmaccsu
|
|
|
++
|
|
|
++VRXUNARY0
|
|
|
++vs2, funct3=X
|
|
|
++00000 vmv.s.x
|
|
|
++
|
|
|
++VWXUNARY0
|
|
|
++vs1, funct3=V
|
|
|
++00000 vmv.x.s
|
|
|
++10000 vpopc
|
|
|
++10001 vfirst
|
|
|
++
|
|
|
++VXUNARY0
|
|
|
++vs1, funct3=V
|
|
|
++00010 vzext.vf8
|
|
|
++00011 vsext.vf8
|
|
|
++00100 vzext.vf4
|
|
|
++00101 vsext.vf4
|
|
|
++00110 vzext.vf2
|
|
|
++00111 vsext.vf2
|
|
|
++
|
|
|
++VMUNARY0
|
|
|
++rs1
|
|
|
++00001 vmsbf
|
|
|
++00010 vmsof
|
|
|
++00011 vmsif
|
|
|
++10000 viota
|
|
|
++10001 vid
|
|
|
++
|
|
|
++VFLOAT
|
|
|
++funct6
|
|
|
++000000 vfadd
|
|
|
++000001 vfredsum
|
|
|
++000010 vfsub
|
|
|
++000011 vfredosum
|
|
|
++000100 vfmin
|
|
|
++000101 vfredmin
|
|
|
++000110 vfmax
|
|
|
++000111 vfredmax
|
|
|
++001000 vfsgnj
|
|
|
++001001 vfsgnn
|
|
|
++001010 vfsgnx
|
|
|
++001011
|
|
|
++001100
|
|
|
++001101
|
|
|
++001110 vfslide1up
|
|
|
++001111 vfslide1down
|
|
|
++010000 VRFUNARY0/VWFUNARY0
|
|
|
++010001
|
|
|
++010010 VFUNARY0
|
|
|
++010011 VFUNARY1
|
|
|
++010100
|
|
|
++010101
|
|
|
++010110
|
|
|
++010111 vfmerge/vfmv
|
|
|
++011000 vmfeq
|
|
|
++011001 vmfle
|
|
|
++011010
|
|
|
++011011 vmflt
|
|
|
++011100 vmfne
|
|
|
++011101 vmfgt
|
|
|
++011110
|
|
|
++011111 vmfge
|
|
|
++100000 vfdiv
|
|
|
++100001 vfrdiv
|
|
|
++100010
|
|
|
++100011
|
|
|
++100100 vfmul
|
|
|
++100101
|
|
|
++100110
|
|
|
++100111 vfrsub
|
|
|
++101000 vfmadd
|
|
|
++101001 vfnmadd
|
|
|
++101010 vfmsub
|
|
|
++101011 vfnmsub
|
|
|
++101100 vfmacc
|
|
|
++101101 vfnmacc
|
|
|
++101110 vfmsac
|
|
|
++101111 vfnmsac
|
|
|
++110000 vfwadd
|
|
|
++110001 vfwredsum
|
|
|
++110010 vfwsub
|
|
|
++110011 vfwredosum
|
|
|
++110100 vfwadd.w
|
|
|
++110101
|
|
|
++110110 vfwsub.w
|
|
|
++110111
|
|
|
++111000 vfwmul
|
|
|
++111001 vfdot
|
|
|
++111010
|
|
|
++111011
|
|
|
++111100 vfwmacc
|
|
|
++111101 vfwnmacc
|
|
|
++111110 vfwmsac
|
|
|
++111111 vfwnmsac
|
|
|
++
|
|
|
++VRFUNARY0
|
|
|
++vs2, funct3=F
|
|
|
++00000 vfmv.s.f
|
|
|
++
|
|
|
++VWFUNARY0
|
|
|
++vs1, funct3=V
|
|
|
++00000 vfmv.f.s
|
|
|
++
|
|
|
++VFUNARY0
|
|
|
++vs1
|
|
|
++00000 vfcvt.xu.f.v
|
|
|
++00001 vfcvt.x.f.v
|
|
|
++00010 vfcvt.f.xu.v
|
|
|
++00011 vfcvt.f.x.v
|
|
|
++00110 vfcvt.rtz.xu.f.v
|
|
|
++00111 vfcvt.rtz.x.f.v
|
|
|
++
|
|
|
++01000 vfwcvt.xu.f.v
|
|
|
++01001 vfwcvt.x.f.v
|
|
|
++01010 vfwcvt.f.xu.v
|
|
|
++01011 vfwcvt.f.x.v
|
|
|
++01100 vfwcvt.f.f.v
|
|
|
++01110 vfwcvt.rtz.xu.f.v
|
|
|
++01111 vfwcvt.rtz.x.f.v
|
|
|
++
|
|
|
++10000 vfncvt.xu.f.w
|
|
|
++10001 vfncvt.x.f.w
|
|
|
++10010 vfncvt.f.xu.w
|
|
|
++10011 vfncvt.f.x.w
|
|
|
++10100 vfncvt.f.f.w
|
|
|
++10101 vfncvt.rod.f.f.w
|
|
|
++10110 vfncvt.rtz.xu.f.v
|
|
|
++10111 vfncvt.rtz.x.f.v
|
|
|
++
|
|
|
++VFUNARY1
|
|
|
++vs1
|
|
|
++00000 vfsqrt.v
|
|
|
++00100 vfrsqrte7.v
|
|
|
++00101 vfrece7.v
|
|
|
++10000 vfclass.v
|
|
|
++
|
|
|
++31-26 25 24-20 19-15 14-12 11-7 6-0
|
|
|
++funct6 VM VS2 VS1/RS1/IMM funct3 VD opcode
|
|
|
++010000 x xxxxx 00000 001 xxxxx 1010111
|
|
|
++0100 00xx xxxx 0000 0001 xxxx x101 0111
|
|
|
++*/
|
|
|
++
|
|
|
++#define MATCH_VADDVV 0x00000057
|
|
|
++#define MASK_VADDVV 0xfc00707f
|
|
|
++#define MATCH_VADDVX 0x00004057
|
|
|
++#define MASK_VADDVX 0xfc00707f
|
|
|
++#define MATCH_VADDVI 0x00003057
|
|
|
++#define MASK_VADDVI 0xfc00707f
|
|
|
++#define MATCH_VSUBVV 0x08000057
|
|
|
++#define MASK_VSUBVV 0xfc00707f
|
|
|
++#define MATCH_VSUBVX 0x08004057
|
|
|
++#define MASK_VSUBVX 0xfc00707f
|
|
|
++#define MATCH_VRSUBVX 0x0c004057
|
|
|
++#define MASK_VRSUBVX 0xfc00707f
|
|
|
++#define MATCH_VRSUBVI 0x0c003057
|
|
|
++#define MASK_VRSUBVI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VWCVTXXV 0xc4006057
|
|
|
++#define MASK_VWCVTXXV 0xfc0ff07f
|
|
|
++#define MATCH_VWCVTUXXV 0xc0006057
|
|
|
++#define MASK_VWCVTUXXV 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VWADDVV 0xc4002057
|
|
|
++#define MASK_VWADDVV 0xfc00707f
|
|
|
++#define MATCH_VWADDVX 0xc4006057
|
|
|
++#define MASK_VWADDVX 0xfc00707f
|
|
|
++#define MATCH_VWSUBVV 0xcc002057
|
|
|
++#define MASK_VWSUBVV 0xfc00707f
|
|
|
++#define MATCH_VWSUBVX 0xcc006057
|
|
|
++#define MASK_VWSUBVX 0xfc00707f
|
|
|
++#define MATCH_VWADDWV 0xd4002057
|
|
|
++#define MASK_VWADDWV 0xfc00707f
|
|
|
++#define MATCH_VWADDWX 0xd4006057
|
|
|
++#define MASK_VWADDWX 0xfc00707f
|
|
|
++#define MATCH_VWSUBWV 0xdc002057
|
|
|
++#define MASK_VWSUBWV 0xfc00707f
|
|
|
++#define MATCH_VWSUBWX 0xdc006057
|
|
|
++#define MASK_VWSUBWX 0xfc00707f
|
|
|
++#define MATCH_VWADDUVV 0xc0002057
|
|
|
++#define MASK_VWADDUVV 0xfc00707f
|
|
|
++#define MATCH_VWADDUVX 0xc0006057
|
|
|
++#define MASK_VWADDUVX 0xfc00707f
|
|
|
++#define MATCH_VWSUBUVV 0xc8002057
|
|
|
++#define MASK_VWSUBUVV 0xfc00707f
|
|
|
++#define MATCH_VWSUBUVX 0xc8006057
|
|
|
++#define MASK_VWSUBUVX 0xfc00707f
|
|
|
++#define MATCH_VWADDUWV 0xd0002057
|
|
|
++#define MASK_VWADDUWV 0xfc00707f
|
|
|
++#define MATCH_VWADDUWX 0xd0006057
|
|
|
++#define MASK_VWADDUWX 0xfc00707f
|
|
|
++#define MATCH_VWSUBUWV 0xd8002057
|
|
|
++#define MASK_VWSUBUWV 0xfc00707f
|
|
|
++#define MATCH_VWSUBUWX 0xd8006057
|
|
|
++#define MASK_VWSUBUWX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VZEXT_VF8 0x48012057
|
|
|
++#define MASK_VZEXT_VF8 0xfc0ff07f
|
|
|
++#define MATCH_VSEXT_VF8 0x4801a057
|
|
|
++#define MASK_VSEXT_VF8 0xfc0ff07f
|
|
|
++#define MATCH_VZEXT_VF4 0x48022057
|
|
|
++#define MASK_VZEXT_VF4 0xfc0ff07f
|
|
|
++#define MATCH_VSEXT_VF4 0x4802a057
|
|
|
++#define MASK_VSEXT_VF4 0xfc0ff07f
|
|
|
++#define MATCH_VZEXT_VF2 0x48032057
|
|
|
++#define MASK_VZEXT_VF2 0xfc0ff07f
|
|
|
++#define MATCH_VSEXT_VF2 0x4803a057
|
|
|
++#define MASK_VSEXT_VF2 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VADCVVM 0x40000057
|
|
|
++#define MASK_VADCVVM 0xfe00707f
|
|
|
++#define MATCH_VADCVXM 0x40004057
|
|
|
++#define MASK_VADCVXM 0xfe00707f
|
|
|
++#define MATCH_VADCVIM 0x40003057
|
|
|
++#define MASK_VADCVIM 0xfe00707f
|
|
|
++#define MATCH_VMADCVVM 0x44000057
|
|
|
++#define MASK_VMADCVVM 0xfe00707f
|
|
|
++#define MATCH_VMADCVXM 0x44004057
|
|
|
++#define MASK_VMADCVXM 0xfe00707f
|
|
|
++#define MATCH_VMADCVIM 0x44003057
|
|
|
++#define MASK_VMADCVIM 0xfe00707f
|
|
|
++#define MATCH_VMADCVV 0x46000057
|
|
|
++#define MASK_VMADCVV 0xfe00707f
|
|
|
++#define MATCH_VMADCVX 0x46004057
|
|
|
++#define MASK_VMADCVX 0xfe00707f
|
|
|
++#define MATCH_VMADCVI 0x46003057
|
|
|
++#define MASK_VMADCVI 0xfe00707f
|
|
|
++#define MATCH_VSBCVVM 0x48000057
|
|
|
++#define MASK_VSBCVVM 0xfe00707f
|
|
|
++#define MATCH_VSBCVXM 0x48004057
|
|
|
++#define MASK_VSBCVXM 0xfe00707f
|
|
|
++#define MATCH_VMSBCVVM 0x4c000057
|
|
|
++#define MASK_VMSBCVVM 0xfe00707f
|
|
|
++#define MATCH_VMSBCVXM 0x4c004057
|
|
|
++#define MASK_VMSBCVXM 0xfe00707f
|
|
|
++#define MATCH_VMSBCVV 0x4e000057
|
|
|
++#define MASK_VMSBCVV 0xfe00707f
|
|
|
++#define MATCH_VMSBCVX 0x4e004057
|
|
|
++#define MASK_VMSBCVX 0xfe00707f
|
|
|
++
|
|
|
++#define MATCH_VNOTV 0x2c0fb057
|
|
|
++#define MASK_VNOTV 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VANDVV 0x24000057
|
|
|
++#define MASK_VANDVV 0xfc00707f
|
|
|
++#define MATCH_VANDVX 0x24004057
|
|
|
++#define MASK_VANDVX 0xfc00707f
|
|
|
++#define MATCH_VANDVI 0x24003057
|
|
|
++#define MASK_VANDVI 0xfc00707f
|
|
|
++#define MATCH_VORVV 0x28000057
|
|
|
++#define MASK_VORVV 0xfc00707f
|
|
|
++#define MATCH_VORVX 0x28004057
|
|
|
++#define MASK_VORVX 0xfc00707f
|
|
|
++#define MATCH_VORVI 0x28003057
|
|
|
++#define MASK_VORVI 0xfc00707f
|
|
|
++#define MATCH_VXORVV 0x2c000057
|
|
|
++#define MASK_VXORVV 0xfc00707f
|
|
|
++#define MATCH_VXORVX 0x2c004057
|
|
|
++#define MASK_VXORVX 0xfc00707f
|
|
|
++#define MATCH_VXORVI 0x2c003057
|
|
|
++#define MASK_VXORVI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSLLVV 0x94000057
|
|
|
++#define MASK_VSLLVV 0xfc00707f
|
|
|
++#define MATCH_VSLLVX 0x94004057
|
|
|
++#define MASK_VSLLVX 0xfc00707f
|
|
|
++#define MATCH_VSLLVI 0x94003057
|
|
|
++#define MASK_VSLLVI 0xfc00707f
|
|
|
++#define MATCH_VSRLVV 0xa0000057
|
|
|
++#define MASK_VSRLVV 0xfc00707f
|
|
|
++#define MATCH_VSRLVX 0xa0004057
|
|
|
++#define MASK_VSRLVX 0xfc00707f
|
|
|
++#define MATCH_VSRLVI 0xa0003057
|
|
|
++#define MASK_VSRLVI 0xfc00707f
|
|
|
++#define MATCH_VSRAVV 0xa4000057
|
|
|
++#define MASK_VSRAVV 0xfc00707f
|
|
|
++#define MATCH_VSRAVX 0xa4004057
|
|
|
++#define MASK_VSRAVX 0xfc00707f
|
|
|
++#define MATCH_VSRAVI 0xa4003057
|
|
|
++#define MASK_VSRAVI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VNCVTXXW 0xb0004057
|
|
|
++#define MASK_VNCVTXXW 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VNSRLWV 0xb0000057
|
|
|
++#define MASK_VNSRLWV 0xfc00707f
|
|
|
++#define MATCH_VNSRLWX 0xb0004057
|
|
|
++#define MASK_VNSRLWX 0xfc00707f
|
|
|
++#define MATCH_VNSRLWI 0xb0003057
|
|
|
++#define MASK_VNSRLWI 0xfc00707f
|
|
|
++#define MATCH_VNSRAWV 0xb4000057
|
|
|
++#define MASK_VNSRAWV 0xfc00707f
|
|
|
++#define MATCH_VNSRAWX 0xb4004057
|
|
|
++#define MASK_VNSRAWX 0xfc00707f
|
|
|
++#define MATCH_VNSRAWI 0xb4003057
|
|
|
++#define MASK_VNSRAWI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMSEQVV 0x60000057
|
|
|
++#define MASK_VMSEQVV 0xfc00707f
|
|
|
++#define MATCH_VMSEQVX 0x60004057
|
|
|
++#define MASK_VMSEQVX 0xfc00707f
|
|
|
++#define MATCH_VMSEQVI 0x60003057
|
|
|
++#define MASK_VMSEQVI 0xfc00707f
|
|
|
++#define MATCH_VMSNEVV 0x64000057
|
|
|
++#define MASK_VMSNEVV 0xfc00707f
|
|
|
++#define MATCH_VMSNEVX 0x64004057
|
|
|
++#define MASK_VMSNEVX 0xfc00707f
|
|
|
++#define MATCH_VMSNEVI 0x64003057
|
|
|
++#define MASK_VMSNEVI 0xfc00707f
|
|
|
++#define MATCH_VMSLTVV 0x6c000057
|
|
|
++#define MASK_VMSLTVV 0xfc00707f
|
|
|
++#define MATCH_VMSLTVX 0x6c004057
|
|
|
++#define MASK_VMSLTVX 0xfc00707f
|
|
|
++#define MATCH_VMSLTUVV 0x68000057
|
|
|
++#define MASK_VMSLTUVV 0xfc00707f
|
|
|
++#define MATCH_VMSLTUVX 0x68004057
|
|
|
++#define MASK_VMSLTUVX 0xfc00707f
|
|
|
++#define MATCH_VMSLEVV 0x74000057
|
|
|
++#define MASK_VMSLEVV 0xfc00707f
|
|
|
++#define MATCH_VMSLEVX 0x74004057
|
|
|
++#define MASK_VMSLEVX 0xfc00707f
|
|
|
++#define MATCH_VMSLEVI 0x74003057
|
|
|
++#define MASK_VMSLEVI 0xfc00707f
|
|
|
++#define MATCH_VMSLEUVV 0x70000057
|
|
|
++#define MASK_VMSLEUVV 0xfc00707f
|
|
|
++#define MATCH_VMSLEUVX 0x70004057
|
|
|
++#define MASK_VMSLEUVX 0xfc00707f
|
|
|
++#define MATCH_VMSLEUVI 0x70003057
|
|
|
++#define MASK_VMSLEUVI 0xfc00707f
|
|
|
++#define MATCH_VMSGTVX 0x7c004057
|
|
|
++#define MASK_VMSGTVX 0xfc00707f
|
|
|
++#define MATCH_VMSGTVI 0x7c003057
|
|
|
++#define MASK_VMSGTVI 0xfc00707f
|
|
|
++#define MATCH_VMSGTUVX 0x78004057
|
|
|
++#define MASK_VMSGTUVX 0xfc00707f
|
|
|
++#define MATCH_VMSGTUVI 0x78003057
|
|
|
++#define MASK_VMSGTUVI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMINVV 0x14000057
|
|
|
++#define MASK_VMINVV 0xfc00707f
|
|
|
++#define MATCH_VMINVX 0x14004057
|
|
|
++#define MASK_VMINVX 0xfc00707f
|
|
|
++#define MATCH_VMAXVV 0x1c000057
|
|
|
++#define MASK_VMAXVV 0xfc00707f
|
|
|
++#define MATCH_VMAXVX 0x1c004057
|
|
|
++#define MASK_VMAXVX 0xfc00707f
|
|
|
++#define MATCH_VMINUVV 0x10000057
|
|
|
++#define MASK_VMINUVV 0xfc00707f
|
|
|
++#define MATCH_VMINUVX 0x10004057
|
|
|
++#define MASK_VMINUVX 0xfc00707f
|
|
|
++#define MATCH_VMAXUVV 0x18000057
|
|
|
++#define MASK_VMAXUVV 0xfc00707f
|
|
|
++#define MATCH_VMAXUVX 0x18004057
|
|
|
++#define MASK_VMAXUVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMULVV 0x94002057
|
|
|
++#define MASK_VMULVV 0xfc00707f
|
|
|
++#define MATCH_VMULVX 0x94006057
|
|
|
++#define MASK_VMULVX 0xfc00707f
|
|
|
++#define MATCH_VMULHVV 0x9c002057
|
|
|
++#define MASK_VMULHVV 0xfc00707f
|
|
|
++#define MATCH_VMULHVX 0x9c006057
|
|
|
++#define MASK_VMULHVX 0xfc00707f
|
|
|
++#define MATCH_VMULHUVV 0x90002057
|
|
|
++#define MASK_VMULHUVV 0xfc00707f
|
|
|
++#define MATCH_VMULHUVX 0x90006057
|
|
|
++#define MASK_VMULHUVX 0xfc00707f
|
|
|
++#define MATCH_VMULHSUVV 0x98002057
|
|
|
++#define MASK_VMULHSUVV 0xfc00707f
|
|
|
++#define MATCH_VMULHSUVX 0x98006057
|
|
|
++#define MASK_VMULHSUVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VWMULVV 0xec002057
|
|
|
++#define MASK_VWMULVV 0xfc00707f
|
|
|
++#define MATCH_VWMULVX 0xec006057
|
|
|
++#define MASK_VWMULVX 0xfc00707f
|
|
|
++#define MATCH_VWMULUVV 0xe0002057
|
|
|
++#define MASK_VWMULUVV 0xfc00707f
|
|
|
++#define MATCH_VWMULUVX 0xe0006057
|
|
|
++#define MASK_VWMULUVX 0xfc00707f
|
|
|
++#define MATCH_VWMULSUVV 0xe8002057
|
|
|
++#define MASK_VWMULSUVV 0xfc00707f
|
|
|
++#define MATCH_VWMULSUVX 0xe8006057
|
|
|
++#define MASK_VWMULSUVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMACCVV 0xb4002057
|
|
|
++#define MASK_VMACCVV 0xfc00707f
|
|
|
++#define MATCH_VMACCVX 0xb4006057
|
|
|
++#define MASK_VMACCVX 0xfc00707f
|
|
|
++#define MATCH_VNMSACVV 0xbc002057
|
|
|
++#define MASK_VNMSACVV 0xfc00707f
|
|
|
++#define MATCH_VNMSACVX 0xbc006057
|
|
|
++#define MASK_VNMSACVX 0xfc00707f
|
|
|
++#define MATCH_VMADDVV 0xa4002057
|
|
|
++#define MASK_VMADDVV 0xfc00707f
|
|
|
++#define MATCH_VMADDVX 0xa4006057
|
|
|
++#define MASK_VMADDVX 0xfc00707f
|
|
|
++#define MATCH_VNMSUBVV 0xac002057
|
|
|
++#define MASK_VNMSUBVV 0xfc00707f
|
|
|
++#define MATCH_VNMSUBVX 0xac006057
|
|
|
++#define MASK_VNMSUBVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VWMACCUVV 0xf0002057
|
|
|
++#define MASK_VWMACCUVV 0xfc00707f
|
|
|
++#define MATCH_VWMACCUVX 0xf0006057
|
|
|
++#define MASK_VWMACCUVX 0xfc00707f
|
|
|
++#define MATCH_VWMACCVV 0xf4002057
|
|
|
++#define MASK_VWMACCVV 0xfc00707f
|
|
|
++#define MATCH_VWMACCVX 0xf4006057
|
|
|
++#define MASK_VWMACCVX 0xfc00707f
|
|
|
++#define MATCH_VWMACCSUVV 0xfc002057
|
|
|
++#define MASK_VWMACCSUVV 0xfc00707f
|
|
|
++#define MATCH_VWMACCSUVX 0xfc006057
|
|
|
++#define MASK_VWMACCSUVX 0xfc00707f
|
|
|
++#define MATCH_VWMACCUSVX 0xf8006057
|
|
|
++#define MASK_VWMACCUSVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VQMACCUVV 0xf0000057
|
|
|
++#define MASK_VQMACCUVV 0xfc00707f
|
|
|
++#define MATCH_VQMACCUVX 0xf0004057
|
|
|
++#define MASK_VQMACCUVX 0xfc00707f
|
|
|
++#define MATCH_VQMACCVV 0xf4000057
|
|
|
++#define MASK_VQMACCVV 0xfc00707f
|
|
|
++#define MATCH_VQMACCVX 0xf4004057
|
|
|
++#define MASK_VQMACCVX 0xfc00707f
|
|
|
++#define MATCH_VQMACCSUVV 0xfc000057
|
|
|
++#define MASK_VQMACCSUVV 0xfc00707f
|
|
|
++#define MATCH_VQMACCSUVX 0xfc004057
|
|
|
++#define MASK_VQMACCSUVX 0xfc00707f
|
|
|
++#define MATCH_VQMACCUSVX 0xf8004057
|
|
|
++#define MASK_VQMACCUSVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VDIVVV 0x84002057
|
|
|
++#define MASK_VDIVVV 0xfc00707f
|
|
|
++#define MATCH_VDIVVX 0x84006057
|
|
|
++#define MASK_VDIVVX 0xfc00707f
|
|
|
++#define MATCH_VDIVUVV 0x80002057
|
|
|
++#define MASK_VDIVUVV 0xfc00707f
|
|
|
++#define MATCH_VDIVUVX 0x80006057
|
|
|
++#define MASK_VDIVUVX 0xfc00707f
|
|
|
++#define MATCH_VREMVV 0x8c002057
|
|
|
++#define MASK_VREMVV 0xfc00707f
|
|
|
++#define MATCH_VREMVX 0x8c006057
|
|
|
++#define MASK_VREMVX 0xfc00707f
|
|
|
++#define MATCH_VREMUVV 0x88002057
|
|
|
++#define MASK_VREMUVV 0xfc00707f
|
|
|
++#define MATCH_VREMUVX 0x88006057
|
|
|
++#define MASK_VREMUVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMERGEVVM 0x5c000057
|
|
|
++#define MASK_VMERGEVVM 0xfe00707f
|
|
|
++#define MATCH_VMERGEVXM 0x5c004057
|
|
|
++#define MASK_VMERGEVXM 0xfe00707f
|
|
|
++#define MATCH_VMERGEVIM 0x5c003057
|
|
|
++#define MASK_VMERGEVIM 0xfe00707f
|
|
|
++
|
|
|
++#define MATCH_VMVVV 0x5e000057
|
|
|
++#define MASK_VMVVV 0xfff0707f
|
|
|
++#define MATCH_VMVVX 0x5e004057
|
|
|
++#define MASK_VMVVX 0xfff0707f
|
|
|
++#define MATCH_VMVVI 0x5e003057
|
|
|
++#define MASK_VMVVI 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VSADDUVV 0x80000057
|
|
|
++#define MASK_VSADDUVV 0xfc00707f
|
|
|
++#define MATCH_VSADDUVX 0x80004057
|
|
|
++#define MASK_VSADDUVX 0xfc00707f
|
|
|
++#define MATCH_VSADDUVI 0x80003057
|
|
|
++#define MASK_VSADDUVI 0xfc00707f
|
|
|
++#define MATCH_VSADDVV 0x84000057
|
|
|
++#define MASK_VSADDVV 0xfc00707f
|
|
|
++#define MATCH_VSADDVX 0x84004057
|
|
|
++#define MASK_VSADDVX 0xfc00707f
|
|
|
++#define MATCH_VSADDVI 0x84003057
|
|
|
++#define MASK_VSADDVI 0xfc00707f
|
|
|
++#define MATCH_VSSUBUVV 0x88000057
|
|
|
++#define MASK_VSSUBUVV 0xfc00707f
|
|
|
++#define MATCH_VSSUBUVX 0x88004057
|
|
|
++#define MASK_VSSUBUVX 0xfc00707f
|
|
|
++#define MATCH_VSSUBVV 0x8c000057
|
|
|
++#define MASK_VSSUBVV 0xfc00707f
|
|
|
++#define MATCH_VSSUBVX 0x8c004057
|
|
|
++#define MASK_VSSUBVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VAADDUVV 0x20002057
|
|
|
++#define MASK_VAADDUVV 0xfc00707f
|
|
|
++#define MATCH_VAADDUVX 0x20006057
|
|
|
++#define MASK_VAADDUVX 0xfc00707f
|
|
|
++#define MATCH_VAADDVV 0x24002057
|
|
|
++#define MASK_VAADDVV 0xfc00707f
|
|
|
++#define MATCH_VAADDVX 0x24006057
|
|
|
++#define MASK_VAADDVX 0xfc00707f
|
|
|
++#define MATCH_VASUBUVV 0x28002057
|
|
|
++#define MASK_VASUBUVV 0xfc00707f
|
|
|
++#define MATCH_VASUBUVX 0x28006057
|
|
|
++#define MASK_VASUBUVX 0xfc00707f
|
|
|
++#define MATCH_VASUBVV 0x2c002057
|
|
|
++#define MASK_VASUBVV 0xfc00707f
|
|
|
++#define MATCH_VASUBVX 0x2c006057
|
|
|
++#define MASK_VASUBVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSMULVV 0x9c000057
|
|
|
++#define MASK_VSMULVV 0xfc00707f
|
|
|
++#define MATCH_VSMULVX 0x9c004057
|
|
|
++#define MASK_VSMULVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSSRLVV 0xa8000057
|
|
|
++#define MASK_VSSRLVV 0xfc00707f
|
|
|
++#define MATCH_VSSRLVX 0xa8004057
|
|
|
++#define MASK_VSSRLVX 0xfc00707f
|
|
|
++#define MATCH_VSSRLVI 0xa8003057
|
|
|
++#define MASK_VSSRLVI 0xfc00707f
|
|
|
++#define MATCH_VSSRAVV 0xac000057
|
|
|
++#define MASK_VSSRAVV 0xfc00707f
|
|
|
++#define MATCH_VSSRAVX 0xac004057
|
|
|
++#define MASK_VSSRAVX 0xfc00707f
|
|
|
++#define MATCH_VSSRAVI 0xac003057
|
|
|
++#define MASK_VSSRAVI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VNCLIPUWV 0xb8000057
|
|
|
++#define MASK_VNCLIPUWV 0xfc00707f
|
|
|
++#define MATCH_VNCLIPUWX 0xb8004057
|
|
|
++#define MASK_VNCLIPUWX 0xfc00707f
|
|
|
++#define MATCH_VNCLIPUWI 0xb8003057
|
|
|
++#define MASK_VNCLIPUWI 0xfc00707f
|
|
|
++#define MATCH_VNCLIPWV 0xbc000057
|
|
|
++#define MASK_VNCLIPWV 0xfc00707f
|
|
|
++#define MATCH_VNCLIPWX 0xbc004057
|
|
|
++#define MASK_VNCLIPWX 0xfc00707f
|
|
|
++#define MATCH_VNCLIPWI 0xbc003057
|
|
|
++#define MASK_VNCLIPWI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFADDVV 0x00001057
|
|
|
++#define MASK_VFADDVV 0xfc00707f
|
|
|
++#define MATCH_VFADDVF 0x00005057
|
|
|
++#define MASK_VFADDVF 0xfc00707f
|
|
|
++#define MATCH_VFSUBVV 0x08001057
|
|
|
++#define MASK_VFSUBVV 0xfc00707f
|
|
|
++#define MATCH_VFSUBVF 0x08005057
|
|
|
++#define MASK_VFSUBVF 0xfc00707f
|
|
|
++#define MATCH_VFRSUBVF 0x9c005057
|
|
|
++#define MASK_VFRSUBVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFWADDVV 0xc0001057
|
|
|
++#define MASK_VFWADDVV 0xfc00707f
|
|
|
++#define MATCH_VFWADDVF 0xc0005057
|
|
|
++#define MASK_VFWADDVF 0xfc00707f
|
|
|
++#define MATCH_VFWSUBVV 0xc8001057
|
|
|
++#define MASK_VFWSUBVV 0xfc00707f
|
|
|
++#define MATCH_VFWSUBVF 0xc8005057
|
|
|
++#define MASK_VFWSUBVF 0xfc00707f
|
|
|
++#define MATCH_VFWADDWV 0xd0001057
|
|
|
++#define MASK_VFWADDWV 0xfc00707f
|
|
|
++#define MATCH_VFWADDWF 0xd0005057
|
|
|
++#define MASK_VFWADDWF 0xfc00707f
|
|
|
++#define MATCH_VFWSUBWV 0xd8001057
|
|
|
++#define MASK_VFWSUBWV 0xfc00707f
|
|
|
++#define MATCH_VFWSUBWF 0xd8005057
|
|
|
++#define MASK_VFWSUBWF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFMULVV 0x90001057
|
|
|
++#define MASK_VFMULVV 0xfc00707f
|
|
|
++#define MATCH_VFMULVF 0x90005057
|
|
|
++#define MASK_VFMULVF 0xfc00707f
|
|
|
++#define MATCH_VFDIVVV 0x80001057
|
|
|
++#define MASK_VFDIVVV 0xfc00707f
|
|
|
++#define MATCH_VFDIVVF 0x80005057
|
|
|
++#define MASK_VFDIVVF 0xfc00707f
|
|
|
++#define MATCH_VFRDIVVF 0x84005057
|
|
|
++#define MASK_VFRDIVVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFWMULVV 0xe0001057
|
|
|
++#define MASK_VFWMULVV 0xfc00707f
|
|
|
++#define MATCH_VFWMULVF 0xe0005057
|
|
|
++#define MASK_VFWMULVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFMADDVV 0xa0001057
|
|
|
++#define MASK_VFMADDVV 0xfc00707f
|
|
|
++#define MATCH_VFMADDVF 0xa0005057
|
|
|
++#define MASK_VFMADDVF 0xfc00707f
|
|
|
++#define MATCH_VFNMADDVV 0xa4001057
|
|
|
++#define MASK_VFNMADDVV 0xfc00707f
|
|
|
++#define MATCH_VFNMADDVF 0xa4005057
|
|
|
++#define MASK_VFNMADDVF 0xfc00707f
|
|
|
++#define MATCH_VFMSUBVV 0xa8001057
|
|
|
++#define MASK_VFMSUBVV 0xfc00707f
|
|
|
++#define MATCH_VFMSUBVF 0xa8005057
|
|
|
++#define MASK_VFMSUBVF 0xfc00707f
|
|
|
++#define MATCH_VFNMSUBVV 0xac001057
|
|
|
++#define MASK_VFNMSUBVV 0xfc00707f
|
|
|
++#define MATCH_VFNMSUBVF 0xac005057
|
|
|
++#define MASK_VFNMSUBVF 0xfc00707f
|
|
|
++#define MATCH_VFMACCVV 0xb0001057
|
|
|
++#define MASK_VFMACCVV 0xfc00707f
|
|
|
++#define MATCH_VFMACCVF 0xb0005057
|
|
|
++#define MASK_VFMACCVF 0xfc00707f
|
|
|
++#define MATCH_VFNMACCVV 0xb4001057
|
|
|
++#define MASK_VFNMACCVV 0xfc00707f
|
|
|
++#define MATCH_VFNMACCVF 0xb4005057
|
|
|
++#define MASK_VFNMACCVF 0xfc00707f
|
|
|
++#define MATCH_VFMSACVV 0xb8001057
|
|
|
++#define MASK_VFMSACVV 0xfc00707f
|
|
|
++#define MATCH_VFMSACVF 0xb8005057
|
|
|
++#define MASK_VFMSACVF 0xfc00707f
|
|
|
++#define MATCH_VFNMSACVV 0xbc001057
|
|
|
++#define MASK_VFNMSACVV 0xfc00707f
|
|
|
++#define MATCH_VFNMSACVF 0xbc005057
|
|
|
++#define MASK_VFNMSACVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFWMACCVV 0xf0001057
|
|
|
++#define MASK_VFWMACCVV 0xfc00707f
|
|
|
++#define MATCH_VFWMACCVF 0xf0005057
|
|
|
++#define MASK_VFWMACCVF 0xfc00707f
|
|
|
++#define MATCH_VFWNMACCVV 0xf4001057
|
|
|
++#define MASK_VFWNMACCVV 0xfc00707f
|
|
|
++#define MATCH_VFWNMACCVF 0xf4005057
|
|
|
++#define MASK_VFWNMACCVF 0xfc00707f
|
|
|
++#define MATCH_VFWMSACVV 0xf8001057
|
|
|
++#define MASK_VFWMSACVV 0xfc00707f
|
|
|
++#define MATCH_VFWMSACVF 0xf8005057
|
|
|
++#define MASK_VFWMSACVF 0xfc00707f
|
|
|
++#define MATCH_VFWNMSACVV 0xfc001057
|
|
|
++#define MASK_VFWNMSACVV 0xfc00707f
|
|
|
++#define MATCH_VFWNMSACVF 0xfc005057
|
|
|
++#define MASK_VFWNMSACVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFSQRTV 0x4c001057
|
|
|
++#define MASK_VFSQRTV 0xfc0ff07f
|
|
|
++#define MATCH_VFRSQRT7V 0x4c021057
|
|
|
++#define MASK_VFRSQRT7V 0xfc0ff07f
|
|
|
++#define MATCH_VFREC7V 0x4c029057
|
|
|
++#define MASK_VFREC7V 0xfc0ff07f
|
|
|
++#define MATCH_VFCLASSV 0x4c081057
|
|
|
++#define MASK_VFCLASSV 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VFMINVV 0x10001057
|
|
|
++#define MASK_VFMINVV 0xfc00707f
|
|
|
++#define MATCH_VFMINVF 0x10005057
|
|
|
++#define MASK_VFMINVF 0xfc00707f
|
|
|
++#define MATCH_VFMAXVV 0x18001057
|
|
|
++#define MASK_VFMAXVV 0xfc00707f
|
|
|
++#define MATCH_VFMAXVF 0x18005057
|
|
|
++#define MASK_VFMAXVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFSGNJVV 0x20001057
|
|
|
++#define MASK_VFSGNJVV 0xfc00707f
|
|
|
++#define MATCH_VFSGNJVF 0x20005057
|
|
|
++#define MASK_VFSGNJVF 0xfc00707f
|
|
|
++#define MATCH_VFSGNJNVV 0x24001057
|
|
|
++#define MASK_VFSGNJNVV 0xfc00707f
|
|
|
++#define MATCH_VFSGNJNVF 0x24005057
|
|
|
++#define MASK_VFSGNJNVF 0xfc00707f
|
|
|
++#define MATCH_VFSGNJXVV 0x28001057
|
|
|
++#define MASK_VFSGNJXVV 0xfc00707f
|
|
|
++#define MATCH_VFSGNJXVF 0x28005057
|
|
|
++#define MASK_VFSGNJXVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMFEQVV 0x60001057
|
|
|
++#define MASK_VMFEQVV 0xfc00707f
|
|
|
++#define MATCH_VMFEQVF 0x60005057
|
|
|
++#define MASK_VMFEQVF 0xfc00707f
|
|
|
++#define MATCH_VMFNEVV 0x70001057
|
|
|
++#define MASK_VMFNEVV 0xfc00707f
|
|
|
++#define MATCH_VMFNEVF 0x70005057
|
|
|
++#define MASK_VMFNEVF 0xfc00707f
|
|
|
++#define MATCH_VMFLTVV 0x6c001057
|
|
|
++#define MASK_VMFLTVV 0xfc00707f
|
|
|
++#define MATCH_VMFLTVF 0x6c005057
|
|
|
++#define MASK_VMFLTVF 0xfc00707f
|
|
|
++#define MATCH_VMFLEVV 0x64001057
|
|
|
++#define MASK_VMFLEVV 0xfc00707f
|
|
|
++#define MATCH_VMFLEVF 0x64005057
|
|
|
++#define MASK_VMFLEVF 0xfc00707f
|
|
|
++#define MATCH_VMFGTVF 0x74005057
|
|
|
++#define MASK_VMFGTVF 0xfc00707f
|
|
|
++#define MATCH_VMFGEVF 0x7c005057
|
|
|
++#define MASK_VMFGEVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFMERGEVFM 0x5c005057
|
|
|
++#define MASK_VFMERGEVFM 0xfe00707f
|
|
|
++#define MATCH_VFMVVF 0x5e005057
|
|
|
++#define MASK_VFMVVF 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VFCVTXUFV 0x48001057
|
|
|
++#define MASK_VFCVTXUFV 0xfc0ff07f
|
|
|
++#define MATCH_VFCVTXFV 0x48009057
|
|
|
++#define MASK_VFCVTXFV 0xfc0ff07f
|
|
|
++#define MATCH_VFCVTFXUV 0x48011057
|
|
|
++#define MASK_VFCVTFXUV 0xfc0ff07f
|
|
|
++#define MATCH_VFCVTFXV 0x48019057
|
|
|
++#define MASK_VFCVTFXV 0xfc0ff07f
|
|
|
++#define MATCH_VFCVTRTZXUFV 0x48031057
|
|
|
++#define MASK_VFCVTRTZXUFV 0xfc0ff07f
|
|
|
++#define MATCH_VFCVTRTZXFV 0x48039057
|
|
|
++#define MASK_VFCVTRTZXFV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTXUFV 0x48041057
|
|
|
++#define MASK_VFWCVTXUFV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTXFV 0x48049057
|
|
|
++#define MASK_VFWCVTXFV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTFXUV 0x48051057
|
|
|
++#define MASK_VFWCVTFXUV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTFXV 0x48059057
|
|
|
++#define MASK_VFWCVTFXV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTFFV 0x48061057
|
|
|
++#define MASK_VFWCVTFFV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTRTZXUFV 0x48071057
|
|
|
++#define MASK_VFWCVTRTZXUFV 0xfc0ff07f
|
|
|
++#define MATCH_VFWCVTRTZXFV 0x48079057
|
|
|
++#define MASK_VFWCVTRTZXFV 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTXUFW 0x48081057
|
|
|
++#define MASK_VFNCVTXUFW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTXFW 0x48089057
|
|
|
++#define MASK_VFNCVTXFW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTFXUW 0x48091057
|
|
|
++#define MASK_VFNCVTFXUW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTFXW 0x48099057
|
|
|
++#define MASK_VFNCVTFXW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTFFW 0x480a1057
|
|
|
++#define MASK_VFNCVTFFW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTRODFFW 0x480a9057
|
|
|
++#define MASK_VFNCVTRODFFW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTRTZXUFW 0x480b1057
|
|
|
++#define MASK_VFNCVTRTZXUFW 0xfc0ff07f
|
|
|
++#define MATCH_VFNCVTRTZXFW 0x480b9057
|
|
|
++#define MASK_VFNCVTRTZXFW 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VREDSUMVS 0x00002057
|
|
|
++#define MASK_VREDSUMVS 0xfc00707f
|
|
|
++#define MATCH_VREDMAXVS 0x1c002057
|
|
|
++#define MASK_VREDMAXVS 0xfc00707f
|
|
|
++#define MATCH_VREDMAXUVS 0x18002057
|
|
|
++#define MASK_VREDMAXUVS 0xfc00707f
|
|
|
++#define MATCH_VREDMINVS 0x14002057
|
|
|
++#define MASK_VREDMINVS 0xfc00707f
|
|
|
++#define MATCH_VREDMINUVS 0x10002057
|
|
|
++#define MASK_VREDMINUVS 0xfc00707f
|
|
|
++#define MATCH_VREDANDVS 0x04002057
|
|
|
++#define MASK_VREDANDVS 0xfc00707f
|
|
|
++#define MATCH_VREDORVS 0x08002057
|
|
|
++#define MASK_VREDORVS 0xfc00707f
|
|
|
++#define MATCH_VREDXORVS 0x0c002057
|
|
|
++#define MASK_VREDXORVS 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VWREDSUMUVS 0xc0000057
|
|
|
++#define MASK_VWREDSUMUVS 0xfc00707f
|
|
|
++#define MATCH_VWREDSUMVS 0xc4000057
|
|
|
++#define MASK_VWREDSUMVS 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFREDOSUMVS 0x0c001057
|
|
|
++#define MASK_VFREDOSUMVS 0xfc00707f
|
|
|
++#define MATCH_VFREDSUMVS 0x04001057
|
|
|
++#define MASK_VFREDSUMVS 0xfc00707f
|
|
|
++#define MATCH_VFREDMAXVS 0x1c001057
|
|
|
++#define MASK_VFREDMAXVS 0xfc00707f
|
|
|
++#define MATCH_VFREDMINVS 0x14001057
|
|
|
++#define MASK_VFREDMINVS 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFWREDOSUMVS 0xcc001057
|
|
|
++#define MASK_VFWREDOSUMVS 0xfc00707f
|
|
|
++#define MATCH_VFWREDSUMVS 0xc4001057
|
|
|
++#define MASK_VFWREDSUMVS 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VMANDMM 0x66002057
|
|
|
++#define MASK_VMANDMM 0xfe00707f
|
|
|
++#define MATCH_VMNANDMM 0x76002057
|
|
|
++#define MASK_VMNANDMM 0xfe00707f
|
|
|
++#define MATCH_VMANDNOTMM 0x62002057
|
|
|
++#define MASK_VMANDNOTMM 0xfe00707f
|
|
|
++#define MATCH_VMXORMM 0x6e002057
|
|
|
++#define MASK_VMXORMM 0xfe00707f
|
|
|
++#define MATCH_VMORMM 0x6a002057
|
|
|
++#define MASK_VMORMM 0xfe00707f
|
|
|
++#define MATCH_VMNORMM 0x7a002057
|
|
|
++#define MASK_VMNORMM 0xfe00707f
|
|
|
++#define MATCH_VMORNOTMM 0x72002057
|
|
|
++#define MASK_VMORNOTMM 0xfe00707f
|
|
|
++#define MATCH_VMXNORMM 0x7e002057
|
|
|
++#define MASK_VMXNORMM 0xfe00707f
|
|
|
++
|
|
|
++#define MATCH_VPOPCM 0x40082057
|
|
|
++#define MASK_VPOPCM 0xfc0ff07f
|
|
|
++#define MATCH_VFIRSTM 0x4008a057
|
|
|
++#define MASK_VFIRSTM 0xfc0ff07f
|
|
|
++
|
|
|
++#define MATCH_VMSBFM 0x5000a057
|
|
|
++#define MASK_VMSBFM 0xfc0ff07f
|
|
|
++#define MATCH_VMSIFM 0x5001a057
|
|
|
++#define MASK_VMSIFM 0xfc0ff07f
|
|
|
++#define MATCH_VMSOFM 0x50012057
|
|
|
++#define MASK_VMSOFM 0xfc0ff07f
|
|
|
++#define MATCH_VIOTAM 0x50082057
|
|
|
++#define MASK_VIOTAM 0xfc0ff07f
|
|
|
++#define MATCH_VIDV 0x5008a057
|
|
|
++#define MASK_VIDV 0xfdfff07f
|
|
|
++
|
|
|
++#define MATCH_VMVXS 0x42002057
|
|
|
++#define MASK_VMVXS 0xfe0ff07f
|
|
|
++#define MATCH_VMVSX 0x42006057
|
|
|
++#define MASK_VMVSX 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VFMVFS 0x42001057
|
|
|
++#define MASK_VFMVFS 0xfe0ff07f
|
|
|
++#define MATCH_VFMVSF 0x42005057
|
|
|
++#define MASK_VFMVSF 0xfff0707f
|
|
|
++
|
|
|
++#define MATCH_VSLIDEUPVX 0x38004057
|
|
|
++#define MASK_VSLIDEUPVX 0xfc00707f
|
|
|
++#define MATCH_VSLIDEUPVI 0x38003057
|
|
|
++#define MASK_VSLIDEUPVI 0xfc00707f
|
|
|
++#define MATCH_VSLIDEDOWNVX 0x3c004057
|
|
|
++#define MASK_VSLIDEDOWNVX 0xfc00707f
|
|
|
++#define MATCH_VSLIDEDOWNVI 0x3c003057
|
|
|
++#define MASK_VSLIDEDOWNVI 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VSLIDE1UPVX 0x38006057
|
|
|
++#define MASK_VSLIDE1UPVX 0xfc00707f
|
|
|
++#define MATCH_VSLIDE1DOWNVX 0x3c006057
|
|
|
++#define MASK_VSLIDE1DOWNVX 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VFSLIDE1UPVF 0x38005057
|
|
|
++#define MASK_VFSLIDE1UPVF 0xfc00707f
|
|
|
++#define MATCH_VFSLIDE1DOWNVF 0x3c005057
|
|
|
++#define MASK_VFSLIDE1DOWNVF 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VRGATHERVV 0x30000057
|
|
|
++#define MASK_VRGATHERVV 0xfc00707f
|
|
|
++#define MATCH_VRGATHERVX 0x30004057
|
|
|
++#define MASK_VRGATHERVX 0xfc00707f
|
|
|
++#define MATCH_VRGATHERVI 0x30003057
|
|
|
++#define MASK_VRGATHERVI 0xfc00707f
|
|
|
++#define MATCH_VRGATHEREI16VV 0x38000057
|
|
|
++#define MASK_VRGATHEREI16VV 0xfc00707f
|
|
|
++
|
|
|
++#define MATCH_VCOMPRESSVM 0x5e002057
|
|
|
++#define MASK_VCOMPRESSVM 0xfe00707f
|
|
|
++
|
|
|
++#define MATCH_VMV1RV 0x9e003057
|
|
|
++#define MASK_VMV1RV 0xfe0ff07f
|
|
|
++#define MATCH_VMV2RV 0x9e00b057
|
|
|
++#define MASK_VMV2RV 0xfe0ff07f
|
|
|
++#define MATCH_VMV4RV 0x9e01b057
|
|
|
++#define MASK_VMV4RV 0xfe0ff07f
|
|
|
++#define MATCH_VMV8RV 0x9e03b057
|
|
|
++#define MASK_VMV8RV 0xfe0ff07f
|
|
|
++
|
|
|
++#define MATCH_VDOTVV 0xe4000057
|
|
|
++#define MASK_VDOTVV 0xfc00707f
|
|
|
++#define MATCH_VDOTUVV 0xe0000057
|
|
|
++#define MASK_VDOTUVV 0xfc00707f
|
|
|
++#define MATCH_VFDOTVV 0xe4001057
|
|
|
++#define MASK_VFDOTVV 0xfc00707f
|
|
|
++/* END RVV */
|
|
|
++
|
|
|
++#define MATCH_CUSTOM0 0xb
|
|
|
++#define MASK_CUSTOM0 0x707f
|
|
|
++#define MATCH_CUSTOM0_RS1 0x200b
|
|
|
++#define MASK_CUSTOM0_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM0_RS1_RS2 0x300b
|
|
|
++#define MASK_CUSTOM0_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM0_RD 0x400b
|
|
|
++#define MASK_CUSTOM0_RD 0x707f
|
|
|
++#define MATCH_CUSTOM0_RD_RS1 0x600b
|
|
|
++#define MASK_CUSTOM0_RD_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
|
|
|
++#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM1 0x2b
|
|
|
++#define MASK_CUSTOM1 0x707f
|
|
|
++#define MATCH_CUSTOM1_RS1 0x202b
|
|
|
++#define MASK_CUSTOM1_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM1_RS1_RS2 0x302b
|
|
|
++#define MASK_CUSTOM1_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM1_RD 0x402b
|
|
|
++#define MASK_CUSTOM1_RD 0x707f
|
|
|
++#define MATCH_CUSTOM1_RD_RS1 0x602b
|
|
|
++#define MASK_CUSTOM1_RD_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
|
|
|
++#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM2 0x5b
|
|
|
++#define MASK_CUSTOM2 0x707f
|
|
|
++#define MATCH_CUSTOM2_RS1 0x205b
|
|
|
++#define MASK_CUSTOM2_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM2_RS1_RS2 0x305b
|
|
|
++#define MASK_CUSTOM2_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM2_RD 0x405b
|
|
|
++#define MASK_CUSTOM2_RD 0x707f
|
|
|
++#define MATCH_CUSTOM2_RD_RS1 0x605b
|
|
|
++#define MASK_CUSTOM2_RD_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
|
|
|
++#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM3 0x7b
|
|
|
++#define MASK_CUSTOM3 0x707f
|
|
|
++#define MATCH_CUSTOM3_RS1 0x207b
|
|
|
++#define MASK_CUSTOM3_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM3_RS1_RS2 0x307b
|
|
|
++#define MASK_CUSTOM3_RS1_RS2 0x707f
|
|
|
++#define MATCH_CUSTOM3_RD 0x407b
|
|
|
++#define MASK_CUSTOM3_RD 0x707f
|
|
|
++#define MATCH_CUSTOM3_RD_RS1 0x607b
|
|
|
++#define MASK_CUSTOM3_RD_RS1 0x707f
|
|
|
++#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
|
|
|
++#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
|
|
|
++/* Privileged CSR addresses (v1.11). */
|
|
|
+ #define CSR_USTATUS 0x0
|
|
|
+ #define CSR_UIE 0x4
|
|
|
+ #define CSR_UTVEC 0x5
|
|
|
+@@ -990,6 +2886,13 @@
|
|
|
+ #define CSR_FFLAGS 0x1
|
|
|
+ #define CSR_FRM 0x2
|
|
|
+ #define CSR_FCSR 0x3
|
|
|
++#define CSR_VSTART 0x008
|
|
|
++#define CSR_VXSAT 0x009
|
|
|
++#define CSR_VXRM 0x00a
|
|
|
++#define CSR_VCSR 0x00f
|
|
|
++#define CSR_VL 0xc20
|
|
|
++#define CSR_VTYPE 0xc21
|
|
|
++#define CSR_VLENB 0xc22
|
|
|
+ #define CSR_DCSR 0x7b0
|
|
|
+ #define CSR_DPC 0x7b1
|
|
|
+ #define CSR_DSCRATCH0 0x7b2
|
|
|
+@@ -1002,7 +2905,7 @@
|
|
|
+ #define CSR_TCONTROL 0x7a5
|
|
|
+ #define CSR_MCONTEXT 0x7a8
|
|
|
+ #define CSR_SCONTEXT 0x7aa
|
|
|
+-#endif /* RISCV_ENCODING_H */
|
|
|
++#endif /* RISCV_ENCODING_H. */
|
|
|
+ #ifdef DECLARE_INSN
|
|
|
+ DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
|
|
|
+ DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
|
|
|
+@@ -1606,6 +3509,13 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
|
|
|
+ DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
++DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+@@ -1632,4 +3542,4 @@ DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
|
|
|
+ DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+ DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
|
|
|
+-#endif /* DECLARE_CSR_ALIAS */
|
|
|
++#endif /* DECLARE_CSR_ALIAS */
|
|
|
+\ No newline at end of file
|
|
|
+diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
|
|
|
+index ae8c6bd33f..a785cb1490 100644
|
|
|
+--- a/include/opcode/riscv.h
|
|
|
++++ b/include/opcode/riscv.h
|
|
|
+@@ -52,6 +52,28 @@ static const char * const riscv_pred_succ[16] =
|
|
|
+ "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
|
|
|
+ };
|
|
|
+
|
|
|
++/* List of vsetvli vsew constants. */
|
|
|
++static const char * const riscv_vsew[8] =
|
|
|
++{
|
|
|
++ "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
|
|
|
++};
|
|
|
++
|
|
|
++/* List of vsetvli vlmul constants. */
|
|
|
++static const char * const riscv_vlmul[8] =
|
|
|
++{
|
|
|
++ "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
|
|
|
++};
|
|
|
++
|
|
|
++static const char * const riscv_vta[2] =
|
|
|
++{
|
|
|
++ "tu", "ta"
|
|
|
++};
|
|
|
++
|
|
|
++static const char * const riscv_vma[2] =
|
|
|
++{
|
|
|
++ "mu", "ma"
|
|
|
++};
|
|
|
++
|
|
|
+ #define RVC_JUMP_BITS 11
|
|
|
+ #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
|
|
|
+
|
|
|
+@@ -101,6 +123,16 @@ static const char * const riscv_pred_succ[16] =
|
|
|
+ ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
|
|
|
+ #define EXTRACT_CJTYPE_IMM(x) \
|
|
|
+ ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
|
|
|
++#define EXTRACT_RVV_VI_IMM(x) \
|
|
|
++ (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
|
|
|
++#define EXTRACT_RVV_VI_UIMM(x) \
|
|
|
++ (RV_X(x, 15, 5))
|
|
|
++#define EXTRACT_RVV_OFFSET(x) \
|
|
|
++ (RV_X(x, 29, 3))
|
|
|
++#define EXTRACT_RVV_VB_IMM(x) \
|
|
|
++ (RV_X(x, 20, 10))
|
|
|
++#define EXTRACT_RVV_VC_IMM(x) \
|
|
|
++ (RV_X(x, 20, 11))
|
|
|
+
|
|
|
+ #define ENCODE_ITYPE_IMM(x) \
|
|
|
+ (RV_X(x, 0, 12) << 20)
|
|
|
+@@ -142,6 +174,10 @@ static const char * const riscv_pred_succ[16] =
|
|
|
+ ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
|
|
|
+ #define ENCODE_CJTYPE_IMM(x) \
|
|
|
+ ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
|
|
|
++#define ENCODE_RVV_VB_IMM(x) \
|
|
|
++ (RV_X(x, 0, 10) << 20)
|
|
|
++#define ENCODE_RVV_VC_IMM(x) \
|
|
|
++ (RV_X(x, 0, 11) << 20)
|
|
|
+
|
|
|
+ #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
|
|
|
+ #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
|
|
|
+@@ -165,6 +201,8 @@ static const char * const riscv_pred_succ[16] =
|
|
|
+ #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
|
|
|
+ #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
|
|
|
+ #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
|
|
|
++#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
|
|
|
++#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
|
|
|
+
|
|
|
+ #define RISCV_RTYPE(insn, rd, rs1, rs2) \
|
|
|
+ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
|
|
|
+@@ -261,6 +299,35 @@ static const char * const riscv_pred_succ[16] =
|
|
|
+ #define OP_MASK_CFUNCT2 0x3
|
|
|
+ #define OP_SH_CFUNCT2 5
|
|
|
+
|
|
|
++/* RVV fields. */
|
|
|
++
|
|
|
++#define OP_MASK_VD 0x1f
|
|
|
++#define OP_SH_VD 7
|
|
|
++#define OP_MASK_VS1 0x1f
|
|
|
++#define OP_SH_VS1 15
|
|
|
++#define OP_MASK_VS2 0x1f
|
|
|
++#define OP_SH_VS2 20
|
|
|
++#define OP_MASK_VIMM 0x1f
|
|
|
++#define OP_SH_VIMM 15
|
|
|
++#define OP_MASK_VMASK 0x1
|
|
|
++#define OP_SH_VMASK 25
|
|
|
++#define OP_MASK_VFUNCT6 0x3f
|
|
|
++#define OP_SH_VFUNCT6 26
|
|
|
++
|
|
|
++#define OP_MASK_VLMUL 0x7
|
|
|
++#define OP_SH_VLMUL 0
|
|
|
++#define OP_MASK_VSEW 0x7
|
|
|
++#define OP_SH_VSEW 3
|
|
|
++#define OP_MASK_VTA 0x1
|
|
|
++#define OP_SH_VTA 6
|
|
|
++#define OP_MASK_VMA 0x1
|
|
|
++#define OP_SH_VMA 7
|
|
|
++#define OP_MASK_VTYPE_RES 0x1
|
|
|
++#define OP_SH_VTYPE_RES 10
|
|
|
++
|
|
|
++#define OP_MASK_VWD 0x1
|
|
|
++#define OP_SH_VWD 26
|
|
|
++
|
|
|
+ /* ABI names for selected x-registers. */
|
|
|
+
|
|
|
+ #define X_RA 1
|
|
|
+@@ -274,6 +341,8 @@ static const char * const riscv_pred_succ[16] =
|
|
|
+
|
|
|
+ #define NGPR 32
|
|
|
+ #define NFPR 32
|
|
|
++#define NVECR 32
|
|
|
++#define NVECM 1
|
|
|
+
|
|
|
+ /* These fake label defines are use by both the assembler, and
|
|
|
+ libopcodes. The assembler uses this when it needs to generate a fake
|
|
|
+@@ -331,6 +400,10 @@ enum riscv_insn_class
|
|
|
+ INSN_CLASS_ZBT,
|
|
|
+ INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
|
|
|
+ INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
|
|
|
++ INSN_CLASS_V,
|
|
|
++ INSN_CLASS_V_AND_F,
|
|
|
++ INSN_CLASS_V_OR_ZVAMO,
|
|
|
++ INSN_CLASS_V_OR_ZVLSSEG,
|
|
|
+ };
|
|
|
+
|
|
|
+ /* This structure holds information for a particular instruction. */
|
|
|
+@@ -371,6 +444,9 @@ struct riscv_opcode
|
|
|
+ unsigned long pinfo;
|
|
|
+ };
|
|
|
+
|
|
|
++
|
|
|
++#define RISCV_UNKNOWN_VERSION -1
|
|
|
++
|
|
|
+ /* Instruction is a simple alias (e.g. "mv" for "addi"). */
|
|
|
+ #define INSN_ALIAS 0x00000001
|
|
|
+
|
|
|
+@@ -434,6 +510,8 @@ enum
|
|
|
+ M_ZEXTW,
|
|
|
+ M_SEXTB,
|
|
|
+ M_SEXTH,
|
|
|
++ M_VMSGE,
|
|
|
++ M_VMSGEU,
|
|
|
+ M_NUM_MACROS
|
|
|
+ };
|
|
|
+
|
|
|
+@@ -442,8 +520,10 @@ extern const char * const riscv_gpr_names_numeric[NGPR];
|
|
|
+ extern const char * const riscv_gpr_names_abi[NGPR];
|
|
|
+ extern const char * const riscv_fpr_names_numeric[NFPR];
|
|
|
+ extern const char * const riscv_fpr_names_abi[NFPR];
|
|
|
++extern const char * const riscv_vecr_names_numeric[NVECR];
|
|
|
++extern const char * const riscv_vecm_names_numeric[NVECM];
|
|
|
+
|
|
|
+ extern const struct riscv_opcode riscv_opcodes[];
|
|
|
+ extern const struct riscv_opcode riscv_insn_types[];
|
|
|
+
|
|
|
+-#endif /* _RISCV_H_ */
|
|
|
++#endif /* _RISCV_H_ */
|
|
|
+\ No newline at end of file
|
|
|
+diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
|
|
|
+index fe8dfb88d9..a36756cb4c 100644
|
|
|
+--- a/opcodes/riscv-dis.c
|
|
|
++++ b/opcodes/riscv-dis.c
|
|
|
+@@ -43,15 +43,17 @@ struct riscv_private_data
|
|
|
+
|
|
|
+ static const char * const *riscv_gpr_names;
|
|
|
+ static const char * const *riscv_fpr_names;
|
|
|
++static const char * const *riscv_vecr_names;
|
|
|
+
|
|
|
+-/* If set, disassemble as most general instruction. */
|
|
|
+-static int no_aliases;
|
|
|
++/* Other options. */
|
|
|
++static int no_aliases; /* If set disassemble as most general inst. */
|
|
|
+
|
|
|
+ static void
|
|
|
+ set_default_riscv_dis_options (void)
|
|
|
+ {
|
|
|
+ riscv_gpr_names = riscv_gpr_names_abi;
|
|
|
+ riscv_fpr_names = riscv_fpr_names_abi;
|
|
|
++ riscv_vecr_names = riscv_vecr_names_numeric;
|
|
|
+ no_aliases = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+@@ -411,6 +413,88 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
|
|
|
+ print (info->stream, "%d", rs1);
|
|
|
+ break;
|
|
|
+
|
|
|
++ case 'V': /* RVV */
|
|
|
++ switch (*++d)
|
|
|
++ {
|
|
|
++ case 'd':
|
|
|
++ case 'f':
|
|
|
++ print (info->stream, "%s",
|
|
|
++ riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'e':
|
|
|
++ if (!EXTRACT_OPERAND (VWD, l))
|
|
|
++ print (info->stream, "%s", riscv_gpr_names[0]);
|
|
|
++ else
|
|
|
++ print (info->stream, "%s",
|
|
|
++ riscv_vecr_names[EXTRACT_OPERAND (VD, l)]);
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 's':
|
|
|
++ print (info->stream, "%s",
|
|
|
++ riscv_vecr_names[EXTRACT_OPERAND (VS1, l)]);
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 't':
|
|
|
++ case 'u': /* VS1 == VS2 already verified at this point. */
|
|
|
++ case 'v': /* VD == VS1 == VS2 already verified at this point. */
|
|
|
++ print (info->stream, "%s",
|
|
|
++ riscv_vecr_names[EXTRACT_OPERAND (VS2, l)]);
|
|
|
++ break;
|
|
|
++
|
|
|
++ case '0':
|
|
|
++ print (info->stream, "%s", riscv_vecr_names[0]);
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'b':
|
|
|
++ case 'c':
|
|
|
++ {
|
|
|
++ int imm = (*d == 'b') ? EXTRACT_RVV_VB_IMM (l)
|
|
|
++ : EXTRACT_RVV_VC_IMM (l);
|
|
|
++ unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
|
|
|
++ unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
|
|
|
++ unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
|
|
|
++ unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
|
|
|
++ unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
|
|
|
++
|
|
|
++ if (imm_vsew < ARRAY_SIZE (riscv_vsew)
|
|
|
++ && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
|
|
|
++ && imm_vta < ARRAY_SIZE (riscv_vta)
|
|
|
++ && imm_vma < ARRAY_SIZE (riscv_vma)
|
|
|
++ && ! imm_vtype_res)
|
|
|
++ print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew],
|
|
|
++ riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
|
|
|
++ riscv_vma[imm_vma]);
|
|
|
++ else
|
|
|
++ print (info->stream, "%d", imm);
|
|
|
++ }
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'i':
|
|
|
++ print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'j':
|
|
|
++ print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'k':
|
|
|
++ print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
|
|
|
++ break;
|
|
|
++
|
|
|
++ case 'm':
|
|
|
++ if (! EXTRACT_OPERAND (VMASK, l))
|
|
|
++ print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
|
|
|
++ break;
|
|
|
++
|
|
|
++ default:
|
|
|
++ /* xgettext:c-format */
|
|
|
++ print (info->stream, _("# internal error, undefined modifier (V%c)"),
|
|
|
++ *d);
|
|
|
++ return;
|
|
|
++ }
|
|
|
++ break;
|
|
|
++
|
|
|
+ default:
|
|
|
+ /* xgettext:c-format */
|
|
|
+ print (info->stream, _("# internal error, undefined modifier (%c)"),
|
|
|
+@@ -653,4 +737,4 @@ with the -M switch (multiple options should be separated by commas):\n"));
|
|
|
+ (1.9, 1.9.1, 1.10, 1.11).\n"));
|
|
|
+
|
|
|
+ fprintf (stream, _("\n"));
|
|
|
+-}
|
|
|
++}
|
|
|
+\ No newline at end of file
|
|
|
+diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
|
|
|
+index 3d9240262c..745c7a990b 100644
|
|
|
+--- a/opcodes/riscv-opc.c
|
|
|
++++ b/opcodes/riscv-opc.c
|
|
|
+@@ -182,6 +182,20 @@ const char * const riscv_fpr_names_abi[NFPR] =
|
|
|
+ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
|
|
|
+ };
|
|
|
+
|
|
|
++const char * const riscv_vecr_names_numeric[NVECR] =
|
|
|
++{
|
|
|
++ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
|
|
|
++ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
|
|
|
++ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
|
|
|
++ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
|
|
|
++};
|
|
|
++
|
|
|
++const char * const riscv_vecm_names_numeric[NVECM] =
|
|
|
++{
|
|
|
++ "v0.t"
|
|
|
++};
|
|
|
++
|
|
|
++
|
|
|
+ /* The order of overloaded instructions matters. Label arguments and
|
|
|
+ register arguments look the same. Instructions that can have either
|
|
|
+ for arguments must apear in the correct order in this table for the
|
|
|
+@@ -209,6 +223,11 @@ const char * const riscv_fpr_names_abi[NFPR] =
|
|
|
+ #define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
|
|
|
+ #define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
|
|
|
+ #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
|
|
|
++#define MASK_VD (OP_MASK_VD << OP_SH_VD)
|
|
|
++#define MASK_VS1 (OP_MASK_VS1 << OP_SH_VS1)
|
|
|
++#define MASK_VS2 (OP_MASK_VS2 << OP_SH_VS2)
|
|
|
++#define MASK_VMASK (OP_MASK_VMASK << OP_SH_VMASK)
|
|
|
++
|
|
|
+
|
|
|
+ static int
|
|
|
+ match_opcode (const struct riscv_opcode *op, insn_t insn)
|
|
|
+@@ -231,6 +250,47 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
|
|
|
+ return match_opcode (op, insn) && rs1 == rs2;
|
|
|
+ }
|
|
|
+
|
|
|
++static int
|
|
|
++match_vs1_eq_vs2 (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++
|
|
|
++ return match_opcode (op, insn) && vs1 == vs2;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vs1_eq_vs2_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn) && vs1 == vs2;
|
|
|
++
|
|
|
++ if (!vm && vm == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn) && vs1 == vs2;
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++
|
|
|
++ return match_opcode (op, insn) && vd == vs1 && vs1 == vs2;
|
|
|
++}
|
|
|
++
|
|
|
++
|
|
|
+ static int
|
|
|
+ match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
|
|
|
+ {
|
|
|
+@@ -324,6 +384,249 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
|
|
|
+ return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0;
|
|
|
+ }
|
|
|
+
|
|
|
++
|
|
|
++/* These are used to check the vector constraints. */
|
|
|
++
|
|
|
++static int
|
|
|
++match_widen_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vd % 2) != 0)
|
|
|
++ return 0;
|
|
|
++ //*error = "illegal operands vd must be multiple of 2";
|
|
|
++ else if (vs1 >= vd && vs1 <= (vd + 1))
|
|
|
++ return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs1";
|
|
|
++ else if (vs2 >= vd && vs2 <= (vd + 1))
|
|
|
++ return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs2";
|
|
|
++ else if (!vm && vm >= vd && vm <= (vd + 1))
|
|
|
++ return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_widen_vd_neq_vs1_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vd % 2) != 0) return 0;
|
|
|
++ //*error = "illegal operands vd must be multiple of 2";
|
|
|
++ else if ((vs2 % 2) != 0) return 0;
|
|
|
++ //*error = "illegal operands vs2 must be multiple of 2";
|
|
|
++ else if (vs1 >= vd && vs1 <= (vd + 1)) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs1";
|
|
|
++ else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_widen_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vd % 2) != 0) return 0;
|
|
|
++ //*error = "illegal operands vd must be multiple of 2";
|
|
|
++ else if (vs2 >= vd && vs2 <= (vd + 1)) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs2";
|
|
|
++ else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_widen_vd_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vd % 2) != 0) return 0;
|
|
|
++ // *error = "illegal operands vd must be multiple of 2";
|
|
|
++ else if ((vs2 % 2) != 0) return 0;
|
|
|
++ // *error = "illegal operands vs2 must be multiple of 2";
|
|
|
++ else if (!vm && vm >= vd && vm <= (vd + 1)) return 0;
|
|
|
++ // *error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_narrow_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vs2 % 2) != 0) return 0;
|
|
|
++ //*error = "illegal operands vd must be multiple of 2";
|
|
|
++ else if (vd >= vs2 && vd <= (vs2 + 1)) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs2";
|
|
|
++ else if (!vm && vd >= vm && vd <= (vm + 1)) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vd_neq_vs1_neq_vs2 (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if (vs1 == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs1";
|
|
|
++ else if (vs2 == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs2";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vd_neq_vs1_neq_vs2_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs1 = (insn & MASK_VS1) >> OP_SH_VS1;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ if (vs1 == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs1";
|
|
|
++ else if (vs2 == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs2";
|
|
|
++ else if (!vm && vm == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vd_neq_vs2_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if (vs2 == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vs2";
|
|
|
++ else if (!vm && vm == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++/* v[m]adc and v[m]sbc use the vm encoding to encode the
|
|
|
++ carry-in v0 register. The carry-in v0 register can not
|
|
|
++ overlap with the vd, too. Therefore, we use the same
|
|
|
++ match_vd_neq_vm to check the overlap constraints. */
|
|
|
++
|
|
|
++static int
|
|
|
++match_vd_neq_vm (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vm = (insn & MASK_VMASK) >> OP_SH_VMASK;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if (!vm && vm == vd) return 0;
|
|
|
++ //*error = "illegal operands vd cannot overlap vm";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vls_nf_rv (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int nf = ((insn & (0x7 << 29) ) >> 29) + 1;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vd % nf) != 0) return 0;
|
|
|
++ //*error = "illegal operands vd must be multiple of nf";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int
|
|
|
++match_vmv_nf_rv (const struct riscv_opcode *op,
|
|
|
++ insn_t insn)
|
|
|
++{
|
|
|
++ int vd = (insn & MASK_VD) >> OP_SH_VD;
|
|
|
++ int vs2 = (insn & MASK_VS2) >> OP_SH_VS2;
|
|
|
++ int nf = ((insn & (0x7 << 15) ) >> 15) + 1;
|
|
|
++
|
|
|
++ //if (!constraints || error == NULL)
|
|
|
++ // return match_opcode (op, insn);
|
|
|
++
|
|
|
++ if ((vd % nf) != 0) return 0;
|
|
|
++ //*error = "illegal operands vd must be multiple of nf";
|
|
|
++ else if ((vs2 % nf) != 0) return 0;
|
|
|
++ //*error = "illegal operands vs2 must be multiple of nf";
|
|
|
++ else
|
|
|
++ return match_opcode (op, insn);
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++
|
|
|
+ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {
|
|
|
+ /* name, xlen, isa, operands, match, mask, match_func, pinfo. */
|
|
|
+@@ -1144,6 +1447,806 @@ const struct riscv_opcode riscv_opcodes[] =
|
|
|
+ {"fsrw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
|
|
|
+ {"fsriw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
|
|
|
+
|
|
|
++/* RVV */
|
|
|
++{"vsetvl", 0, INSN_CLASS_V, "d,s,t", MATCH_VSETVL, MASK_VSETVL, match_opcode, 0},
|
|
|
++{"vsetvli", 0, INSN_CLASS_V, "d,s,Vc", MATCH_VSETVLI, MASK_VSETVLI, match_opcode, 0},
|
|
|
++{"vsetivli", 0, INSN_CLASS_V, "d,Z,Vb", MATCH_VSETIVLI, MASK_VSETIVLI, match_opcode, 0},
|
|
|
++
|
|
|
++{"vle1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VLE1V, MASK_VLE1V, match_opcode, INSN_DREF },
|
|
|
++{"vse1.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VSE1V, MASK_VSE1V, match_opcode, INSN_DREF },
|
|
|
++
|
|
|
++{"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vloxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vloxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vloxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vsoxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsoxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlsseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg2e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg3e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg4e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg5e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg6e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E8V, MASK_VLSSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg7e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg8e8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlsseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg2e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg3e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg4e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg5e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg6e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg7e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg8e16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlsseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg2e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg3e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg4e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg5e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg6e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg7e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg8e32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlsseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg2e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg3e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg4e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg5e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg6e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg7e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlsseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vssseg8e64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vloxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vloxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vloxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vloxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vloxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsoxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vluxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg2ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI8V, MASK_VLUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg3ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI8V, MASK_VSUXSEG3EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI8V, MASK_VLUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg4ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI8V, MASK_VSUXSEG4EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI8V, MASK_VLUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg5ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI8V, MASK_VSUXSEG5EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI8V, MASK_VLUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg6ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI8V, MASK_VSUXSEG6EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI8V, MASK_VLUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg7ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI8V, MASK_VSUXSEG7EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI8V, MASK_VLUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg8ei8.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI8V, MASK_VSUXSEG8EI8V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vluxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI16V, MASK_VLUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg2ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI16V, MASK_VSUXSEG2EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI16V, MASK_VLUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg3ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI16V, MASK_VSUXSEG3EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI16V, MASK_VLUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg4ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI16V, MASK_VSUXSEG4EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI16V, MASK_VLUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg5ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI16V, MASK_VSUXSEG5EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI16V, MASK_VLUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg6ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI16V, MASK_VSUXSEG6EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI16V, MASK_VLUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg7ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI16V, MASK_VSUXSEG7EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI16V, MASK_VLUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg8ei16.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI16V, MASK_VSUXSEG8EI16V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vluxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI32V, MASK_VLUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg2ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI32V, MASK_VSUXSEG2EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI32V, MASK_VLUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg3ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI32V, MASK_VSUXSEG3EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI32V, MASK_VLUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg4ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI32V, MASK_VSUXSEG4EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI32V, MASK_VLUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg5ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI32V, MASK_VSUXSEG5EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI32V, MASK_VLUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg6ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI32V, MASK_VSUXSEG6EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI32V, MASK_VLUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg7ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI32V, MASK_VSUXSEG7EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg8ei32.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vluxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg2ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg3ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg4ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg5ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg6ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg7ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vluxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++{"vsuxseg8ei64.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_vd_neq_vs2_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e8ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e16ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e32ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vlseg2e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg3e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg4e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg5e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg6e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg7e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++{"vlseg8e64ff.v", 0, INSN_CLASS_V_OR_ZVLSSEG, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_vd_neq_vm, INSN_DREF },
|
|
|
++
|
|
|
++{"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
++{"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
++
|
|
|
++{"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
++{"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
++
|
|
|
++{"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
++{"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
++
|
|
|
++{"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF|INSN_ALIAS },
|
|
|
++{"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_vls_nf_rv, INSN_DREF },
|
|
|
++
|
|
|
++{"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vs4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS4RV, MASK_VS4RV, match_vls_nf_rv, INSN_DREF },
|
|
|
++{"vs8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS8RV, MASK_VS8RV, match_vls_nf_rv, INSN_DREF },
|
|
|
++
|
|
|
++{"vamoaddei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI8V, MASK_VAMOADDEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoswapei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI8V, MASK_VAMOSWAPEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoxorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI8V, MASK_VAMOXOREI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoandei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI8V, MASK_VAMOANDEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoorei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI8V, MASK_VAMOOREI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI8V, MASK_VAMOMINEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI8V, MASK_VAMOMAXEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI8V, MASK_VAMOMINUEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxuei8.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI8V, MASK_VAMOMAXUEI8V, match_vd_neq_vm, INSN_DREF},
|
|
|
++
|
|
|
++{"vamoaddei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI16V, MASK_VAMOADDEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoswapei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI16V, MASK_VAMOSWAPEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoxorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI16V, MASK_VAMOXOREI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoandei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI16V, MASK_VAMOANDEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoorei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI16V, MASK_VAMOOREI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI16V, MASK_VAMOMINEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI16V, MASK_VAMOMAXEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI16V, MASK_VAMOMINUEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxuei16.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI16V, MASK_VAMOMAXUEI16V, match_vd_neq_vm, INSN_DREF},
|
|
|
++
|
|
|
++{"vamoaddei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI32V, MASK_VAMOADDEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoswapei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI32V, MASK_VAMOSWAPEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoxorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI32V, MASK_VAMOXOREI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoandei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI32V, MASK_VAMOANDEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoorei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI32V, MASK_VAMOOREI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI32V, MASK_VAMOMINEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI32V, MASK_VAMOMAXEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI32V, MASK_VAMOMINUEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxuei32.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI32V, MASK_VAMOMAXUEI32V, match_vd_neq_vm, INSN_DREF},
|
|
|
++
|
|
|
++{"vamoaddei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOADDEI64V, MASK_VAMOADDEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoswapei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOSWAPEI64V, MASK_VAMOSWAPEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoxorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOXOREI64V, MASK_VAMOXOREI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoandei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOANDEI64V, MASK_VAMOANDEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamoorei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOOREI64V, MASK_VAMOOREI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINEI64V, MASK_VAMOMINEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXEI64V, MASK_VAMOMAXEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamominuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMINUEI64V, MASK_VAMOMINUEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++{"vamomaxuei64.v", 0, INSN_CLASS_V_OR_ZVAMO, "Ve,0(s),Vt,VfVm", MATCH_VAMOMAXUEI64V, MASK_VAMOMAXUEI64V, match_vd_neq_vm, INSN_DREF},
|
|
|
++
|
|
|
++{"vneg.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VRSUBVX, MASK_VRSUBVX | MASK_RS1, match_vd_neq_vm, INSN_ALIAS },
|
|
|
++
|
|
|
++{"vadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VADDVV, MASK_VADDVV, match_vd_neq_vm, 0 },
|
|
|
++{"vadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VADDVX, MASK_VADDVX, match_vd_neq_vm, 0 },
|
|
|
++{"vadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VADDVI, MASK_VADDVI, match_vd_neq_vm, 0 },
|
|
|
++{"vsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSUBVV, MASK_VSUBVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSUBVX, MASK_VSUBVX, match_vd_neq_vm, 0 },
|
|
|
++{"vrsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRSUBVX, MASK_VRSUBVX, match_vd_neq_vm, 0 },
|
|
|
++{"vrsub.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VRSUBVI, MASK_VRSUBVI, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vwcvt.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTXXV, MASK_VWCVTXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
|
|
|
++{"vwcvtu.x.x.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VWCVTUXXV, MASK_VWCVTUXXV, match_widen_vd_neq_vs2_neq_vm, INSN_ALIAS },
|
|
|
++
|
|
|
++{"vwaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUVV, MASK_VWADDUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUVX, MASK_VWADDUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwsubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUVV, MASK_VWSUBUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwsubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUVX, MASK_VWSUBUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDVV, MASK_VWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDVX, MASK_VWADDVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwsub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBVV, MASK_VWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwsub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBVX, MASK_VWSUBVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwaddu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDUWV, MASK_VWADDUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
|
|
|
++{"vwaddu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDUWX, MASK_VWADDUWX, match_widen_vd_neq_vm, 0 },
|
|
|
++{"vwsubu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBUWV, MASK_VWSUBUWV, match_widen_vd_neq_vs1_neq_vm, 0 },
|
|
|
++{"vwsubu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBUWX, MASK_VWSUBUWX, match_widen_vd_neq_vm, 0 },
|
|
|
++{"vwadd.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWADDWV, MASK_VWADDWV, match_widen_vd_neq_vs1_neq_vm, 0 },
|
|
|
++{"vwadd.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWADDWX, MASK_VWADDWX, match_widen_vd_neq_vm, 0 },
|
|
|
++{"vwsub.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWSUBWV, MASK_VWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0 },
|
|
|
++{"vwsub.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWSUBWX, MASK_VWSUBWX, match_widen_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vzext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF2, MASK_VZEXT_VF2, match_vd_neq_vm, 0 },
|
|
|
++{"vsext.vf2", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF2, MASK_VSEXT_VF2, match_vd_neq_vm, 0 },
|
|
|
++{"vzext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF4, MASK_VZEXT_VF4, match_vd_neq_vm, 0 },
|
|
|
++{"vsext.vf4", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF4, MASK_VSEXT_VF4, match_vd_neq_vm, 0 },
|
|
|
++{"vzext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VZEXT_VF8, MASK_VZEXT_VF8, match_vd_neq_vm, 0 },
|
|
|
++{"vsext.vf8", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VSEXT_VF8, MASK_VSEXT_VF8, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VADCVVM, MASK_VADCVVM, match_vd_neq_vm, 0 },
|
|
|
++{"vadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VADCVXM, MASK_VADCVXM, match_vd_neq_vm, 0 },
|
|
|
++{"vadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VADCVIM, MASK_VADCVIM, match_vd_neq_vm, 0 },
|
|
|
++{"vmadc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMADCVVM, MASK_VMADCVVM, match_opcode, 0 },
|
|
|
++{"vmadc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMADCVXM, MASK_VMADCVXM, match_opcode, 0 },
|
|
|
++{"vmadc.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMADCVIM, MASK_VMADCVIM, match_opcode, 0 },
|
|
|
++{"vmadc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMADCVV, MASK_VMADCVV, match_opcode, 0 },
|
|
|
++{"vmadc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMADCVX, MASK_VMADCVX, match_opcode, 0 },
|
|
|
++{"vmadc.vi", 0, INSN_CLASS_V, "Vd,Vt,Vi", MATCH_VMADCVI, MASK_VMADCVI, match_opcode, 0 },
|
|
|
++{"vsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VSBCVVM, MASK_VSBCVVM, match_vd_neq_vm, 0 },
|
|
|
++{"vsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VSBCVXM, MASK_VSBCVXM, match_vd_neq_vm, 0 },
|
|
|
++{"vmsbc.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMSBCVVM, MASK_VMSBCVVM, match_opcode, 0 },
|
|
|
++{"vmsbc.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMSBCVXM, MASK_VMSBCVXM, match_opcode, 0 },
|
|
|
++{"vmsbc.vv", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMSBCVV, MASK_VMSBCVV, match_opcode, 0 },
|
|
|
++{"vmsbc.vx", 0, INSN_CLASS_V, "Vd,Vt,s", MATCH_VMSBCVX, MASK_VMSBCVX, match_opcode, 0 },
|
|
|
++
|
|
|
++{"vnot.v", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNOTV, MASK_VNOTV, match_vd_neq_vm, INSN_ALIAS },
|
|
|
++
|
|
|
++{"vand.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VANDVV, MASK_VANDVV, match_vd_neq_vm, 0 },
|
|
|
++{"vand.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VANDVX, MASK_VANDVX, match_vd_neq_vm, 0 },
|
|
|
++{"vand.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VANDVI, MASK_VANDVI, match_vd_neq_vm, 0 },
|
|
|
++{"vor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VORVV, MASK_VORVV, match_vd_neq_vm, 0 },
|
|
|
++{"vor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VORVX, MASK_VORVX, match_vd_neq_vm, 0 },
|
|
|
++{"vor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VORVI, MASK_VORVI, match_vd_neq_vm, 0 },
|
|
|
++{"vxor.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VXORVV, MASK_VXORVV, match_vd_neq_vm, 0 },
|
|
|
++{"vxor.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VXORVX, MASK_VXORVX, match_vd_neq_vm, 0 },
|
|
|
++{"vxor.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VXORVI, MASK_VXORVI, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vsll.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSLLVV, MASK_VSLLVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsll.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLLVX, MASK_VSLLVX, match_vd_neq_vm, 0 },
|
|
|
++{"vsll.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLLVI, MASK_VSLLVI, match_vd_neq_vm, 0 },
|
|
|
++{"vsrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRLVV, MASK_VSRLVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRLVX, MASK_VSRLVX, match_vd_neq_vm, 0 },
|
|
|
++{"vsrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRLVI, MASK_VSRLVI, match_vd_neq_vm, 0 },
|
|
|
++{"vsra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSRAVV, MASK_VSRAVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSRAVX, MASK_VSRAVX, match_vd_neq_vm, 0 },
|
|
|
++{"vsra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSRAVI, MASK_VSRAVI, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vncvt.x.x.w",0, INSN_CLASS_V, "Vd,VtVm", MATCH_VNCVTXXW, MASK_VNCVTXXW, match_narrow_vd_neq_vs2_neq_vm, INSN_ALIAS },
|
|
|
++
|
|
|
++{"vnsrl.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRLWV, MASK_VNSRLWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnsrl.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRLWX, MASK_VNSRLWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnsrl.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRLWI, MASK_VNSRLWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnsra.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNSRAWV, MASK_VNSRAWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnsra.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNSRAWX, MASK_VNSRAWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnsra.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNSRAWI, MASK_VNSRAWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vmseq.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, 0 },
|
|
|
++{"vmseq.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSEQVX, MASK_VMSEQVX, match_opcode, 0 },
|
|
|
++{"vmseq.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSEQVI, MASK_VMSEQVI, match_opcode, 0 },
|
|
|
++{"vmsne.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, 0 },
|
|
|
++{"vmsne.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSNEVX, MASK_VMSNEVX, match_opcode, 0 },
|
|
|
++{"vmsne.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSNEVI, MASK_VMSNEVI, match_opcode, 0 },
|
|
|
++{"vmsltu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, 0 },
|
|
|
++{"vmsltu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTUVX, MASK_VMSLTUVX, match_opcode, 0 },
|
|
|
++{"vmslt.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, 0 },
|
|
|
++{"vmslt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLTVX, MASK_VMSLTVX, match_opcode, 0 },
|
|
|
++{"vmsleu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, 0 },
|
|
|
++{"vmsleu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEUVX, MASK_VMSLEUVX, match_opcode, 0 },
|
|
|
++{"vmsleu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, 0 },
|
|
|
++{"vmsle.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, 0 },
|
|
|
++{"vmsle.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSLEVX, MASK_VMSLEVX, match_opcode, 0 },
|
|
|
++{"vmsle.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, 0 },
|
|
|
++{"vmsgtu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTUVX, MASK_VMSGTUVX, match_opcode, 0 },
|
|
|
++{"vmsgtu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, 0 },
|
|
|
++{"vmsgt.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMSGTVX, MASK_VMSGTVX, match_opcode, 0 },
|
|
|
++{"vmsgt.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, 0 },
|
|
|
++
|
|
|
++/* These aliases are for assembly but not disassembly. */
|
|
|
++{"vmsgt.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTVV, MASK_VMSLTVV, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsgtu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLTUVV, MASK_VMSLTUVV, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsge.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEVV, MASK_VMSLEVV, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsgeu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMSLEUVV, MASK_VMSLEUVV, match_opcode, INSN_ALIAS },
|
|
|
++{"vmslt.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEVI, MASK_VMSLEVI, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSNEVV, MASK_VMSNEVV, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsltu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSLEUVI, MASK_VMSLEUVI, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsge.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTVI, MASK_VMSGTVI, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vu,0Vm", MATCH_VMSEQVV, MASK_VMSEQVV, match_opcode, INSN_ALIAS },
|
|
|
++{"vmsgeu.vi", 0, INSN_CLASS_V, "Vd,Vt,VkVm", MATCH_VMSGTUVI, MASK_VMSGTUVI, match_opcode, INSN_ALIAS },
|
|
|
++
|
|
|
++{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
|
|
|
++{"vmsge.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
|
|
|
++{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
|
|
|
++{"vmsgeu.vx", 0, INSN_CLASS_V, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGEU, match_never, INSN_MACRO },
|
|
|
++
|
|
|
++{"vminu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINUVV, MASK_VMINUVV, match_vd_neq_vm, 0},
|
|
|
++{"vminu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINUVX, MASK_VMINUVX, match_vd_neq_vm, 0},
|
|
|
++{"vmin.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMINVV, MASK_VMINVV, match_vd_neq_vm, 0},
|
|
|
++{"vmin.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMINVX, MASK_VMINVX, match_vd_neq_vm, 0},
|
|
|
++{"vmaxu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXUVV, MASK_VMAXUVV, match_vd_neq_vm, 0},
|
|
|
++{"vmaxu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXUVX, MASK_VMAXUVX, match_vd_neq_vm, 0},
|
|
|
++{"vmax.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMAXVV, MASK_VMAXVV, match_vd_neq_vm, 0},
|
|
|
++{"vmax.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMAXVX, MASK_VMAXVX, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULVV, MASK_VMULVV, match_vd_neq_vm, 0 },
|
|
|
++{"vmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULVX, MASK_VMULVX, match_vd_neq_vm, 0 },
|
|
|
++{"vmulh.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHVV, MASK_VMULHVV, match_vd_neq_vm, 0 },
|
|
|
++{"vmulh.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHVX, MASK_VMULHVX, match_vd_neq_vm, 0 },
|
|
|
++{"vmulhu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHUVV, MASK_VMULHUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vmulhu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHUVX, MASK_VMULHUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vmulhsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VMULHSUVV, MASK_VMULHSUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vmulhsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VMULHSUVX, MASK_VMULHSUVX, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vwmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULVV, MASK_VWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULVX, MASK_VWMULVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwmulu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULUVV, MASK_VWMULUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwmulu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULUVX, MASK_VWMULUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwmulsu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWMULSUVV, MASK_VWMULSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0 },
|
|
|
++{"vwmulsu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VWMULSUVX, MASK_VWMULSUVX, match_widen_vd_neq_vs2_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMACCVV, MASK_VMACCVV, match_vd_neq_vm, 0},
|
|
|
++{"vmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMACCVX, MASK_VMACCVX, match_vd_neq_vm, 0},
|
|
|
++{"vnmsac.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSACVV, MASK_VNMSACVV, match_vd_neq_vm, 0},
|
|
|
++{"vnmsac.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSACVX, MASK_VNMSACVX, match_vd_neq_vm, 0},
|
|
|
++{"vmadd.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VMADDVV, MASK_VMADDVV, match_vd_neq_vm, 0},
|
|
|
++{"vmadd.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VMADDVX, MASK_VMADDVX, match_vd_neq_vm, 0},
|
|
|
++{"vnmsub.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VNMSUBVV, MASK_VNMSUBVV, match_vd_neq_vm, 0},
|
|
|
++{"vnmsub.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VNMSUBVX, MASK_VNMSUBVX, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vwmaccu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCUVV, MASK_VWMACCUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vwmaccu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUVX, MASK_VWMACCUVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vwmacc.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCVV, MASK_VWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vwmacc.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCVX, MASK_VWMACCVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vwmaccsu.vv", 0, INSN_CLASS_V, "Vd,Vs,VtVm", MATCH_VWMACCSUVV, MASK_VWMACCSUVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vwmaccsu.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCSUVX, MASK_VWMACCSUVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vwmaccus.vx", 0, INSN_CLASS_V, "Vd,s,VtVm", MATCH_VWMACCUSVX, MASK_VWMACCUSVX, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++
|
|
|
++{"vdivu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVUVV, MASK_VDIVUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vdivu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVUVX, MASK_VDIVUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vdiv.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VDIVVV, MASK_VDIVVV, match_vd_neq_vm, 0 },
|
|
|
++{"vdiv.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VDIVVX, MASK_VDIVVX, match_vd_neq_vm, 0 },
|
|
|
++{"vremu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMUVV, MASK_VREMUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vremu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMUVX, MASK_VREMUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vrem.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREMVV, MASK_VREMVV, match_vd_neq_vm, 0 },
|
|
|
++{"vrem.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VREMVX, MASK_VREMVX, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vmerge.vvm", 0, INSN_CLASS_V, "Vd,Vt,Vs,V0", MATCH_VMERGEVVM, MASK_VMERGEVVM, match_opcode, 0 },
|
|
|
++{"vmerge.vxm", 0, INSN_CLASS_V, "Vd,Vt,s,V0", MATCH_VMERGEVXM, MASK_VMERGEVXM, match_opcode, 0 },
|
|
|
++{"vmerge.vim", 0, INSN_CLASS_V, "Vd,Vt,Vi,V0", MATCH_VMERGEVIM, MASK_VMERGEVIM, match_opcode, 0 },
|
|
|
++
|
|
|
++{"vmv.v.v", 0, INSN_CLASS_V, "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
|
|
|
++{"vmv.v.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
|
|
|
++{"vmv.v.i", 0, INSN_CLASS_V, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
|
|
|
++
|
|
|
++{"vsaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vsaddu.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_vd_neq_vm, 0 },
|
|
|
++{"vsadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_vd_neq_vm, 0 },
|
|
|
++{"vsadd.vi", 0, INSN_CLASS_V, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_vd_neq_vm, 0 },
|
|
|
++{"vssubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vssubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vssub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_vd_neq_vm, 0 },
|
|
|
++{"vssub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vaaddu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDUVV, MASK_VAADDUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vaaddu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDUVX, MASK_VAADDUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vaadd.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VAADDVV, MASK_VAADDVV, match_vd_neq_vm, 0 },
|
|
|
++{"vaadd.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VAADDVX, MASK_VAADDVX, match_vd_neq_vm, 0 },
|
|
|
++{"vasubu.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBUVV, MASK_VASUBUVV, match_vd_neq_vm, 0 },
|
|
|
++{"vasubu.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBUVX, MASK_VASUBUVX, match_vd_neq_vm, 0 },
|
|
|
++{"vasub.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VASUBVV, MASK_VASUBVV, match_vd_neq_vm, 0 },
|
|
|
++{"vasub.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VASUBVX, MASK_VASUBVX, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vsmul.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_vd_neq_vm, 0 },
|
|
|
++{"vsmul.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vssrl.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_vd_neq_vm, 0 },
|
|
|
++{"vssrl.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_vd_neq_vm, 0 },
|
|
|
++{"vssrl.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_vd_neq_vm, 0 },
|
|
|
++{"vssra.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_vd_neq_vm, 0 },
|
|
|
++{"vssra.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_vd_neq_vm, 0 },
|
|
|
++{"vssra.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_vd_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vnclipu.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnclipu.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnclipu.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnclip.wv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnclip.wx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++{"vnclip.wi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_narrow_vd_neq_vs2_neq_vm, 0 },
|
|
|
++
|
|
|
++{"vfadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_vd_neq_vm, 0},
|
|
|
++{"vfadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_vd_neq_vm, 0},
|
|
|
++{"vfsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_vd_neq_vm, 0},
|
|
|
++{"vfsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_vd_neq_vm, 0},
|
|
|
++{"vfrsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfwadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwadd.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_widen_vd_neq_vs1_neq_vm, 0},
|
|
|
++{"vfwadd.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_widen_vd_neq_vm, 0},
|
|
|
++{"vfwsub.wv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_widen_vd_neq_vs1_neq_vm, 0},
|
|
|
++{"vfwsub.wf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_widen_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_vd_neq_vm, 0},
|
|
|
++{"vfdiv.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_vd_neq_vm, 0},
|
|
|
++{"vfdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_vd_neq_vm, 0},
|
|
|
++{"vfrdiv.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfwmul.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwmul.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_vd_neq_vm, 0},
|
|
|
++{"vfnmadd.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_vd_neq_vm, 0},
|
|
|
++{"vfnmadd.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_vd_neq_vm, 0},
|
|
|
++{"vfmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_vd_neq_vm, 0},
|
|
|
++{"vfnmsub.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_vd_neq_vm, 0},
|
|
|
++{"vfnmsub.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_vd_neq_vm, 0},
|
|
|
++{"vfmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_vd_neq_vm, 0},
|
|
|
++{"vfnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_vd_neq_vm, 0},
|
|
|
++{"vfnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_vd_neq_vm, 0},
|
|
|
++{"vfmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_vd_neq_vm, 0},
|
|
|
++{"vfnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_vd_neq_vm, 0},
|
|
|
++{"vfnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfwmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwnmacc.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwnmacc.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwnmsac.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_widen_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwnmsac.vf", 0, INSN_CLASS_V_AND_F, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfsqrt.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFSQRTV, MASK_VFSQRTV, match_vd_neq_vm, 0},
|
|
|
++{"vfrsqrt7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
|
|
|
++{"vfrsqrte7.v",0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFRSQRT7V, MASK_VFRSQRT7V, match_vd_neq_vm, 0},
|
|
|
++{"vfrec7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
|
|
|
++{"vfrece7.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFREC7V, MASK_VFREC7V, match_vd_neq_vm, 0},
|
|
|
++{"vfclass.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCLASSV, MASK_VFCLASSV, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfmin.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmin.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_vd_neq_vm, 0},
|
|
|
++{"vfmax.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_vd_neq_vm, 0},
|
|
|
++{"vfmax.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfneg.v", 0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
|
|
|
++{"vfabs.v", 0, INSN_CLASS_V_AND_F, "Vd,VuVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vs1_eq_vs2_neq_vm, INSN_ALIAS },
|
|
|
++
|
|
|
++{"vfsgnj.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_vd_neq_vm, 0},
|
|
|
++{"vfsgnj.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_vd_neq_vm, 0},
|
|
|
++{"vfsgnjn.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_vd_neq_vm, 0},
|
|
|
++{"vfsgnjn.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_vd_neq_vm, 0},
|
|
|
++{"vfsgnjx.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_vd_neq_vm, 0},
|
|
|
++{"vfsgnjx.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vmfeq.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
|
|
|
++{"vmfeq.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
|
|
|
++{"vmfne.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
|
|
|
++{"vmfne.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
|
|
|
++{"vmflt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
|
|
|
++{"vmflt.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
|
|
|
++{"vmfle.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
|
|
|
++{"vmfle.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
|
|
|
++{"vmfgt.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
|
|
|
++{"vmfge.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
|
|
|
++
|
|
|
++/* These aliases are for assembly but not disassembly. */
|
|
|
++{"vmfgt.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
|
|
|
++{"vmfge.vv", 0, INSN_CLASS_V_AND_F, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
|
|
|
++
|
|
|
++{"vfmerge.vfm",0, INSN_CLASS_V_AND_F, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
|
|
|
++{"vfmv.v.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
|
|
|
++
|
|
|
++{"vfcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXUFV, MASK_VFCVTXUFV, match_vd_neq_vm, 0},
|
|
|
++{"vfcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTXFV, MASK_VFCVTXFV, match_vd_neq_vm, 0},
|
|
|
++{"vfcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXUFV, MASK_VFCVTRTZXUFV, match_vd_neq_vm, 0},
|
|
|
++{"vfcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTRTZXFV, MASK_VFCVTRTZXFV, match_vd_neq_vm, 0},
|
|
|
++{"vfcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXUV, MASK_VFCVTFXUV, match_vd_neq_vm, 0},
|
|
|
++{"vfcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFCVTFXV, MASK_VFCVTFXV, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfwcvt.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXUFV, MASK_VFWCVTXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwcvt.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTXFV, MASK_VFWCVTXFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwcvt.rtz.xu.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXUFV, MASK_VFWCVTRTZXUFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwcvt.rtz.x.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTRTZXFV, MASK_VFWCVTRTZXFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwcvt.f.xu.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXUV, MASK_VFWCVTFXUV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwcvt.f.x.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFXV, MASK_VFWCVTFXV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfwcvt.f.f.v", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFWCVTFFV, MASK_VFWCVTFFV, match_widen_vd_neq_vs2_neq_vm, 0},
|
|
|
++
|
|
|
++{"vfncvt.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXUFW, MASK_VFNCVTXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTXFW, MASK_VFNCVTXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.rtz.xu.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXUFW, MASK_VFNCVTRTZXUFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.rtz.x.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRTZXFW, MASK_VFNCVTRTZXFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.f.xu.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXUW, MASK_VFNCVTFXUW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.f.x.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFXW, MASK_VFNCVTFXW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTFFW, MASK_VFNCVTFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfncvt.rod.f.f.w", 0, INSN_CLASS_V_AND_F, "Vd,VtVm", MATCH_VFNCVTRODFFW, MASK_VFNCVTRODFFW, match_narrow_vd_neq_vs2_neq_vm, 0},
|
|
|
++
|
|
|
++{"vredsum.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDSUMVS, MASK_VREDSUMVS, match_opcode, 0},
|
|
|
++{"vredmaxu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXUVS, MASK_VREDMAXUVS, match_opcode, 0},
|
|
|
++{"vredmax.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMAXVS, MASK_VREDMAXVS, match_opcode, 0},
|
|
|
++{"vredminu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINUVS, MASK_VREDMINUVS, match_opcode, 0},
|
|
|
++{"vredmin.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDMINVS, MASK_VREDMINVS, match_opcode, 0},
|
|
|
++{"vredand.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDANDVS, MASK_VREDANDVS, match_opcode, 0},
|
|
|
++{"vredor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDORVS, MASK_VREDORVS, match_opcode, 0},
|
|
|
++{"vredxor.vs", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VREDXORVS, MASK_VREDXORVS, match_opcode, 0},
|
|
|
++
|
|
|
++{"vwredsumu.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMUVS, MASK_VWREDSUMUVS, match_opcode, 0},
|
|
|
++{"vwredsum.vs",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VWREDSUMVS, MASK_VWREDSUMVS, match_opcode, 0},
|
|
|
++
|
|
|
++{"vfredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDOSUMVS, MASK_VFREDOSUMVS, match_opcode, 0},
|
|
|
++{"vfredusum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, 0},
|
|
|
++{"vfredmax.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMAXVS, MASK_VFREDMAXVS, match_opcode, 0},
|
|
|
++{"vfredmin.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
|
|
|
++
|
|
|
++{"vfwredosum.vs",0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
|
|
|
++{"vfwredusum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, 0},
|
|
|
++
|
|
|
++{"vfredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFREDSUMVS, MASK_VFREDSUMVS, match_opcode, INSN_ALIAS},
|
|
|
++{"vfwredsum.vs", 0, INSN_CLASS_V_AND_F, "Vd,Vt,VsVm", MATCH_VFWREDSUMVS, MASK_VFWREDSUMVS, match_opcode, INSN_ALIAS},
|
|
|
++{"vmmv.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
|
|
|
++{"vmcpy.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
|
|
|
++{"vmclr.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
|
|
|
++{"vmset.m", 0, INSN_CLASS_V, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
|
|
|
++{"vmnot.m", 0, INSN_CLASS_V, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
|
|
|
++
|
|
|
++{"vmand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
|
|
|
++{"vmnand.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
|
|
|
++{"vmandnot.mm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMANDNOTMM, MASK_VMANDNOTMM, match_opcode, 0},
|
|
|
++{"vmxor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
|
|
|
++{"vmor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
|
|
|
++{"vmnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
|
|
|
++{"vmornot.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMORNOTMM, MASK_VMORNOTMM, match_opcode, 0},
|
|
|
++{"vmxnor.mm", 0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
|
|
|
++
|
|
|
++{"vpopc.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VPOPCM, MASK_VPOPCM, match_opcode, 0},
|
|
|
++{"vfirst.m", 0, INSN_CLASS_V, "d,VtVm", MATCH_VFIRSTM, MASK_VFIRSTM, match_opcode, 0},
|
|
|
++{"vmsbf.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSBFM, MASK_VMSBFM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vmsif.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSIFM, MASK_VMSIFM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vmsof.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VMSOFM, MASK_VMSOFM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"viota.m", 0, INSN_CLASS_V, "Vd,VtVm", MATCH_VIOTAM, MASK_VIOTAM, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vid.v", 0, INSN_CLASS_V, "VdVm", MATCH_VIDV, MASK_VIDV, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vmv.x.s", 0, INSN_CLASS_V, "d,Vt", MATCH_VMVXS, MASK_VMVXS, match_opcode, 0},
|
|
|
++{"vmv.s.x", 0, INSN_CLASS_V, "Vd,s", MATCH_VMVSX, MASK_VMVSX, match_opcode, 0},
|
|
|
++
|
|
|
++{"vfmv.f.s", 0, INSN_CLASS_V_AND_F, "D,Vt", MATCH_VFMVFS, MASK_VFMVFS, match_opcode, 0},
|
|
|
++{"vfmv.s.f", 0, INSN_CLASS_V_AND_F, "Vd,S", MATCH_VFMVSF, MASK_VFMVSF, match_opcode, 0},
|
|
|
++
|
|
|
++{"vslideup.vx",0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vslideup.vi",0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vslidedown.vx",0,INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_vd_neq_vm, 0},
|
|
|
++{"vslidedown.vi",0,INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vslide1up.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vslide1down.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_vd_neq_vm, 0},
|
|
|
++{"vfslide1up.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1UPVF, MASK_VFSLIDE1UPVF, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vfslide1down.vf", 0, INSN_CLASS_V_AND_F, "Vd,Vt,SVm", MATCH_VFSLIDE1DOWNVF, MASK_VFSLIDE1DOWNVF, match_vd_neq_vm, 0},
|
|
|
++
|
|
|
++{"vrgather.vv", 0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++{"vrgather.vx", 0, INSN_CLASS_V, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vrgather.vi", 0, INSN_CLASS_V, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_vd_neq_vs2_neq_vm, 0},
|
|
|
++{"vrgatherei16.vv",0, INSN_CLASS_V, "Vd,Vt,VsVm", MATCH_VRGATHEREI16VV, MASK_VRGATHEREI16VV, match_vd_neq_vs1_neq_vs2_neq_vm, 0},
|
|
|
++
|
|
|
++{"vcompress.vm",0, INSN_CLASS_V, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_vd_neq_vs1_neq_vs2, 0},
|
|
|
++
|
|
|
++{"vmv1r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV1RV, MASK_VMV1RV, match_vmv_nf_rv, 0},
|
|
|
++{"vmv2r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV2RV, MASK_VMV2RV, match_vmv_nf_rv, 0},
|
|
|
++{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_vmv_nf_rv, 0},
|
|
|
++{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_vmv_nf_rv, 0},
|
|
|
++/* END RVV */
|
|
|
++
|
|
|
+ /* Terminate the list. */
|
|
|
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
|
|
|
+ };
|
|
|
+@@ -1160,6 +2263,26 @@ const struct riscv_opcode riscv_insn_types[] =
|
|
|
+ {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 },
|
|
|
+ {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 },
|
|
|
+ {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 },
|
|
|
++
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,s,t", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,t", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,s,T", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,T", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,Vs,t", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,t", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,d,Vs,T", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,T", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,s,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,s,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,d,S,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,S,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,Vs,t", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,Vs,T", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,s,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,Vd,S,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,d,Vs,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V_AND_F, "O4,F3,F7,D,Vs,Vt", 0, 0, match_opcode, 0 },
|
|
|
++{"r", 0, INSN_CLASS_V, "O4,F3,F7,Vd,Vs,Vt", 0, 0, match_opcode, 0 },
|
|
|
+ {"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
|
|
|
+ {"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
|
|
|
+ {"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
|
|
|
+@@ -1257,4 +2380,4 @@ const struct riscv_opcode riscv_insn_types[] =
|
|
|
+
|
|
|
+ /* Terminate the list. */
|
|
|
+ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
|
|
|
+-};
|
|
|
++};
|
|
|
+\ No newline at end of file
|
|
|
+--
|
|
|
+2.33.1
|
|
|
+
|