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@@ -0,0 +1,545 @@
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+From e243539f72938317c85bb9859576c39b1baf011d Mon Sep 17 00:00:00 2001
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+From: "yilun.xie" <yilun.xie@starfivetech.com>
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+Date: Thu, 18 Nov 2021 14:25:18 +0800
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+Subject: [PATCH 16/26] merge sifve change for bitmanip
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+
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+---
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+ gcc/config/riscv/bitmanip.md | 446 ++++++++++++++---------------------
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+ 1 file changed, 173 insertions(+), 273 deletions(-)
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+
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+diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
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+index ceb5c89dd47..d2e1d6c936b 100644
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+--- a/gcc/config/riscv/bitmanip.md
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++++ b/gcc/config/riscv/bitmanip.md
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+@@ -1,5 +1,5 @@
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+ ;; Machine description for RISC-V Bit Manipulation operations.
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+-;; Copyright (C) 2019 Free Software Foundation, Inc.
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++;; Copyright (C) 2021 Free Software Foundation, Inc.
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+
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+ ;; This file is part of GCC.
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+
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+@@ -19,7 +19,7 @@
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+
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+ (define_code_iterator bitmanip_bitwise [and ior])
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+
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+-(define_code_iterator any_minmax [smin smax umin umax])
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++(define_code_iterator bitmanip_minmax [smin umin smax umax])
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+
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+ (define_code_iterator clz_ctz_pcnt [clz ctz popcount])
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+
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+@@ -31,6 +31,7 @@
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+ (ctz "ctz")
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+ (popcount "popcount")])
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+
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++
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+ (define_code_attr bitmanip_insn [(smin "min")
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+ (smax "max")
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+ (umin "minu")
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+@@ -41,74 +42,206 @@
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+
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+ (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
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+
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++;; ZBA extension.
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++
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++(define_insn "*zero_extendsidi2_bitmanip"
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++ [(set (match_operand:DI 0 "register_operand" "=r,r")
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++ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
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++ "TARGET_64BIT && TARGET_ZBA"
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++ "@
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++ zext.w\t%0,%1
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++ lwu\t%0,%1"
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++ [(set_attr "type" "bitmanip,load")
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++ (set_attr "mode" "DI")])
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++
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++(define_insn "*shNadd"
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++ [(set (match_operand:X 0 "register_operand" "=r")
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++ (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
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++ (match_operand:QI 2 "immediate_operand" "I"))
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++ (match_operand:X 3 "register_operand" "r")))]
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++ "TARGET_ZBA
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++ && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
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++ "sh%2add\t%0,%1,%3"
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "<X:MODE>")])
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++
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++(define_insn "*shNadduw"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (plus:DI
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++ (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
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++ (match_operand:QI 2 "immediate_operand" "I"))
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++ (match_operand 3 "immediate_operand" ""))
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++ (match_operand:DI 4 "register_operand" "r")))]
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++ "TARGET_64BIT && TARGET_ZBA
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++ && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
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++ && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
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++ "sh%2add.uw\t%0,%1,%4"
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "DI")])
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++
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++(define_insn "*add.uw"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (plus:DI (zero_extend:DI
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++ (match_operand:SI 1 "register_operand" "r"))
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++ (match_operand:DI 2 "register_operand" "r")))]
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++ "TARGET_64BIT && TARGET_ZBA"
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++ "add.uw\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "DI")])
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++
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++(define_insn "*slliuw"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
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++ (match_operand:QI 2 "immediate_operand" "I"))
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++ (match_operand 3 "immediate_operand" "")))]
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++ "TARGET_64BIT && TARGET_ZBA
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++ && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
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++ "slli.uw\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "DI")])
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++
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++;; ZBB extension.
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++
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++(define_insn "*<optab>_not<mode>"
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++ [(set (match_operand:X 0 "register_operand" "=r")
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++ (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
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++ (match_operand:X 2 "register_operand" "r")))]
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++ "TARGET_ZBB"
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++ "<insn>n\t%0,%2,%1"
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "<X:MODE>")])
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++
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++(define_insn "*xor_not<mode>"
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++ [(set (match_operand:X 0 "register_operand" "=r")
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++ (not:X (xor:X (match_operand:X 1 "register_operand" "r")
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++ (match_operand:X 2 "register_operand" "r"))))]
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++ "TARGET_ZBB"
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++ "xnor\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "<X:MODE>")])
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++
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+ (define_insn "<bitmanip_optab>si2"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+- (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
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++ (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
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+ "TARGET_ZBB"
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+ { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
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+- [(set_attr "type" "bitmanip")])
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "SI")])
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+
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+-;; TODO: In theory zero_extend should be OK to combine too, since the output
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+-;; range is 0 ~ 32, zero_extend or sign_extend will get same result.
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+ (define_insn "*<bitmanip_optab>disi2"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+- (sign_extend:DI
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+- (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
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++ (sign_extend:DI
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++ (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
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+ "TARGET_64BIT && TARGET_ZBB"
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+ "<bitmanip_insn>w\t%0,%1"
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+- [(set_attr "type" "bitmanip")])
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "SI")])
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+
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+ (define_insn "<bitmanip_optab>di2"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+- (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
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++ (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
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+ "TARGET_64BIT && TARGET_ZBB"
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+ "<bitmanip_insn>\t%0,%1"
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+- [(set_attr "type" "bitmanip")])
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++ [(set_attr "type" "bitmanip")
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++ (set_attr "mode" "DI")])
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+
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+-(define_insn "*<optab>_not<mode>"
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+- [(set (match_operand:X 0 "register_operand" "=r")
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+- (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
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+- (match_operand:X 2 "register_operand" "r")))]
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++(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
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++ [(set (match_operand:GPR 0 "register_operand" "=r,r")
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++ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
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+ "TARGET_ZBB"
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+- "<insn>n\t%0,%2,%1"
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+- [(set_attr "type" "bitmanip")])
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++ "@
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++ zext.h\t%0,%1
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++ lhu\t%0,%1"
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++ [(set_attr "type" "bitmanip,load")
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++ (set_attr "mode" "<GPR:MODE>")])
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+
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+-(define_insn "*xor_not<mode>"
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+- [(set (match_operand:X 0 "register_operand" "=r")
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+- (not:X (xor:X (match_operand:X 1 "register_operand" "r")
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+- (match_operand:X 2 "register_operand" "r"))))]
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++(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
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++ [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
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++ (sign_extend:SUPERQI
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++ (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
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+ "TARGET_ZBB"
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+- "xnor\t%0,%1,%2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+-;;; ??? pack
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++ "@
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++ sext.<SHORT:size>\t%0,%1
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++ l<SHORT:size>\t%0,%1"
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++ [(set_attr "type" "bitmanip,load")
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++ (set_attr "mode" "<SUPERQI:MODE>")])
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+
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+-(define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
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+- [(set (match_operand:GPR 0 "register_operand" "=r,r")
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+- (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
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++(define_insn "*zero_extendhi<GPR:mode>2_zbb"
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++ [(set (match_operand:GPR 0 "register_operand" "=r,r")
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++ (zero_extend:GPR
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++ (match_operand:HI 1 "nonimmediate_operand" " r,m")))]
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+ "TARGET_ZBB"
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+ "@
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+ zext.h\t%0,%1
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+ lhu\t%0,%1"
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+- [(set_attr "type" "bitmanip,load")])
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++ [(set_attr "type" "bitmanip,load")
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++ (set_attr "mode" "HI")])
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+
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+-(define_insn "*zero_extendsidi2_bitmanip"
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+- [(set (match_operand:DI 0 "register_operand" "=r,r")
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+- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
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+- "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBA)"
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+- "@
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+- zext.w\t%0,%1
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+- lwu\t%0,%1"
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+- [(set_attr "type" "bitmanip,load")])
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++(define_insn "rotrsi3"
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++ [(set (match_operand:SI 0 "register_operand" "=r")
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++ (rotatert:SI (match_operand:SI 1 "register_operand" "r")
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++ (match_operand:QI 2 "arith_operand" "rI")))]
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++ "TARGET_ZBB"
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++ { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
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++ [(set_attr "type" "bitmanip")])
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++
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++(define_insn "rotrdi3"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (rotatert:DI (match_operand:DI 1 "register_operand" "r")
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++ (match_operand:QI 2 "arith_operand" "rI")))]
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++ "TARGET_64BIT && TARGET_ZBB"
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++ "ror%i2\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")])
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++
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++(define_insn "rotrsi3_sext"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
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++ (match_operand:QI 2 "register_operand" "r"))))]
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++ "TARGET_64BIT && TARGET_ZBB"
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++ "rorw\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")])
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++
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++(define_insn "rotlsi3"
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++ [(set (match_operand:SI 0 "register_operand" "=r")
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++ (rotate:SI (match_operand:SI 1 "register_operand" "r")
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++ (match_operand:QI 2 "register_operand" "r")))]
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++ "TARGET_ZBB"
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++ { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
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++ [(set_attr "type" "bitmanip")])
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++
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++(define_insn "rotldi3"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (rotate:DI (match_operand:DI 1 "register_operand" "r")
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++ (match_operand:QI 2 "register_operand" "r")))]
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++ "TARGET_64BIT && TARGET_ZBB"
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++ "rol\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")])
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++
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++(define_insn "rotlsi3_sext"
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++ [(set (match_operand:DI 0 "register_operand" "=r")
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++ (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
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++ (match_operand:QI 2 "register_operand" "r"))))]
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++ "TARGET_64BIT && TARGET_ZBB"
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++ "rolw\t%0,%1,%2"
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++ [(set_attr "type" "bitmanip")])
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++
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++(define_insn "bswap<mode>2"
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++ [(set (match_operand:X 0 "register_operand" "=r")
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++ (bswap:X (match_operand:X 1 "register_operand" "r")))]
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++ "TARGET_64BIT && TARGET_ZBB"
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++ "rev8\t%0,%1"
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++ [(set_attr "type" "bitmanip")])
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+
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+ (define_insn "<bitmanip_optab><mode>3"
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+- (any_minmax:X (match_operand:X 1 "register_operand" "r")
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+- (match_operand:X 2 "register_operand" "r")))]
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++ (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
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++ (match_operand:X 2 "register_operand" "r")))]
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+ "TARGET_ZBB"
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+ "<bitmanip_insn>\t%0,%1,%2"
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+ [(set_attr "type" "bitmanip")])
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+
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++;; ZBS extension.
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++
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+ (define_insn "*bset<mode>"
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (ior:X (ashift:X (const_int 1)
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+@@ -155,41 +288,6 @@
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+ "bseti\t%0,%1,%S2"
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+ [(set_attr "type" "bitmanip")])
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+
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+-(define_insn "*bsetw"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (sign_extend:DI
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+- (subreg:SI
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+- (ior:DI (subreg:DI
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+- (ashift:SI (const_int 1)
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+- (match_operand:QI 2 "register_operand" "r")) 0)
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+- (match_operand:DI 1 "register_operand" "r")) 0)))]
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+- "TARGET_64BIT && TARGET_ZBS"
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+- "bsetw\t%0,%1,%2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+-(define_insn "*bsetw_mask"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (sign_extend:DI
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+- (subreg:SI
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+- (ior:DI (subreg:DI
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+- (ashift:SI
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+- (const_int 1)
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+- (subreg:QI
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+- (and:DI (match_operand:DI 2 "register_operand" "r")
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+- (match_operand 3 "const31_operand" "i")) 0)) 0)
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+- (match_operand:DI 1 "register_operand" "r")) 0)))]
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+- "TARGET_64BIT && TARGET_ZBS"
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+- "bsetw\t%0,%1,%2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+-(define_insn "*bsetiw"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
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+- (match_operand 2 "single_bit_mask_operand" "i")))]
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+- "TARGET_64BIT && TARGET_ZBS"
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+- "bsetiw\t%0,%1,%S2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+ (define_insn "*bclr<mode>"
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (and:X (rotate:X (const_int -2)
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+@@ -207,27 +305,6 @@
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+ "bclri\t%0,%1,%T2"
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+ [(set_attr "type" "bitmanip")])
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+
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+-(define_insn "*bclrw"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (sign_extend:DI
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+- (subreg:SI
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+- (and:DI
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+- (not:DI (subreg:DI
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+- (ashift:SI (const_int 1)
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+- (match_operand:QI 2 "register_operand" "r")) 0))
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+- (match_operand:DI 1 "register_operand" "r")) 0)))]
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+- "TARGET_64BIT && TARGET_ZBS"
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+- "bclrw\t%0,%1,%2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+-(define_insn "*bclriw"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (and:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
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+- (match_operand 2 "not_single_bit_mask_operand" "i")))]
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+- "TARGET_64BIT && TARGET_ZBS"
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+- "bclriw\t%0,%1,%T2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+ (define_insn "*binv<mode>"
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+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (xor:X (ashift:X (const_int 1)
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+@@ -245,26 +322,6 @@
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+ "binvi\t%0,%1,%S2"
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+ [(set_attr "type" "bitmanip")])
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+
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+-(define_insn "*binvw"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (sign_extend:DI
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+- (subreg:SI
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+- (xor:DI (subreg:DI
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+- (ashift:SI (const_int 1)
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+- (match_operand:QI 2 "register_operand" "r")) 0)
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+- (match_operand:DI 1 "register_operand" "r")) 0)))]
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+- "TARGET_64BIT && TARGET_ZBS"
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+- "binvw\t%0,%1,%2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+-(define_insn "*binviw"
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+- [(set (match_operand:DI 0 "register_operand" "=r")
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+- (xor:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
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+- (match_operand 2 "single_bit_mask_operand" "i")))]
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+- "TARGET_64BIT && TARGET_ZBS"
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|
+- "binviw\t%0,%1,%S2"
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+- [(set_attr "type" "bitmanip")])
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+-
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+ (define_insn "*bext<mode>"
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|
+ [(set (match_operand:X 0 "register_operand" "=r")
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+ (zero_extract:X (match_operand:X 1 "register_operand" "r")
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|
+@@ -282,161 +339,4 @@
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+ (match_operand 2 "immediate_operand" "i")))]
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+ "TARGET_ZBS"
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|
+ "bexti\t%0,%1,%2"
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|
+- [(set_attr "type" "bitmanip")])
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+-
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|
+-(define_insn "*bextw"
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|
+- [(set (match_operand:DI 0 "register_operand" "=r")
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|
+- (and:DI
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|
+- (subreg:DI
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|
+- (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
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|
+- (match_operand:QI 2 "register_operand" "r")) 0)
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|
+- (const_int 1)))]
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|
+- "TARGET_64BIT && TARGET_ZBS"
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|
+- "bextw\t%0,%1,%2"
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|
+- [(set_attr "type" "bitmanip")])
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+-
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|
+-;;; ??? s[lr]o*
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+-
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|
+-(define_insn "rotrsi3"
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|
+- [(set (match_operand:SI 0 "register_operand" "=r")
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|
+- (rotatert:SI (match_operand:SI 1 "register_operand" "r")
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|
+- (match_operand:QI 2 "arith_operand" "rI")))]
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|
+- "TARGET_ZBB"
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|
+- { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
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|
+- [(set_attr "type" "bitmanip")])
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+-
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|
+-(define_insn "rotrdi3"
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|
+- [(set (match_operand:DI 0 "register_operand" "=r")
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|
+- (rotatert:DI (match_operand:DI 1 "register_operand" "r")
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|
+- (match_operand:QI 2 "arith_operand" "rI")))]
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|
+- "TARGET_64BIT && TARGET_ZBB"
|
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|
+- "ror%i2\t%0,%1,%2"
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|
+- [(set_attr "type" "bitmanip")])
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|
+-
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|
|
+-(define_expand "riscv_rolw"
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|
+- [(match_operand:SI 0 "register_operand" "=r")
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|
+- (match_operand:SI 1 "register_operand" "r")
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|
+- (match_operand:SI 2 "register_operand" "r")]
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|
+- "TARGET_64BIT && TARGET_ZBB"
|
|
|
+-{
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|
+- emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
|
|
|
+- DONE;
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|
|
+-})
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|
|
+-
|
|
|
+-(define_insn "rotlsi3"
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|
+- [(set (match_operand:SI 0 "register_operand" "=r")
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|
+- (rotate:SI (match_operand:SI 1 "register_operand" "r")
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|
+- (match_operand:QI 2 "register_operand" "r")))]
|
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|
+- "TARGET_ZBB"
|
|
|
+- { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
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|
|
+- [(set_attr "type" "bitmanip")])
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|
+-
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|
|
+-(define_insn "rotldi3"
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|
+- [(set (match_operand:DI 0 "register_operand" "=r")
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|
+- (rotate:DI (match_operand:DI 1 "register_operand" "r")
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|
+- (match_operand:QI 2 "register_operand" "r")))]
|
|
|
+- "TARGET_64BIT && TARGET_ZBB"
|
|
|
+- "rol\t%0,%1,%2"
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|
|
+- [(set_attr "type" "bitmanip")])
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|
|
+-
|
|
|
+-(define_insn "rotlsi3_sext"
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|
|
+- [(set (match_operand:DI 0 "register_operand" "=r")
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|
|
+- (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
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|
|
+- (match_operand:QI 2 "register_operand" "r"))))]
|
|
|
+- "TARGET_64BIT && TARGET_ZBB"
|
|
|
+- "rolw\t%0,%1,%2"
|
|
|
+- [(set_attr "type" "bitmanip")])
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|
|
+-
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|
|
+-;;; ??? grev
|
|
|
+-
|
|
|
+-(define_insn "bswapsi2"
|
|
|
+- [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
+- (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
|
|
|
+- "TARGET_ZBB"
|
|
|
+-{
|
|
|
+- if (TARGET_64BIT)
|
|
|
+- return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
|
|
|
+- else
|
|
|
+- return "rev8\t%0,%1";
|
|
|
+-}
|
|
|
+- [(set_attr "type" "bitmanip")])
|
|
|
+-
|
|
|
+-(define_insn "bswapdi2"
|
|
|
+- [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
+- (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
|
|
|
+- "TARGET_64BIT && TARGET_ZBB"
|
|
|
+- "rev8\t%0,%1"
|
|
|
+- [(set_attr "type" "bitmanip")])
|
|
|
+-
|
|
|
+-;;; ??? shfl/unshfl
|
|
|
+-
|
|
|
+-;;; ??? bext/bdep
|
|
|
+-
|
|
|
+-;;; ??? clmul
|
|
|
+-
|
|
|
+-;;; ??? crc
|
|
|
+-
|
|
|
+-;;; ??? bmat
|
|
|
+-
|
|
|
+-;; ??? Can we do this by using the % communtative constraint?
|
|
|
+-
|
|
|
+-;;; ??? cmov
|
|
|
+-
|
|
|
+-;;; ??? fs[lr]
|
|
|
+-
|
|
|
+-(define_insn "*shNadd"
|
|
|
+- [(set (match_operand:X 0 "register_operand" "=r")
|
|
|
+- (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
|
|
|
+- (match_operand:QI 2 "immediate_operand" "I"))
|
|
|
+- (match_operand:X 3 "register_operand" "r")))]
|
|
|
+- "TARGET_ZBA
|
|
|
+- && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
|
|
|
+- "sh%2add\t%0,%1,%3"
|
|
|
+- [(set_attr "type" "bitmanip")])
|
|
|
+-
|
|
|
+-(define_insn "*shNadduw"
|
|
|
+- [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
+- (plus:DI
|
|
|
+- (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
|
|
|
+- (match_operand:QI 2 "immediate_operand" "I"))
|
|
|
+- (match_operand 3 "immediate_operand" ""))
|
|
|
+- (match_operand:DI 4 "register_operand" "r")))]
|
|
|
+- "TARGET_64BIT && TARGET_ZBA
|
|
|
+- && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
|
|
|
+- && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
|
|
|
+- "sh%2add.uw\t%0,%1,%4"
|
|
|
+- [(set_attr "type" "bitmanip")])
|
|
|
+-
|
|
|
+-(define_insn "*add.uw"
|
|
|
+- [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
+- (plus:DI (zero_extend:DI
|
|
|
+- (match_operand:SI 1 "register_operand" "r"))
|
|
|
+- (match_operand:DI 2 "register_operand" "r")))]
|
|
|
+- "TARGET_64BIT && TARGET_ZBA"
|
|
|
+- "add.uw\t%0,%1,%2"
|
|
|
+- [(set_attr "type" "bitmanip")])
|
|
|
+-
|
|
|
+-(define_insn "*slliuw"
|
|
|
+- [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
+- (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
|
|
|
+- (match_operand:QI 2 "immediate_operand" "I"))
|
|
|
+- (match_operand 3 "immediate_operand" "")))]
|
|
|
+- "TARGET_64BIT && TARGET_ZBA
|
|
|
+- && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
|
|
|
+- "slli.uw\t%0,%1,%2"
|
|
|
+- [(set_attr "type" "bitmanip")])
|
|
|
+-
|
|
|
+-;; ??? bfxp
|
|
|
+-
|
|
|
+-;; sext
|
|
|
+-
|
|
|
+-(define_insn "*extend<SHORT:mode><SUPERQI:mode>2_bitmanip"
|
|
|
+- [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
|
|
|
+- (sign_extend:SUPERQI
|
|
|
+- (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))]
|
|
|
+- "TARGET_ZBB"
|
|
|
+- "@
|
|
|
+- sext.<SHORT:size>\t%0,%1
|
|
|
+- l<SHORT:size>\t%0,%1"
|
|
|
+- [(set_attr "type" "bitmanip")
|
|
|
+- (set_attr "length" "4")])
|
|
|
++ [(set_attr "type" "bitmanip")])
|
|
|
+\ No newline at end of file
|
|
|
+--
|
|
|
+2.33.1
|
|
|
+
|