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- From 4bbe6648eb8c452a9dcd77895caf2c3f0d8771f7 Mon Sep 17 00:00:00 2001
- From: "max.ma" <max.ma@starfivetech.com>
- Date: Wed, 19 May 2021 02:19:34 -0700
- Subject: [PATCH 02/28] Add support for B extension
- ---
- bfd/elfxx-riscv.c | 2 +-
- gas/config/tc-riscv.c | 31 +++
- gas/testsuite/gas/riscv/b-ext-64.d | 117 +++++++++++
- gas/testsuite/gas/riscv/b-ext-64.s | 108 ++++++++++
- gas/testsuite/gas/riscv/b-ext.d | 74 +++++++
- gas/testsuite/gas/riscv/b-ext.s | 65 +++++++
- include/opcode/riscv-opc.h | 303 +++++++++++++++++++++++++++++
- include/opcode/riscv.h | 15 ++
- opcodes/riscv-dis.c | 4 +
- opcodes/riscv-opc.c | 139 +++++++++++++
- 10 files changed, 857 insertions(+), 1 deletion(-)
- create mode 100755 gas/testsuite/gas/riscv/b-ext-64.d
- create mode 100755 gas/testsuite/gas/riscv/b-ext-64.s
- create mode 100755 gas/testsuite/gas/riscv/b-ext.d
- create mode 100755 gas/testsuite/gas/riscv/b-ext.s
- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
- index 0d5bec4762..8c8af2386b 100644
- --- a/bfd/elfxx-riscv.c
- +++ b/bfd/elfxx-riscv.c
- @@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
-
- static const char * const riscv_std_z_ext_strtab[] =
- {
- - "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg", NULL
- + "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt", "zvamo", "zvlsseg",NULL
- };
-
- static const char * const riscv_std_s_ext_strtab[] =
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index 3322f17ccb..3e76e538c4 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -253,6 +253,37 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
- case INSN_CLASS_ZIHINTPAUSE:
- return riscv_subset_supports ("zihintpause");
-
- + case INSN_CLASS_ZBB:
- + return riscv_subset_supports ("zbb");
- + case INSN_CLASS_ZBA:
- + return riscv_subset_supports ("zba");
- + case INSN_CLASS_ZBC:
- + return riscv_subset_supports ("zbc");
- + case INSN_CLASS_ZBE:
- + return riscv_subset_supports ("zbe");
- + case INSN_CLASS_ZBF:
- + return riscv_subset_supports ("zbf");
- + case INSN_CLASS_ZBM:
- + return riscv_subset_supports ("zbm");
- + case INSN_CLASS_ZBP:
- + return riscv_subset_supports ("zbp");
- + case INSN_CLASS_ZBR:
- + return riscv_subset_supports ("zbr");
- + case INSN_CLASS_ZBS:
- + return riscv_subset_supports ("zbs");
- + case INSN_CLASS_ZBT:
- + return riscv_subset_supports ("zbt");
- + case INSN_CLASS_ZBB_OR_ZBP:
- + return (riscv_subset_supports ("zbb") || riscv_subset_supports ("zbp"));
- + case INSN_CLASS_ZBS_OR_ZBE:
- + return (riscv_subset_supports ("zbs") || riscv_subset_supports ("zbe"));
- + case INSN_CLASS_ZBP_OR_ZBM:
- + return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbm"));
- + case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF:
- + return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
- + case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
- + return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
- +
- default:
- as_fatal ("Unreachable");
- return FALSE;
- diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
- new file mode 100755
- index 0000000000..23da2e0d58
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/b-ext-64.d
- @@ -0,0 +1,117 @@
- +#as: -march=rv64i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
- +#source: b-ext-64.s
- +#objdump: -d
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <target>:
- +[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
- +[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
- +[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
- +[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
- +[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
- +[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
- +[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
- +[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
- +[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
- +[ ]+24:[ ]+0805453b[ ]+zext.h[ ]+a0,a0
- +[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
- +[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
- +[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
- +[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
- +[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
- +[ ]+3c:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
- +[ ]+40:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
- +[ ]+44:[ ]+6b855513[ ]+rev8[ ]+a0,a0
- +[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
- +[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
- +[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
- +[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
- +[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
- +[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
- +[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
- +[ ]+64:[ ]+6005151b[ ]+clzw[ ]+a0,a0
- +[ ]+68:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
- +[ ]+6c:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
- +[ ]+70:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
- +[ ]+74:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
- +[ ]+78:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
- +[ ]+7c:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
- +[ ]+80:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
- +[ ]+84:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
- +[ ]+88:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
- +[ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
- +[ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
- +[ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
- +[ ]+98:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
- +[ ]+9c:[ ]+48c5c533[ ]+packu[ ]+a0,a1,a2
- +[ ]+a0:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
- +[ ]+a4:[ ]+0825c53b[ ]+packw[ ]+a0,a1,0x2
- +[ ]+a8:[ ]+4825c53b[ ]+packuw[ ]+a0,a1,0x2
- +[ ]+ac:[ ]+68c5d533[ ]+grev[ ]+a0,a1,a2
- +[ ]+b0:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
- +[ ]+b4:[ ]+6825d53b[ ]+grevw[ ]+a0,a1,0x2
- +[ ]+b8:[ ]+6825d51b[ ]+greviw[ ]+a0,a1,0x2
- +[ ]+bc:[ ]+28c5d533[ ]+gorc[ ]+a0,a1,a2
- +[ ]+c0:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
- +[ ]+c4:[ ]+2825d53b[ ]+gorcw[ ]+a0,a1,0x2
- +[ ]+c8:[ ]+2825d51b[ ]+gorciw[ ]+a0,a1,0x2
- +[ ]+cc:[ ]+08c59533[ ]+shfl[ ]+a0,a1,a2
- +[ ]+d0:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
- +[ ]+d4:[ ]+0825953b[ ]+shflw[ ]+a0,a1,0x2
- +[ ]+d8:[ ]+08c5d533[ ]+unshfl[ ]+a0,a1,a2
- +[ ]+dc:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
- +[ ]+e0:[ ]+0825d53b[ ]+unshflw[ ]+a0,a1,0x2
- +[ ]+e4:[ ]+28c5a533[ ]+xperm.n[ ]+a0,a1,a2
- +[ ]+e8:[ ]+28c5c533[ ]+xperm.b[ ]+a0,a1,a2
- +[ ]+ec:[ ]+28c5e533[ ]+xperm.h[ ]+a0,a1,a2
- +[ ]+f0:[ ]+28258533[ ]+xperm.w[ ]+a0,a1,0x2
- +[ ]+f4:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
- +[ ]+f8:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
- +[ ]+fc:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
- +[ ]+100:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
- +[ ]+104:[ ]+48c5e533[ ]+bdep[ ]+a0,a1,a2
- +[ ]+108:[ ]+28259513[ ]+bseti[ ]+a0,a1,0x2
- +[ ]+10c:[ ]+48259513[ ]+bclri[ ]+a0,a1,0x2
- +[ ]+110:[ ]+68259513[ ]+binvi[ ]+a0,a1,0x2
- +[ ]+114:[ ]+4825d513[ ]+bexti[ ]+a0,a1,0x2
- +[ ]+118:[ ]+28c5953b[ ]+bsetw[ ]+a0,a1,a2
- +[ ]+11c:[ ]+48c5953b[ ]+bclrw[ ]+a0,a1,a2
- +[ ]+120:[ ]+68c5953b[ ]+binvw[ ]+a0,a1,a2
- +[ ]+124:[ ]+48c5d53b[ ]+bextw[ ]+a0,a1,a2
- +[ ]+128:[ ]+4825e53b[ ]+bdepw[ ]+a0,a1,0x2
- +[ ]+12c:[ ]+2825951b[ ]+bsetiw[ ]+a0,a1,0x2
- +[ ]+130:[ ]+4825951b[ ]+bclriw[ ]+a0,a1,0x2
- +[ ]+134:[ ]+6825951b[ ]+binviw[ ]+a0,a1,0x2
- +[ ]+138:[ ]+20c59533[ ]+slo[ ]+a0,a1,a2
- +[ ]+13c:[ ]+20c5d533[ ]+sro[ ]+a0,a1,a2
- +[ ]+140:[ ]+20259513[ ]+sloi[ ]+a0,a1,0x2
- +[ ]+144:[ ]+2025d513[ ]+sroi[ ]+a0,a1,0x2
- +[ ]+148:[ ]+2025953b[ ]+slow[ ]+a0,a1,0x2
- +[ ]+14c:[ ]+2025d53b[ ]+srow[ ]+a0,a1,0x2
- +[ ]+150:[ ]+2025951b[ ]+sloiw[ ]+a0,a1,0x2
- +[ ]+154:[ ]+2025d51b[ ]+sroiw[ ]+a0,a1,0x2
- +[ ]+158:[ ]+48c5f533[ ]+bfp[ ]+a0,a1,a2
- +[ ]+15c:[ ]+4825f53b[ ]+bfpw[ ]+a0,a1,0x2
- +[ ]+160:[ ]+08c5b533[ ]+bmator[ ]+a0,a1,a2
- +[ ]+164:[ ]+48c5b533[ ]+bmatxor[ ]+a0,a1,a2
- +[ ]+168:[ ]+60351513[ ]+bmatflip[ ]+a0,a0
- +[ ]+16c:[ ]+61051513[ ]+crc32.b[ ]+a0,a0
- +[ ]+170:[ ]+61151513[ ]+crc32.h[ ]+a0,a0
- +[ ]+174:[ ]+61251513[ ]+crc32.w[ ]+a0,a0
- +[ ]+178:[ ]+61851513[ ]+crc32c.b[ ]+a0,a0
- +[ ]+17c:[ ]+61951513[ ]+crc32c.h[ ]+a0,a0
- +[ ]+180:[ ]+61a51513[ ]+crc32c.w[ ]+a0,a0
- +[ ]+184:[ ]+61351513[ ]+crc32.d[ ]+a0,a0
- +[ ]+188:[ ]+61b51513[ ]+crc32c.d[ ]+a0,a0
- +[ ]+18c:[ ]+6ec59533[ ]+cmix[ ]+a0,a1,a2,a3
- +[ ]+190:[ ]+6ec5d533[ ]+cmov[ ]+a0,a1,a2,a3
- +[ ]+194:[ ]+6cc59533[ ]+fsl[ ]+a0,a1,a2,a3
- +[ ]+198:[ ]+6cc5d533[ ]+fsr[ ]+a0,a1,a2,a3
- +[ ]+19c:[ ]+6c25d513[ ]+fsri[ ]+a0,a1,0x2,a3
- +[ ]+1a0:[ ]+6c25953b[ ]+fslw[ ]+a0,a1,0x2,a3
- +[ ]+1a4:[ ]+6c25b53b[ ]+fsrw[ ]+a0,a1,0x2,a3
- +[ ]+1a8:[ ]+6c25b51b[ ]+fsriw[ ]+a0,a1,0x2,a3
- diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
- new file mode 100755
- index 0000000000..176d617be5
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/b-ext-64.s
- @@ -0,0 +1,108 @@
- +target:
- + clz a0, a0
- + ctz a0, a0
- + cpop a0, a0
- + min a0, a1, a2
- + minu a0, a1, a2
- + max a0, a1, a2
- + maxu a0, a1, a2
- + sext.b a0, a0
- + sext.h a0, a0
- + zext.h a0, a0
- + andn a0, a1, a2
- + orn a0, a1, a2
- + xnor a0, a1, a2
- + rol a0, a1, a2
- + ror a0, a1, a2
- + ror a0, a1, 2
- + rori a0, a1, 2
- + rev8 a0, a0
- + orc.b a0, a0
- + sh1add a0, a1, a2
- + sh2add a0, a1, a2
- + sh3add a0, a1, a2
- + clmul a0, a1, a2
- + clmulh a0, a1, a2
- + clmulr a0, a1, a2
- + clzw a0, a0
- + ctzw a0, a0
- + cpopw a0, a0
- + rolw a0, a1, a2
- + rorw a0, a1, a2
- + rorw a0, a1, 2
- + roriw a0, a1, 2
- + sh1add.uw a0, a1, a2
- + sh2add.uw a0, a1, a2
- + sh3add.uw a0, a1, a2
- + add.uw a0, a1, a2
- + zext.w a0, a1
- + slli.uw a0, a1, 2
- + pack a0, a1, a2
- + packu a0, a1, a2
- + packh a0, a1, a2
- + packw a0, a1, 2
- + packuw a0, a1, 2
- + grev a0, a1, a2
- + grevi a0, a1, 2
- + grevw a0, a1, 2
- + greviw a0, a1, 2
- + gorc a0, a1, a2
- + gorci a0, a1, 2
- + gorcw a0, a1, 2
- + gorciw a0, a1, 2
- + shfl a0, a1, a2
- + shfli a0, a1, 2
- + shflw a0, a1, 2
- + unshfl a0, a1, a2
- + unshfli a0, a1, 2
- + unshflw a0, a1, 2
- + xperm.n a0, a1, a2
- + xperm.b a0, a1, a2
- + xperm.h a0, a1, a2
- + xperm.w a0, a1, 2
- + bset a0, a1, a2
- + bclr a0, a1, a2
- + binv a0, a1, a2
- + bext a0, a1, a2
- + bdep a0, a1, a2
- + bseti a0, a1, 2
- + bclri a0, a1, 2
- + binvi a0, a1, 2
- + bexti a0, a1, 2
- + bsetw a0, a1, a2
- + bclrw a0, a1, a2
- + binvw a0, a1, a2
- + bextw a0, a1, a2
- + bdepw a0, a1, 2
- + bsetiw a0, a1, 2
- + bclriw a0, a1, 2
- + binviw a0, a1, 2
- + slo a0, a1, a2
- + sro a0, a1, a2
- + sloi a0, a1, 2
- + sroi a0, a1, 2
- + slow a0, a1, 2
- + srow a0, a1, 2
- + sloiw a0, a1, 2
- + sroiw a0, a1, 2
- + bfp a0, a1, a2
- + bfpw a0, a1, 2
- + bmator a0, a1, a2
- + bmatxor a0, a1, a2
- + bmatflip a0, a0
- + crc32.b a0, a0
- + crc32.h a0, a0
- + crc32.w a0, a0
- + crc32c.b a0, a0
- + crc32c.h a0, a0
- + crc32c.w a0, a0
- + crc32.d a0, a0
- + crc32c.d a0, a0
- + cmix a0, a1, a2, a3
- + cmov a0, a1, a2, a3
- + fsl a0, a1, a2, a3
- + fsr a0, a1, a2, a3
- + fsri a0, a1, 2, a3
- + fslw a0, a1, 2, a3
- + fsrw a0, a1, 2, a3
- + fsriw a0, a1, 2, a3
- diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
- new file mode 100755
- index 0000000000..4df9e90693
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/b-ext.d
- @@ -0,0 +1,74 @@
- +#as: -march=rv32i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
- +#source: b-ext.s
- +#objdump: -d
- +
- +.*:[ ]+file format .*
- +
- +
- +Disassembly of section .text:
- +
- +0+000 <target>:
- +[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
- +[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
- +[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
- +[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
- +[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
- +[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
- +[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
- +[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
- +[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
- +[ ]+24:[ ]+08054533[ ]+zext.h[ ]+a0,a0
- +[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
- +[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
- +[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
- +[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
- +[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
- +[ ]+3c:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
- +[ ]+40:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
- +[ ]+44:[ ]+69855513[ ]+rev8[ ]+a0,a0
- +[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
- +[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
- +[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
- +[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
- +[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
- +[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
- +[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
- +[ ]+64:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
- +[ ]+68:[ ]+48c5c533[ ]+packu[ ]+a0,a1,a2
- +[ ]+6c:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
- +[ ]+70:[ ]+68c5d533[ ]+grev[ ]+a0,a1,a2
- +[ ]+74:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
- +[ ]+78:[ ]+28c5d533[ ]+gorc[ ]+a0,a1,a2
- +[ ]+7c:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
- +[ ]+80:[ ]+08c59533[ ]+shfl[ ]+a0,a1,a2
- +[ ]+84:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
- +[ ]+88:[ ]+08c5d533[ ]+unshfl[ ]+a0,a1,a2
- +[ ]+8c:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
- +[ ]+90:[ ]+28c5a533[ ]+xperm.n[ ]+a0,a1,a2
- +[ ]+94:[ ]+28c5c533[ ]+xperm.b[ ]+a0,a1,a2
- +[ ]+98:[ ]+28c5e533[ ]+xperm.h[ ]+a0,a1,a2
- +[ ]+9c:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
- +[ ]+a0:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
- +[ ]+a4:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
- +[ ]+a8:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
- +[ ]+ac:[ ]+48c5e533[ ]+bdep[ ]+a0,a1,a2
- +[ ]+b0:[ ]+28259513[ ]+bseti[ ]+a0,a1,0x2
- +[ ]+b4:[ ]+48259513[ ]+bclri[ ]+a0,a1,0x2
- +[ ]+b8:[ ]+68259513[ ]+binvi[ ]+a0,a1,0x2
- +[ ]+bc:[ ]+4825d513[ ]+bexti[ ]+a0,a1,0x2
- +[ ]+c0:[ ]+20c59533[ ]+slo[ ]+a0,a1,a2
- +[ ]+c4:[ ]+20c5d533[ ]+sro[ ]+a0,a1,a2
- +[ ]+c8:[ ]+20259513[ ]+sloi[ ]+a0,a1,0x2
- +[ ]+cc:[ ]+2025d513[ ]+sroi[ ]+a0,a1,0x2
- +[ ]+d0:[ ]+48c5f533[ ]+bfp[ ]+a0,a1,a2
- +[ ]+d4:[ ]+61051513[ ]+crc32.b[ ]+a0,a0
- +[ ]+d8:[ ]+61151513[ ]+crc32.h[ ]+a0,a0
- +[ ]+dc:[ ]+61251513[ ]+crc32.w[ ]+a0,a0
- +[ ]+e0:[ ]+61851513[ ]+crc32c.b[ ]+a0,a0
- +[ ]+e4:[ ]+61951513[ ]+crc32c.h[ ]+a0,a0
- +[ ]+e8:[ ]+61a51513[ ]+crc32c.w[ ]+a0,a0
- +[ ]+ec:[ ]+6ec59533[ ]+cmix[ ]+a0,a1,a2,a3
- +[ ]+f0:[ ]+6ec5d533[ ]+cmov[ ]+a0,a1,a2,a3
- +[ ]+f4:[ ]+6cc59533[ ]+fsl[ ]+a0,a1,a2,a3
- +[ ]+f8:[ ]+6cc5d533[ ]+fsr[ ]+a0,a1,a2,a3
- +[ ]+fc:[ ]+6c25d513[ ]+fsri[ ]+a0,a1,0x2,a3
- diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
- new file mode 100755
- index 0000000000..429c005849
- --- /dev/null
- +++ b/gas/testsuite/gas/riscv/b-ext.s
- @@ -0,0 +1,65 @@
- +target:
- + clz a0, a0
- + ctz a0, a0
- + cpop a0, a0
- + min a0, a1, a2
- + minu a0, a1, a2
- + max a0, a1, a2
- + maxu a0, a1, a2
- + sext.b a0, a0
- + sext.h a0, a0
- + zext.h a0, a0
- + andn a0, a1, a2
- + orn a0, a1, a2
- + xnor a0, a1, a2
- + rol a0, a1, a2
- + ror a0, a1, a2
- + ror a0, a1, 2
- + rori a0, a1, 2
- + rev8 a0, a0
- + orc.b a0, a0
- + sh1add a0, a1, a2
- + sh2add a0, a1, a2
- + sh3add a0, a1, a2
- + clmul a0, a1, a2
- + clmulh a0, a1, a2
- + clmulr a0, a1, a2
- + pack a0, a1, a2
- + packu a0, a1, a2
- + packh a0, a1, a2
- + grev a0, a1, a2
- + grevi a0, a1, 2
- + gorc a0, a1, a2
- + gorci a0, a1, 2
- + shfl a0, a1, a2
- + shfli a0, a1, 2
- + unshfl a0, a1, a2
- + unshfli a0, a1, 2
- + xperm.n a0, a1, a2
- + xperm.b a0, a1, a2
- + xperm.h a0, a1, a2
- + bset a0, a1, a2
- + bclr a0, a1, a2
- + binv a0, a1, a2
- + bext a0, a1, a2
- + bdep a0, a1, a2
- + bseti a0, a1, 2
- + bclri a0, a1, 2
- + binvi a0, a1, 2
- + bexti a0, a1, 2
- + slo a0, a1, a2
- + sro a0, a1, a2
- + sloi a0, a1, 2
- + sroi a0, a1, 2
- + bfp a0, a1, a2
- + crc32.b a0, a0
- + crc32.h a0, a0
- + crc32.w a0, a0
- + crc32c.b a0, a0
- + crc32c.h a0, a0
- + crc32c.w a0, a0
- + cmix a0, a1, a2, a3
- + cmov a0, a1, a2, a3
- + fsl a0, a1, a2, a3
- + fsr a0, a1, a2, a3
- + fsri a0, a1, 2, a3
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index b0e549a0f2..1a9e313fc3 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -113,6 +113,18 @@
- #define MASK_SRL 0xfe00707f
- #define MATCH_SRA 0x40005033
- #define MASK_SRA 0xfe00707f
- +#define MATCH_SLO 0x20001033
- +#define MASK_SLO 0xfe00707f
- +#define MATCH_SLOI 0x20001013
- +#define MASK_SLOI 0xfc00707f
- +#define MATCH_SLOW 0x2000103b
- +#define MASK_SLOW 0xfe00707f
- +#define MATCH_SRO 0x20005033
- +#define MASK_SRO 0xfe00707f
- +#define MATCH_SROI 0x20005013
- +#define MASK_SROI 0xfc00707f
- +#define MATCH_SROW 0x2000503b
- +#define MASK_SROW 0xfe00707f
- #define MATCH_OR 0x6033
- #define MASK_OR 0xfe00707f
- #define MATCH_AND 0x7033
- @@ -423,6 +435,196 @@
- #define MASK_FCVT_Q_LU 0xfff0007f
- #define MATCH_FMV_Q_X 0xf6000053
- #define MASK_FMV_Q_X 0xfff0707f
- +#define MATCH_CLZ 0x60001013
- +#define MASK_CLZ 0xfff0707f
- +#define MATCH_CTZ 0x60101013
- +#define MASK_CTZ 0xfff0707f
- +#define MATCH_CPOP 0x60201013
- +#define MASK_CPOP 0xfff0707f
- +#define MATCH_BMATFLIP 0x60301013
- +#define MASK_BMATFLIP 0xfff0707f
- +#define MATCH_CRC32_B 0x61001013
- +#define MASK_CRC32_B 0xfff0707f
- +#define MATCH_CRC32_H 0x61101013
- +#define MASK_CRC32_H 0xfff0707f
- +#define MATCH_CRC32_W 0x61201013
- +#define MASK_CRC32_W 0xfff0707f
- +#define MATCH_CRC32_D 0x61301013
- +#define MASK_CRC32_D 0xfff0707f
- +#define MATCH_CRC32C_B 0x61801013
- +#define MASK_CRC32C_B 0xfff0707f
- +#define MATCH_CRC32C_H 0x61901013
- +#define MASK_CRC32C_H 0xfff0707f
- +#define MATCH_CRC32C_W 0x61A01013
- +#define MASK_CRC32C_W 0xfff0707f
- +#define MATCH_CRC32C_D 0x61B01013
- +#define MASK_CRC32C_D 0xfff0707f
- +#define MATCH_MIN 0xa004033
- +#define MASK_MIN 0xfe00707f
- +#define MATCH_MINU 0xa005033
- +#define MASK_MINU 0xfe00707f
- +#define MATCH_MAX 0xa006033
- +#define MASK_MAX 0xfe00707f
- +#define MATCH_MAXU 0xa007033
- +#define MASK_MAXU 0xfe00707f
- +#define MATCH_SHFL 0x8001033
- +#define MASK_SHFL 0xfe00707f
- +#define MATCH_SHFLI 0x8001013
- +#define MASK_SHFLI 0xfc00707f
- +#define MATCH_UNSHFL 0x8005033
- +#define MASK_UNSHFL 0xfe00707f
- +#define MATCH_UNSHFLI 0x8005013
- +#define MASK_UNSHFLI 0xfc00707f
- +#define MATCH_BDEP 0x48006033
- +#define MASK_BDEP 0xfe00707f
- +#define MATCH_SEXT_B 0x60401013
- +#define MASK_SEXT_B 0xfff0707f
- +#define MATCH_SEXT_H 0x60501013
- +#define MASK_SEXT_H 0xfff0707f
- +#define MATCH_PACK 0x8004033
- +#define MASK_PACK 0xfe00707f
- +#define MATCH_PACKU 0x48004033
- +#define MASK_PACKU 0xfe00707f
- +#define MATCH_BMATOR 0x8003033
- +#define MASK_BMATOR 0xfe00707f
- +#define MATCH_BMATXOR 0x48003033
- +#define MASK_BMATXOR 0xfe00707f
- +#define MATCH_PACKH 0x8007033
- +#define MASK_PACKH 0xfe00707f
- +#define MATCH_BFP 0x48007033
- +#define MASK_BFP 0xfe00707f
- +#define MATCH_PACKW 0x800403b
- +#define MASK_PACKW 0xfe00707f
- +#define MATCH_PACKUW 0x4800403b
- +#define MASK_PACKUW 0xfe00707f
- +#define MATCH_ANDN 0x40007033
- +#define MASK_ANDN 0xfe00707f
- +#define MATCH_ORN 0x40006033
- +#define MASK_ORN 0xfe00707f
- +#define MATCH_XNOR 0x40004033
- +#define MASK_XNOR 0xfe00707f
- +#define MATCH_ROL 0x60001033
- +#define MASK_ROL 0xfe00707f
- +#define MATCH_ROR 0x60005033
- +#define MASK_ROR 0xfe00707f
- +#define MATCH_RORI 0x60005013
- +#define MASK_RORI 0xfc00707f
- +#define MATCH_BCLR 0x48001033
- +#define MASK_BCLR 0xfe00707f
- +#define MATCH_BCLRI 0x48001013
- +#define MASK_BCLRI 0xfc00707f
- +#define MATCH_BSET 0x28001033
- +#define MASK_BSET 0xfe00707f
- +#define MATCH_BSETI 0x28001013
- +#define MASK_BSETI 0xfc00707f
- +#define MATCH_BINV 0x68001033
- +#define MASK_BINV 0xfe00707f
- +#define MATCH_BINVI 0x68001013
- +#define MASK_BINVI 0xfc00707f
- +#define MATCH_BEXT 0x48005033
- +#define MASK_BEXT 0xfe00707f
- +#define MATCH_BEXTI 0x48005013
- +#define MASK_BEXTI 0xfc00707f
- +#define MATCH_GREV 0x68005033
- +#define MASK_GREV 0xfe00707f
- +#define MATCH_GREVI 0x68005013
- +#define MASK_GREVI 0xfc00707f
- +#define MATCH_GORC 0x28005033
- +#define MASK_GORC 0xfe00707f
- +#define MATCH_GORCI 0x28005013
- +#define MASK_GORCI 0xfc00707f
- +#define MATCH_CMIX 0x6001033
- +#define MASK_CMIX 0x600707f
- +#define MATCH_CMOV 0x6005033
- +#define MASK_CMOV 0x600707f
- +#define MATCH_FSL 0x4001033
- +#define MASK_FSL 0x600707f
- +#define MATCH_FSR 0x4005033
- +#define MASK_FSR 0x600707f
- +#define MATCH_FSRI 0x4005013
- +#define MASK_FSRI 0x400707f
- +#define MATCH_CLZW 0x6000101b
- +#define MASK_CLZW 0xfff0707f
- +#define MATCH_CTZW 0x6010101b
- +#define MASK_CTZW 0xfff0707f
- +#define MATCH_CPOPW 0x6020101b
- +#define MASK_CPOPW 0xfff0707f
- +#define MATCH_ROLW 0x6000103b
- +#define MASK_ROLW 0xfe00707f
- +#define MATCH_RORW 0x6000503b
- +#define MASK_RORW 0xfe00707f
- +#define MATCH_RORIW 0x6000501b
- +#define MASK_RORIW 0xfe00707f
- +#define MATCH_SH1ADD 0x20002033
- +#define MASK_SH1ADD 0xfe00707f
- +#define MATCH_SH2ADD 0x20004033
- +#define MASK_SH2ADD 0xfe00707f
- +#define MATCH_SH3ADD 0x20006033
- +#define MASK_SH3ADD 0xfe00707f
- +#define MATCH_SH1ADD_UW 0x2000203b
- +#define MASK_SH1ADD_UW 0xfe00707f
- +#define MATCH_SH2ADD_UW 0x2000403b
- +#define MASK_SH2ADD_UW 0xfe00707f
- +#define MATCH_SH3ADD_UW 0x2000603b
- +#define MASK_SH3ADD_UW 0xfe00707f
- +#define MATCH_BCLRW 0x4800103b
- +#define MASK_BCLRW 0xfe00707f
- +#define MATCH_BSETW 0x2800103b
- +#define MASK_BSETW 0xfe00707f
- +#define MATCH_BINVW 0x6800103b
- +#define MASK_BINVW 0xfe00707f
- +#define MATCH_BEXTW 0x4800503b
- +#define MASK_BEXTW 0xfe00707f
- +#define MATCH_GORCW 0x2800503b
- +#define MASK_GORCW 0xfe00707f
- +#define MATCH_GREVW 0x6800503b
- +#define MASK_GREVW 0xfe00707f
- +#define MATCH_SLOIW 0x2000101b
- +#define MASK_SLOIW 0xfe00707f
- +#define MATCH_SROIW 0x2000501b
- +#define MASK_SROIW 0xfe00707f
- +#define MATCH_BCLRIW 0x4800101b
- +#define MASK_BCLRIW 0xfe00707f
- +#define MATCH_BSETIW 0x2800101b
- +#define MASK_BSETIW 0xfe00707f
- +#define MATCH_BINVIW 0x6800101b
- +#define MASK_BINVIW 0xfe00707f
- +#define MATCH_GORCIW 0x2800501b
- +#define MASK_GORCIW 0xfe00707f
- +#define MATCH_GREVIW 0x6800501b
- +#define MASK_GREVIW 0xfe00707f
- +#define MATCH_FSLW 0x400103b
- +#define MASK_FSLW 0x600707f
- +#define MATCH_FSRW 0x400303b
- +#define MASK_FSRW 0x600707f
- +#define MATCH_FSRIW 0x400301b
- +#define MASK_FSRIW 0x600707f
- +#define MATCH_SHFLW 0x800103b
- +#define MASK_SHFLW 0xfe00707f
- +#define MATCH_UNSHFLW 0x800503b
- +#define MASK_UNSHFLW 0xfe00707f
- +#define MATCH_BDEPW 0x4800603b
- +#define MASK_BDEPW 0xfe00707f
- +#define MATCH_BFPW 0x4800703b
- +#define MASK_BFPW 0xfe00707f
- +#define MATCH_XPERM_N 0x28002033
- +#define MASK_XPERM_N 0xfe00707f
- +#define MATCH_XPERM_B 0x28004033
- +#define MASK_XPERM_B 0xfe00707f
- +#define MATCH_XPERM_H 0x28006033
- +#define MASK_XPERM_H 0xfe00707f
- +#define MATCH_XPERM_W 0x28000033
- +#define MASK_XPERM_W 0xfe00707f
- +#define MATCH_ADD_UW 0x800003b
- +#define MASK_ADD_UW 0xfe00707f
- +#define MATCH_SLLI_UW 0x800101b
- +#define MASK_SLLI_UW 0xfc00707f
- +#define MATCH_CLMUL 0xa001033
- +#define MASK_CLMUL 0xfe00707f
- +#define MATCH_CLMULH 0xa003033
- +#define MASK_CLMULH 0xfe00707f
- +#define MATCH_CLMULR 0xa002033
- +#define MASK_CLMULR 0xfe00707f
- #define MATCH_FLW 0x2007
- #define MASK_FLW 0x707f
- #define MATCH_FLD 0x3007
- @@ -1046,6 +1248,107 @@ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
- DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
- DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
- DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
- +DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
- +DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
- +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
- +DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
- +DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
- +DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
- +DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
- +DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
- +DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
- +DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
- +DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
- +DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
- +DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
- +DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
- +DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
- +DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
- +DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
- +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
- +DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
- +DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
- +DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
- +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
- +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
- +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
- +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
- +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
- +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
- +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
- +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
- +DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
- +DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
- +DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
- +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
- +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
- +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
- +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
- +DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
- +DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
- +DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
- +DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
- +DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
- +DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
- +DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
- +DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
- +DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
- +DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
- +DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
- +DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
- +DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
- +DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
- +DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
- +DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
- +DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
- +DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
- +DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
- +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
- +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
- +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
- +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
- +DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
- +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
- +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
- +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
- +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
- +DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
- +DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
- +DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
- +DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
- +DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
- +DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
- +DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
- +DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
- +DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
- +DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
- +DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
- +DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
- +DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
- +DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
- +DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
- +DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
- +DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
- +DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
- +DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
- +DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
- +DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
- +DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
- +DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
- +DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
- +DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
- +DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
- +DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
- +DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
- +DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
- +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
- +DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
- +DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
- +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
- +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
- +DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
- +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
- +DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
- DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
- DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
- DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
- diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
- index caaaea5162..87d1aedb40 100644
- --- a/include/opcode/riscv.h
- +++ b/include/opcode/riscv.h
- @@ -312,6 +312,21 @@ enum riscv_insn_class
- INSN_CLASS_ZICSR,
- INSN_CLASS_ZIFENCEI,
- INSN_CLASS_ZIHINTPAUSE,
- + INSN_CLASS_ZBA,
- + INSN_CLASS_ZBB,
- + INSN_CLASS_ZBC,
- + INSN_CLASS_ZBP,
- + INSN_CLASS_ZBB_OR_ZBP,
- + INSN_CLASS_ZBS,
- + INSN_CLASS_ZBE,
- + INSN_CLASS_ZBS_OR_ZBE,
- + INSN_CLASS_ZBF,
- + INSN_CLASS_ZBM,
- + INSN_CLASS_ZBP_OR_ZBM,
- + INSN_CLASS_ZBR,
- + INSN_CLASS_ZBT,
- + INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
- + INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
- };
-
- /* This structure holds information for a particular instruction. */
- diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
- index c3d9bb8745..a169d013c4 100644
- --- a/opcodes/riscv-dis.c
- +++ b/opcodes/riscv-dis.c
- @@ -238,6 +238,10 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
- info->target = EXTRACT_RVC_J_IMM (l) + pc;
- (*info->print_address_func) (info->target, info);
- break;
- + case 'r':
- + print (info->stream, "%s",
- + riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
- + break;
- case 'u':
- print (info->stream, "0x%x",
- (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index a2ea66a723..d73c980acd 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -24,6 +24,11 @@
- #include "opcode/riscv.h"
- #include <stdio.h>
-
- +#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
- +#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
- +#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
- +#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
- +
- /* Register names used by gas and objdump. */
-
- const char * const riscv_gpr_names_numeric[NGPR] =
- @@ -786,6 +791,127 @@ const struct riscv_opcode riscv_opcodes[] =
- {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
- {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
-
- +
- +/* RVB instructions. */
- +{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
- +{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
- +{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
- +{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
- +{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
- +{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
- +{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
- +{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
- +{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
- +{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
- +{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
- +{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
- +{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
- +{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
- +{"andn", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
- +{"orn", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
- +{"xnor", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
- +{"rol", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
- +{"rori", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
- +{"ror", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
- +{"ror", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
- +{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
- +{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
- +{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
- +{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
- +{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
- +{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
- +{"rolw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
- +{"roriw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
- +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
- +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
- +{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
- +{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
- +{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
- +{"sh1add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
- +{"sh2add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
- +{"sh3add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
- +{"zext.w", 64, INSN_CLASS_ZBA, "d,s", MATCH_ADD_UW, MASK_ADD_UW|MASK_RS2, match_opcode, INSN_ALIAS },
- +{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
- +{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
- +{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
- +{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
- +{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
- +{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
- +
- +{"pack", 0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
- +{"packu", 0, INSN_CLASS_ZBP_OR_ZBM, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
- +{"packh", 0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
- +{"packw", 64, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF, "d,s,<", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
- +{"packuw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
- +{"grev", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
- +{"grevi", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
- +{"grevw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
- +{"greviw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
- +{"gorc", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
- +{"gorci", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
- +{"gorcw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
- +{"gorciw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
- +{"shfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
- +{"shfli", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
- +{"shflw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
- +{"unshfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
- +{"unshfli", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
- +{"unshflw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
- +{"xperm.n", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
- +{"xperm.b", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
- +{"xperm.h", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
- +{"xperm.w", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
- +
- +{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
- +{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
- +{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
- +{"bext", 0, INSN_CLASS_ZBS_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
- +{"bdep", 0, INSN_CLASS_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
- +{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
- +{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
- +{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
- +{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
- +{"bsetw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
- +{"bclrw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
- +{"binvw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
- +{"bextw", 64, INSN_CLASS_ZBS_OR_ZBE, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
- +{"bdepw", 64, INSN_CLASS_ZBE, "d,s,<", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
- +{"bsetiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
- +{"bclriw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
- +{"binviw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
- +{"slo", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_SLO, MASK_SLO, match_opcode, 0 },
- +{"sro", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_SRO, MASK_SRO, match_opcode, 0 },
- +{"sloi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
- +{"sroi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, 0 },
- +{"slow", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
- +{"srow", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SROW, MASK_SROW, match_opcode, 0 },
- +{"sloiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
- +{"sroiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
- +
- +{"bfp", 0, INSN_CLASS_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
- +{"bfpw", 64, INSN_CLASS_ZBF, "d,s,<", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
- +
- +{"bmator", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
- +{"bmatxor", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
- +{"bmatflip", 64, INSN_CLASS_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
- +
- +{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
- +{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
- +{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
- +{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
- +{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
- +{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
- +{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
- +{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
- +
- +{"cmix", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
- +{"cmov", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
- +{"fsl", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_FSL, MASK_FSL, match_opcode, 0 },
- +{"fsr", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_FSR, MASK_FSR, match_opcode, 0 },
- +{"fsri", 0, INSN_CLASS_ZBT, "d,s,>,r", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
- +{"fslw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
- +{"fsrw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
- +{"fsriw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
- /* Terminate the list. */
- {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
- };
- @@ -935,6 +1061,19 @@ const struct riscv_ext_version riscv_ext_version_table[] =
-
- {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
-
- +{"b", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbe", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbf", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbm", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbp", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbr", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbs", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +{"zbt", ISA_SPEC_CLASS_DRAFT, 0, 93},
- +
- +
- /* Terminate the list. */
- {NULL, 0, 0, 0}
- };
- --
- 2.33.0
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