0002-Add-support-for-B-extension.patch 40 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001
  1. From 4bbe6648eb8c452a9dcd77895caf2c3f0d8771f7 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Wed, 19 May 2021 02:19:34 -0700
  4. Subject: [PATCH 02/28] Add support for B extension
  5. ---
  6. bfd/elfxx-riscv.c | 2 +-
  7. gas/config/tc-riscv.c | 31 +++
  8. gas/testsuite/gas/riscv/b-ext-64.d | 117 +++++++++++
  9. gas/testsuite/gas/riscv/b-ext-64.s | 108 ++++++++++
  10. gas/testsuite/gas/riscv/b-ext.d | 74 +++++++
  11. gas/testsuite/gas/riscv/b-ext.s | 65 +++++++
  12. include/opcode/riscv-opc.h | 303 +++++++++++++++++++++++++++++
  13. include/opcode/riscv.h | 15 ++
  14. opcodes/riscv-dis.c | 4 +
  15. opcodes/riscv-opc.c | 139 +++++++++++++
  16. 10 files changed, 857 insertions(+), 1 deletion(-)
  17. create mode 100755 gas/testsuite/gas/riscv/b-ext-64.d
  18. create mode 100755 gas/testsuite/gas/riscv/b-ext-64.s
  19. create mode 100755 gas/testsuite/gas/riscv/b-ext.d
  20. create mode 100755 gas/testsuite/gas/riscv/b-ext.s
  21. diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
  22. index 0d5bec4762..8c8af2386b 100644
  23. --- a/bfd/elfxx-riscv.c
  24. +++ b/bfd/elfxx-riscv.c
  25. @@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
  26. static const char * const riscv_std_z_ext_strtab[] =
  27. {
  28. - "zicsr", "zifencei", "zihintpause", "zvamo", "zvlsseg", NULL
  29. + "zicsr", "zifencei", "zihintpause", "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt", "zvamo", "zvlsseg",NULL
  30. };
  31. static const char * const riscv_std_s_ext_strtab[] =
  32. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
  33. index 3322f17ccb..3e76e538c4 100644
  34. --- a/gas/config/tc-riscv.c
  35. +++ b/gas/config/tc-riscv.c
  36. @@ -253,6 +253,37 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
  37. case INSN_CLASS_ZIHINTPAUSE:
  38. return riscv_subset_supports ("zihintpause");
  39. + case INSN_CLASS_ZBB:
  40. + return riscv_subset_supports ("zbb");
  41. + case INSN_CLASS_ZBA:
  42. + return riscv_subset_supports ("zba");
  43. + case INSN_CLASS_ZBC:
  44. + return riscv_subset_supports ("zbc");
  45. + case INSN_CLASS_ZBE:
  46. + return riscv_subset_supports ("zbe");
  47. + case INSN_CLASS_ZBF:
  48. + return riscv_subset_supports ("zbf");
  49. + case INSN_CLASS_ZBM:
  50. + return riscv_subset_supports ("zbm");
  51. + case INSN_CLASS_ZBP:
  52. + return riscv_subset_supports ("zbp");
  53. + case INSN_CLASS_ZBR:
  54. + return riscv_subset_supports ("zbr");
  55. + case INSN_CLASS_ZBS:
  56. + return riscv_subset_supports ("zbs");
  57. + case INSN_CLASS_ZBT:
  58. + return riscv_subset_supports ("zbt");
  59. + case INSN_CLASS_ZBB_OR_ZBP:
  60. + return (riscv_subset_supports ("zbb") || riscv_subset_supports ("zbp"));
  61. + case INSN_CLASS_ZBS_OR_ZBE:
  62. + return (riscv_subset_supports ("zbs") || riscv_subset_supports ("zbe"));
  63. + case INSN_CLASS_ZBP_OR_ZBM:
  64. + return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbm"));
  65. + case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF:
  66. + return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf"));
  67. + case INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM:
  68. + return (riscv_subset_supports ("zbp") || riscv_subset_supports ("zbe") || riscv_subset_supports ("zbf") || riscv_subset_supports ("zbm"));
  69. +
  70. default:
  71. as_fatal ("Unreachable");
  72. return FALSE;
  73. diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
  74. new file mode 100755
  75. index 0000000000..23da2e0d58
  76. --- /dev/null
  77. +++ b/gas/testsuite/gas/riscv/b-ext-64.d
  78. @@ -0,0 +1,117 @@
  79. +#as: -march=rv64i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
  80. +#source: b-ext-64.s
  81. +#objdump: -d
  82. +
  83. +.*:[ ]+file format .*
  84. +
  85. +
  86. +Disassembly of section .text:
  87. +
  88. +0+000 <target>:
  89. +[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
  90. +[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
  91. +[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
  92. +[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
  93. +[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
  94. +[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
  95. +[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
  96. +[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
  97. +[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
  98. +[ ]+24:[ ]+0805453b[ ]+zext.h[ ]+a0,a0
  99. +[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
  100. +[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
  101. +[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
  102. +[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
  103. +[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
  104. +[ ]+3c:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
  105. +[ ]+40:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
  106. +[ ]+44:[ ]+6b855513[ ]+rev8[ ]+a0,a0
  107. +[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
  108. +[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
  109. +[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
  110. +[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
  111. +[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
  112. +[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
  113. +[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
  114. +[ ]+64:[ ]+6005151b[ ]+clzw[ ]+a0,a0
  115. +[ ]+68:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
  116. +[ ]+6c:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
  117. +[ ]+70:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
  118. +[ ]+74:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
  119. +[ ]+78:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
  120. +[ ]+7c:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
  121. +[ ]+80:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
  122. +[ ]+84:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
  123. +[ ]+88:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
  124. +[ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
  125. +[ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
  126. +[ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
  127. +[ ]+98:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
  128. +[ ]+9c:[ ]+48c5c533[ ]+packu[ ]+a0,a1,a2
  129. +[ ]+a0:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
  130. +[ ]+a4:[ ]+0825c53b[ ]+packw[ ]+a0,a1,0x2
  131. +[ ]+a8:[ ]+4825c53b[ ]+packuw[ ]+a0,a1,0x2
  132. +[ ]+ac:[ ]+68c5d533[ ]+grev[ ]+a0,a1,a2
  133. +[ ]+b0:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
  134. +[ ]+b4:[ ]+6825d53b[ ]+grevw[ ]+a0,a1,0x2
  135. +[ ]+b8:[ ]+6825d51b[ ]+greviw[ ]+a0,a1,0x2
  136. +[ ]+bc:[ ]+28c5d533[ ]+gorc[ ]+a0,a1,a2
  137. +[ ]+c0:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
  138. +[ ]+c4:[ ]+2825d53b[ ]+gorcw[ ]+a0,a1,0x2
  139. +[ ]+c8:[ ]+2825d51b[ ]+gorciw[ ]+a0,a1,0x2
  140. +[ ]+cc:[ ]+08c59533[ ]+shfl[ ]+a0,a1,a2
  141. +[ ]+d0:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
  142. +[ ]+d4:[ ]+0825953b[ ]+shflw[ ]+a0,a1,0x2
  143. +[ ]+d8:[ ]+08c5d533[ ]+unshfl[ ]+a0,a1,a2
  144. +[ ]+dc:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
  145. +[ ]+e0:[ ]+0825d53b[ ]+unshflw[ ]+a0,a1,0x2
  146. +[ ]+e4:[ ]+28c5a533[ ]+xperm.n[ ]+a0,a1,a2
  147. +[ ]+e8:[ ]+28c5c533[ ]+xperm.b[ ]+a0,a1,a2
  148. +[ ]+ec:[ ]+28c5e533[ ]+xperm.h[ ]+a0,a1,a2
  149. +[ ]+f0:[ ]+28258533[ ]+xperm.w[ ]+a0,a1,0x2
  150. +[ ]+f4:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
  151. +[ ]+f8:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
  152. +[ ]+fc:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
  153. +[ ]+100:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
  154. +[ ]+104:[ ]+48c5e533[ ]+bdep[ ]+a0,a1,a2
  155. +[ ]+108:[ ]+28259513[ ]+bseti[ ]+a0,a1,0x2
  156. +[ ]+10c:[ ]+48259513[ ]+bclri[ ]+a0,a1,0x2
  157. +[ ]+110:[ ]+68259513[ ]+binvi[ ]+a0,a1,0x2
  158. +[ ]+114:[ ]+4825d513[ ]+bexti[ ]+a0,a1,0x2
  159. +[ ]+118:[ ]+28c5953b[ ]+bsetw[ ]+a0,a1,a2
  160. +[ ]+11c:[ ]+48c5953b[ ]+bclrw[ ]+a0,a1,a2
  161. +[ ]+120:[ ]+68c5953b[ ]+binvw[ ]+a0,a1,a2
  162. +[ ]+124:[ ]+48c5d53b[ ]+bextw[ ]+a0,a1,a2
  163. +[ ]+128:[ ]+4825e53b[ ]+bdepw[ ]+a0,a1,0x2
  164. +[ ]+12c:[ ]+2825951b[ ]+bsetiw[ ]+a0,a1,0x2
  165. +[ ]+130:[ ]+4825951b[ ]+bclriw[ ]+a0,a1,0x2
  166. +[ ]+134:[ ]+6825951b[ ]+binviw[ ]+a0,a1,0x2
  167. +[ ]+138:[ ]+20c59533[ ]+slo[ ]+a0,a1,a2
  168. +[ ]+13c:[ ]+20c5d533[ ]+sro[ ]+a0,a1,a2
  169. +[ ]+140:[ ]+20259513[ ]+sloi[ ]+a0,a1,0x2
  170. +[ ]+144:[ ]+2025d513[ ]+sroi[ ]+a0,a1,0x2
  171. +[ ]+148:[ ]+2025953b[ ]+slow[ ]+a0,a1,0x2
  172. +[ ]+14c:[ ]+2025d53b[ ]+srow[ ]+a0,a1,0x2
  173. +[ ]+150:[ ]+2025951b[ ]+sloiw[ ]+a0,a1,0x2
  174. +[ ]+154:[ ]+2025d51b[ ]+sroiw[ ]+a0,a1,0x2
  175. +[ ]+158:[ ]+48c5f533[ ]+bfp[ ]+a0,a1,a2
  176. +[ ]+15c:[ ]+4825f53b[ ]+bfpw[ ]+a0,a1,0x2
  177. +[ ]+160:[ ]+08c5b533[ ]+bmator[ ]+a0,a1,a2
  178. +[ ]+164:[ ]+48c5b533[ ]+bmatxor[ ]+a0,a1,a2
  179. +[ ]+168:[ ]+60351513[ ]+bmatflip[ ]+a0,a0
  180. +[ ]+16c:[ ]+61051513[ ]+crc32.b[ ]+a0,a0
  181. +[ ]+170:[ ]+61151513[ ]+crc32.h[ ]+a0,a0
  182. +[ ]+174:[ ]+61251513[ ]+crc32.w[ ]+a0,a0
  183. +[ ]+178:[ ]+61851513[ ]+crc32c.b[ ]+a0,a0
  184. +[ ]+17c:[ ]+61951513[ ]+crc32c.h[ ]+a0,a0
  185. +[ ]+180:[ ]+61a51513[ ]+crc32c.w[ ]+a0,a0
  186. +[ ]+184:[ ]+61351513[ ]+crc32.d[ ]+a0,a0
  187. +[ ]+188:[ ]+61b51513[ ]+crc32c.d[ ]+a0,a0
  188. +[ ]+18c:[ ]+6ec59533[ ]+cmix[ ]+a0,a1,a2,a3
  189. +[ ]+190:[ ]+6ec5d533[ ]+cmov[ ]+a0,a1,a2,a3
  190. +[ ]+194:[ ]+6cc59533[ ]+fsl[ ]+a0,a1,a2,a3
  191. +[ ]+198:[ ]+6cc5d533[ ]+fsr[ ]+a0,a1,a2,a3
  192. +[ ]+19c:[ ]+6c25d513[ ]+fsri[ ]+a0,a1,0x2,a3
  193. +[ ]+1a0:[ ]+6c25953b[ ]+fslw[ ]+a0,a1,0x2,a3
  194. +[ ]+1a4:[ ]+6c25b53b[ ]+fsrw[ ]+a0,a1,0x2,a3
  195. +[ ]+1a8:[ ]+6c25b51b[ ]+fsriw[ ]+a0,a1,0x2,a3
  196. diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
  197. new file mode 100755
  198. index 0000000000..176d617be5
  199. --- /dev/null
  200. +++ b/gas/testsuite/gas/riscv/b-ext-64.s
  201. @@ -0,0 +1,108 @@
  202. +target:
  203. + clz a0, a0
  204. + ctz a0, a0
  205. + cpop a0, a0
  206. + min a0, a1, a2
  207. + minu a0, a1, a2
  208. + max a0, a1, a2
  209. + maxu a0, a1, a2
  210. + sext.b a0, a0
  211. + sext.h a0, a0
  212. + zext.h a0, a0
  213. + andn a0, a1, a2
  214. + orn a0, a1, a2
  215. + xnor a0, a1, a2
  216. + rol a0, a1, a2
  217. + ror a0, a1, a2
  218. + ror a0, a1, 2
  219. + rori a0, a1, 2
  220. + rev8 a0, a0
  221. + orc.b a0, a0
  222. + sh1add a0, a1, a2
  223. + sh2add a0, a1, a2
  224. + sh3add a0, a1, a2
  225. + clmul a0, a1, a2
  226. + clmulh a0, a1, a2
  227. + clmulr a0, a1, a2
  228. + clzw a0, a0
  229. + ctzw a0, a0
  230. + cpopw a0, a0
  231. + rolw a0, a1, a2
  232. + rorw a0, a1, a2
  233. + rorw a0, a1, 2
  234. + roriw a0, a1, 2
  235. + sh1add.uw a0, a1, a2
  236. + sh2add.uw a0, a1, a2
  237. + sh3add.uw a0, a1, a2
  238. + add.uw a0, a1, a2
  239. + zext.w a0, a1
  240. + slli.uw a0, a1, 2
  241. + pack a0, a1, a2
  242. + packu a0, a1, a2
  243. + packh a0, a1, a2
  244. + packw a0, a1, 2
  245. + packuw a0, a1, 2
  246. + grev a0, a1, a2
  247. + grevi a0, a1, 2
  248. + grevw a0, a1, 2
  249. + greviw a0, a1, 2
  250. + gorc a0, a1, a2
  251. + gorci a0, a1, 2
  252. + gorcw a0, a1, 2
  253. + gorciw a0, a1, 2
  254. + shfl a0, a1, a2
  255. + shfli a0, a1, 2
  256. + shflw a0, a1, 2
  257. + unshfl a0, a1, a2
  258. + unshfli a0, a1, 2
  259. + unshflw a0, a1, 2
  260. + xperm.n a0, a1, a2
  261. + xperm.b a0, a1, a2
  262. + xperm.h a0, a1, a2
  263. + xperm.w a0, a1, 2
  264. + bset a0, a1, a2
  265. + bclr a0, a1, a2
  266. + binv a0, a1, a2
  267. + bext a0, a1, a2
  268. + bdep a0, a1, a2
  269. + bseti a0, a1, 2
  270. + bclri a0, a1, 2
  271. + binvi a0, a1, 2
  272. + bexti a0, a1, 2
  273. + bsetw a0, a1, a2
  274. + bclrw a0, a1, a2
  275. + binvw a0, a1, a2
  276. + bextw a0, a1, a2
  277. + bdepw a0, a1, 2
  278. + bsetiw a0, a1, 2
  279. + bclriw a0, a1, 2
  280. + binviw a0, a1, 2
  281. + slo a0, a1, a2
  282. + sro a0, a1, a2
  283. + sloi a0, a1, 2
  284. + sroi a0, a1, 2
  285. + slow a0, a1, 2
  286. + srow a0, a1, 2
  287. + sloiw a0, a1, 2
  288. + sroiw a0, a1, 2
  289. + bfp a0, a1, a2
  290. + bfpw a0, a1, 2
  291. + bmator a0, a1, a2
  292. + bmatxor a0, a1, a2
  293. + bmatflip a0, a0
  294. + crc32.b a0, a0
  295. + crc32.h a0, a0
  296. + crc32.w a0, a0
  297. + crc32c.b a0, a0
  298. + crc32c.h a0, a0
  299. + crc32c.w a0, a0
  300. + crc32.d a0, a0
  301. + crc32c.d a0, a0
  302. + cmix a0, a1, a2, a3
  303. + cmov a0, a1, a2, a3
  304. + fsl a0, a1, a2, a3
  305. + fsr a0, a1, a2, a3
  306. + fsri a0, a1, 2, a3
  307. + fslw a0, a1, 2, a3
  308. + fsrw a0, a1, 2, a3
  309. + fsriw a0, a1, 2, a3
  310. diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
  311. new file mode 100755
  312. index 0000000000..4df9e90693
  313. --- /dev/null
  314. +++ b/gas/testsuite/gas/riscv/b-ext.d
  315. @@ -0,0 +1,74 @@
  316. +#as: -march=rv32i_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
  317. +#source: b-ext.s
  318. +#objdump: -d
  319. +
  320. +.*:[ ]+file format .*
  321. +
  322. +
  323. +Disassembly of section .text:
  324. +
  325. +0+000 <target>:
  326. +[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
  327. +[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
  328. +[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
  329. +[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
  330. +[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
  331. +[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
  332. +[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
  333. +[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
  334. +[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
  335. +[ ]+24:[ ]+08054533[ ]+zext.h[ ]+a0,a0
  336. +[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
  337. +[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
  338. +[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
  339. +[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
  340. +[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
  341. +[ ]+3c:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
  342. +[ ]+40:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
  343. +[ ]+44:[ ]+69855513[ ]+rev8[ ]+a0,a0
  344. +[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
  345. +[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
  346. +[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
  347. +[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
  348. +[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
  349. +[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
  350. +[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
  351. +[ ]+64:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
  352. +[ ]+68:[ ]+48c5c533[ ]+packu[ ]+a0,a1,a2
  353. +[ ]+6c:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
  354. +[ ]+70:[ ]+68c5d533[ ]+grev[ ]+a0,a1,a2
  355. +[ ]+74:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
  356. +[ ]+78:[ ]+28c5d533[ ]+gorc[ ]+a0,a1,a2
  357. +[ ]+7c:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
  358. +[ ]+80:[ ]+08c59533[ ]+shfl[ ]+a0,a1,a2
  359. +[ ]+84:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
  360. +[ ]+88:[ ]+08c5d533[ ]+unshfl[ ]+a0,a1,a2
  361. +[ ]+8c:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
  362. +[ ]+90:[ ]+28c5a533[ ]+xperm.n[ ]+a0,a1,a2
  363. +[ ]+94:[ ]+28c5c533[ ]+xperm.b[ ]+a0,a1,a2
  364. +[ ]+98:[ ]+28c5e533[ ]+xperm.h[ ]+a0,a1,a2
  365. +[ ]+9c:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
  366. +[ ]+a0:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
  367. +[ ]+a4:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
  368. +[ ]+a8:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
  369. +[ ]+ac:[ ]+48c5e533[ ]+bdep[ ]+a0,a1,a2
  370. +[ ]+b0:[ ]+28259513[ ]+bseti[ ]+a0,a1,0x2
  371. +[ ]+b4:[ ]+48259513[ ]+bclri[ ]+a0,a1,0x2
  372. +[ ]+b8:[ ]+68259513[ ]+binvi[ ]+a0,a1,0x2
  373. +[ ]+bc:[ ]+4825d513[ ]+bexti[ ]+a0,a1,0x2
  374. +[ ]+c0:[ ]+20c59533[ ]+slo[ ]+a0,a1,a2
  375. +[ ]+c4:[ ]+20c5d533[ ]+sro[ ]+a0,a1,a2
  376. +[ ]+c8:[ ]+20259513[ ]+sloi[ ]+a0,a1,0x2
  377. +[ ]+cc:[ ]+2025d513[ ]+sroi[ ]+a0,a1,0x2
  378. +[ ]+d0:[ ]+48c5f533[ ]+bfp[ ]+a0,a1,a2
  379. +[ ]+d4:[ ]+61051513[ ]+crc32.b[ ]+a0,a0
  380. +[ ]+d8:[ ]+61151513[ ]+crc32.h[ ]+a0,a0
  381. +[ ]+dc:[ ]+61251513[ ]+crc32.w[ ]+a0,a0
  382. +[ ]+e0:[ ]+61851513[ ]+crc32c.b[ ]+a0,a0
  383. +[ ]+e4:[ ]+61951513[ ]+crc32c.h[ ]+a0,a0
  384. +[ ]+e8:[ ]+61a51513[ ]+crc32c.w[ ]+a0,a0
  385. +[ ]+ec:[ ]+6ec59533[ ]+cmix[ ]+a0,a1,a2,a3
  386. +[ ]+f0:[ ]+6ec5d533[ ]+cmov[ ]+a0,a1,a2,a3
  387. +[ ]+f4:[ ]+6cc59533[ ]+fsl[ ]+a0,a1,a2,a3
  388. +[ ]+f8:[ ]+6cc5d533[ ]+fsr[ ]+a0,a1,a2,a3
  389. +[ ]+fc:[ ]+6c25d513[ ]+fsri[ ]+a0,a1,0x2,a3
  390. diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
  391. new file mode 100755
  392. index 0000000000..429c005849
  393. --- /dev/null
  394. +++ b/gas/testsuite/gas/riscv/b-ext.s
  395. @@ -0,0 +1,65 @@
  396. +target:
  397. + clz a0, a0
  398. + ctz a0, a0
  399. + cpop a0, a0
  400. + min a0, a1, a2
  401. + minu a0, a1, a2
  402. + max a0, a1, a2
  403. + maxu a0, a1, a2
  404. + sext.b a0, a0
  405. + sext.h a0, a0
  406. + zext.h a0, a0
  407. + andn a0, a1, a2
  408. + orn a0, a1, a2
  409. + xnor a0, a1, a2
  410. + rol a0, a1, a2
  411. + ror a0, a1, a2
  412. + ror a0, a1, 2
  413. + rori a0, a1, 2
  414. + rev8 a0, a0
  415. + orc.b a0, a0
  416. + sh1add a0, a1, a2
  417. + sh2add a0, a1, a2
  418. + sh3add a0, a1, a2
  419. + clmul a0, a1, a2
  420. + clmulh a0, a1, a2
  421. + clmulr a0, a1, a2
  422. + pack a0, a1, a2
  423. + packu a0, a1, a2
  424. + packh a0, a1, a2
  425. + grev a0, a1, a2
  426. + grevi a0, a1, 2
  427. + gorc a0, a1, a2
  428. + gorci a0, a1, 2
  429. + shfl a0, a1, a2
  430. + shfli a0, a1, 2
  431. + unshfl a0, a1, a2
  432. + unshfli a0, a1, 2
  433. + xperm.n a0, a1, a2
  434. + xperm.b a0, a1, a2
  435. + xperm.h a0, a1, a2
  436. + bset a0, a1, a2
  437. + bclr a0, a1, a2
  438. + binv a0, a1, a2
  439. + bext a0, a1, a2
  440. + bdep a0, a1, a2
  441. + bseti a0, a1, 2
  442. + bclri a0, a1, 2
  443. + binvi a0, a1, 2
  444. + bexti a0, a1, 2
  445. + slo a0, a1, a2
  446. + sro a0, a1, a2
  447. + sloi a0, a1, 2
  448. + sroi a0, a1, 2
  449. + bfp a0, a1, a2
  450. + crc32.b a0, a0
  451. + crc32.h a0, a0
  452. + crc32.w a0, a0
  453. + crc32c.b a0, a0
  454. + crc32c.h a0, a0
  455. + crc32c.w a0, a0
  456. + cmix a0, a1, a2, a3
  457. + cmov a0, a1, a2, a3
  458. + fsl a0, a1, a2, a3
  459. + fsr a0, a1, a2, a3
  460. + fsri a0, a1, 2, a3
  461. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  462. index b0e549a0f2..1a9e313fc3 100644
  463. --- a/include/opcode/riscv-opc.h
  464. +++ b/include/opcode/riscv-opc.h
  465. @@ -113,6 +113,18 @@
  466. #define MASK_SRL 0xfe00707f
  467. #define MATCH_SRA 0x40005033
  468. #define MASK_SRA 0xfe00707f
  469. +#define MATCH_SLO 0x20001033
  470. +#define MASK_SLO 0xfe00707f
  471. +#define MATCH_SLOI 0x20001013
  472. +#define MASK_SLOI 0xfc00707f
  473. +#define MATCH_SLOW 0x2000103b
  474. +#define MASK_SLOW 0xfe00707f
  475. +#define MATCH_SRO 0x20005033
  476. +#define MASK_SRO 0xfe00707f
  477. +#define MATCH_SROI 0x20005013
  478. +#define MASK_SROI 0xfc00707f
  479. +#define MATCH_SROW 0x2000503b
  480. +#define MASK_SROW 0xfe00707f
  481. #define MATCH_OR 0x6033
  482. #define MASK_OR 0xfe00707f
  483. #define MATCH_AND 0x7033
  484. @@ -423,6 +435,196 @@
  485. #define MASK_FCVT_Q_LU 0xfff0007f
  486. #define MATCH_FMV_Q_X 0xf6000053
  487. #define MASK_FMV_Q_X 0xfff0707f
  488. +#define MATCH_CLZ 0x60001013
  489. +#define MASK_CLZ 0xfff0707f
  490. +#define MATCH_CTZ 0x60101013
  491. +#define MASK_CTZ 0xfff0707f
  492. +#define MATCH_CPOP 0x60201013
  493. +#define MASK_CPOP 0xfff0707f
  494. +#define MATCH_BMATFLIP 0x60301013
  495. +#define MASK_BMATFLIP 0xfff0707f
  496. +#define MATCH_CRC32_B 0x61001013
  497. +#define MASK_CRC32_B 0xfff0707f
  498. +#define MATCH_CRC32_H 0x61101013
  499. +#define MASK_CRC32_H 0xfff0707f
  500. +#define MATCH_CRC32_W 0x61201013
  501. +#define MASK_CRC32_W 0xfff0707f
  502. +#define MATCH_CRC32_D 0x61301013
  503. +#define MASK_CRC32_D 0xfff0707f
  504. +#define MATCH_CRC32C_B 0x61801013
  505. +#define MASK_CRC32C_B 0xfff0707f
  506. +#define MATCH_CRC32C_H 0x61901013
  507. +#define MASK_CRC32C_H 0xfff0707f
  508. +#define MATCH_CRC32C_W 0x61A01013
  509. +#define MASK_CRC32C_W 0xfff0707f
  510. +#define MATCH_CRC32C_D 0x61B01013
  511. +#define MASK_CRC32C_D 0xfff0707f
  512. +#define MATCH_MIN 0xa004033
  513. +#define MASK_MIN 0xfe00707f
  514. +#define MATCH_MINU 0xa005033
  515. +#define MASK_MINU 0xfe00707f
  516. +#define MATCH_MAX 0xa006033
  517. +#define MASK_MAX 0xfe00707f
  518. +#define MATCH_MAXU 0xa007033
  519. +#define MASK_MAXU 0xfe00707f
  520. +#define MATCH_SHFL 0x8001033
  521. +#define MASK_SHFL 0xfe00707f
  522. +#define MATCH_SHFLI 0x8001013
  523. +#define MASK_SHFLI 0xfc00707f
  524. +#define MATCH_UNSHFL 0x8005033
  525. +#define MASK_UNSHFL 0xfe00707f
  526. +#define MATCH_UNSHFLI 0x8005013
  527. +#define MASK_UNSHFLI 0xfc00707f
  528. +#define MATCH_BDEP 0x48006033
  529. +#define MASK_BDEP 0xfe00707f
  530. +#define MATCH_SEXT_B 0x60401013
  531. +#define MASK_SEXT_B 0xfff0707f
  532. +#define MATCH_SEXT_H 0x60501013
  533. +#define MASK_SEXT_H 0xfff0707f
  534. +#define MATCH_PACK 0x8004033
  535. +#define MASK_PACK 0xfe00707f
  536. +#define MATCH_PACKU 0x48004033
  537. +#define MASK_PACKU 0xfe00707f
  538. +#define MATCH_BMATOR 0x8003033
  539. +#define MASK_BMATOR 0xfe00707f
  540. +#define MATCH_BMATXOR 0x48003033
  541. +#define MASK_BMATXOR 0xfe00707f
  542. +#define MATCH_PACKH 0x8007033
  543. +#define MASK_PACKH 0xfe00707f
  544. +#define MATCH_BFP 0x48007033
  545. +#define MASK_BFP 0xfe00707f
  546. +#define MATCH_PACKW 0x800403b
  547. +#define MASK_PACKW 0xfe00707f
  548. +#define MATCH_PACKUW 0x4800403b
  549. +#define MASK_PACKUW 0xfe00707f
  550. +#define MATCH_ANDN 0x40007033
  551. +#define MASK_ANDN 0xfe00707f
  552. +#define MATCH_ORN 0x40006033
  553. +#define MASK_ORN 0xfe00707f
  554. +#define MATCH_XNOR 0x40004033
  555. +#define MASK_XNOR 0xfe00707f
  556. +#define MATCH_ROL 0x60001033
  557. +#define MASK_ROL 0xfe00707f
  558. +#define MATCH_ROR 0x60005033
  559. +#define MASK_ROR 0xfe00707f
  560. +#define MATCH_RORI 0x60005013
  561. +#define MASK_RORI 0xfc00707f
  562. +#define MATCH_BCLR 0x48001033
  563. +#define MASK_BCLR 0xfe00707f
  564. +#define MATCH_BCLRI 0x48001013
  565. +#define MASK_BCLRI 0xfc00707f
  566. +#define MATCH_BSET 0x28001033
  567. +#define MASK_BSET 0xfe00707f
  568. +#define MATCH_BSETI 0x28001013
  569. +#define MASK_BSETI 0xfc00707f
  570. +#define MATCH_BINV 0x68001033
  571. +#define MASK_BINV 0xfe00707f
  572. +#define MATCH_BINVI 0x68001013
  573. +#define MASK_BINVI 0xfc00707f
  574. +#define MATCH_BEXT 0x48005033
  575. +#define MASK_BEXT 0xfe00707f
  576. +#define MATCH_BEXTI 0x48005013
  577. +#define MASK_BEXTI 0xfc00707f
  578. +#define MATCH_GREV 0x68005033
  579. +#define MASK_GREV 0xfe00707f
  580. +#define MATCH_GREVI 0x68005013
  581. +#define MASK_GREVI 0xfc00707f
  582. +#define MATCH_GORC 0x28005033
  583. +#define MASK_GORC 0xfe00707f
  584. +#define MATCH_GORCI 0x28005013
  585. +#define MASK_GORCI 0xfc00707f
  586. +#define MATCH_CMIX 0x6001033
  587. +#define MASK_CMIX 0x600707f
  588. +#define MATCH_CMOV 0x6005033
  589. +#define MASK_CMOV 0x600707f
  590. +#define MATCH_FSL 0x4001033
  591. +#define MASK_FSL 0x600707f
  592. +#define MATCH_FSR 0x4005033
  593. +#define MASK_FSR 0x600707f
  594. +#define MATCH_FSRI 0x4005013
  595. +#define MASK_FSRI 0x400707f
  596. +#define MATCH_CLZW 0x6000101b
  597. +#define MASK_CLZW 0xfff0707f
  598. +#define MATCH_CTZW 0x6010101b
  599. +#define MASK_CTZW 0xfff0707f
  600. +#define MATCH_CPOPW 0x6020101b
  601. +#define MASK_CPOPW 0xfff0707f
  602. +#define MATCH_ROLW 0x6000103b
  603. +#define MASK_ROLW 0xfe00707f
  604. +#define MATCH_RORW 0x6000503b
  605. +#define MASK_RORW 0xfe00707f
  606. +#define MATCH_RORIW 0x6000501b
  607. +#define MASK_RORIW 0xfe00707f
  608. +#define MATCH_SH1ADD 0x20002033
  609. +#define MASK_SH1ADD 0xfe00707f
  610. +#define MATCH_SH2ADD 0x20004033
  611. +#define MASK_SH2ADD 0xfe00707f
  612. +#define MATCH_SH3ADD 0x20006033
  613. +#define MASK_SH3ADD 0xfe00707f
  614. +#define MATCH_SH1ADD_UW 0x2000203b
  615. +#define MASK_SH1ADD_UW 0xfe00707f
  616. +#define MATCH_SH2ADD_UW 0x2000403b
  617. +#define MASK_SH2ADD_UW 0xfe00707f
  618. +#define MATCH_SH3ADD_UW 0x2000603b
  619. +#define MASK_SH3ADD_UW 0xfe00707f
  620. +#define MATCH_BCLRW 0x4800103b
  621. +#define MASK_BCLRW 0xfe00707f
  622. +#define MATCH_BSETW 0x2800103b
  623. +#define MASK_BSETW 0xfe00707f
  624. +#define MATCH_BINVW 0x6800103b
  625. +#define MASK_BINVW 0xfe00707f
  626. +#define MATCH_BEXTW 0x4800503b
  627. +#define MASK_BEXTW 0xfe00707f
  628. +#define MATCH_GORCW 0x2800503b
  629. +#define MASK_GORCW 0xfe00707f
  630. +#define MATCH_GREVW 0x6800503b
  631. +#define MASK_GREVW 0xfe00707f
  632. +#define MATCH_SLOIW 0x2000101b
  633. +#define MASK_SLOIW 0xfe00707f
  634. +#define MATCH_SROIW 0x2000501b
  635. +#define MASK_SROIW 0xfe00707f
  636. +#define MATCH_BCLRIW 0x4800101b
  637. +#define MASK_BCLRIW 0xfe00707f
  638. +#define MATCH_BSETIW 0x2800101b
  639. +#define MASK_BSETIW 0xfe00707f
  640. +#define MATCH_BINVIW 0x6800101b
  641. +#define MASK_BINVIW 0xfe00707f
  642. +#define MATCH_GORCIW 0x2800501b
  643. +#define MASK_GORCIW 0xfe00707f
  644. +#define MATCH_GREVIW 0x6800501b
  645. +#define MASK_GREVIW 0xfe00707f
  646. +#define MATCH_FSLW 0x400103b
  647. +#define MASK_FSLW 0x600707f
  648. +#define MATCH_FSRW 0x400303b
  649. +#define MASK_FSRW 0x600707f
  650. +#define MATCH_FSRIW 0x400301b
  651. +#define MASK_FSRIW 0x600707f
  652. +#define MATCH_SHFLW 0x800103b
  653. +#define MASK_SHFLW 0xfe00707f
  654. +#define MATCH_UNSHFLW 0x800503b
  655. +#define MASK_UNSHFLW 0xfe00707f
  656. +#define MATCH_BDEPW 0x4800603b
  657. +#define MASK_BDEPW 0xfe00707f
  658. +#define MATCH_BFPW 0x4800703b
  659. +#define MASK_BFPW 0xfe00707f
  660. +#define MATCH_XPERM_N 0x28002033
  661. +#define MASK_XPERM_N 0xfe00707f
  662. +#define MATCH_XPERM_B 0x28004033
  663. +#define MASK_XPERM_B 0xfe00707f
  664. +#define MATCH_XPERM_H 0x28006033
  665. +#define MASK_XPERM_H 0xfe00707f
  666. +#define MATCH_XPERM_W 0x28000033
  667. +#define MASK_XPERM_W 0xfe00707f
  668. +#define MATCH_ADD_UW 0x800003b
  669. +#define MASK_ADD_UW 0xfe00707f
  670. +#define MATCH_SLLI_UW 0x800101b
  671. +#define MASK_SLLI_UW 0xfc00707f
  672. +#define MATCH_CLMUL 0xa001033
  673. +#define MASK_CLMUL 0xfe00707f
  674. +#define MATCH_CLMULH 0xa003033
  675. +#define MASK_CLMULH 0xfe00707f
  676. +#define MATCH_CLMULR 0xa002033
  677. +#define MASK_CLMULR 0xfe00707f
  678. #define MATCH_FLW 0x2007
  679. #define MASK_FLW 0x707f
  680. #define MATCH_FLD 0x3007
  681. @@ -1046,6 +1248,107 @@ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
  682. DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
  683. DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
  684. DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
  685. +DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
  686. +DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
  687. +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
  688. +DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
  689. +DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
  690. +DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
  691. +DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
  692. +DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
  693. +DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
  694. +DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
  695. +DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
  696. +DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
  697. +DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
  698. +DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
  699. +DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
  700. +DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
  701. +DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
  702. +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
  703. +DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
  704. +DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
  705. +DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
  706. +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
  707. +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
  708. +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
  709. +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
  710. +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
  711. +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
  712. +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
  713. +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
  714. +DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
  715. +DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
  716. +DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
  717. +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
  718. +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
  719. +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
  720. +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
  721. +DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
  722. +DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
  723. +DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
  724. +DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
  725. +DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
  726. +DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
  727. +DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
  728. +DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
  729. +DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
  730. +DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
  731. +DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
  732. +DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
  733. +DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
  734. +DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
  735. +DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
  736. +DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N)
  737. +DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B)
  738. +DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H)
  739. +DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W)
  740. +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
  741. +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
  742. +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
  743. +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
  744. +DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
  745. +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
  746. +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
  747. +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
  748. +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
  749. +DECLARE_INSN(bsetw, MATCH_BSETW, MASK_BSETW)
  750. +DECLARE_INSN(bclrw, MATCH_BCLRW, MASK_BCLRW)
  751. +DECLARE_INSN(binvw, MATCH_BINVW, MASK_BINVW)
  752. +DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
  753. +DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
  754. +DECLARE_INSN(bsetiw, MATCH_BSETIW, MASK_BSETIW)
  755. +DECLARE_INSN(bclriw, MATCH_BCLRIW, MASK_BCLRIW)
  756. +DECLARE_INSN(binviw, MATCH_BINVIW, MASK_BINVIW)
  757. +DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
  758. +DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
  759. +DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
  760. +DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
  761. +DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
  762. +DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
  763. +DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
  764. +DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
  765. +DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
  766. +DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
  767. +DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
  768. +DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
  769. +DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
  770. +DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
  771. +DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
  772. +DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
  773. +DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
  774. +DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
  775. +DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
  776. +DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
  777. +DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
  778. +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
  779. +DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
  780. +DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
  781. +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
  782. +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
  783. +DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
  784. +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
  785. +DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
  786. DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
  787. DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
  788. DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
  789. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
  790. index caaaea5162..87d1aedb40 100644
  791. --- a/include/opcode/riscv.h
  792. +++ b/include/opcode/riscv.h
  793. @@ -312,6 +312,21 @@ enum riscv_insn_class
  794. INSN_CLASS_ZICSR,
  795. INSN_CLASS_ZIFENCEI,
  796. INSN_CLASS_ZIHINTPAUSE,
  797. + INSN_CLASS_ZBA,
  798. + INSN_CLASS_ZBB,
  799. + INSN_CLASS_ZBC,
  800. + INSN_CLASS_ZBP,
  801. + INSN_CLASS_ZBB_OR_ZBP,
  802. + INSN_CLASS_ZBS,
  803. + INSN_CLASS_ZBE,
  804. + INSN_CLASS_ZBS_OR_ZBE,
  805. + INSN_CLASS_ZBF,
  806. + INSN_CLASS_ZBM,
  807. + INSN_CLASS_ZBP_OR_ZBM,
  808. + INSN_CLASS_ZBR,
  809. + INSN_CLASS_ZBT,
  810. + INSN_CLASS_ZBP_OR_ZBE_OR_ZBF,
  811. + INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM,
  812. };
  813. /* This structure holds information for a particular instruction. */
  814. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
  815. index c3d9bb8745..a169d013c4 100644
  816. --- a/opcodes/riscv-dis.c
  817. +++ b/opcodes/riscv-dis.c
  818. @@ -238,6 +238,10 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
  819. info->target = EXTRACT_RVC_J_IMM (l) + pc;
  820. (*info->print_address_func) (info->target, info);
  821. break;
  822. + case 'r':
  823. + print (info->stream, "%s",
  824. + riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
  825. + break;
  826. case 'u':
  827. print (info->stream, "0x%x",
  828. (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
  829. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  830. index a2ea66a723..d73c980acd 100644
  831. --- a/opcodes/riscv-opc.c
  832. +++ b/opcodes/riscv-opc.c
  833. @@ -24,6 +24,11 @@
  834. #include "opcode/riscv.h"
  835. #include <stdio.h>
  836. +#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
  837. +#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
  838. +#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
  839. +#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
  840. +
  841. /* Register names used by gas and objdump. */
  842. const char * const riscv_gpr_names_numeric[NGPR] =
  843. @@ -786,6 +791,127 @@ const struct riscv_opcode riscv_opcodes[] =
  844. {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
  845. {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
  846. +
  847. +/* RVB instructions. */
  848. +{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
  849. +{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
  850. +{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
  851. +{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
  852. +{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
  853. +{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
  854. +{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
  855. +{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
  856. +{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
  857. +{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
  858. +{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
  859. +{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
  860. +{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
  861. +{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
  862. +{"andn", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
  863. +{"orn", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
  864. +{"xnor", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
  865. +{"rol", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
  866. +{"rori", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
  867. +{"ror", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
  868. +{"ror", 0, INSN_CLASS_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
  869. +{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_32, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
  870. +{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI|MATCH_SHAMT_REV8_64, MASK_GREVI|MASK_SHAMT, match_opcode, 0 },
  871. +{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI|MATCH_SHAMT_ORC_B, MASK_GORCI|MASK_SHAMT, match_opcode, 0 },
  872. +{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
  873. +{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
  874. +{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
  875. +{"rolw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
  876. +{"roriw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  877. +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
  878. +{"rorw", 64, INSN_CLASS_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
  879. +{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
  880. +{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
  881. +{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
  882. +{"sh1add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
  883. +{"sh2add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
  884. +{"sh3add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
  885. +{"zext.w", 64, INSN_CLASS_ZBA, "d,s", MATCH_ADD_UW, MASK_ADD_UW|MASK_RS2, match_opcode, INSN_ALIAS },
  886. +{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
  887. +{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
  888. +{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
  889. +{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
  890. +{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
  891. +{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
  892. +
  893. +{"pack", 0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF_OR_ZBM, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
  894. +{"packu", 0, INSN_CLASS_ZBP_OR_ZBM, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
  895. +{"packh", 0, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
  896. +{"packw", 64, INSN_CLASS_ZBP_OR_ZBE_OR_ZBF, "d,s,<", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
  897. +{"packuw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
  898. +{"grev", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
  899. +{"grevi", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
  900. +{"grevw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
  901. +{"greviw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
  902. +{"gorc", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
  903. +{"gorci", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
  904. +{"gorcw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
  905. +{"gorciw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
  906. +{"shfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
  907. +{"shfli", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
  908. +{"shflw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
  909. +{"unshfl", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
  910. +{"unshfli", 0, INSN_CLASS_ZBP, "d,s,>", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
  911. +{"unshflw", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
  912. +{"xperm.n", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_N, MASK_XPERM_N, match_opcode, 0 },
  913. +{"xperm.b", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_B, MASK_XPERM_B, match_opcode, 0 },
  914. +{"xperm.h", 0, INSN_CLASS_ZBP, "d,s,t", MATCH_XPERM_H, MASK_XPERM_H, match_opcode, 0 },
  915. +{"xperm.w", 64, INSN_CLASS_ZBP, "d,s,<", MATCH_XPERM_W, MASK_XPERM_W, match_opcode, 0 },
  916. +
  917. +{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
  918. +{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
  919. +{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
  920. +{"bext", 0, INSN_CLASS_ZBS_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
  921. +{"bdep", 0, INSN_CLASS_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
  922. +{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
  923. +{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
  924. +{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
  925. +{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
  926. +{"bsetw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BSETW, MASK_BSETW, match_opcode, 0 },
  927. +{"bclrw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLRW, MASK_BCLRW, match_opcode, 0 },
  928. +{"binvw", 64, INSN_CLASS_ZBS, "d,s,t", MATCH_BINVW, MASK_BINVW, match_opcode, 0 },
  929. +{"bextw", 64, INSN_CLASS_ZBS_OR_ZBE, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
  930. +{"bdepw", 64, INSN_CLASS_ZBE, "d,s,<", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
  931. +{"bsetiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BSETIW, MASK_BSETIW, match_opcode, 0 },
  932. +{"bclriw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BCLRIW, MASK_BCLRIW, match_opcode, 0 },
  933. +{"binviw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_BINVIW, MASK_BINVIW, match_opcode, 0 },
  934. +{"slo", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_SLO, MASK_SLO, match_opcode, 0 },
  935. +{"sro", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_SRO, MASK_SRO, match_opcode, 0 },
  936. +{"sloi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_SLOI, MASK_SLOI, match_opcode, 0 },
  937. +{"sroi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_SROI, MASK_SROI, match_opcode, 0 },
  938. +{"slow", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SLOW, MASK_SLOW, match_opcode, 0 },
  939. +{"srow", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SROW, MASK_SROW, match_opcode, 0 },
  940. +{"sloiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SLOIW, MASK_SLOIW, match_opcode, 0 },
  941. +{"sroiw", 64, INSN_CLASS_ZBS, "d,s,<", MATCH_SROIW, MASK_SROIW, match_opcode, 0 },
  942. +
  943. +{"bfp", 0, INSN_CLASS_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
  944. +{"bfpw", 64, INSN_CLASS_ZBF, "d,s,<", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
  945. +
  946. +{"bmator", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
  947. +{"bmatxor", 64, INSN_CLASS_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
  948. +{"bmatflip", 64, INSN_CLASS_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
  949. +
  950. +{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
  951. +{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
  952. +{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
  953. +{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
  954. +{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
  955. +{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
  956. +{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
  957. +{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
  958. +
  959. +{"cmix", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
  960. +{"cmov", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
  961. +{"fsl", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_FSL, MASK_FSL, match_opcode, 0 },
  962. +{"fsr", 0, INSN_CLASS_ZBT, "d,s,t,r", MATCH_FSR, MASK_FSR, match_opcode, 0 },
  963. +{"fsri", 0, INSN_CLASS_ZBT, "d,s,>,r", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
  964. +{"fslw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
  965. +{"fsrw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
  966. +{"fsriw", 64, INSN_CLASS_ZBT, "d,s,<,r", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
  967. /* Terminate the list. */
  968. {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
  969. };
  970. @@ -935,6 +1061,19 @@ const struct riscv_ext_version riscv_ext_version_table[] =
  971. {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
  972. +{"b", ISA_SPEC_CLASS_DRAFT, 0, 93},
  973. +{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
  974. +{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
  975. +{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
  976. +{"zbe", ISA_SPEC_CLASS_DRAFT, 0, 93},
  977. +{"zbf", ISA_SPEC_CLASS_DRAFT, 0, 93},
  978. +{"zbm", ISA_SPEC_CLASS_DRAFT, 0, 93},
  979. +{"zbp", ISA_SPEC_CLASS_DRAFT, 0, 93},
  980. +{"zbr", ISA_SPEC_CLASS_DRAFT, 0, 93},
  981. +{"zbs", ISA_SPEC_CLASS_DRAFT, 0, 93},
  982. +{"zbt", ISA_SPEC_CLASS_DRAFT, 0, 93},
  983. +
  984. +
  985. /* Terminate the list. */
  986. {NULL, 0, 0, 0}
  987. };
  988. --
  989. 2.33.0