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{Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition

All these platforms have an ABase, so move the definition to enable
common silicon code in IntelSiliconPkg. Otherwise, library shims would
be required, because PCDs are GUID-ed and package DEC specific.

Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Benjamin Doron 1 year ago
parent
commit
b74194d8b8
28 changed files with 34 additions and 18 deletions
  1. 1 0
      Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
  2. 1 1
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  3. 1 0
      Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
  4. 1 1
      Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  5. 1 1
      Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
  6. 1 0
      Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
  7. 1 1
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
  8. 1 0
      Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
  9. 1 0
      Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
  10. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  11. 1 0
      Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
  12. 1 0
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
  13. 1 0
      Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
  14. 3 2
      Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
  15. 2 1
      Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
  16. 1 1
      Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
  17. 0 1
      Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
  18. 4 0
      Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
  19. 1 0
      Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
  20. 1 1
      Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
  21. 2 1
      Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
  22. 1 1
      Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
  23. 1 1
      Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
  24. 0 1
      Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
  25. 2 1
      Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
  26. 2 1
      Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
  27. 0 1
      Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
  28. 1 0
      Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc

+ 1 - 0
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc

@@ -65,6 +65,7 @@
 
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
   #
   # PCIe Reserved Memory Space Range
   #

+ 1 - 1
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf

@@ -49,7 +49,7 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength      ## CONSUMES
 
 [FixedPcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress       ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress            ## CONSUMES
 
 [Sources]
   TbtSmiHandler.h

+ 1 - 0
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc

@@ -241,6 +241,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
 !endif
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01

+ 1 - 1
Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf

@@ -46,7 +46,7 @@
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
 
 [FixedPcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress       ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress         ## CONSUMES
 
 [Sources]
   TbtSmiHandler.h

+ 1 - 1
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf

@@ -35,7 +35,7 @@
   KabylakeSiliconPkg/SiPkg.dec
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress                         ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress               ## CONSUMES
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort          ## CONSUMES
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort           ## CONSUMES
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort   ## CONSUMES

+ 1 - 0
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc

@@ -194,6 +194,7 @@
   gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
 !endif
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
   gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
 !endif

+ 1 - 1
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf

@@ -35,7 +35,7 @@
   KabylakeSiliconPkg/SiPkg.dec
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress                         ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress               ## CONSUMES
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort          ## CONSUMES
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort           ## CONSUMES
   gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort   ## CONSUMES

+ 1 - 0
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc

@@ -194,6 +194,7 @@
   gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
 !endif
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
   gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
 !endif

+ 1 - 0
Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc

@@ -117,6 +117,7 @@
 #!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
 #!endif
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
   gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
 
   #

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf

@@ -49,7 +49,7 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength      ## CONSUMES
 
 [FixedPcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress       ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress            ## CONSUMES
 
 [Sources]
   TbtSmiHandler.h

+ 1 - 0
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc

@@ -65,6 +65,7 @@
 
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
 
 [PcdsFeatureFlag.common]
   ######################################

+ 1 - 0
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc

@@ -65,6 +65,7 @@
 
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
 
 [PcdsFeatureFlag.common]
   ######################################

+ 1 - 0
Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc

@@ -42,6 +42,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable         |FALSE
 [PcdsFixedAtBuild.common]
 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress       |0xE0000000
 gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress       |0x1800
 
   gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin        |10
   gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax        |18

+ 3 - 2
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf

@@ -32,6 +32,7 @@
 
 [Packages]
   MdePkg/MdePkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
   CoffeelakeSiliconPkg/SiPkg.dec
 
 [Sources]
@@ -42,5 +43,5 @@
   gTcoWdtHobGuid                              ## CONSUMES
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress     ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdTcoBaseAddress      ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress  ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdTcoBaseAddress             ## CONSUMES

+ 2 - 1
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf

@@ -32,11 +32,12 @@ BaseMemoryLib
 
 [Packages]
 MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
 CoffeelakeSiliconPkg/SiPkg.dec
 
 
 [Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
 
 
 [Sources]

+ 1 - 1
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf

@@ -39,7 +39,7 @@ CoffeelakeSiliconPkg/SiPkg.dec
 IntelSiliconPkg/IntelSiliconPkg.dec
 
 [Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
 
 
 [Sources]

+ 0 - 1
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec

@@ -516,7 +516,6 @@ gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
 ## This value is used to set the base address of PCH devices
 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
 
 ## 32KB window
 gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000

+ 4 - 0
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec

@@ -147,6 +147,10 @@
   # @Prompt Error code for VTd error.
   gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005
 
+  ## ABase I/O address.<BR><BR>
+  # @Prompt ABase I/O address.
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x0|UINT16|0x0000000D
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT)
   # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.

+ 1 - 0
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc

@@ -48,6 +48,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable         |FALSE
 [PcdsFixedAtBuild.common]
 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress    |0xE0000000
 gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength     |0x10000000
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress    |0x1800
 #
 # This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can be FixedAtBuild
 #

+ 1 - 1
Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf

@@ -46,7 +46,7 @@
   SiliconInitPreMem.c
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress                      ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress            ## CONSUMES
   gSiPkgTokenSpaceGuid.PcdTcoBaseAddress                       ## CONSUMES
 
 

+ 2 - 1
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf

@@ -30,11 +30,12 @@ PchCycleDecodingLib
 
 [Packages]
 MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
 KabylakeSiliconPkg/SiPkg.dec
 
 
 [Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
 
 
 [Sources]

+ 1 - 1
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf

@@ -35,7 +35,7 @@ KabylakeSiliconPkg/SiPkg.dec
 IntelSiliconPkg/IntelSiliconPkg.dec
 
 [Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
 gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable
 gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber

+ 1 - 1
Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf

@@ -39,7 +39,7 @@
   PeiSpiLib.c
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress       ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress       ## CONSUMES
 
 [Ppis]
   gPchSpi2PpiGuid      ## PRODUCES

+ 0 - 1
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec

@@ -497,7 +497,6 @@ gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f
 gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
 
 ## 32KB window
 gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000

+ 2 - 1
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf

@@ -31,11 +31,12 @@ BaseMemoryLib
 
 [Packages]
 MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
 TigerlakeSiliconPkg/SiPkg.dec
 
 
 [Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress
 
 [Sources]

+ 2 - 1
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf

@@ -27,11 +27,12 @@ PmcLib
 
 [Packages]
 MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
 TigerlakeSiliconPkg/SiPkg.dec
 
 
 [Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
 
 [FixedPcd]
 

+ 0 - 1
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec

@@ -976,7 +976,6 @@ gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002
 ## This value is used to set the base address of PCH devices
 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
 
 
 ## Stack size in the temporary RAM.

+ 1 - 0
Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc

@@ -60,6 +60,7 @@ gSiPkgTokenSpaceGuid.PcdSpaEnable                    |FALSE
 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress       |0xC0000000
 gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress         |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
 gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress       |0x1800
 
 [PcdsDynamicDefault.common]
 gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength          |0x10000000