OpenBoardPkgPcd.dsc 16 KB

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  1. ## @file
  2. # PCD configuration build description file for the WhiskeylakeURvp board.
  3. #
  4. # Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. ################################################################################
  10. #
  11. # Pcd Section - list of all PCD Entries used by this board.
  12. #
  13. ################################################################################
  14. [PcdsFixedAtBuild.common]
  15. ######################################
  16. # Key Boot Stage and FSP configuration
  17. ######################################
  18. #
  19. # Please select the Boot Stage here.
  20. # Stage 1 - enable debug (system deadloop after debug init)
  21. # Stage 2 - mem init (system deadloop after mem init)
  22. # Stage 3 - boot to shell only
  23. # Stage 4 - boot to OS
  24. # Stage 5 - boot to OS with security boot enabled
  25. # Stage 6 - boot with advanced features enabled
  26. #
  27. gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
  28. #
  29. # 0: FSP Wrapper is running in Dispatch mode.
  30. # 1: FSP Wrapper is running in API mode.
  31. # Note: Dispatch mode is currently NOT supported for this board.
  32. #
  33. gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
  34. #
  35. # FALSE: The board is not a FSP wrapper (FSP binary not used)
  36. # TRUE: The board is a FSP wrapper (FSP binary is used)
  37. #
  38. gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
  39. #
  40. # FSP Base address PCD will be updated in FDF basing on flash map.
  41. #
  42. gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
  43. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
  44. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
  45. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
  46. gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
  47. gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
  48. gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
  49. #
  50. # When sharing stack with boot loader, FSP only needs a small temp ram for heap
  51. #
  52. gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000
  53. #
  54. # Boot loader stack size has to be large enough for FSP execution
  55. #
  56. gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
  57. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
  58. gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
  59. gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
  60. [PcdsFeatureFlag.common]
  61. ######################################
  62. # Edk2 Configuration
  63. ######################################
  64. gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
  65. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
  66. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
  67. gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
  68. ######################################
  69. # Silicon Configuration
  70. ######################################
  71. # Build switches
  72. gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
  73. # CPU
  74. gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
  75. gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
  76. # SA
  77. gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
  78. gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
  79. gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
  80. gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
  81. gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
  82. gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
  83. gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
  84. gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
  85. gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
  86. # ME
  87. gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
  88. gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
  89. gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
  90. # Others
  91. gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
  92. gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
  93. gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
  94. gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
  95. gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
  96. gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
  97. gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
  98. gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
  99. gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
  100. gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
  101. gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
  102. gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
  103. gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
  104. gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
  105. gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used.
  106. ######################################
  107. # Platform Configuration
  108. ######################################
  109. #
  110. # MinPlatform common include for required feature PCD
  111. # These PCD must be set before the core include files, CoreCommonLib,
  112. # CorePeiLib, and CoreDxeLib.
  113. # Optional MinPlatformPkg features should be enabled after this
  114. #
  115. !include MinPlatformPkg/Include/Dsc/MinPlatformFeaturesPcd.dsc.inc
  116. #
  117. # Commonly used MinPlatform feature configuration logic that maps functionity to stage
  118. #
  119. !include BoardModulePkg/Include/Dsc/CommonStageConfig.dsc.inc
  120. ######################################
  121. # Board Configuration
  122. ######################################
  123. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
  124. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
  125. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
  126. [PcdsFixedAtBuild.common]
  127. ######################################
  128. # Edk2 Configuration
  129. ######################################
  130. !if $(TARGET) == RELEASE
  131. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
  132. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
  133. !else
  134. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
  135. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
  136. !endif
  137. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  138. gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
  139. !endif
  140. gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
  141. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
  142. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
  143. gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
  144. gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
  145. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
  146. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  147. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
  148. !endif
  149. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
  150. gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
  151. gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
  152. !if $(TARGET) == DEBUG
  153. gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
  154. !endif
  155. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
  156. !if $(TARGET) == RELEASE
  157. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
  158. !else
  159. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
  160. !endif
  161. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
  162. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
  163. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
  164. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
  165. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
  166. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
  167. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
  168. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
  169. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
  170. # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
  171. gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
  172. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
  173. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
  174. #
  175. # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
  176. # (They will be DynamicEx in FSP Dispatch mode)
  177. #
  178. ## Specifies the size of the microcode Region.
  179. # @Prompt Microcode Region size.
  180. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
  181. ## Specifies the AP wait loop state during POST phase.
  182. # The value is defined as below.
  183. # 1: Place AP in the Hlt-Loop state.
  184. # 2: Place AP in the Mwait-Loop state.
  185. # 3: Place AP in the Run-Loop state.
  186. # @Prompt The AP wait loop state.
  187. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
  188. ######################################
  189. # Silicon Configuration
  190. ######################################
  191. gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  192. #
  193. # Set the location of the DUTY_CYCLE field in the P_CNT register
  194. # and indicate the width of the clock duty cycle to OS power management
  195. #
  196. gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
  197. gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
  198. ######################################
  199. # Platform Configuration
  200. ######################################
  201. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
  202. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
  203. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
  204. #
  205. # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
  206. #
  207. # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
  208. # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
  209. # that lie entirely within the expected fixed memory regions.
  210. # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
  211. # BIT3-31: Reserved
  212. #
  213. gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
  214. !if $(TARGET) == RELEASE
  215. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
  216. !else
  217. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
  218. !endif
  219. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
  220. !if $(TARGET) == RELEASE
  221. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
  222. !else
  223. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
  224. !endif
  225. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
  226. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  227. !endif
  228. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
  229. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  230. !endif
  231. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
  232. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  233. !endif
  234. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
  235. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  236. !endif
  237. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
  238. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  239. !endif
  240. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
  241. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  242. !endif
  243. ######################################
  244. # Board Configuration
  245. ######################################
  246. gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1
  247. gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, 0x1F, 0x00}
  248. [PcdsFixedAtBuild.IA32]
  249. ######################################
  250. # Edk2 Configuration
  251. ######################################
  252. gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
  253. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
  254. gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
  255. ######################################
  256. # Platform Configuration
  257. ######################################
  258. gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
  259. [PcdsFixedAtBuild.X64]
  260. ######################################
  261. # Edk2 Configuration
  262. ######################################
  263. # Default platform supported RFC 4646 languages: (American) English
  264. gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
  265. [PcdsPatchableInModule.common]
  266. ######################################
  267. # Edk2 Configuration
  268. ######################################
  269. gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
  270. gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
  271. ######################################
  272. # Silicon Configuration
  273. ######################################
  274. !if $(TARGET) == DEBUG
  275. gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
  276. !endif
  277. [PcdsDynamicDefault]
  278. ######################################
  279. # Edk2 Configuration
  280. ######################################
  281. gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
  282. gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
  283. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
  284. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
  285. gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
  286. #
  287. # Set video to native resolution as Windows 8 WHCK requirement.
  288. #
  289. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
  290. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
  291. gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
  292. #
  293. # FSP Base address PCD will be updated in FDF basing on flash map.
  294. #
  295. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
  296. # Platform will pre-allocate UPD buffer and pass it to FspWrapper
  297. # Those dummy address will be patched before FspWrapper executing
  298. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
  299. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
  300. gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
  301. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
  302. ######################################
  303. # Board Configuration
  304. ######################################
  305. # Thunderbolt Configuration
  306. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
  307. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
  308. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
  309. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
  310. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
  311. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
  312. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
  313. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
  314. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
  315. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
  316. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
  317. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
  318. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
  319. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
  320. gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDciEnable|FALSE
  321. [PcdsDynamicHii.X64.DEFAULT]
  322. ######################################
  323. # Edk2 Configuration
  324. ######################################
  325. gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
  326. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  327. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
  328. !else
  329. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
  330. !endif