OpenBoardPkgPcd.dsc 15 KB

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  1. ## @file
  2. # PCD configuration build description file for the TigerlakeURvp board.
  3. #
  4. # Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
  5. # SPDX-License-Identifier: BSD-2-Clause-Patent
  6. #
  7. ##
  8. ################################################################################
  9. #
  10. # Pcd Section - list of all PCD Entries used by this board.
  11. #
  12. ################################################################################
  13. [PcdsFixedAtBuild.common]
  14. ######################################
  15. # Key Boot Stage and FSP configuration
  16. ######################################
  17. #
  18. # Please select the Boot Stage here.
  19. # Stage 1 - enable debug (system deadloop after debug init)
  20. # Stage 2 - mem init (system deadloop after mem init)
  21. # Stage 3 - boot to shell only
  22. # Stage 4 - boot to OS
  23. # Stage 5 - boot to OS with security boot enabled
  24. # Stage 6 - boot with advanced features enabled
  25. #
  26. gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
  27. #
  28. # 0: FSP Wrapper is running in Dispatch mode.
  29. # 1: FSP Wrapper is running in API mode.
  30. #
  31. gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
  32. #
  33. # FALSE: The board is not a FSP wrapper (FSP binary not used)
  34. # TRUE: The board is a FSP wrapper (FSP binary is used)
  35. #
  36. gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
  37. #
  38. # FSP Base address PCD will be updated in FDF basing on flash map.
  39. #
  40. gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
  41. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
  42. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
  43. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00080000
  44. gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
  45. gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
  46. gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
  47. #
  48. # PCD declared for TigerlakeSiliconPkg Fru
  49. #
  50. gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|FALSE
  51. gSiPkgTokenSpaceGuid.PcdCpuPcieEnable|TRUE
  52. gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0
  53. gSiPkgTokenSpaceGuid.PcdThcEnable|TRUE
  54. gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE
  55. ######################################
  56. # Silicon Configuration
  57. ######################################
  58. # Build switches
  59. gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
  60. # CPU
  61. gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
  62. # SA
  63. gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
  64. gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
  65. gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
  66. gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
  67. gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
  68. # ME
  69. gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
  70. gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
  71. gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
  72. # Others
  73. gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
  74. gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
  75. gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
  76. gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
  77. gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
  78. gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
  79. gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
  80. gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
  81. gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
  82. gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
  83. gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
  84. gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
  85. gSiPkgTokenSpaceGuid.PcdFspWrapperEnable|TRUE
  86. #
  87. # When sharing stack with boot loader, FSP only needs a small temp ram for heap
  88. #
  89. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  90. gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000
  91. !else
  92. #
  93. # FSP Dispatch mode will not establish separate Stack or Heap.
  94. #
  95. gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0
  96. !endif
  97. #
  98. # Boot loader stack size has to be large enough for FSP execution
  99. #
  100. gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
  101. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000
  102. #!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  103. gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
  104. #!endif
  105. gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
  106. gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
  107. #
  108. # Set the location of the DUTY_CYCLE field in the P_CNT register
  109. # and indicate the width of the clock duty cycle to OS power management
  110. #
  111. gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
  112. gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
  113. [PcdsFeatureFlag.common]
  114. ######################################
  115. # Edk2 Configuration
  116. ######################################
  117. gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
  118. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
  119. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
  120. gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
  121. ######################################
  122. # Platform Configuration
  123. ######################################
  124. #
  125. # MinPlatform common include for required feature PCD
  126. # These PCD must be set before the core include files, CoreCommonLib,
  127. # CorePeiLib, and CoreDxeLib.
  128. # Optional MinPlatformPkg features should be enabled after this
  129. #
  130. !include MinPlatformPkg/Include/Dsc/MinPlatformFeaturesPcd.dsc.inc
  131. #
  132. # Commonly used MinPlatform feature configuration logic that maps functionity to stage
  133. #
  134. !include BoardModulePkg/Include/Dsc/CommonStageConfig.dsc.inc
  135. ######################################
  136. # Board Configuration
  137. ######################################
  138. gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE
  139. [PcdsFixedAtBuild.common]
  140. ######################################
  141. # Edk2 Configuration
  142. ######################################
  143. !if $(TARGET) == RELEASE
  144. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
  145. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
  146. !else
  147. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
  148. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
  149. !endif
  150. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  151. gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
  152. !endif
  153. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
  154. !if $(TARGET) == RELEASE
  155. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
  156. !else
  157. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
  158. !endif
  159. gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
  160. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
  161. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
  162. gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
  163. gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
  164. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
  165. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  166. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
  167. !endif
  168. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
  169. gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
  170. gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
  171. !if $(TARGET) == DEBUG
  172. gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
  173. !endif
  174. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
  175. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
  176. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
  177. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
  178. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
  179. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
  180. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
  181. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
  182. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
  183. # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
  184. gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000
  185. gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0
  186. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
  187. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
  188. #
  189. # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
  190. # (They will be DynamicEx in FSP Dispatch mode)
  191. #
  192. ## Specifies the size of the microcode Region.
  193. # @Prompt Microcode Region size.
  194. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
  195. ## Specifies the AP wait loop state during POST phase.
  196. # The value is defined as below.
  197. # 1: Place AP in the Hlt-Loop state.
  198. # 2: Place AP in the Mwait-Loop state.
  199. # 3: Place AP in the Run-Loop state.
  200. # @Prompt The AP wait loop state.
  201. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
  202. ######################################
  203. # Platform Configuration
  204. ######################################
  205. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
  206. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
  207. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
  208. gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0xA0000000
  209. gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF
  210. #
  211. # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
  212. #
  213. # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
  214. # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
  215. # that lie entirely within the expected fixed memory regions.
  216. # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
  217. # BIT3-31: Reserved
  218. #
  219. gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
  220. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0xCC
  221. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA2
  222. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x3100
  223. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x2A
  224. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xC4
  225. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
  226. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  227. !endif
  228. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
  229. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  230. !endif
  231. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
  232. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  233. !endif
  234. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
  235. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  236. !endif
  237. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
  238. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  239. !endif
  240. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
  241. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  242. !endif
  243. [PcdsFixedAtBuild.IA32]
  244. ######################################
  245. # Edk2 Configuration
  246. ######################################
  247. gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
  248. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
  249. gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
  250. ######################################
  251. # Platform Configuration
  252. ######################################
  253. gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
  254. [PcdsFixedAtBuild.X64]
  255. ######################################
  256. # Edk2 Configuration
  257. ######################################
  258. # Default platform supported RFC 4646 languages: (American) English
  259. gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
  260. [PcdsPatchableInModule.common]
  261. ######################################
  262. # Edk2 Configuration
  263. ######################################
  264. gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0301
  265. gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
  266. ######################################
  267. # Silicon Configuration
  268. ######################################
  269. !if $(TARGET) == DEBUG
  270. gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
  271. !endif
  272. [PcdsDynamicDefault]
  273. ######################################
  274. # Edk2 Configuration
  275. ######################################
  276. gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
  277. gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
  278. ######################################
  279. # Silicon Configuration
  280. ######################################
  281. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  282. gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  283. !endif
  284. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
  285. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
  286. #gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
  287. #
  288. # Set video to native resolution as Windows 8 WHCK requirement.
  289. #
  290. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
  291. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
  292. gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
  293. #
  294. # FSP Base address PCD will be updated in FDF basing on flash map.
  295. #
  296. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
  297. # Platform will pre-allocate UPD buffer and pass it to FspWrapper
  298. # Those dummy address will be patched before FspWrapper executing
  299. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
  300. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
  301. gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
  302. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
  303. [PcdsDynamicHii.X64.DEFAULT]
  304. ######################################
  305. # Edk2 Configuration
  306. ######################################
  307. gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
  308. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  309. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
  310. !else
  311. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
  312. !endif
  313. [PcdsDynamicExDefault]
  314. gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
  315. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0
  316. #
  317. # Include FSP PCD settings.
  318. #
  319. !include $(PLATFORM_FSP_BIN_PACKAGE)/TigerLakeFspPcds.dsc
  320. !endif