## @file # PCD configuration build description file for the TigerlakeURvp board. # # Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## ################################################################################ # # Pcd Section - list of all PCD Entries used by this board. # ################################################################################ [PcdsFixedAtBuild.common] ###################################### # Key Boot Stage and FSP configuration ###################################### # # Please select the Boot Stage here. # Stage 1 - enable debug (system deadloop after debug init) # Stage 2 - mem init (system deadloop after mem init) # Stage 3 - boot to shell only # Stage 4 - boot to OS # Stage 5 - boot to OS with security boot enabled # Stage 6 - boot with advanced features enabled # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 # # 0: FSP Wrapper is running in Dispatch mode. # 1: FSP Wrapper is running in API mode. # gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 # # FALSE: The board is not a FSP wrapper (FSP binary not used) # TRUE: The board is a FSP wrapper (FSP binary is used) # gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE # # FSP Base address PCD will be updated in FDF basing on flash map. # gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00080000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 # # PCD declared for TigerlakeSiliconPkg Fru # gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|FALSE gSiPkgTokenSpaceGuid.PcdCpuPcieEnable|TRUE gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0 gSiPkgTokenSpaceGuid.PcdThcEnable|TRUE gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE ###################################### # Silicon Configuration ###################################### # Build switches gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE # CPU gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE # SA gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE # ME gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE # Others gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE gSiPkgTokenSpaceGuid.PcdFspWrapperEnable|TRUE # # When sharing stack with boot loader, FSP only needs a small temp ram for heap # !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000 !else # # FSP Dispatch mode will not establish separate Stack or Heap. # gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0 !endif # # Boot loader stack size has to be large enough for FSP execution # gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000 #!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 #!endif gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 # # Set the location of the DUTY_CYCLE field in the P_CNT register # and indicate the width of the clock duty cycle to OS power management # gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 [PcdsFeatureFlag.common] ###################################### # Edk2 Configuration ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE ###################################### # Platform Configuration ###################################### # # MinPlatform common include for required feature PCD # These PCD must be set before the core include files, CoreCommonLib, # CorePeiLib, and CoreDxeLib. # Optional MinPlatformPkg features should be enabled after this # !include MinPlatformPkg/Include/Dsc/MinPlatformFeaturesPcd.dsc.inc # # Commonly used MinPlatform feature configuration logic that maps functionity to stage # !include BoardModulePkg/Include/Dsc/CommonStageConfig.dsc.inc ###################################### # Board Configuration ###################################### gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE [PcdsFixedAtBuild.common] ###################################### # Edk2 Configuration ###################################### !if $(TARGET) == RELEASE gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 !else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endif gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE !if $(TARGET) == RELEASE gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE !else gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE !endif gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS) gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE !if $(TARGET) == DEBUG gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE !endif gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 # Specifies timeout value in microseconds for the BSP to detect all APs for the first time. gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000 gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 # # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild # (They will be DynamicEx in FSP Dispatch mode) # ## Specifies the size of the microcode Region. # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. # 2: Place AP in the Mwait-Loop state. # 3: Place AP in the Run-Loop state. # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 ###################################### # Platform Configuration ###################################### gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0xA0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags # # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions. # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \ # that lie entirely within the expected fixed memory regions. # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms. # BIT3-31: Reserved # gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0xCC gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA2 gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x3100 gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x2A gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xC4 !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} !endif !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} !endif !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} !endif !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} !endif !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} !endif !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} !endif [PcdsFixedAtBuild.IA32] ###################################### # Edk2 Configuration ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 ###################################### # Platform Configuration ###################################### gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 [PcdsFixedAtBuild.X64] ###################################### # Edk2 Configuration ###################################### # Default platform supported RFC 4646 languages: (American) English gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" [PcdsPatchableInModule.common] ###################################### # Edk2 Configuration ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0301 gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 ###################################### # Silicon Configuration ###################################### !if $(TARGET) == DEBUG gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 !endif [PcdsDynamicDefault] ###################################### # Edk2 Configuration ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE ###################################### # Silicon Configuration ###################################### !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength !endif gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 #gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 # # Set video to native resolution as Windows 8 WHCK requirement. # gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00 # # FSP Base address PCD will be updated in FDF basing on flash map. # gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 # Platform will pre-allocate UPD buffer and pass it to FspWrapper # Those dummy address will be patched before FspWrapper executing gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 [PcdsDynamicHii.X64.DEFAULT] ###################################### # Edk2 Configuration ###################################### gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout" !else gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" !endif [PcdsDynamicExDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0 # # Include FSP PCD settings. # !include $(PLATFORM_FSP_BIN_PACKAGE)/TigerLakeFspPcds.dsc !endif