Browse Source

CometlakeOpenBoardPkg: Add library instances

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Common package library instances.

* BaseAcpiTimerLib - Support for ACPI timer services.
* BaseGpioExpanderLib - Support for the TCA6424 IO expander.
* DxePolicyUpdateLib - Policy update in DXE.
* DxeTbtPolicyLib - DXE Thunderbolt policy initialization.
* PeiDTbtInitLib - PEI discrete Thunderbolt initialization services.
* PeiFspPolicyInitLib - PEI Intel FSP policy initialization.
* PeiI2cAccessLib - Provides I2C read and write services.
* PeiPolicyInitLib - Policy initialization in PEI.
* PeiPolicyUpdateLib - Policy update in PEI.
* PeiSiliconPolicyUpdateLibFsp - PEI FSP silicon policy initialization.
* PeiTbtPolicyLib - PEI Thunderbolt policy initialization.
* SecFspWrapperPlatformSecLib - FSP wrapper PlatformSecLib instance.
* TbtCommonLib - Common Thunderbolt services.
* PeiHdaVerbTableLib - PEI Intel HD Audio Verb Table library.
* BaseGpioExpanderLib - Common Gpio Expander functions

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Kathappan Esakkithevar 4 years ago
parent
commit
852554068b
72 changed files with 11368 additions and 0 deletions
  1. 148 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c
  2. 45 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
  3. 24 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
  4. 316 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c
  5. 60 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
  6. 206 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c
  7. 51 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
  8. 19 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
  9. 567 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c
  10. 45 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
  11. 460 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
  12. 121 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c
  13. 77 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c
  14. 743 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c
  15. 223 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
  16. 233 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h
  17. 162 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
  18. 848 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c
  19. 70 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c
  20. 96 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c
  21. 100 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
  22. 124 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
  23. 25 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
  24. 60 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
  25. 27 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
  26. 39 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
  27. 85 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
  28. 30 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
  29. 87 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
  30. 140 0
      Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
  31. 394 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/AcpiTimerLib.c
  32. 48 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
  33. 54 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
  34. 15 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.uni
  35. 308 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
  36. 36 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
  37. 2053 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c
  38. 137 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
  39. 69 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
  40. 115 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.c
  41. 39 0
      Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
  42. 88 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeCpuPolicyUpdate.c
  43. 105 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.c
  44. 90 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.h
  45. 40 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxePchPolicyUpdate.c
  46. 59 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf
  47. 58 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.c
  48. 25 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.h
  49. 37 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiCpuPolicyInit.h
  50. 23 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiMePolicyInit.h
  51. 65 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInit.c
  52. 23 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInit.h
  53. 62 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf
  54. 60 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInitPreMem.c
  55. 114 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiSaPolicyInit.c
  56. 58 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiSaPolicyInit.h
  57. 22 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiSiPolicyInit.h
  58. 80 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
  59. 32 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
  60. 108 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
  61. 49 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
  62. 14 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.h
  63. 32 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
  64. 518 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
  65. 24 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
  66. 114 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
  67. 273 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
  68. 243 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
  69. 53 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
  70. 213 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
  71. 169 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
  72. 18 0
      Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h

+ 148 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c

@@ -0,0 +1,148 @@
+/** @file
+  This file is DxeTbtPolicyLib library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <DxeTbtPolicyLibrary.h>
+#include <TbtBoardInfo.h>
+#include <Protocol/DxeTbtPolicy.h>
+#include <Guid/HobList.h>
+#include <Library/HobLib.h>
+
+
+/**
+  Update Tbt Policy Callback
+**/
+
+VOID
+EFIAPI
+UpdateTbtPolicyCallback (
+  VOID
+  )
+{
+  EFI_STATUS                     Status;
+  DXE_TBT_POLICY_PROTOCOL        *DxeTbtConfig;
+
+  DxeTbtConfig = NULL;
+  Status = EFI_NOT_FOUND;
+  DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n"));
+
+  Status = gBS->LocateProtocol (
+                  &gDxeTbtPolicyProtocolGuid,
+                  NULL,
+                  (VOID **) &DxeTbtConfig
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"));
+  } else {
+
+  }
+
+  return;
+}
+
+/**
+  Print DXE TBT Policy
+**/
+VOID
+TbtPrintDxePolicyConfig (
+  VOID
+  )
+{
+  EFI_STATUS                       Status;
+  UINT8                            Index;
+  DXE_TBT_POLICY_PROTOCOL          *DxeTbtConfig;
+
+  DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n"));
+
+  DxeTbtConfig = NULL;
+  Status = EFI_NOT_FOUND;
+  Status = gBS->LocateProtocol (
+                  &gDxeTbtPolicyProtocolGuid,
+                  NULL,
+                  (VOID **) &DxeTbtConfig
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"));
+  }
+  ASSERT_EFI_ERROR (Status);
+  //
+  // Print DTBT Policy
+  //
+  DEBUG ((DEBUG_ERROR, " ========================= DXE TBT POLICY ========================= \n"));
+  for (Index = 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
+    DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieExtraBusRsvd = %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieExtraBusRsvd));
+    DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemRsvd = %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemRsvd));
+    DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemAddrRngMax = %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemAddrRngMax));
+    DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMemRsvd = %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMemRsvd));
+    DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMemAddrRngMax = %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMemAddrRngMax));
+  }
+
+  //
+  // Print TBT Common Policy
+  //
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm = %x\n", DxeTbtConfig->TbtCommonConfig.TbtAspm));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtL1SubStates = %x\n", DxeTbtConfig->TbtCommonConfig.TbtL1SubStates));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify = %x\n", DxeTbtConfig->TbtCommonConfig.TbtHotNotify));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI = %x\n", DxeTbtConfig->TbtCommonConfig.TbtHotSMI));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr = %x\n", DxeTbtConfig->TbtCommonConfig.TbtLtr));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtPtm = %x\n", DxeTbtConfig->TbtCommonConfig.TbtPtm));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq = %x\n", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport = %x\n", DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode = %x\n", DxeTbtConfig->TbtCommonConfig.SecurityMode));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter = %x\n", DxeTbtConfig->TbtCommonConfig.Gpio5Filter));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TrA0OsupWa = %x\n", DxeTbtConfig->TbtCommonConfig.TrA0OsupWa));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch = %x\n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt = %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3Tbt));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay = %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq = %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay = %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support = %x\n", DxeTbtConfig->TbtCommonConfig.Win10Support));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity = %x\n", DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity));
+  DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.ControlIommu = %x\n", DxeTbtConfig->TbtCommonConfig.ControlIommu));
+  return;
+}
+
+/**
+  Install Tbt Policy
+
+  @param[in] ImageHandle                Image handle of this driver.
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallTbtPolicy (
+  IN  EFI_HANDLE                    ImageHandle
+  )
+{
+  EFI_STATUS                    Status;
+  DXE_TBT_POLICY_PROTOCOL       *DxeTbtPolicy;
+
+  DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n"));
+
+  DxeTbtPolicy = NULL;
+  //Alloc memory for DxeTbtPolicy
+  DxeTbtPolicy = (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof (DXE_TBT_POLICY_PROTOCOL));
+  if (DxeTbtPolicy == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gDxeTbtPolicyProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  DxeTbtPolicy
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol failed\n"));
+  }
+  return Status;
+}
+
+

+ 45 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf

@@ -0,0 +1,45 @@
+## @file
+# Component description file for Tbt functionality
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeTbtPolicyLib
+FILE_GUID = 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeTbtPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+HobLib
+
+[Packages]
+MdePkg/MdePkg.dec
+CoffeelakeSiliconPkg/SiPkg.dec
+CometlakeOpenBoardPkg/OpenBoardPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+DxeTbtPolicyLib.c
+
+
+[Guids]
+gEfiEndOfDxeEventGroupGuid
+gTbtInfoHobGuid
+
+[Protocols]
+gDxeTbtPolicyProtocolGuid
+

+ 24 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h

@@ -0,0 +1,24 @@
+/** @file
+  Header file for the DxeTBTPolicy library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_LIBRARY_H_
+#define _DXE_TBT_POLICY_LIBRARY_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <ConfigBlock.h>
+//#include <SetupVariable.h>
+#include <Guid/EventGroup.h>
+
+#endif // _DXE_TBT_POLICY_LIBRARY_H_
+

+ 316 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c

@@ -0,0 +1,316 @@
+/** @file
+  PeiTbtInit library implementition with empty functions.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/TbtCommonLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/GpioLib.h>
+
+
+/**
+  Selects the proper TBT Root port to assign resources
+  based on the user input value
+
+  @param[in]  SetupData          Pointer to Setup data
+
+  @retval     TbtSelectorChosen  Rootport number.
+**/
+VOID
+GetRootporttoSetResourcesforTbt (
+  IN UINTN                              RpIndex,
+  OUT UINT8                             *RsvdExtraBusNum,
+  OUT UINT16                            *RsvdPcieMegaMem,
+  OUT UINT8                             *PcieMemAddrRngMax,
+  OUT UINT16                            *RsvdPciePMegaMem,
+  OUT UINT8                             *PciePMemAddrRngMax,
+  OUT BOOLEAN                           *SetResourceforTbt
+  )
+{
+  UINTN TbtRpNumber;
+  TbtRpNumber = (UINTN) PcdGet8 (PcdDTbtPcieRpNumber);
+
+    if (RpIndex == (TbtRpNumber - 1)) {
+        *RsvdExtraBusNum = PcdGet8 (PcdDTbtPcieExtraBusRsvd);
+        *RsvdPcieMegaMem = PcdGet16 (PcdDTbtPcieMemRsvd);
+        *PcieMemAddrRngMax = PcdGet8 (PcdDTbtPcieMemAddrRngMax);
+        *RsvdPciePMegaMem = PcdGet16 (PcdDTbtPciePMemRsvd);
+        *PciePMemAddrRngMax = PcdGet8 (PcdDTbtPciePMemAddrRngMax);
+        *SetResourceforTbt = TRUE;
+      }
+      else {
+        *SetResourceforTbt = FALSE;
+      }
+  }
+
+/**
+  Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
+  @param[in]  CommandOffsetAddress      Tbt2Pcie Register Address
+  @param[in]  TimeOut                   Time out with 100 ms garnularity
+  @param[in]  Tbt2PcieDone              Wait condition (wait for Bit to Clear/Set)
+  @param[out] *Tbt2PcieValue Function   Register value
+**/
+BOOLEAN
+InternalWaitforCommandCompletion(
+  IN  UINT64   CommandOffsetAddress,
+  IN  UINT32   TimeOut,
+  IN  BOOLEAN  Tbt2PcieDone,
+  OUT UINT32   *Tbt2PcieValue
+  )
+{
+  BOOLEAN ReturnFlag;
+  UINT32  Tbt2PcieCheck;
+
+  ReturnFlag = FALSE;
+  while (TimeOut-- > 0) {
+    *Tbt2PcieValue = PciSegmentRead32 (CommandOffsetAddress);
+
+    if (0xFFFFFFFF == *Tbt2PcieValue ) {
+      //
+      // Device is not here return now
+      //
+      ReturnFlag     = FALSE;
+      break;
+    }
+
+    if(Tbt2PcieDone) {
+      Tbt2PcieCheck  =  *Tbt2PcieValue & TBT2PCIE_DON_R;
+    } else {
+      Tbt2PcieCheck  = !(*Tbt2PcieValue & TBT2PCIE_DON_R);
+    }
+
+    if (Tbt2PcieCheck) {
+      ReturnFlag     = TRUE;
+      break;
+    }
+
+    MicroSecondDelay(TBT_MAIL_BOX_DELAY);
+  }
+  return ReturnFlag;
+}
+/**
+  Get Security Level.
+  @param[in]  Bus       Bus number Host Router (DTBT)
+  @param[in]  Device    Device number for Host Router (DTBT)
+  @param[in]  Function  Function number for  Host Router (DTBT)
+  @param[in]  Command   Command for  Host Router (DTBT)
+  @param[in]  Timeout   Time out with 100 ms garnularity
+**/
+UINT8
+GetSecLevel (
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT8                   Command,
+  IN    UINT32                  Timeout
+  )
+{
+  UINT64       Pcie2Tbt;
+  UINT64       Tbt2Pcie;
+  UINT32       RegisterValue;
+  UINT8        ReturnFlag;
+
+  ReturnFlag           = 0xFF;
+
+  DEBUG ((DEBUG_INFO, "GetSecLevel() \n"));
+
+  GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+  GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+  PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
+
+  if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue)) {
+    ReturnFlag     = (UINT8) (0xFF & (RegisterValue >> 8));
+  }
+
+  PciSegmentWrite32 (Pcie2Tbt, 0);
+
+  InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValue);
+  DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag));
+
+  return ReturnFlag;
+}
+
+/**
+  Set Security Level.
+  @param[in]  Data      Security State
+  @param[in]  Bus       Bus number for Host Router (DTBT)
+  @param[in]  Device    Device number for Host Router (DTBT)
+  @param[in]  Function  Function number for Host Router (DTBT)
+  @param[in]  Command   Command for  Host Router (DTBT)
+  @param[in]  Timeout   Time out with 100 ms garnularity
+**/
+BOOLEAN
+SetSecLevel (
+  IN    UINT8                   Data,
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT8                   Command,
+  IN    UINT32                  Timeout
+  )
+{
+  UINT64       Pcie2Tbt;
+  UINT64       Tbt2Pcie;
+  UINT32       RegisterValue;
+  BOOLEAN      ReturnFlag;
+
+  ReturnFlag   = FALSE;
+
+  DEBUG ((DEBUG_INFO, "SetSecLevel() \n"));
+
+  GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+  GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+  PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B);
+
+  ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
+  DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue));
+  PciSegmentWrite32 (Pcie2Tbt, 0);
+
+  InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValue);
+  DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag));
+  return ReturnFlag;
+}
+
+/**
+Based on the Security Mode Selection, BIOS drives FORCE_PWR.
+
+@param[in]  GpioNumber
+@param[in]  Value
+**/
+VOID
+ForceDtbtPower(
+  IN  UINT8          GpioAccessType,
+  IN  UINT8          Expander,
+  IN  UINT32         GpioNumber,
+  IN  BOOLEAN        Value
+)
+{
+  if (GpioAccessType == 0x01) {
+    // PCH
+    GpioSetOutputValue (GpioNumber, (UINT32)Value);
+  } else if (GpioAccessType == 0x02) {
+    // IoExpander {TCA6424A}
+    GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value);
+  }
+}
+
+/**
+Execute TBT Mail Box Command
+
+@param[in]  Command   TBT Command
+@param[in]  Bus       Bus number for  Host Router (DTBT)
+@param[in]  Device    Device number for  Host Router (DTBT)
+@param[in]  Function  Function number for  Host Router (DTBT)
+@param[in]  Timeout   Time out with 100 ms garnularity
+@Retval     true      if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtCommand(
+   IN    UINT8                   Command,
+   IN    UINT8                   Bus,
+   IN    UINT8                   Device,
+   IN    UINT8                   Function,
+   IN    UINT32                  Timeout
+)
+{
+   UINT64      Pcie2Tbt;
+   UINT64      Tbt2Pcie;
+   UINT32      RegisterValue;
+   BOOLEAN     ReturnFlag;
+
+   GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+   GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+   PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
+
+   ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
+
+   PciSegmentWrite32(Pcie2Tbt, 0);
+
+   return ReturnFlag;
+}
+/**
+  Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
+
+  @param[in]  RpNumber              Root port physical number. (0-based)
+  @param[out] RpDev                 Return corresponding root port device number.
+  @param[out] RpFun                 Return corresponding root port function number.
+
+  @retval     EFI_SUCCESS           Root port device and function is retrieved
+  @retval     EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE is Passed
+**/
+EFI_STATUS
+EFIAPI
+GetDTbtRpDevFun (
+  IN  BOOLEAN Type,
+  IN  UINTN   RpNumber,
+  OUT UINTN   *RpDev,
+  OUT UINTN   *RpFunc
+  )
+{
+  EFI_STATUS            Status;
+  UINTN                 TbtRpDev;
+  UINTN                 TbtRpFunc;
+
+  Status = EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if valid input found.
+  //
+  // PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be
+  // with device number 0x1 and Function number 0,1 and 2 respectively.
+  //
+  if (Type == DTBT_TYPE_PEG)
+  {
+    //
+    //  PEG Rootport
+    //
+    if (RpNumber <= 2) {
+      *RpDev  =   0x01;
+      *RpFunc =   RpNumber;
+      Status  =   EFI_SUCCESS;
+    }
+  }
+  if (Type == DTBT_TYPE_PCH)
+  {
+    //
+    //  PCH Rootport
+    //
+    if (RpNumber <= 23) {
+      Status  = GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc);
+      *RpDev  = TbtRpDev;
+      *RpFunc = TbtRpFunc;
+    }
+  }
+
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
+
+BOOLEAN
+IsTbtHostRouter (
+  IN    UINT16  DeviceID
+  )
+{
+  switch (DeviceID) {
+  case AR_HR_2C:
+  case AR_HR_4C:
+  case AR_HR_LP:
+  case AR_HR_C0_2C:
+  case AR_HR_C0_4C:
+  case TR_HR_2C:
+  case TR_HR_4C:
+    return TRUE;
+  }
+
+  return FALSE;
+} // IsTbtHostRouter
+
+

+ 60 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf

@@ -0,0 +1,60 @@
+## @file
+# Component information file for Tbt common library
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = TbtCommonLib
+  FILE_GUID                      = 5F03614E-CB56-40B1-9989-A09E25BBA294
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = TbtCommonLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[LibraryClasses]
+  DebugLib
+  PchPcieRpLib
+  PciSegmentLib
+  TimerLib
+  BaseLib
+  GpioLib
+  GpioExpanderLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode        ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI              ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch          ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax   ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd        ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber
+
+[Sources]
+  TbtCommonLib.c
+
+

+ 206 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c

@@ -0,0 +1,206 @@
+/** @file
+  This file is PeiTbtPolicyLib library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+#include <PiPei.h>
+#include <PeiTbtPolicyLibrary.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/PeiTbtPolicy.h>
+#include <Base.h>
+#include <GpioConfig.h>
+
+/**
+  Update PEI TBT Policy Callback
+**/
+VOID
+EFIAPI
+UpdatePeiTbtPolicy (
+  VOID
+  )
+{
+  EFI_STATUS                       Status;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariableServices;
+  PEI_TBT_POLICY                   *PeiTbtConfig;
+
+  PeiTbtConfig = NULL;
+  Status = EFI_NOT_FOUND;
+
+  DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n"));
+
+  Status = PeiServicesLocatePpi (
+             &gEfiPeiReadOnlyVariable2PpiGuid,
+             0,
+             NULL,
+             (VOID **) &VariableServices
+             );
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PeiServicesLocatePpi (
+             &gPeiTbtPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &PeiTbtConfig
+             );
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+  }
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Update DTBT Policy
+  //
+  PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn = PcdGet8 (PcdDTbtControllerEn);
+  if (PcdGet8 (PcdDTbtControllerType) == TYPE_PEG)
+  {
+    PeiTbtConfig-> DTbtControllerConfig.Type = (UINT8) TYPE_PEG;
+    PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber = 1; // PEG RP 1 (Function no. 0)
+  }
+  else {
+    PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber = PcdGet8 (PcdDTbtPcieRpNumber);
+    PeiTbtConfig-> DTbtControllerConfig.Type = PcdGet8 (PcdDTbtControllerType);
+  }
+  PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad = (GPIO_PAD) PcdGet32 (PcdDTbtCioPlugEventGpioPad);
+  if (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad)) {
+    PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting = 0;
+    PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
+  }
+  else {
+    PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting = 1;
+    //
+    // Update Signature based on platform GPIO.
+    //
+    PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = SIGNATURE_32('X', 'T', 'B', 'T');
+  }
+  PeiTbtConfig->DTbtCommonConfig.TbtBootOn = PcdGet8 (PcdDTbtBootOn);
+  PeiTbtConfig->DTbtCommonConfig.TbtUsbOn = PcdGet8 (PcdDTbtUsbOn);
+  PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr = PcdGet8 (PcdDTbtGpio3ForcePwr);
+  PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly = PcdGet16 (PcdDTbtGpio3ForcePwrDly);
+
+  return;
+}
+
+/**
+  Print PEI TBT Policy
+**/
+VOID
+EFIAPI
+TbtPrintPeiPolicyConfig (
+  VOID
+  )
+{
+  DEBUG_CODE_BEGIN ();
+  EFI_STATUS                       Status;
+  PEI_TBT_POLICY                   *PeiTbtConfig;
+
+  PeiTbtConfig = NULL;
+  Status = EFI_NOT_FOUND;
+  DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n"));
+
+  Status = PeiServicesLocatePpi (
+             &gPeiTbtPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &PeiTbtConfig
+             );
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+  }
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Print DTBT Policy
+  //
+  DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print BEGIN -----------------\n"));
+  DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION));
+  DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG  -----------------\n"));
+  DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION));
+
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn = %x\n", PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type = %x\n", PeiTbtConfig-> DTbtControllerConfig.Type));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber = %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.GpioPad = %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.GpioLevel = %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.GpioPad = %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.GpioLevel = %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad = %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting = %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting));
+
+
+  //
+  // Print DTBT Common Policy
+  //
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn = %x\n", PeiTbtConfig->DTbtCommonConfig.TbtBootOn));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn = %x\n", PeiTbtConfig->DTbtCommonConfig.TbtUsbOn));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr = %x\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly = %x\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration = %x\n", PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration));
+  DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport = %x\n", PeiTbtConfig->DTbtCommonConfig.PcieRstSupport));
+
+  DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print END -----------------\n"));
+  DEBUG_CODE_END ();
+
+  return;
+}
+
+/**
+  Install Tbt Policy
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallPeiTbtPolicy (
+  VOID
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_PEI_PPI_DESCRIPTOR        *PeiTbtPolicyPpiDesc;
+  PEI_TBT_POLICY                *PeiTbtConfig;
+
+  DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n"));
+
+  PeiTbtConfig = NULL;
+
+  //
+  // Allocate memory for PeiTbtPolicyPpiDesc
+  //
+  PeiTbtPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  ASSERT (PeiTbtPolicyPpiDesc != NULL);
+  if (PeiTbtPolicyPpiDesc == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  //
+  // Allocate memory and initialize all default to zero for PeiTbtPolicy
+  //
+  PeiTbtConfig = (PEI_TBT_POLICY *) AllocateZeroPool (sizeof (PEI_TBT_POLICY));
+  ASSERT (PeiTbtConfig != NULL);
+  if (PeiTbtConfig == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  //
+  // Initialize PPI
+  //
+  PeiTbtPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  PeiTbtPolicyPpiDesc->Guid = &gPeiTbtPolicyPpiGuid;
+  PeiTbtPolicyPpiDesc->Ppi = PeiTbtConfig;
+
+  Status = PeiServicesInstallPpi (PeiTbtPolicyPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n"));
+  }
+  return Status;
+}
+
+

+ 51 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf

@@ -0,0 +1,51 @@
+## @file
+# Component description file for Tbt policy
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiTbtPolicyLib
+FILE_GUID = 4A95FDBB-2535-49eb-9A79-D56D24257106
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = PeiTbtPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+PeiServicesLib
+PeiServicesTablePointerLib
+MemoryAllocationLib
+DebugLib
+PostCodeLib
+HobLib
+GpioLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad    ## CONSUMES
+
+[Sources]
+PeiTbtPolicyLib.c
+
+[Guids]
+gTbtInfoHobGuid
+
+[Ppis]
+gEfiPeiReadOnlyVariable2PpiGuid
+gPeiTbtPolicyPpiGuid
+

+ 19 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h

@@ -0,0 +1,19 @@
+/** @file
+  Header file for the PeiTBTPolicy library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_LIBRARY_H_
+#define _PEI_TBT_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#endif // _PEI_TBT_POLICY_LIBRARY_H_
+

+ 567 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c

@@ -0,0 +1,567 @@
+/** @file
+  Thunderbolt(TM) Pei Library
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/GpioExpanderLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <Base.h>
+#include <Library/TbtCommonLib.h>
+#include <TbtBoardInfo.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Ppi/PeiTbtPolicy.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiTbtPolicyLib.h>
+#include <Library/PchPmcLib.h>
+#include <Private/Library/PeiDTbtInitLib.h>
+
+/**
+Is host router (For dTBT) or End Point (For iTBT) present before sleep
+
+@param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER
+@param[in] Controller     - Controller begin offset of CMOS
+
+@Retval     TRUE      There is a TBT HostRouter presented before sleep
+@Retval     FALSE     There is no TBT HostRouter presented before sleep
+
+BOOLEAN
+IsHostRouterPresentBeforeSleep(
+IN  UINT8        ControllerType,
+IN  UINT8        Controller
+)
+{
+  UINT8 SavedState;
+
+  SavedState = (UINT8)GetTbtHostRouterStatus();
+  if (ControllerType == DTBT_CONTROLLER){
+    return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) == (DTBT_SAVE_STATE_OFFSET << Controller));
+  } else {
+    if (ControllerType == ITBT_CONTROLLER) {
+      return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) == (ITBT_SAVE_STATE_OFFSET << Controller));
+    }
+  }
+  return 0;
+}
+**/
+
+/**
+Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode with PreBootAclEnable
+
+@param[in]  Bus       Bus number for Host Router (DTBT)
+@param[in]  Device    Device number for Host Router (DTBT)
+@param[in]  Function  Function number for Host Router (DTBT)
+@param[in]  Timeout   Time out with 100 ms garnularity
+@Retval     true      if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(
+   IN    UINT8                   Bus,
+   IN    UINT8                   Device,
+   IN    UINT8                   Function,
+   IN    UINT32                  Timeout
+)
+{
+  UINT64      Pcie2Tbt;
+  UINT64      Tbt2Pcie;
+  UINT32      RegisterValue;
+  BOOLEAN     ReturnFlag;
+  UINT32      Command;
+
+  GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+  GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
+
+// If PreBootAcl is Enable, we need to enable DATA bit while sending SX EXIT MAIL BOX Command
+  Command = (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED;
+  PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
+
+  ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
+
+  PciSegmentWrite32(Pcie2Tbt, 0);
+
+  return ReturnFlag;
+}
+
+/**
+Set the Sleep Mode if the HR is up.
+@param[in]  Bus       Bus number for Host Router (DTBT)
+@param[in]  Device    Device number for Host Router (DTBT)
+@param[in]  Function  Function number for Host Router (DTBT)
+**/
+VOID
+TbtSetSxMode(
+IN    UINT8                   Bus,
+IN    UINT8                   Device,
+IN    UINT8                   Function,
+IN    UINT8                   TbtBootOn
+)
+{
+  UINT64                          TbtUsDevId;
+  UINT64                          Tbt2Pcie;
+  UINT32                          RegVal;
+  UINT32                          MaxLoopCount;
+  UINTN                           Delay;
+  UINT8                           RetCode;
+  EFI_BOOT_MODE                   BootMode;
+  EFI_STATUS                      Status;
+
+  TbtUsDevId = PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0);
+  GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
+
+  MaxLoopCount = TBT_5S_TIMEOUT;  // Wait 5 sec
+  Delay = 100 * 1000;
+  RetCode = 0x62;
+
+  Status = PeiServicesGetBootMode(&BootMode);
+  ASSERT_EFI_ERROR(Status);
+
+  if ((BootMode == BOOT_ON_S4_RESUME) && (TbtBootOn == 2)) {
+    MaxLoopCount = TBT_3S_TIMEOUT;
+    if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Function, MaxLoopCount)) {
+      //
+      // Nothing to wait, HR is not responsive
+      //
+      return;
+    }
+  }
+  else {
+    if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device, Function, MaxLoopCount)) {
+      //
+      // Nothing to wait, HR is not responsive
+      //
+      return;
+    }
+  }
+
+  DEBUG((DEBUG_INFO, "Wait for Dev ID != 0xFF\n"));
+
+  while (MaxLoopCount-- > 0) {
+    //
+    // Check what HR still here
+    //
+    RegVal = PciSegmentRead32(Tbt2Pcie);
+    if (0xFFFFFFFF == RegVal) {
+      RetCode = 0x6F;
+      break;
+    }
+    //
+    // Check completion of TBT link
+    //
+    RegVal = PciSegmentRead32(TbtUsDevId);
+    if (0xFFFFFFFF != RegVal) {
+      RetCode = 0x61;
+      break;
+    }
+
+    MicroSecondDelay(Delay);
+  }
+
+  DEBUG((DEBUG_INFO, "Return code = 0x%x\n", RetCode));
+}
+/**
+  set tPCH25 Timing to 10 ms for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSetTPch25Timing (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+)
+{
+  DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n"));
+  UINT32                PchPwrmBase;
+
+  //
+  //During boot, reboot and wake  tPCH25 Timing should be set to 10 ms
+  //
+  MmioOr32 (
+    (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG),
+    (BIT0 | BIT1)
+    );
+
+  DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n"));
+  return EFI_SUCCESS;
+}
+
+/**
+  Do ForcePower for DTBT Controller
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtForcePower (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+)
+{
+
+  DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n"));
+
+      if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) {
+        DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad = %x \n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
+        ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel);
+        DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n"));
+        MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly * 1000);
+        DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower = 0x%x ms \n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
+      }
+
+  DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n"));
+  return EFI_SUCCESS;
+}
+
+/**
+  Clear VGA Registers for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtClearVgaRegisters (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+)
+{
+  UINTN      RpDev;
+  UINTN      RpFunc;
+  EFI_STATUS Status;
+  UINT64     BridngeBaseAddress;
+  UINT16     Data16;
+
+  DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n"));
+
+  Status = EFI_SUCCESS;
+
+  Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+  ASSERT_EFI_ERROR(Status);
+  //
+  // VGA Enable and VGA 16-bit decode registers of Bridge control register of Root port where
+  // Host router resides should be cleaned
+  //
+
+  BridngeBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UINT32)RpFunc, 0);
+  Data16 = PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSET);
+  Data16 &= (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16));
+  PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSET, Data16);
+
+  DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n"));
+  return Status;
+}
+
+/**
+  Exectue Mail box command "Boot On".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtBootOn(
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+)
+{
+  EFI_STATUS Status;
+  UINT32     OrgBusNumberConfiguration;
+  UINTN      RpDev;
+  UINTN      RpFunc;
+
+  DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n"));
+
+  Status = EFI_SUCCESS;
+
+      Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+      ASSERT_EFI_ERROR(Status);
+      OrgBusNumberConfiguration = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
+      //
+      // Set Sec/Sub buses to 0xF0
+      //
+      PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
+      //
+      //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we need to do the below:
+      //Bios should send "Boot On" message through PCIE2TBT register
+      //The Boot On command as described above would include the command and acknowledge from FW (with the default timeout in BIOS),
+      //once the Boot On command is completed it is guaranteed that the AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
+      //next step from BIOS is enumeration using SMI
+      //
+
+      if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
+        //
+        // Exectue Mail box command "Boot On / Pre-Boot ACL"
+        //
+        //Command may be executed only during boot/reboot and not during Sx exit flow
+        if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 1) {
+          if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_TIMEOUT)) {
+            //
+            // Nothing to wait, HR is not responsive
+            //
+            DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Boot On message sent failed \n"));
+          }
+        }
+        if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2) {
+          if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_3S_TIMEOUT)) {
+            //
+            // Nothing to wait, HR is not responsive
+            //
+            DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Pre-Boot ACL message sent failed \n"));
+          }
+        }
+      }
+      //
+      // Reset Sec/Sub buses to original value
+      //
+      PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
+
+  DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n"));
+  return Status;
+}
+
+/**
+  Exectue Mail box command "USB On".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtUsbOn(
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+)
+{
+  EFI_STATUS                      Status;
+  UINTN                           RpDev;
+  UINTN                           RpFunc;
+  UINT32                          OrgBusNumberConfiguration;
+  UINT64                          TbtBaseAddress;
+  UINT32                          MaxWaitIter;
+  UINT32                          RegVal;
+  EFI_BOOT_MODE                   BootMode;
+
+  DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n"));
+
+  Status = EFI_SUCCESS;
+
+      Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+      ASSERT_EFI_ERROR(Status);
+      OrgBusNumberConfiguration = PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
+      //
+      // Set Sec/Sub buses to 0xF0
+      //
+      PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
+
+      //
+      //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup we need to do the below:
+      //Bios should send "Usb On" message through PCIE2TBT register
+      //The Usb On command as described above would include the command and acknowledge from FW (with the default timeout in BIOS),
+      //once the Usb On command is completed it is guaranteed that the AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
+      //next step from BIOS is enumeration using SMI
+      //
+      if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) {
+        if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
+          MaxWaitIter = 50;   // Wait 5 sec
+          TbtBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0);
+          //
+          // Driver clears the PCIe2TBT Valid bit to support two consicutive mailbox commands
+          //
+          PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0);
+          DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R = 0x%lx \n", TbtBaseAddress + PCIE2TBT_DTBT_R));
+          while (MaxWaitIter-- > 0) {
+            RegVal = PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R);
+            if (0xFFFFFFFF == RegVal) {
+              //
+              // Device is not here return now
+              //
+              DEBUG((DEBUG_INFO, "TBT device is not present \n"));
+              break;
+            }
+
+            if (!(RegVal & TBT2PCIE_DON_R)) {
+              break;
+            }
+            MicroSecondDelay(100 * 1000);
+          }
+        }
+
+        Status = PeiServicesGetBootMode(&BootMode);
+        ASSERT_EFI_ERROR(Status);
+
+        //
+        // Exectue Mail box command "Usb On"
+        //
+        //Command may be executed only during boot/reboot and not during S3 exit flow
+        //In case of S4 Exit send USB ON cmd only if Host Router was inactive/not present during S4 entry
+        if ((BootMode == BOOT_ON_S4_RESUME) ) {
+          // USB_ON cmd not required
+        } else {
+          if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_TIMEOUT)) {
+            //
+            // Nothing to wait, HR is not responsive
+            //
+            DEBUG((DEBUG_INFO, "<TbtPei> TbtBootSupport - Usb On message sent failed \n"));
+          }
+        }
+      }
+      //
+      // Reset Sec/Sub buses to original value
+      //
+      PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
+
+  DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n"));
+  return Status;
+}
+
+/**
+  Exectue Mail box command "Sx Exit".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSxExitFlow(
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+)
+{
+  EFI_STATUS                      Status;
+  UINT32                          OrgBusNumberConfiguration;
+  UINTN                           RpDev;
+  UINTN                           RpFunc;
+  UINT32                          Count;
+
+  DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n"));
+
+  Status = EFI_SUCCESS;
+  Count = 0;
+
+      Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
+      ASSERT_EFI_ERROR(Status);
+      OrgBusNumberConfiguration = PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
+      //
+      // Set Sec/Sub buses to 0xF0
+      //
+      PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
+
+      if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2)) {
+        //
+        // WA: When system with TBT 3.1 device, resume SX system need to wait device ready. In document that maximum time out should be 500ms.
+        //
+        while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0, 0x08)) == 0xffffffff) { //End Device will be with Device Number 0x0, Function Number 0x0.
+          MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec
+          Count++;
+          if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S board.
+          break;
+          }
+        }
+
+        //
+        // Upon wake, if BIOS saved pre-Sx Host Router state as active (system went to sleep with
+        // attached devices), BIOS should:
+        // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
+        // 2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
+        // 3. Continue regular wake flow.
+        //
+        //
+        // Exectue Mail box command and perform "wait for fast link bring-up" loop
+        //
+        TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn);
+      }
+      //
+      // Reset Sec/Sub buses to original value
+      //
+      PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
+
+  DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n"));
+  return Status;
+}
+
+
+/**
+  Initialize Thunderbolt(TM)
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     others
+**/
+EFI_STATUS
+EFIAPI
+TbtInit (
+  VOID
+  )
+{
+  EFI_STATUS            Status;
+  PEI_TBT_POLICY             *PeiTbtConfig;
+
+  //
+  // Get the TBT Policy
+  //
+  Status = PeiServicesLocatePpi (
+             &gPeiTbtPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &PeiTbtConfig
+             );
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+  }
+  ASSERT_EFI_ERROR (Status);
+  //
+  // Exectue Mail box command "Boot On"
+  //
+  Status = DTbtBootOn (PeiTbtConfig);
+  //
+  // Exectue Mail box command "Usb On"
+  //
+  Status = DTbtUsbOn (PeiTbtConfig);
+  //
+  //During boot, reboot and wake  (bits [1:0]) of PCH PM_CFG register should be
+  //set to 11b - 10 ms (default value is 0b - 10 us)
+  //
+  Status = DTbtSetTPch25Timing (PeiTbtConfig);
+  //
+  // Configure Tbt Force Power
+  //
+  Status = DTbtForcePower (PeiTbtConfig);
+  //
+  // VGA Enable and VGA 16-bit decode registers of Bridge control register of Root port where
+  // Host router resides should be cleaned
+  //
+  Status = DTbtClearVgaRegisters (PeiTbtConfig);
+  //
+  // Upon wake, if BIOS saved pre-Sx Host Router state as active (system went to sleep with
+  // attached devices), BIOS should:
+  // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
+  // 2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
+  // 3. Continue regular wake flow.
+  //
+  Status = DTbtSxExitFlow (PeiTbtConfig);
+  return EFI_SUCCESS;
+}
+

+ 45 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf

@@ -0,0 +1,45 @@
+## @file
+# Component description file for PEI DTBT Init library.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiDTbtInitLib
+  FILE_GUID                      = 06768A8D-8152-403f-83C1-59584FD2B438
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiDTbtInitLib
+
+[LibraryClasses]
+  PeiServicesLib
+  DebugLib
+  PcdLib
+  TbtCommonLib
+  PciSegmentLib
+  PeiTbtPolicyLib
+  PchPmcLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[Ppis]
+  gPeiTbtPolicyPpiGuid                          ## CONSUMES
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress  ## CONSUMES
+  #gClientCommonModuleTokenSpaceGuid.PcdTbtSupport    ## PRODUCES
+
+[Sources]
+  PeiDTbtInitLib.c
+

+ 460 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c

@@ -0,0 +1,460 @@
+/** @file
+  Implementation of Fsp CPU Policy Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Ppi/SecPlatformInformation2.h>
+
+#include <CpuAccess.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PcdLib.h>
+#include <FspEas.h>
+
+/**
+  Performs FSP CPU PEI Policy initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                      Status;
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
+  CPU_OVERCLOCKING_PREMEM_CONFIG  *CpuOverClockingPreMemConfig;
+  CPU_CONFIG_LIB_PREMEM_CONFIG    *CpuConfigLibPreMemConfig;
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n"));
+
+  //
+  // Locate SiPreMemPolicyPpi
+  //
+  SiPreMemPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPreMemPolicyPpi
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclockingPreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  ///
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n"));
+
+  //
+  // Overclocking PreMem policies
+  //
+  FspmUpd->FspmConfig.OcSupport               = (UINT8) CpuOverClockingPreMemConfig->OcSupport;
+  FspmUpd->FspmConfig.OcLock                  = (UINT8) CpuOverClockingPreMemConfig->OcLock;
+  FspmUpd->FspmConfig.CoreMaxOcRatio          = (UINT8) CpuOverClockingPreMemConfig->CoreMaxOcRatio;
+  FspmUpd->FspmConfig.CoreVoltageMode         = (UINT8) CpuOverClockingPreMemConfig->CoreVoltageMode;
+  FspmUpd->FspmConfig.CoreVoltageOverride     = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOverride;
+  FspmUpd->FspmConfig.CoreVoltageAdaptive     = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageAdaptive;
+  FspmUpd->FspmConfig.CoreVoltageOffset       = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOffset;
+  FspmUpd->FspmConfig.CorePllVoltageOffset    = (UINT8) CpuOverClockingPreMemConfig->CorePllVoltageOffset;
+  FspmUpd->FspmConfig.RingMaxOcRatio          = (UINT8) CpuOverClockingPreMemConfig->RingMaxOcRatio;
+  FspmUpd->FspmConfig.RingVoltageOverride     = (UINT16) CpuOverClockingPreMemConfig->RingVoltageOverride;
+  FspmUpd->FspmConfig.RingVoltageAdaptive     = (UINT16) CpuOverClockingPreMemConfig->RingVoltageAdaptive;
+  FspmUpd->FspmConfig.RingVoltageOffset       = (UINT16) CpuOverClockingPreMemConfig->RingVoltageOffset;
+  FspmUpd->FspmConfig.RingPllVoltageOffset    = (UINT8) CpuOverClockingPreMemConfig->RingPllVoltageOffset;
+  FspmUpd->FspmConfig.GtPllVoltageOffset      = (UINT8) CpuOverClockingPreMemConfig->GtPllVoltageOffset;
+  FspmUpd->FspmConfig.RingPllVoltageOffset    = (UINT8) CpuOverClockingPreMemConfig->RingPllVoltageOffset;
+  FspmUpd->FspmConfig.SaPllVoltageOffset      = (UINT8) CpuOverClockingPreMemConfig->SaPllVoltageOffset;
+  FspmUpd->FspmConfig.McPllVoltageOffset      = (UINT8) CpuOverClockingPreMemConfig->McPllVoltageOffset;
+  FspmUpd->FspmConfig.RingDownBin             = (UINT8) CpuOverClockingPreMemConfig->RingDownBin;
+  FspmUpd->FspmConfig.RingVoltageMode         = (UINT8) CpuOverClockingPreMemConfig->RingVoltageMode;
+  FspmUpd->FspmConfig.Avx2RatioOffset         = (UINT8) CpuOverClockingPreMemConfig->Avx2RatioOffset;
+  FspmUpd->FspmConfig.Avx3RatioOffset         = (UINT8) CpuOverClockingPreMemConfig->Avx3RatioOffset;
+  FspmUpd->FspmConfig.BclkAdaptiveVoltage     = (UINT8) CpuOverClockingPreMemConfig->BclkAdaptiveVoltage;
+  FspmUpd->FspmConfig.TjMaxOffset             = (UINT8) CpuOverClockingPreMemConfig->TjMaxOffset;
+  FspmUpd->FspmConfig.TvbRatioClipping        = (UINT8) CpuOverClockingPreMemConfig->TvbRatioClipping;
+  FspmUpd->FspmConfig.TvbVoltageOptimization  = (UINT8) CpuOverClockingPreMemConfig->TvbVoltageOptimization;
+
+  //
+  //  Cpu Config Lib policies
+  //
+  FspmUpd->FspmConfig.HyperThreading            = (UINT8) CpuConfigLibPreMemConfig->HyperThreading;
+  FspmUpd->FspmConfig.BootFrequency             = (UINT8) CpuConfigLibPreMemConfig->BootFrequency;
+  FspmUpd->FspmConfig.ActiveCoreCount           = (UINT8) CpuConfigLibPreMemConfig->ActiveCoreCount;
+  FspmUpd->FspmConfig.JtagC10PowerGateDisable   = (UINT8) CpuConfigLibPreMemConfig->JtagC10PowerGateDisable;
+  FspmUpd->FspmConfig.FClkFrequency             = (UINT8) CpuConfigLibPreMemConfig->FClkFrequency;
+  FspmUpd->FspmConfig.BistOnReset               = (UINT8) CpuConfigLibPreMemConfig->BistOnReset;
+  FspmUpd->FspmConfig.VmxEnable                 = (UINT8) CpuConfigLibPreMemConfig->VmxEnable;
+  FspmUpd->FspmConfig.CpuRatio                  = (UINT8) CpuConfigLibPreMemConfig->CpuRatio;
+  FspmUpd->FspmConfig.PeciSxReset               = (UINT8) CpuConfigLibPreMemConfig->PeciSxReset;
+  FspmUpd->FspmConfig.PeciC10Reset              = (UINT8) CpuConfigLibPreMemConfig->PeciC10Reset;
+  FspmUpd->FspmConfig.SkipMpInit                = (UINT8) CpuConfigLibPreMemConfig->SkipMpInit;
+
+  //
+  // DisableMtrrProgram <1> Disable Mtrrs program. <0> Program Mtrrs in FSP
+  //
+  FspmUpd->FspmConfig.DisableMtrrProgram        = (UINT8) 0;
+
+  return EFI_SUCCESS;
+}
+
+/**
+ This routine is used to get Sec Platform Information Record2 Pointer.
+
+ @param[in] PeiServices    Pointer to the PEI services table
+
+ @retval GetSecPlatformInformation2 - The pointer of Sec Platform Information Record2 Pointer.
+ **/
+
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformation2(
+  IN EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_SEC_PLATFORM_INFORMATION2_PPI    *SecPlatformInformation2Ppi;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 = NULL;
+  UINT64                               InformationSize;
+  EFI_STATUS Status;
+
+  //
+  // Get BIST information from Sec Platform Information2 Ppi firstly
+  //
+  Status = PeiServicesLocatePpi (
+             &gEfiSecPlatformInformation2PpiGuid,   // GUID
+             0,                                     // Instance
+             NULL,                                  // EFI_PEI_PPI_DESCRIPTOR
+             (VOID ** ) &SecPlatformInformation2Ppi // PPI
+             );
+
+  DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi2 Status - %x\n", Status));
+  if (EFI_ERROR(Status)) {
+    return NULL;
+  }
+
+  InformationSize = 0;
+
+  Status = SecPlatformInformation2Ppi->PlatformInformation2 (
+                                         (CONST EFI_PEI_SERVICES  **) PeiServices,
+                                         &InformationSize,
+                                         SecPlatformInformation2
+                                         );
+
+  ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+  if (Status != EFI_BUFFER_TOO_SMALL) {
+    return NULL;
+  }
+
+  SecPlatformInformation2 = AllocatePool((UINTN)InformationSize);
+  ASSERT (SecPlatformInformation2 != NULL);
+  if (SecPlatformInformation2 == NULL) {
+    return NULL;
+  }
+
+  //
+  // Retrieve BIST data from SecPlatform2
+  //
+  Status = SecPlatformInformation2Ppi->PlatformInformation2 (
+                                         (CONST EFI_PEI_SERVICES  **) PeiServices,
+                                         &InformationSize,
+                                         SecPlatformInformation2
+                                         );
+  DEBUG((DEBUG_INFO, "SecPlatformInformation2Ppi->PlatformInformation2 Status - %x\n", Status));
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return NULL;
+  }
+
+  return SecPlatformInformation2;
+}
+
+/**
+ This routine is used to get Sec Platform Information Record Pointer.
+
+ @param[in] PeiServices    Pointer to the PEI services table
+
+ @retval GetSecPlatformInformation2 - The pointer of Sec Platform Information Record Pointer.
+ **/
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformationInfoInFormat2(
+  IN EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_SEC_PLATFORM_INFORMATION_PPI     *SecPlatformInformationPpi;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD  *SecPlatformInformation = NULL;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+  UINT64                               InformationSize;
+  EFI_STATUS                           Status;
+
+  //
+  // Get BIST information from Sec Platform Information
+  //
+  Status = PeiServicesLocatePpi (
+             &gEfiSecPlatformInformationPpiGuid,    // GUID
+             0,                                     // Instance
+             NULL,                                  // EFI_PEI_PPI_DESCRIPTOR
+             (VOID ** ) &SecPlatformInformationPpi  // PPI
+             );
+
+  DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi Status - %x\n", Status));
+  if (EFI_ERROR(Status)) {
+    return NULL;
+  }
+
+  InformationSize = 0;
+  Status = SecPlatformInformationPpi->PlatformInformation (
+                                        (CONST EFI_PEI_SERVICES  **) PeiServices,
+                                        &InformationSize,
+                                        SecPlatformInformation
+                                        );
+
+  ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+  if (Status != EFI_BUFFER_TOO_SMALL) {
+    return NULL;
+  }
+
+  SecPlatformInformation = AllocatePool((UINTN)InformationSize);
+  ASSERT (SecPlatformInformation != NULL);
+  if (SecPlatformInformation == NULL) {
+    return NULL;
+  }
+
+  //
+  // Retrieve BIST data from SecPlatform
+  //
+  Status = SecPlatformInformationPpi->PlatformInformation (
+                                        (CONST EFI_PEI_SERVICES  **) PeiServices,
+                                        &InformationSize,
+                                        SecPlatformInformation
+                                        );
+  DEBUG((DEBUG_INFO, "FSP  SecPlatformInformation2Ppi->PlatformInformation Status - %x\n", Status));
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return NULL;
+  }
+
+  SecPlatformInformation2 = AllocatePool(sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2));
+  ASSERT (SecPlatformInformation2 != NULL);
+  if (SecPlatformInformation2 == NULL) {
+    return NULL;
+  }
+
+  SecPlatformInformation2->NumberOfCpus = 1;
+  SecPlatformInformation2->CpuInstance[0].CpuLocation = 0;
+  SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32 = SecPlatformInformation->x64HealthFlags.Uint32;
+
+  FreePool(SecPlatformInformation);
+
+  return SecPlatformInformation2;
+}
+
+
+/**
+ Performs FSP CPU PEI Policy post memory initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  EFI_STATUS                           Status;
+  SI_POLICY_PPI                        *SiPolicyPpi;
+  CPU_CONFIG                           *CpuConfig;
+  CPU_POWER_MGMT_BASIC_CONFIG          *CpuPowerMgmtBasicConfig;
+  CPU_POWER_MGMT_CUSTOM_CONFIG         *CpuPowerMgmtCustomConfig;
+  CPU_TEST_CONFIG                      *CpuTestConfig;
+  CPU_POWER_MGMT_TEST_CONFIG           *CpuPowerMgmtTestConfig;
+  UINTN                                Index;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+  EFI_PEI_SERVICES                     **PeiServices;
+
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n"));
+  PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();
+  //
+  // Locate gSiPolicyPpiGuid
+  //
+  SiPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPolicyPpi
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomConfigGuid, (VOID *) &CpuPowerMgmtCustomConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (VOID *) &CpuTestConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfigGuid, (VOID *) &CpuPowerMgmtTestConfig);
+  ASSERT_EFI_ERROR (Status);
+  ///
+  ///Production RC Policies
+  ///
+
+  FspsUpd->FspsConfig.AesEnable                 = (UINT8) CpuConfig->AesEnable;
+  FspsUpd->FspsConfig.DebugInterfaceEnable      = (UINT8) CpuConfig->DebugInterfaceEnable;
+
+  FspsUpd->FspsConfig.TurboMode                 = (UINT8) CpuPowerMgmtBasicConfig->TurboMode;
+
+  ///
+  /// Test RC Policies
+  ///
+  FspsUpd->FspsTestConfig.MlcStreamerPrefetcher      = (UINT8) CpuTestConfig->MlcStreamerPrefetcher;
+  FspsUpd->FspsTestConfig.MlcSpatialPrefetcher       = (UINT8) CpuTestConfig->MlcSpatialPrefetcher;
+  FspsUpd->FspsTestConfig.MonitorMwaitEnable         = (UINT8) CpuTestConfig->MonitorMwaitEnable;
+  FspsUpd->FspsTestConfig.DebugInterfaceLockEnable   = (UINT8) CpuTestConfig->DebugInterfaceLockEnable;
+  FspsUpd->FspsTestConfig.ApIdleManner               = PcdGet8 (PcdCpuApLoopMode);
+  FspsUpd->FspsTestConfig.ProcessorTraceOutputScheme = (UINT8) CpuTestConfig->ProcessorTraceOutputScheme;
+  FspsUpd->FspsTestConfig.ProcessorTraceEnable       = (UINT8) CpuTestConfig->ProcessorTraceEnable;
+  FspsUpd->FspsTestConfig.ProcessorTraceMemBase      = CpuTestConfig->ProcessorTraceMemBase;
+  FspsUpd->FspsTestConfig.ProcessorTraceMemLength    = (UINT32) CpuTestConfig->ProcessorTraceMemLength;
+  FspsUpd->FspsTestConfig.VoltageOptimization        = (UINT8) CpuTestConfig->VoltageOptimization;
+  FspsUpd->FspsTestConfig.ThreeStrikeCounterDisable  = (UINT8) CpuTestConfig->ThreeStrikeCounterDisable;
+  FspsUpd->FspsTestConfig.MachineCheckEnable         = (UINT8) CpuTestConfig->MachineCheckEnable;
+  FspsUpd->FspsTestConfig.CpuWakeUpTimer             = (UINT8) CpuTestConfig->CpuWakeUpTimer;
+
+  FspsUpd->FspsTestConfig.OneCoreRatioLimit          = (UINT8) CpuPowerMgmtBasicConfig->OneCoreRatioLimit;
+  FspsUpd->FspsTestConfig.TwoCoreRatioLimit          = (UINT8) CpuPowerMgmtBasicConfig->TwoCoreRatioLimit;
+  FspsUpd->FspsTestConfig.ThreeCoreRatioLimit        = (UINT8) CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit;
+  FspsUpd->FspsTestConfig.FourCoreRatioLimit         = (UINT8) CpuPowerMgmtBasicConfig->FourCoreRatioLimit;
+  FspsUpd->FspsTestConfig.FiveCoreRatioLimit         = (UINT8) CpuPowerMgmtBasicConfig->FiveCoreRatioLimit;
+  FspsUpd->FspsTestConfig.SixCoreRatioLimit          = (UINT8) CpuPowerMgmtBasicConfig->SixCoreRatioLimit;
+  FspsUpd->FspsTestConfig.SevenCoreRatioLimit        = (UINT8) CpuPowerMgmtBasicConfig->SevenCoreRatioLimit;
+  FspsUpd->FspsTestConfig.EightCoreRatioLimit        = (UINT8) CpuPowerMgmtBasicConfig->EightCoreRatioLimit;
+  FspsUpd->FspsTestConfig.Hwp                        = (UINT8) CpuPowerMgmtBasicConfig->Hwp;
+  FspsUpd->FspsTestConfig.HdcControl                 = (UINT8) CpuPowerMgmtBasicConfig->HdcControl;
+  FspsUpd->FspsTestConfig.PowerLimit1Time            = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit1Time;
+  FspsUpd->FspsTestConfig.PowerLimit2                = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit2;
+  FspsUpd->FspsTestConfig.TurboPowerLimitLock        = (UINT8) CpuPowerMgmtBasicConfig->TurboPowerLimitLock;
+  FspsUpd->FspsTestConfig.PowerLimit3Time            = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Time;
+  FspsUpd->FspsTestConfig.PowerLimit3DutyCycle       = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle;
+  FspsUpd->FspsTestConfig.PowerLimit3Lock            = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Lock;
+  FspsUpd->FspsTestConfig.PowerLimit4Lock            = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit4Lock;
+  FspsUpd->FspsTestConfig.TccActivationOffset        = (UINT8) CpuPowerMgmtBasicConfig->TccActivationOffset;
+  FspsUpd->FspsTestConfig.TccOffsetClamp             = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetClamp;
+  FspsUpd->FspsTestConfig.TccOffsetLock              = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetLock;
+  FspsUpd->FspsTestConfig.PowerLimit1                = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit1 * 125);
+  FspsUpd->FspsTestConfig.PowerLimit2Power           = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit2Power * 125);
+  FspsUpd->FspsTestConfig.PowerLimit3                = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit3 * 125);
+  FspsUpd->FspsTestConfig.PowerLimit4                = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit4 * 125);
+  FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl = (UINT32) CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl;
+  FspsUpd->FspsTestConfig.HwpInterruptControl        = (UINT8) CpuPowerMgmtBasicConfig->HwpInterruptControl;
+  FspsUpd->FspsTestConfig.EnableItbm                 = (UINT8) CpuPowerMgmtBasicConfig->EnableItbm;
+  FspsUpd->FspsTestConfig.EnableItbmDriver           = (UINT8) CpuPowerMgmtBasicConfig->EnableItbmDriver;
+  FspsUpd->FspsTestConfig.MinRingRatioLimit          = (UINT8) CpuPowerMgmtBasicConfig->MinRingRatioLimit;
+  FspsUpd->FspsTestConfig.MaxRingRatioLimit          = (UINT8) CpuPowerMgmtBasicConfig->MaxRingRatioLimit;
+  FspsUpd->FspsTestConfig.NumberOfEntries             = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries;
+  FspsUpd->FspsTestConfig.Custom1PowerLimit1Time      = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time;
+  FspsUpd->FspsTestConfig.Custom2PowerLimit1Time      = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time;
+  FspsUpd->FspsTestConfig.Custom3PowerLimit1Time      = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time;
+  FspsUpd->FspsTestConfig.Custom1TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio;
+  FspsUpd->FspsTestConfig.Custom2TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio;
+  FspsUpd->FspsTestConfig.Custom3TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio;
+  FspsUpd->FspsTestConfig.ConfigTdpLock               = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpLock;
+  FspsUpd->FspsTestConfig.ConfigTdpBios               = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpBios;
+  FspsUpd->FspsTestConfig.MaxRatio                    = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio;
+  for (Index = 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; Index++) {
+    FspsUpd->FspsTestConfig.StateRatio[Index]         = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index];
+  }
+  for (Index = 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) {
+    FspsUpd->FspsTestConfig.StateRatioMax16[Index]    = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatioMax16[Index];
+  }
+  FspsUpd->FspsTestConfig.Custom1PowerLimit1          = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125);
+  FspsUpd->FspsTestConfig.Custom1PowerLimit2          = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125);
+  FspsUpd->FspsTestConfig.Custom2PowerLimit1          = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125);
+  FspsUpd->FspsTestConfig.Custom2PowerLimit2          = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125);
+  FspsUpd->FspsTestConfig.Custom3PowerLimit1          = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125);
+  FspsUpd->FspsTestConfig.Custom3PowerLimit2          = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125);
+
+  FspsUpd->FspsTestConfig.Eist                          = (UINT8) CpuPowerMgmtTestConfig->Eist;
+  FspsUpd->FspsTestConfig.EnergyEfficientPState         = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientPState;
+  FspsUpd->FspsTestConfig.EnergyEfficientTurbo          = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientTurbo;
+  FspsUpd->FspsTestConfig.TStates                       = (UINT8) CpuPowerMgmtTestConfig->TStates;
+  FspsUpd->FspsTestConfig.BiProcHot                     = (UINT8) CpuPowerMgmtTestConfig->BiProcHot;
+  FspsUpd->FspsTestConfig.DisableProcHotOut             = (UINT8) CpuPowerMgmtTestConfig->DisableProcHotOut;
+  FspsUpd->FspsTestConfig.ProcHotResponse               = (UINT8) CpuPowerMgmtTestConfig->ProcHotResponse;
+  FspsUpd->FspsTestConfig.DisableVrThermalAlert         = (UINT8) CpuPowerMgmtTestConfig->DisableVrThermalAlert;
+  FspsUpd->FspsTestConfig.AutoThermalReporting          = (UINT8) CpuPowerMgmtTestConfig->AutoThermalReporting;
+  FspsUpd->FspsTestConfig.ThermalMonitor                = (UINT8) CpuPowerMgmtTestConfig->ThermalMonitor;
+  FspsUpd->FspsTestConfig.Cx                            = (UINT8) CpuPowerMgmtTestConfig->Cx;
+  FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock             = (UINT8) CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock;
+  FspsUpd->FspsTestConfig.C1e                           = (UINT8) CpuPowerMgmtTestConfig->C1e;
+  FspsUpd->FspsTestConfig.C1StateAutoDemotion           = (UINT8) CpuPowerMgmtTestConfig->C1AutoDemotion;
+  FspsUpd->FspsTestConfig.C1StateUnDemotion             = (UINT8) CpuPowerMgmtTestConfig->C1UnDemotion;
+  FspsUpd->FspsTestConfig.C3StateAutoDemotion           = (UINT8) CpuPowerMgmtTestConfig->C3AutoDemotion;
+  FspsUpd->FspsTestConfig.C3StateUnDemotion             = (UINT8) CpuPowerMgmtTestConfig->C3UnDemotion;
+  FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit;
+  FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl     = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl;
+  FspsUpd->FspsTestConfig.PkgCStateDemotion             = (UINT8) CpuPowerMgmtTestConfig->PkgCStateDemotion;
+  FspsUpd->FspsTestConfig.PkgCStateUnDemotion           = (UINT8) CpuPowerMgmtTestConfig->PkgCStateUnDemotion;
+  FspsUpd->FspsTestConfig.CStatePreWake                 = (UINT8) CpuPowerMgmtTestConfig->CStatePreWake;
+  FspsUpd->FspsTestConfig.TimedMwait                    = (UINT8) CpuPowerMgmtTestConfig->TimedMwait;
+  FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection   = (UINT8) CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection;
+  FspsUpd->FspsTestConfig.PkgCStateLimit                = (UINT8) CpuPowerMgmtTestConfig->PkgCStateLimit;
+  FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit;
+  FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit;
+  FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit;
+  FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit;
+  FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit;
+  FspsUpd->FspsTestConfig.PpmIrmSetting                 = (UINT8) CpuPowerMgmtTestConfig->PpmIrmSetting;
+  FspsUpd->FspsTestConfig.ProcHotLock                   = (UINT8) CpuPowerMgmtTestConfig->ProcHotLock;
+  FspsUpd->FspsTestConfig.RaceToHalt                    = (UINT8) CpuPowerMgmtTestConfig->RaceToHalt;
+  FspsUpd->FspsTestConfig.ConfigTdpLevel                = (UINT8) CpuPowerMgmtTestConfig->ConfigTdpLevel;
+  FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl     = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl;
+  FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl     = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl;
+  FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl     = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl;
+  FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl     = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl;
+  FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl     = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl;
+
+  //
+  // Get BIST information from Sec Platform Information
+  //
+  SecPlatformInformation2 = GetSecPlatformInformation2 (PeiServices);
+  if (SecPlatformInformation2 == NULL) {
+    SecPlatformInformation2 = GetSecPlatformInformationInfoInFormat2 (PeiServices);
+  }
+
+  ASSERT (SecPlatformInformation2 != NULL);
+
+  if (SecPlatformInformation2 != NULL) {
+    FspsUpd->FspsConfig.CpuBistData = (UINT32)SecPlatformInformation2;
+    DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", SecPlatformInformation2->NumberOfCpus));
+    DEBUG ((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32));
+  }
+  return EFI_SUCCESS;
+}
+

+ 121 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c

@@ -0,0 +1,121 @@
+/** @file
+  Implementation of Fsp Me Policy Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <ConfigBlock/MePeiConfig.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  Performs FSP ME PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                Status;
+  SI_PREMEM_POLICY_PPI      *SiPreMemPolicy;
+  ME_PEI_PREMEM_CONFIG      *MePeiPreMemConfig;
+
+  DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n"));
+
+  //
+  // Locate gSiPreMemPolicyPpi
+  //
+  SiPreMemPolicy = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPreMemPolicy
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  FspmUpd->FspmConfig.HeciTimeouts                      = (UINT8)  MePeiPreMemConfig->HeciTimeouts;
+  //
+  // Test policies
+  //
+  FspmUpd->FspmTestConfig.DidInitStat                   = (UINT8) MePeiPreMemConfig->DidInitStat;
+  FspmUpd->FspmTestConfig.DisableCpuReplacedPolling     = (UINT8) MePeiPreMemConfig->DisableCpuReplacedPolling;
+  FspmUpd->FspmTestConfig.SendDidMsg                    = (UINT8) MePeiPreMemConfig->SendDidMsg;
+  FspmUpd->FspmTestConfig.DisableMessageCheck           = (UINT8) MePeiPreMemConfig->DisableMessageCheck;
+  FspmUpd->FspmTestConfig.SkipMbpHob                    = (UINT8) MePeiPreMemConfig->SkipMbpHob;
+
+  FspmUpd->FspmTestConfig.HeciCommunication2            = (UINT8) MePeiPreMemConfig->HeciCommunication2;
+  FspmUpd->FspmTestConfig.KtDeviceEnable                = (UINT8) MePeiPreMemConfig->KtDeviceEnable;
+
+  FspmUpd->FspmConfig.Heci1BarAddress                   = MePeiPreMemConfig->Heci1BarAddress;
+  FspmUpd->FspmConfig.Heci2BarAddress                   = MePeiPreMemConfig->Heci2BarAddress;
+  FspmUpd->FspmConfig.Heci3BarAddress                   = MePeiPreMemConfig->Heci3BarAddress;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Performs FSP ME PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  EFI_STATUS                Status;
+  SI_POLICY_PPI             *SiPolicyPpi;
+  ME_PEI_CONFIG             *MePeiConfig;
+
+  DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n"));
+  //
+  // Locate gSiPolicyPpiGuid
+  //
+  SiPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPolicyPpi
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  FspsUpd->FspsConfig.Heci3Enabled                  = (UINT8) MePeiConfig->Heci3Enabled;
+  FspsUpd->FspsConfig.MeUnconfigOnRtcClear          = (UINT8) MePeiConfig->MeUnconfigOnRtcClear;
+
+  //
+  // Test policies
+  //
+  FspsUpd->FspsTestConfig.MctpBroadcastCycle        = (UINT8) MePeiConfig->MctpBroadcastCycle;
+  FspsUpd->FspsTestConfig.EndOfPostMessage          = (UINT8) MePeiConfig->EndOfPostMessage;
+  FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci = (UINT8) MePeiConfig->DisableD0I3SettingForHeci;
+
+  return EFI_SUCCESS;
+}
+

+ 77 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c

@@ -0,0 +1,77 @@
+/** @file
+  Implementation of Fsp Misc UPD Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+
+#define STATUS_CODE_USE_RAM        BIT0
+#define STATUS_CODE_USE_ISA_SERIAL BIT1
+#define STATUS_CODE_USE_USB        BIT2
+#define STATUS_CODE_USE_USB3       BIT3
+#define STATUS_CODE_USE_SERIALIO   BIT4
+#define STATUS_CODE_USE_TRACEHUB   BIT5
+#define STATUS_CODE_CMOS_INVALID   BIT6
+#define STATUS_CODE_CMOS_VALID     BIT7
+/**
+  Performs FSP Misc UPD initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                        Status;
+  EFI_PEI_HOB_POINTERS              Hob;
+  DEBUG_CONFIG_DATA_HOB             *DebugConfigData;
+  UINT8                             DebugInterfaces;
+
+  FspmUpd->FspmArchUpd.StackBase = (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize) + PcdGet32(PcdFspReservedBufferSize)));
+  FspmUpd->FspmArchUpd.StackSize = PcdGet32(PcdFspTemporaryRamSize);
+
+  Status = PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode));
+  if (EFI_ERROR (Status)) {
+    FspmUpd->FspmArchUpd.BootMode = BOOT_WITH_FULL_CONFIGURATION;
+  }
+
+  FspmUpd->FspmArchUpd.BootLoaderTolumSize = 0x0;
+
+  //
+  // Initialize DebugConfigData
+  //
+  DebugInterfaces = 0x00;
+  Hob.Guid = GetFirstGuidHob (&gDebugConfigHobGuid);
+  if (Hob.Guid != NULL) {
+    DebugConfigData = (DEBUG_CONFIG_DATA_HOB *) GET_GUID_HOB_DATA (Hob.Guid);
+    if (DebugConfigData != NULL) {
+      // Debug Interfaces
+      if (DebugConfigData->RamDebugInterface)      { DebugInterfaces |= STATUS_CODE_USE_RAM; }
+      if (DebugConfigData->UartDebugInterface)     { DebugInterfaces |= STATUS_CODE_USE_ISA_SERIAL; }
+      if (DebugConfigData->Usb3DebugInterface)     { DebugInterfaces |= STATUS_CODE_USE_USB3; }
+      if (DebugConfigData->SerialIoDebugInterface) { DebugInterfaces |= STATUS_CODE_USE_SERIALIO; }
+      if (DebugConfigData->TraceHubDebugInterface) { DebugInterfaces |= STATUS_CODE_USE_TRACEHUB; }
+      FspmUpd->FspmConfig.PcdDebugInterfaceFlags  = DebugInterfaces;
+      // Serial debug message baud rate
+      FspmUpd->FspmConfig.PcdSerialDebugBaudRate  = DebugConfigData->SerialDebugBaudRate;
+      //Serial debug message level
+      FspmUpd->FspmConfig.PcdSerialDebugLevel     = DebugConfigData->SerialDebug;
+    }
+  }
+  DEBUG ((DEBUG_INFO, "FspmConfig.PcdDebugInterfaceFlags is 0x%X\n", FspmUpd->FspmConfig.PcdDebugInterfaceFlags));
+  DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugBaudRate is 0x%X\n", FspmUpd->FspmConfig.PcdSerialDebugBaudRate));
+  DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugLevel is 0x%X\n", FspmUpd->FspmConfig.PcdSerialDebugLevel));
+
+  return EFI_SUCCESS;
+}
+

+ 743 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c

@@ -0,0 +1,743 @@
+/** @file
+  Implementation of Fsp PCH Policy Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  Performs FSP PCH PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                       Status;
+  UINTN                            Index;
+  UINTN                            MaxPcieRootPorts;
+  SI_PREMEM_POLICY_PPI             *SiPreMemPolicy;
+  PCH_TRACE_HUB_PREMEM_CONFIG      *PchTraceHubPreMemConfig;
+  PCH_SMBUS_PREMEM_CONFIG          *SmbusPreMemConfig;
+  PCH_DCI_PREMEM_CONFIG            *DciPreMemConfig;
+  PCH_HSIO_PCIE_PREMEM_CONFIG      *HsioPciePreMemConfig;
+  PCH_HSIO_SATA_PREMEM_CONFIG      *HsioSataPreMemConfig;
+  PCH_PCIE_RP_PREMEM_CONFIG        *PcieRpPreMemConfig;
+  PCH_LPC_PREMEM_CONFIG            *LpcPreMemConfig;
+  PCH_GENERAL_PREMEM_CONFIG        *PchGeneralPreMemConfig;
+  PCH_WDT_PREMEM_CONFIG            *WdtPreMemConfig;
+  PCH_HDAUDIO_PREMEM_CONFIG        *HdaPreMemConfig;
+  PCH_ISH_PREMEM_CONFIG            *IshPreMemConfig;
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n"));
+  DEBUG((DEBUG_INFO | DEBUG_INIT, "FspmUpd = 0x%x\n", FspmUpd));
+  //
+  // Locate PchPreMemPolicyPpi
+  //
+  SiPreMemPolicy = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPreMemPolicy
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemConfigGuid, (VOID *) &PchTraceHubPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGuid, (VOID *) &IshPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ UpdatePeiPchPolicyPreMem\n"));
+  //
+  // Update PCIE RP policies
+  //
+//  MaxPcieRootPorts = 16;
+
+  MaxPcieRootPorts = GetPchMaxPciePortNum ();
+//  MaxPcieRootPorts = 16;
+  FspmUpd->FspmConfig.PcieRpEnableMask = PcieRpPreMemConfig->RpEnabledMask & ((1 << MaxPcieRootPorts) - 1);
+  FspmUpd->FspmConfig.PcieImrEnabled = PcieRpPreMemConfig->PcieImrEnabled;
+  FspmUpd->FspmConfig.PcieImrSize = PcieRpPreMemConfig->PcieImrSize;
+  FspmUpd->FspmConfig.ImrRpSelection = PcieRpPreMemConfig->ImrRpSelection;
+  //
+  // Update TraceHub policies
+  //
+  FspmUpd->FspmConfig.PchTraceHubMode = (UINT8) PchTraceHubPreMemConfig->EnableMode;
+  FspmUpd->FspmConfig.PchTraceHubMemReg0Size = (UINT8) PchTraceHubPreMemConfig->MemReg0Size;
+  FspmUpd->FspmConfig.PchTraceHubMemReg1Size = (UINT8) PchTraceHubPreMemConfig->MemReg1Size;
+
+  //
+  // Update Smbus policies
+  //
+  FspmUpd->FspmConfig.SmbusEnable = (UINT8)SmbusPreMemConfig->Enable;
+  FspmUpd->FspmConfig.SmbusArpEnable = (UINT8)SmbusPreMemConfig->ArpEnable;
+  FspmUpd->FspmTestConfig.SmbusDynamicPowerGating = (UINT8)SmbusPreMemConfig->DynamicPowerGating;
+  FspmUpd->FspmTestConfig.SmbusSpdWriteDisable = (UINT8)SmbusPreMemConfig->SpdWriteDisable;
+  FspmUpd->FspmConfig.PchSmbAlertEnable = (UINT8)SmbusPreMemConfig->SmbAlertEnable;
+  FspmUpd->FspmConfig.PchSmbusIoBase = (UINT16)SmbusPreMemConfig->SmbusIoBase;
+  FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses = (UINT8)SmbusPreMemConfig->NumRsvdSmbusAddresses;
+  FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr = (UINT32)SmbusPreMemConfig->RsvdSmbusAddressTable;
+
+  DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ1 UpdatePeiPchPolicyPreMem\n"));
+  //
+  // Update Dci policies
+  //
+  FspmUpd->FspmConfig.PlatformDebugConsent = (UINT8)DciPreMemConfig->PlatformDebugConsent;
+  DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ11 UpdatePeiPchPolicyPreMem\n"));
+  FspmUpd->FspmConfig.DciUsb3TypecUfpDbg = (UINT8)DciPreMemConfig->DciUsb3TypecUfpDbg;
+  //
+  // Update HSIO PCIE policies
+  //
+  for (Index = 0; Index < MaxPcieRootPorts; Index ++) {
+    FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index]           = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable;
+    FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index]                 = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index]  = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index]        = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index]  = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index]        = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index]  = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index]        = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index]        = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index]              = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index]     = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index]           = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index]     = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable;
+    FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index]           = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0;
+  }
+
+  //
+  // Update HSIO SATA policies
+  //
+  for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index ++) {
+    FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index]    = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable;
+    FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index]          = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag;
+    FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index]    = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable;
+    FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index]          = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag;
+    FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index]    = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable;
+    FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index]          = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag;
+    FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index]  = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable;
+    FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index]        = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp;
+    FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index]  = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable;
+    FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index]        = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp;
+    FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index]  = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable;
+    FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index]        = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp;
+    FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index]        = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable;
+    FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index]              = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph;
+    FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index]        = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable;
+    FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index]              = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph;
+    FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index]        = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable;
+    FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index]              = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph;
+  }
+  DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ2 UpdatePeiPchPolicyPreMem\n"));
+  // Update LPC policies
+  //
+  FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding = (UINT8)LpcPreMemConfig->EnhancePort8xhDecoding;
+
+  //
+  // Update Pch General Premem policies
+  //
+  FspmUpd->FspmConfig.PchPort80Route = (UINT8)PchGeneralPreMemConfig->Port80Route;
+
+  //
+  // Update Wdt policies
+  //
+  FspmUpd->FspmTestConfig.WdtDisableAndLock = (UINT8)WdtPreMemConfig->DisableAndLock;
+
+  //
+  // HdAudioConfig
+  //
+  FspmUpd->FspmConfig.PchHdaEnable = (UINT8)HdaPreMemConfig->Enable;
+
+  //
+  // IshConfig
+  //
+  FspmUpd->FspmConfig.PchIshEnable = (UINT8)IshPreMemConfig->Enable;
+
+  DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ3 UpdatePeiPchPolicyPreMem\n"));
+  return EFI_SUCCESS;
+}
+
+/**
+  Performs FSP PCH PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  EFI_STATUS                   Status;
+  UINTN                        Index;
+  UINTN                        MaxPcieRootPorts;
+  UINT8                        Data8;
+  SI_POLICY_PPI                *SiPolicy;
+  PCH_LAN_CONFIG               *LanConfig;
+  PCH_HDAUDIO_CONFIG           *HdAudioConfig;
+  PCH_SCS_CONFIG               *ScsConfig;
+  PCH_ISH_CONFIG               *IshConfig;
+  PCH_SATA_CONFIG              *SataConfig;
+  USB_CONFIG                   *UsbConfig;
+  PCH_SERIAL_IO_CONFIG         *SerialIoConfig;
+  PCH_INTERRUPT_CONFIG         *InterruptConfig;
+  PCH_LOCK_DOWN_CONFIG         *LockDownConfig;
+  PCH_CNVI_CONFIG              *CnviConfig;
+  PCH_HSIO_CONFIG              *HsioConfig;
+  PCH_ESPI_CONFIG              *EspiConfig;
+  PCH_PCIE_CONFIG              *PcieRpConfig;
+  PCH_DMI_CONFIG               *DmiConfig;
+  PCH_FLASH_PROTECTION_CONFIG  *FlashProtectionConfig;
+  PCH_IOAPIC_CONFIG            *IoApicConfig;
+  PCH_P2SB_CONFIG              *P2sbConfig;
+  PCH_GENERAL_CONFIG           *PchGeneralConfig;
+  PCH_PM_CONFIG                *PmConfig;
+  PCH_LPC_SIRQ_CONFIG          *PchSerialIrqConfig;
+  PCH_THERMAL_CONFIG           *PchThermalConfig;
+
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));
+  //
+  // Locate SiPolicyPpi
+  //
+  SiPolicy = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPolicy
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *) &P2sbConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &PchSerialIrqConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &PchThermalConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gHsioConfigGuid, (VOID *) &HsioConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *) &EspiConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Update LAN policies
+  //
+  FspsUpd->FspsConfig.PchLanEnable          = (UINT8)LanConfig->Enable;
+  FspsUpd->FspsConfig.PchLanLtrEnable       = (UINT8)LanConfig->LtrEnable;
+
+  //
+  // Update HDA policies
+  //
+  FspsUpd->FspsConfig.PchHdaDspEnable             = (UINT8)HdAudioConfig->DspEnable;
+  FspsUpd->FspsConfig.PchHdaPme                   = (UINT8)HdAudioConfig->Pme;
+  FspsUpd->FspsConfig.PchHdaVcType                = (UINT8)HdAudioConfig->VcType;
+  FspsUpd->FspsConfig.PchHdaLinkFrequency         = (UINT8)HdAudioConfig->HdAudioLinkFrequency;
+  FspsUpd->FspsConfig.PchHdaIDispLinkFrequency    = (UINT8)HdAudioConfig->IDispLinkFrequency;
+  FspsUpd->FspsConfig.PchHdaIDispLinkTmode        = (UINT8)HdAudioConfig->IDispLinkTmode;
+  FspsUpd->FspsConfig.PchHdaDspUaaCompliance      = (UINT8)HdAudioConfig->DspUaaCompliance;
+  FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect  = (UINT8)HdAudioConfig->IDispCodecDisconnect;
+  FspsUpd->FspsConfig.PchHdaCodecSxWakeCapability = (UINT8)HdAudioConfig->CodecSxWakeCapability;
+  FspsUpd->FspsTestConfig.PchHdaResetWaitTimer    = (UINT16)HdAudioConfig->ResetWaitTimer;
+  FspsUpd->FspsConfig.PchHdaVerbTableEntryNum     = HdAudioConfig->VerbTableEntryNum;
+  FspsUpd->FspsConfig.PchHdaVerbTablePtr          = HdAudioConfig->VerbTablePtr;
+  FspsUpd->FspsConfig.PchHdaAudioLinkHda          = (UINT8)HdAudioConfig->AudioLinkHda;
+  FspsUpd->FspsConfig.PchHdaAudioLinkDmic0        = (UINT8)HdAudioConfig->AudioLinkDmic0;
+  FspsUpd->FspsConfig.PchHdaAudioLinkDmic1        = (UINT8)HdAudioConfig->AudioLinkDmic1;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSsp0         = (UINT8)HdAudioConfig->AudioLinkSsp0;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSsp1         = (UINT8)HdAudioConfig->AudioLinkSsp1;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSsp2         = (UINT8)HdAudioConfig->AudioLinkSsp2;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSndw1        = (UINT8)HdAudioConfig->AudioLinkSndw1;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSndw2        = (UINT8)HdAudioConfig->AudioLinkSndw2;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSndw3        = (UINT8)HdAudioConfig->AudioLinkSndw3;
+  FspsUpd->FspsConfig.PchHdaAudioLinkSndw4        = (UINT8)HdAudioConfig->AudioLinkSndw4;
+  FspsUpd->FspsConfig.PchHdaSndwBufferRcomp       = (UINT8)HdAudioConfig->SndwBufferRcomp;
+
+  //
+  // Update SCS policies
+  //
+  FspsUpd->FspsConfig.ScsEmmcEnabled = (UINT8)ScsConfig->ScsEmmcEnabled;
+  FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)ScsConfig->ScsEmmcHs400Enabled;
+  FspsUpd->FspsConfig.ScsSdCardEnabled = (UINT8)ScsConfig->ScsSdcardEnabled;
+  FspsUpd->FspsConfig.SdCardPowerEnableActiveHigh = (UINT8)ScsConfig->SdCardPowerEnableActiveHigh;
+#ifdef CFL_SIMICS
+  FspsUpd->FspsConfig.ScsUfsEnabled    = 0;
+#else
+  FspsUpd->FspsConfig.ScsUfsEnabled    = (UINT8)ScsConfig->ScsUfsEnabled;
+#endif
+  FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired = (UINT8)ScsConfig->ScsEmmcHs400TuningRequired;
+  FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid   = (UINT8)ScsConfig->ScsEmmcHs400DllDataValid;
+  FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1   = (UINT8)ScsConfig->ScsEmmcHs400RxStrobeDll1;
+  FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll      = (UINT8)ScsConfig->ScsEmmcHs400TxDataDll;
+  FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength = (UINT8)ScsConfig->ScsEmmcHs400DriverStrength;
+
+  //
+  // Update ISH policies
+  //
+  FspsUpd->FspsConfig.PchIshSpiGpioAssign   = (UINT8)IshConfig->SpiGpioAssign;
+  FspsUpd->FspsConfig.PchIshUart0GpioAssign = (UINT8)IshConfig->Uart0GpioAssign;
+  FspsUpd->FspsConfig.PchIshUart1GpioAssign = (UINT8)IshConfig->Uart1GpioAssign;
+  FspsUpd->FspsConfig.PchIshI2c0GpioAssign  = (UINT8)IshConfig->I2c0GpioAssign;
+  FspsUpd->FspsConfig.PchIshI2c1GpioAssign  = (UINT8)IshConfig->I2c1GpioAssign;
+  FspsUpd->FspsConfig.PchIshI2c2GpioAssign  = (UINT8)IshConfig->I2c2GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp0GpioAssign   = (UINT8)IshConfig->Gp0GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp1GpioAssign   = (UINT8)IshConfig->Gp1GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp2GpioAssign   = (UINT8)IshConfig->Gp2GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp3GpioAssign   = (UINT8)IshConfig->Gp3GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp4GpioAssign   = (UINT8)IshConfig->Gp4GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp5GpioAssign   = (UINT8)IshConfig->Gp5GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp6GpioAssign   = (UINT8)IshConfig->Gp6GpioAssign;
+  FspsUpd->FspsConfig.PchIshGp7GpioAssign   = (UINT8)IshConfig->Gp7GpioAssign;
+  FspsUpd->FspsConfig.PchIshPdtUnlock       = (UINT8)IshConfig->PdtUnlock;
+
+  //
+  // Update PCIE RP RootPort policies
+  //
+  MaxPcieRootPorts = GetPchMaxPciePortNum ();
+  FspsUpd->FspsConfig.PcieRpDpcMask = 0;
+  FspsUpd->FspsConfig.PcieRpDpcExtensionsMask = 0;
+  FspsUpd->FspsConfig.PcieRpPtmMask = 0;
+  for (Index = 0; Index < MaxPcieRootPorts; Index ++) {
+    FspsUpd->FspsConfig.PcieRpHotPlug[Index] = (UINT8)PcieRpConfig->RootPort[Index].HotPlug;
+    FspsUpd->FspsConfig.PcieRpSlotImplemented[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotImplemented;
+    FspsUpd->FspsConfig.PcieRpPmSci[Index] = (UINT8)PcieRpConfig->RootPort[Index].PmSci;
+    FspsUpd->FspsConfig.PcieRpExtSync[Index] = (UINT8)PcieRpConfig->RootPort[Index].ExtSync;
+    FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] = (UINT8)PcieRpConfig->RootPort[Index].TransmitterHalfSwing;
+    FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqDetect;
+    FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] = (UINT8)PcieRpConfig->RootPort[Index].AdvancedErrorReporting;
+    FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].UnsupportedRequestReport;
+    FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].FatalErrorReport;
+    FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].NoFatalErrorReport;
+    FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].CorrectableErrorReport;
+    FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnFatalError;
+    FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError;
+    FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError;
+    FspsUpd->FspsConfig.PcieRpMaxPayload[Index] = (UINT8)PcieRpConfig->RootPort[Index].MaxPayload;
+    if (PcieRpConfig->RootPort[Index].DpcEnabled) {
+      FspsUpd->FspsConfig.PcieRpDpcMask |= (BIT0<<Index);
+    }
+    if (PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled) {
+      FspsUpd->FspsConfig.PcieRpDpcExtensionsMask |= (BIT0<<Index);
+    }
+    if (PcieRpConfig->RootPort[Index].PtmEnabled) {
+      FspsUpd->FspsConfig.PcieRpPtmMask |= (BIT0<<Index);
+    }
+    FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieSpeed;
+    FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] = (UINT8)PcieRpConfig->RootPort[Index].Gen3EqPh3Method;
+    FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].PhysicalSlotNumber;
+    FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] = (UINT8)PcieRpConfig->RootPort[Index].CompletionTimeout;
+    FspsUpd->FspsConfig.PcieRpAspm[Index] = (UINT8)PcieRpConfig->RootPort[Index].Aspm;
+    FspsUpd->FspsConfig.PcieRpL1Substates[Index] = (UINT8)PcieRpConfig->RootPort[Index].L1Substates;
+    FspsUpd->FspsConfig.PcieRpLtrEnable[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrEnable;
+    FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrConfigLock;
+    FspsUpd->FspsConfig.PcieRpAcsEnabled[Index] = (UINT8)PcieRpConfig->RootPort[Index].AcsEnabled;
+    FspsUpd->FspsConfig.PcieRpDetectTimeoutMs[Index] = (UINT16)PcieRpConfig->RootPort[Index].DetectTimeoutMs;
+    FspsUpd->FspsConfig.PcieRootPortGen2PllL1CgDisable[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieRootPortGen2PllL1CgDisable;
+
+    FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency;
+    FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency;
+
+    FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode;
+    FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier;
+    FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue;
+
+    FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode;
+    FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier;
+    FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue;
+
+    FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotPowerLimitScale;
+    FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SlotPowerLimitValue;
+    FspsUpd->FspsTestConfig.PcieRpUptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Uptp;
+    FspsUpd->FspsTestConfig.PcieRpDptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Dptp;
+
+  }
+  for (Index = 0; Index < GetPchMaxPcieClockNum (); Index ++) {
+    FspsUpd->FspsConfig.PcieClkSrcUsage[Index] = PcieRpConfig->PcieClock[Index].Usage;
+    FspsUpd->FspsConfig.PcieClkSrcClkReq[Index] = PcieRpConfig->PcieClock[Index].ClkReq;
+  }
+
+  //
+  // Update PCIE RP EqPh3LaneParam policies
+  //
+  for (Index = 0; Index < MaxPcieRootPorts; Index ++) {
+    FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cm;
+    FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cp;
+  }
+
+  //
+  // Update PCIE RP SwEqCoeffList policies
+  //
+  for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) {
+    FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cm;
+    FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cp;
+  }
+
+  //
+  // Update PCIE RP policies
+  //
+  FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode        = (UINT8)PcieRpConfig->EnablePort8xhDecode;
+  FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex  = (UINT8)PcieRpConfig->PchPciePort8xhDecodePortIndex;
+  FspsUpd->FspsConfig.PcieDisableRootPortClockGating = (UINT8)PcieRpConfig->DisableRootPortClockGating;
+  FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite      = (UINT8)PcieRpConfig->EnablePeerMemoryWrite;
+  FspsUpd->FspsConfig.PcieComplianceTestMode         = (UINT8)PcieRpConfig->ComplianceTestMode;
+  FspsUpd->FspsConfig.PcieRpFunctionSwap             = (UINT8)PcieRpConfig->RpFunctionSwap;
+  FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr  = PcieRpConfig->PcieDeviceOverrideTablePtr;
+
+  //
+  // Update Sata Policies
+  //
+  FspsUpd->FspsConfig.SataEnable                     = (UINT8)SataConfig->Enable;
+  FspsUpd->FspsTestConfig.SataTestMode               = (UINT8)SataConfig->TestMode;
+  FspsUpd->FspsConfig.SataSalpSupport                = (UINT8)SataConfig->SalpSupport;
+  FspsUpd->FspsConfig.SataPwrOptEnable = (UINT8)SataConfig->PwrOptEnable;
+  FspsUpd->FspsConfig.EsataSpeedLimit  = (UINT8)SataConfig->EsataSpeedLimit;
+  FspsUpd->FspsConfig.SataLedEnable    = (UINT8)SataConfig->LedEnable;
+  FspsUpd->FspsConfig.SataMode         = (UINT8)SataConfig->SataMode;
+  FspsUpd->FspsConfig.SataSpeedLimit   = (UINT8)SataConfig->SpeedLimit;
+
+  for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) {
+    FspsUpd->FspsConfig.SataPortsEnable[Index] = (UINT8)SataConfig->PortSettings[Index].Enable;
+    FspsUpd->FspsConfig.SataPortsHotPlug[Index]     = (UINT8)SataConfig->PortSettings[Index].HotPlug;
+    FspsUpd->FspsConfig.SataPortsInterlockSw[Index] = (UINT8)SataConfig->PortSettings[Index].InterlockSw;
+    FspsUpd->FspsConfig.SataPortsExternal[Index]    = (UINT8)SataConfig->PortSettings[Index].External;
+    FspsUpd->FspsConfig.SataPortsSpinUp[Index]      = (UINT8)SataConfig->PortSettings[Index].SpinUp;
+    FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index]  = (UINT8)SataConfig->PortSettings[Index].SolidStateDrive;
+    FspsUpd->FspsConfig.SataPortsDevSlp[Index] = (UINT8)SataConfig->PortSettings[Index].DevSlp;
+    FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] = (UINT8)SataConfig->PortSettings[Index].EnableDitoConfig;
+    FspsUpd->FspsConfig.SataPortsDmVal[Index]       = (UINT8)SataConfig->PortSettings[Index].DmVal;
+    FspsUpd->FspsConfig.SataPortsDitoVal[Index]     = (UINT16)SataConfig->PortSettings[Index].DitoVal;
+    FspsUpd->FspsConfig.SataPortsZpOdd[Index]       = (UINT8)SataConfig->PortSettings[Index].ZpOdd;
+  }
+
+  FspsUpd->FspsConfig.SataRstRaidDeviceId            = (UINT8)SataConfig->Rst.RaidDeviceId;
+  FspsUpd->FspsConfig.SataRstInterrupt               = (UINT8)SataConfig->Rst.SataRstInterrupt;
+  FspsUpd->FspsConfig.SataRstRaid0                   = (UINT8)SataConfig->Rst.Raid0;
+  FspsUpd->FspsConfig.SataRstRaid1                   = (UINT8)SataConfig->Rst.Raid1;
+  FspsUpd->FspsConfig.SataRstRaid10                  = (UINT8)SataConfig->Rst.Raid10;
+  FspsUpd->FspsConfig.SataRstRaid5                   = (UINT8)SataConfig->Rst.Raid5;
+  FspsUpd->FspsConfig.SataRstIrrt                    = (UINT8)SataConfig->Rst.Irrt;
+  FspsUpd->FspsConfig.SataRstOromUiBanner            = (UINT8)SataConfig->Rst.OromUiBanner;
+  FspsUpd->FspsConfig.SataRstOromUiDelay             = (UINT8)SataConfig->Rst.OromUiDelay;
+  FspsUpd->FspsConfig.SataRstHddUnlock               = (UINT8)SataConfig->Rst.HddUnlock;
+  FspsUpd->FspsConfig.SataRstLedLocate               = (UINT8)SataConfig->Rst.LedLocate;
+  FspsUpd->FspsConfig.SataRstIrrtOnly                = (UINT8)SataConfig->Rst.IrrtOnly;
+  FspsUpd->FspsConfig.SataRstSmartStorage            = (UINT8)SataConfig->Rst.SmartStorage;
+  FspsUpd->FspsConfig.SataRstOptaneMemory            = (UINT8)SataConfig->Rst.OptaneMemory;
+  FspsUpd->FspsConfig.SataRstLegacyOrom              = (UINT8)SataConfig->Rst.LegacyOrom;
+  FspsUpd->FspsConfig.SataRstCpuAttachedStorage      = (UINT8)SataConfig->Rst.CpuAttachedStorage;
+
+  for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
+    FspsUpd->FspsConfig.SataRstPcieEnable[Index]           = (UINT8)SataConfig->RstPcieStorageRemap[Index].Enable;
+    FspsUpd->FspsConfig.SataRstPcieStoragePort[Index]      = (UINT8)SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort;
+    FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay;
+  }
+
+  FspsUpd->FspsConfig.SataP0T1M            = (UINT8)SataConfig->ThermalThrottling.P0T1M;
+  FspsUpd->FspsConfig.SataP0T2M            = (UINT8)SataConfig->ThermalThrottling.P0T2M;
+  FspsUpd->FspsConfig.SataP0T3M            = (UINT8)SataConfig->ThermalThrottling.P0T3M;
+  FspsUpd->FspsConfig.SataP0TDisp          = (UINT8)SataConfig->ThermalThrottling.P0TDisp;
+  FspsUpd->FspsConfig.SataP1T1M            = (UINT8)SataConfig->ThermalThrottling.P1T1M;
+  FspsUpd->FspsConfig.SataP1T2M            = (UINT8)SataConfig->ThermalThrottling.P1T2M;
+  FspsUpd->FspsConfig.SataP1T3M            = (UINT8)SataConfig->ThermalThrottling.P1T3M;
+  FspsUpd->FspsConfig.SataP1TDisp          = (UINT8)SataConfig->ThermalThrottling.P1TDisp;
+  FspsUpd->FspsConfig.SataP0Tinact         = (UINT8)SataConfig->ThermalThrottling.P0Tinact;
+  FspsUpd->FspsConfig.SataP0TDispFinit     = (UINT8)SataConfig->ThermalThrottling.P0TDispFinit;
+  FspsUpd->FspsConfig.SataP1Tinact         = (UINT8)SataConfig->ThermalThrottling.P1Tinact;
+  FspsUpd->FspsConfig.SataP1TDispFinit     = (UINT8)SataConfig->ThermalThrottling.P1TDispFinit;
+  FspsUpd->FspsConfig.SataThermalSuggestedSetting = (UINT8)SataConfig->ThermalThrottling.SuggestedSetting;
+
+  //
+  // Update USB policies
+  //
+  FspsUpd->FspsConfig.PchEnableComplianceMode           = (UINT8)UsbConfig->EnableComplianceMode;
+  FspsUpd->FspsConfig.UsbPdoProgramming                 = (UINT8)UsbConfig->PdoProgramming;
+  FspsUpd->FspsConfig.PchUsbOverCurrentEnable           = (UINT8)UsbConfig->OverCurrentEnable;
+  FspsUpd->FspsConfig.PchUsb2PhySusPgEnable             = (UINT8)UsbConfig->Usb2PhySusPgEnable;
+  FspsUpd->FspsTestConfig.PchXhciOcLock                 = (UINT8)UsbConfig->XhciOcLock;
+  for (Index = 0; Index < PCH_MAX_USB2_PORTS; Index++) {
+    FspsUpd->FspsConfig.PortUsb20Enable[Index]  = (UINT8)UsbConfig->PortUsb20[Index].Enable;
+    FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb20[Index].OverCurrentPin;
+    FspsUpd->FspsConfig.Usb2AfePetxiset[Index]  = (UINT8)UsbConfig->PortUsb20[Index].Afe.Petxiset;
+    FspsUpd->FspsConfig.Usb2AfeTxiset[Index]    = (UINT8)UsbConfig->PortUsb20[Index].Afe.Txiset;
+    FspsUpd->FspsConfig.Usb2AfePredeemp[Index]  = (UINT8)UsbConfig->PortUsb20[Index].Afe.Predeemp;
+    FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Pehalfbit;
+  }
+  for (Index = 0; Index < PCH_MAX_USB3_PORTS; Index++) {
+    FspsUpd->FspsConfig.PortUsb30Enable[Index]              = (UINT8)UsbConfig->PortUsb30[Index].Enable;
+    FspsUpd->FspsConfig.Usb3OverCurrentPin[Index]           = (UINT8)UsbConfig->PortUsb30[Index].OverCurrentPin;
+    FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index]       = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable;
+    FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index]             = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmph;
+    FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable;
+    FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index]       = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp;
+
+    Data8 = 0;
+    Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEnable ? B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN : 0;
+    Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable ? B_XHCI_HSIO_FILTER_SELECT_N_EN : 0;
+    Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable ? B_XHCI_HSIO_FILTER_SELECT_P_EN : 0;
+    Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResEnable ? B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN : 0;
+    FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] = Data8;
+
+    Data8 = ((UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg & 0x1F) << N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG) |
+            ((UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes & 0x7) << N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES);
+    FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] = Data8;
+
+    Data8 = ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN & 0x7) << N_XHCI_UPD_HSIO_FILTER_SELECT_N) |
+            ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP & 0x7) << N_XHCI_UPD_HSIO_FILTER_SELECT_P);
+    FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] = Data8;
+  }
+
+  FspsUpd->FspsConfig.XdciEnable     = (UINT8)UsbConfig->XdciConfig.Enable;
+
+  //
+  // Update SerialIo policies
+  //
+  for (Index = 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++) {
+    FspsUpd->FspsConfig.SerialIoSpiMode[Index] = SerialIoConfig->DevMode[Index];
+  }
+
+  //
+  // SPI CS Polarity
+  //
+  FspsUpd->FspsConfig.SerialIoSpi0CsPolarity[0] = 1;
+  FspsUpd->FspsConfig.SerialIoSpi0CsPolarity[1] = 0;
+  FspsUpd->FspsConfig.SerialIoSpi1CsPolarity[0] = 0;
+  FspsUpd->FspsConfig.SerialIoSpi1CsPolarity[1] = 0;
+  FspsUpd->FspsConfig.SerialIoSpi2CsPolarity[0] = 1;
+  FspsUpd->FspsConfig.SerialIoSpi2CsPolarity[1] = 0;
+  for (Index = 0; Index < GetPchMaxSerialIoUartControllersNum (); Index++) {
+    FspsUpd->FspsConfig.SerialIoUartAutoFlow[Index] = SerialIoConfig->UartHwFlowCtrl[Index];
+  }
+  for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+    FspsUpd->FspsConfig.SerialIoI2cMode[Index]               = SerialIoConfig->DevMode[Index];
+    FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index] = SerialIoConfig->I2cPadsTermination[Index];
+  }
+
+  FspsUpd->FspsConfig.SerialIoDebugUartNumber          = (UINT8)SerialIoConfig->DebugUartNumber;
+  FspsUpd->FspsConfig.SerialIoUartPinMux[0]            = (UINT8)SerialIoConfig->Uart0PinMuxing;
+
+  //
+  // Update Interrupt policies
+  //
+  FspsUpd->FspsConfig.DevIntConfigPtr = (UINT32)InterruptConfig->DevIntConfig;
+  FspsUpd->FspsConfig.NumOfDevIntConfig = InterruptConfig->NumOfDevIntConfig;
+  for (Index = 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) {
+    FspsUpd->FspsConfig.PxRcConfig[Index] = (UINT8)InterruptConfig->PxRcConfig[Index];
+  }
+  FspsUpd->FspsConfig.GpioIrqRoute = (UINT8)InterruptConfig->GpioIrqRoute;
+  FspsUpd->FspsConfig.SciIrqSelect = (UINT8)InterruptConfig->SciIrqSelect;
+  FspsUpd->FspsConfig.TcoIrqSelect = (UINT8)InterruptConfig->TcoIrqSelect;
+  FspsUpd->FspsConfig.TcoIrqEnable = (UINT8)InterruptConfig->TcoIrqEnable;
+
+  //
+  // Update LockDown policies
+  //
+  FspsUpd->FspsTestConfig.PchLockDownGlobalSmi     = (UINT8)LockDownConfig->GlobalSmi;
+  FspsUpd->FspsTestConfig.PchLockDownBiosInterface = (UINT8)LockDownConfig->BiosInterface;
+  FspsUpd->FspsConfig.PchLockDownBiosLock          = (UINT8)LockDownConfig->BiosLock;
+  FspsUpd->FspsConfig.PchLockDownRtcMemoryLock     = (UINT8)LockDownConfig->RtcMemoryLock;
+  FspsUpd->FspsTestConfig.PchUnlockGpioPads        = (UINT8)LockDownConfig->UnlockGpioPads;
+
+  //
+  // Update Dmi policies
+  //
+  FspsUpd->FspsConfig.PchPwrOptEnable = (UINT8)DmiConfig->PwrOptEnable;
+  FspsUpd->FspsConfig.PchDmiAspmCtrl = (UINT8)DmiConfig->DmiAspmCtrl;
+
+  //
+  // Update Flash Protection policies
+  //
+  for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) {
+    FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable;
+    FspsUpd->FspsConfig.PchReadProtectionEnable[Index]  = (UINT8)FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable;
+    FspsUpd->FspsConfig.PchProtectedRangeLimit[Index]  = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit;
+    FspsUpd->FspsConfig.PchProtectedRangeBase[Index]   = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase;
+  }
+
+  //
+  // Update IO Apic policies
+  //
+  FspsUpd->FspsConfig.PchIoApicEntry24_119       = (UINT8)IoApicConfig->IoApicEntry24_119;
+  FspsUpd->FspsConfig.Enable8254ClockGating      = (UINT8)IoApicConfig->Enable8254ClockGating;
+  FspsUpd->FspsConfig.Enable8254ClockGatingOnS3  = (UINT8)IoApicConfig->Enable8254ClockGatingOnS3;
+  FspsUpd->FspsConfig.PchIoApicId                = (UINT8)IoApicConfig->IoApicId;
+
+  //
+  // Update P2sb policies
+  //
+  FspsUpd->FspsTestConfig.PchSbAccessUnlock  = (UINT8)P2sbConfig->SbAccessUnlock;
+
+  //
+  // Update Pch General policies
+  //
+  FspsUpd->FspsConfig.PchCrid               = (UINT8)PchGeneralConfig->Crid;
+  FspsUpd->FspsConfig.PchLegacyIoLowLatency = (UINT8)PchGeneralConfig->LegacyIoLowLatency;
+
+  //
+  // Update Pm policies
+  //
+  FspsUpd->FspsConfig.PchPmPmeB0S5Dis         = (UINT8)PmConfig->WakeConfig.PmeB0S5Dis;
+  FspsUpd->FspsConfig.PchPmWolEnableOverride  = (UINT8)PmConfig->WakeConfig.WolEnableOverride;
+  FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.PcieWakeFromDeepSx;
+  FspsUpd->FspsConfig.PchPmWoWlanEnable       = (UINT8)PmConfig->WakeConfig.WoWlanEnable;
+  FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable = (UINT8)PmConfig->WakeConfig.WoWlanDeepSxEnable;
+  FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx  = (UINT8)PmConfig->WakeConfig.LanWakeFromDeepSx;
+
+  FspsUpd->FspsConfig.PchPmDeepSxPol          = (UINT8)PmConfig->PchDeepSxPol;
+  FspsUpd->FspsConfig.PchPmSlpS3MinAssert     = (UINT8)PmConfig->PchSlpS3MinAssert;
+  FspsUpd->FspsConfig.PchPmSlpS4MinAssert     = (UINT8)PmConfig->PchSlpS4MinAssert;
+  FspsUpd->FspsConfig.PchPmSlpSusMinAssert    = (UINT8)PmConfig->PchSlpSusMinAssert;
+  FspsUpd->FspsConfig.PchPmSlpAMinAssert      = (UINT8)PmConfig->PchSlpAMinAssert;
+  FspsUpd->FspsConfig.PchPmLpcClockRun        = (UINT8)PmConfig->LpcClockRun;
+  FspsUpd->FspsConfig.PchPmSlpStrchSusUp      = (UINT8)PmConfig->SlpStrchSusUp;
+  FspsUpd->FspsConfig.PchPmSlpLanLowDc        = (UINT8)PmConfig->SlpLanLowDc;
+  FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod = (UINT8)PmConfig->PwrBtnOverridePeriod;
+  FspsUpd->FspsTestConfig.PchPmDisableEnergyReport  = (UINT8)PmConfig->DisableEnergyReport;
+  FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown = (UINT8)PmConfig->DisableDsxAcPresentPulldown;
+  FspsUpd->FspsConfig.PchPmDisableNativePowerButton    = (UINT8)PmConfig->DisableNativePowerButton;
+  FspsUpd->FspsConfig.PmcPowerButtonDebounce  = PmConfig->PowerButtonDebounce;
+  FspsUpd->FspsConfig.PchPmSlpS0Enable        = (UINT8)PmConfig->SlpS0Enable;
+  FspsUpd->FspsConfig.PchPmMeWakeSts          = (UINT8)PmConfig->MeWakeSts;
+  FspsUpd->FspsConfig.PchPmWolOvrWkSts        = (UINT8)PmConfig->WolOvrWkSts;
+  FspsUpd->FspsConfig.EnableTcoTimer          = (UINT8)PmConfig->EnableTcoTimer;
+  FspsUpd->FspsConfig.PchPmVrAlert            = (UINT8)PmConfig->VrAlert;
+  FspsUpd->FspsConfig.PchPmPwrCycDur          = (UINT8)PmConfig->PchPwrCycDur;
+  FspsUpd->FspsConfig.PchPmPciePllSsc         = (UINT8)PmConfig->PciePllSsc;
+  FspsUpd->FspsConfig.PchPmSlpS0VmRuntimeControl = (UINT8)PmConfig->SlpS0VmRuntimeControl;
+  FspsUpd->FspsConfig.PchPmSlpS0Vm070VSupport   = (UINT8)PmConfig->SlpS0Vm070VSupport;
+  FspsUpd->FspsConfig.PchPmSlpS0Vm075VSupport   = (UINT8)PmConfig->SlpS0Vm075VSupport;
+  FspsUpd->FspsConfig.SlpS0Override             = (UINT8)PmConfig->SlpS0Override;
+  FspsUpd->FspsConfig.SlpS0DisQForDebug         = (UINT8)PmConfig->SlpS0DisQForDebug;
+  FspsUpd->FspsConfig.PmcDbgMsgEn               = (UINT8)PmConfig->PmcDbgMsgEn;
+  FspsUpd->FspsConfig.PsOnEnable                = (UINT8)PmConfig->PsOnEnable;
+  FspsUpd->FspsConfig.PmcCpuC10GatePinEnable    = (UINT8)PmConfig->CpuC10GatePinEnable;
+  FspsUpd->FspsConfig.PmcModPhySusPgEnable      = (UINT8)PmConfig->ModPhySusPgEnable;
+  FspsUpd->FspsConfig.SlpS0WithGbeSupport       = (UINT8)PmConfig->SlpS0WithGbeSupport;
+  //
+  // Update Pch Serial IRQ policies
+  //
+  FspsUpd->FspsConfig.PchSirqEnable       = (UINT8)PchSerialIrqConfig->SirqEnable;
+  FspsUpd->FspsConfig.PchSirqMode         = (UINT8)PchSerialIrqConfig->SirqMode;
+  FspsUpd->FspsConfig.PchStartFramePulse  = (UINT8)PchSerialIrqConfig->StartFramePulse;
+  //
+  // Update Pch Thermal policies
+  //
+  FspsUpd->FspsConfig.PchTsmicLock        = (UINT8)PchThermalConfig->TsmicLock;
+  FspsUpd->FspsConfig.PchHotEnable        = (UINT8)PchThermalConfig->PchHotEnable;
+
+  FspsUpd->FspsConfig.PchT0Level          = (UINT16)PchThermalConfig->TTLevels.T0Level;
+  FspsUpd->FspsConfig.PchT1Level          = (UINT16)PchThermalConfig->TTLevels.T1Level;
+  FspsUpd->FspsConfig.PchT2Level          = (UINT16)PchThermalConfig->TTLevels.T2Level;
+  FspsUpd->FspsConfig.PchTTEnable         = (UINT8)PchThermalConfig->TTLevels.TTEnable;
+  FspsUpd->FspsConfig.PchTTState13Enable  = (UINT8)PchThermalConfig->TTLevels.TTState13Enable;
+  FspsUpd->FspsConfig.PchTTLock           = (UINT8)PchThermalConfig->TTLevels.TTLock;
+  FspsUpd->FspsConfig.TTSuggestedSetting  = (UINT8)PchThermalConfig->TTLevels.SuggestedSetting;
+  FspsUpd->FspsConfig.TTCrossThrottling   = (UINT8)PchThermalConfig->TTLevels.PchCrossThrottling;
+
+  FspsUpd->FspsConfig.PchDmiTsawEn        = (UINT8)PchThermalConfig->DmiHaAWC.DmiTsawEn;
+  FspsUpd->FspsConfig.DmiSuggestedSetting = (UINT8)PchThermalConfig->DmiHaAWC.SuggestedSetting;
+  FspsUpd->FspsConfig.DmiTS0TW            = (UINT8)PchThermalConfig->DmiHaAWC.TS0TW;
+  FspsUpd->FspsConfig.DmiTS1TW            = (UINT8)PchThermalConfig->DmiHaAWC.TS1TW;
+  FspsUpd->FspsConfig.DmiTS2TW            = (UINT8)PchThermalConfig->DmiHaAWC.TS2TW;
+  FspsUpd->FspsConfig.DmiTS3TW            = (UINT8)PchThermalConfig->DmiHaAWC.TS3TW;
+
+  FspsUpd->FspsConfig.PchMemoryThrottlingEnable    = (UINT8)PchThermalConfig->MemoryThrottling.Enable;
+  FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0]     = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable;
+  FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1]     = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable;
+  FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable;
+  FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable;
+  FspsUpd->FspsConfig.PchMemoryPinSelection[0]     = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection;
+  FspsUpd->FspsConfig.PchMemoryPinSelection[1]     = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection;
+
+  FspsUpd->FspsConfig.PchTemperatureHotLevel = (UINT16)PchThermalConfig->PchHotLevel;
+
+  //
+  // Update Pch CNVi policies
+  //
+  FspsUpd->FspsConfig.CnviMode = (UINT8)CnviConfig->Mode;
+
+  //
+  // Update Pch HSIO policies
+  //
+  FspsUpd->FspsConfig.ChipsetInitBinPtr = HsioConfig->ChipsetInitBinPtr;
+  FspsUpd->FspsConfig.ChipsetInitBinLen = HsioConfig->ChipsetInitBinLen;
+
+  //
+  // Update Pch Espi policies
+  //
+  FspsUpd->FspsConfig.PchEspiLgmrEnable = (UINT8)EspiConfig->LgmrEnable;
+
+  return EFI_SUCCESS;
+}
+

+ 223 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c

@@ -0,0 +1,223 @@
+/** @file
+  Instance of Fsp Policy Initialization Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Library/SpiLib.h>
+
+VOID
+EFIAPI
+FspPolicyInitPreMem(
+  IN FSPM_UPD           *FspmUpdDataPtr
+);
+
+VOID *
+EFIAPI
+SiliconPolicyInitPreMem(
+  IN OUT VOID    *FspmUpd
+)
+{
+  FspPolicyInitPreMem((FSPM_UPD *)FspmUpd);
+  return FspmUpd;
+}
+
+RETURN_STATUS
+EFIAPI
+SiliconPolicyDonePreMem(
+  IN VOID *FspmUpd
+)
+{
+  EFI_STATUS         Status;
+
+  Status = SpiServiceInit();
+  ASSERT_EFI_ERROR(Status);
+
+  return RETURN_SUCCESS;
+}
+
+/**
+  Performs FSP PEI Policy Pre-memory initialization.
+
+  @param[in] FspmUpdDataPtr       Pointer to FSPM UPD data.
+**/
+VOID
+EFIAPI
+FspPolicyInitPreMem (
+  IN FSPM_UPD           *FspmUpdDataPtr
+  )
+{
+  EFI_STATUS            Status;
+
+  //
+  // SI Pei Fsp Policy Initialization
+  //
+  Status = PeiFspSiPolicyInitPreMem (FspmUpdDataPtr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // PCH Pei Fsp Policy Initialization
+  //
+  Status = PeiFspPchPolicyInitPreMem (FspmUpdDataPtr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // Cpu Pei Fsp Policy Initialization
+  //
+  Status = PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // Security Pei Fsp Policy Initialization
+  //
+  Status = PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // ME Pei Fsp Policy Initialization
+  //
+  Status = PeiFspMePolicyInitPreMem (FspmUpdDataPtr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // SystemAgent Pei Fsp Policy Initialization
+  //
+  Status = PeiFspSaPolicyInitPreMem (FspmUpdDataPtr);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // Other Upd Initialization
+  //
+  Status = PeiFspMiscUpdInitPreMem (FspmUpdDataPtr);
+
+}
+
+/**
+  Performs FSP PEI Policy initialization.
+
+  @param[in][out] FspsUpd  Pointer UPD data region
+
+**/
+VOID
+EFIAPI
+FspPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  EFI_STATUS            Status;
+
+  //
+  // SI Pei Fsp Policy Initialization
+  //
+  Status = PeiFspSiPolicyInit (FspsUpd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy iInitialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // PCH Pei Fsp Policy Initialization
+  //
+  Status = PeiFspPchPolicyInit (FspsUpd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // ME Pei Fsp Policy Initialization
+  //
+  Status = PeiFspMePolicyInit (FspsUpd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // SystemAgent Pei Fsp Policy Initialization
+  //
+  Status = PeiFspSaPolicyInit (FspsUpd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // Cpu Pei Fsp Policy Initialization
+  //
+  Status = PeiFspCpuPolicyInit (FspsUpd);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+  }
+
+  //
+  // Security Pei Fsp Policy Initialization
+  //
+  Status = PeiFspSecurityPolicyInit(FspsUpd);
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+  }
+
+}
+
+/**
+Performs silicon post-mem policy initialization.
+
+The meaning of Policy is defined by silicon code.
+It could be the raw data, a handle, a PPI, etc.
+
+The returned data must be used as input data for SiliconPolicyDonePostMem(),
+and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem().
+
+1) In FSP path, the input Policy should be FspsUpd.
+Value of FspsUpd has been initialized by FSP binary default value.
+Only a subset of FspsUpd needs to be updated for different silicon sku.
+The return data is same FspsUpd.
+
+2) In non-FSP path, the input policy could be NULL.
+The return data is the initialized policy.
+
+@param[in, out] Policy       Pointer to policy.
+
+@return the initialized policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyInitPostMem(
+  IN OUT VOID    *FspsUpd
+)
+{
+  FspPolicyInit((FSPS_UPD *)FspsUpd);
+  return FspsUpd;
+}
+
+/*
+The silicon post-mem policy is finalized.
+Silicon code can do initialization based upon the policy data.
+
+The input Policy must be returned by SiliconPolicyInitPostMem().
+
+@param[in] Policy       Pointer to policy.
+
+@retval EFI_SUCCESS The policy is handled consumed by silicon code.
+*/
+EFI_STATUS
+EFIAPI
+SiliconPolicyDonePostMem(
+  IN OUT VOID    *FspsUpd
+)
+{
+  return EFI_SUCCESS;
+}
+

+ 233 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h

@@ -0,0 +1,233 @@
+/** @file
+  Internal header file for Fsp Policy Initialization Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_FSP_POLICY_INIT_LIB_H_
+#define _PEI_FSP_POLICY_INIT_LIB_H_
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Setup.h>
+
+/**
+  Performs FSP SI PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP SI PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+/**
+  Performs FSP PCH PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP PCH PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInit (
+  IN OUT FSPS_UPD     *FspsUpd
+  );
+
+/**
+  Performs FSP CPU PEI Policy initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+Performs FSP Security PEI Policy initialization.
+
+@param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+@retval          EFI_SUCCESS         FSP UPD Data is updated.
+@retval          EFI_NOT_FOUND       Fail to locate required PPI.
+@retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInitPreMem(
+IN OUT FSPM_UPD    *FspmUpd
+);
+
+/**
+  Performs FSP ME PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP ME PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInit (
+  IN OUT FSPS_UPD     *FspsUpd
+  );
+
+/**
+  Performs FSP SA PEI Policy initialization in pre-memory.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+/**
+  Performs FSP SA PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+/**
+  Performs FSP CPU PEI Policy post memory initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+/**
+Performs FSP Security PEI Policy post memory initialization.
+
+@param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+@retval          EFI_SUCCESS         FSP UPD Data is updated.
+@retval          EFI_NOT_FOUND       Fail to locate required PPI.
+@retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInit(
+IN OUT FSPS_UPD    *FspsUpd
+);
+
+/**
+  PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+  @param[in] NameGuid              - File GUID
+  @param[out] Address              - Pointer to the File Address
+  @param[out] Size                 - Pointer to File Size
+
+  @retval EFI_SUCCESS                Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+  IN CONST  EFI_GUID        NameGuid,
+  OUT VOID                  **Address,
+  OUT UINT32               *Size
+  );
+
+/**
+  Performs FSP Misc UPD initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+#endif // _PEI_FSP_POLICY_INIT_LIB_H_
+

+ 162 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf

@@ -0,0 +1,162 @@
+## @file
+# Library functions for Fsp Policy Initialization Library.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiFspPolicyInitLib
+  FILE_GUID                      = 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SiliconPolicyInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+  PeiFspPolicyInitLib.c
+  PeiFspSiPolicyInitLib.c
+  PeiFspPchPolicyInitLib.c
+  PeiFspCpuPolicyInitLib.c
+  PeiFspMePolicyInitLib.c
+  PeiFspSaPolicyInitLib.c
+  PeiFspSecurityPolicyInitLib.c
+  PeiFspMiscUpdInitLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+#                              this module.
+#
+################################################################################
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  IoLib
+  PeiServicesLib
+  SmbusLib
+  ConfigBlockLib
+  PcdLib
+  MemoryAllocationLib
+  PchInfoLib
+  SpiLib
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdTsegSize
+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor          ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap              ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize          ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize     ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase                   ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize                   ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize                ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize              ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode                        ## CONSUMES
+
+[Ppis]
+  gSiPolicyPpiGuid                        ## CONSUMES
+  gSiPreMemPolicyPpiGuid                  ## CONSUMES
+  gEfiSecPlatformInformation2PpiGuid      ## CONSUMES
+  gEfiSecPlatformInformationPpiGuid       ## CONSUMES
+
+[Guids]
+  gPchTraceHubPreMemConfigGuid            ## CONSUMES
+  gSmbusPreMemConfigGuid                  ## CONSUMES
+  gDciPreMemConfigGuid                    ## CONSUMES
+  gPcieRpPreMemConfigGuid                 ## CONSUMES
+  gHdAudioPreMemConfigGuid                ## CONSUMES
+  gIshPreMemConfigGuid                    ## CONSUMES
+  gHsioPciePreMemConfigGuid               ## CONSUMES
+  gHsioSataPreMemConfigGuid               ## CONSUMES
+  gLpcPreMemConfigGuid                    ## CONSUMES
+  gPchGeneralPreMemConfigGuid             ## CONSUMES
+  gWatchDogPreMemConfigGuid               ## CONSUMES
+  gLanConfigGuid                          ## CONSUMES
+  gPcieRpConfigGuid                       ## CONSUMES
+  gSataConfigGuid                         ## CONSUMES
+  gHdAudioConfigGuid                      ## CONSUMES
+  gScsConfigGuid                          ## CONSUMES
+  gIshConfigGuid                          ## CONSUMES
+  gSataConfigGuid                         ## CONSUMES
+  gUsbConfigGuid                          ## CONSUMES
+  gSerialIoConfigGuid                     ## CONSUMES
+  gInterruptConfigGuid                    ## CONSUMES
+  gLockDownConfigGuid                     ## CONSUMES
+  gSaMiscPeiPreMemConfigGuid              ## PRODUCES
+  gSaMiscPeiConfigGuid                    ## PRODUCES
+  gMemoryConfigGuid                       ## CONSUMES
+  gMemoryConfigNoCrcGuid                  ## CONSUMES
+  gSwitchableGraphicsConfigGuid           ## CONSUMES
+  gGraphicsPeiPreMemConfigGuid            ## CONSUMES
+  gSaPciePeiPreMemConfigGuid              ## CONSUMES
+  gSaMiscPeiConfigGuid                    ## CONSUMES
+  gSaPciePeiConfigGuid                    ## CONSUMES
+  gGraphicsPeiConfigGuid                  ## CONSUMES
+  gCpuTraceHubConfigGuid                  ## CONSUMES
+  gIpuPreMemConfigGuid                    ## CONSUMES
+  gCnviConfigGuid                         ## CONSUMES
+  gHsioConfigGuid                         ## CONSUMES
+  gEspiConfigGuid                         ## CONSUMES
+  gGnaConfigGuid                          ## CONSUMES
+  gVtdConfigGuid                          ## CONSUMES
+  gSaOverclockingPreMemConfigGuid         ## CONSUMES
+  gMePeiPreMemConfigGuid                  ## CONSUMES
+  gMePeiConfigGuid                        ## CONSUMES
+  gDmiConfigGuid                          ## CONSUMES
+  gFlashProtectionConfigGuid              ## CONSUMES
+  gIoApicConfigGuid                       ## CONSUMES
+  gPmConfigGuid                           ## CONSUMES
+  gP2sbConfigGuid                         ## CONSUMES
+  gPchGeneralConfigGuid                   ## CONSUMES
+  gSerialIrqConfigGuid                    ## CONSUMES
+  gThermalConfigGuid                      ## CONSUMES
+  gCpuSecurityPreMemConfigGuid            ## CONSUMES
+  gCpuConfigGuid                          ## CONSUMES
+  gCpuOverclockingPreMemConfigGuid        ## CONSUMES
+  gCpuConfigLibPreMemConfigGuid           ## CONSUMES
+  gCpuPowerMgmtBasicConfigGuid            ## CONSUMES
+  gCpuPowerMgmtCustomConfigGuid           ## CONSUMES
+  gCpuTestConfigGuid                      ## CONSUMES
+  gCpuPidTestConfigGuid                   ## CONSUMES
+  gCpuPowerMgmtTestConfigGuid             ## CONSUMES
+  gFspNonVolatileStorageHobGuid           ## CONSUMES
+  gSmramCpuDataHeaderGuid                 ## CONSUMES
+  gFspReservedMemoryResourceHobTsegGuid   ## CONSUMES
+  gSiConfigGuid                           ## CONSUMES
+  gDebugConfigHobGuid                     ## CONSUMES
+

+ 848 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c

@@ -0,0 +1,848 @@
+/** @file
+  Implementation of Fsp SA Policy Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <PchAccess.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/ConfigBlockLib.h>
+
+#define MAX_SPD_PAGE_COUNT           (2)
+#define MAX_SPD_PAGE_SIZE            (256)
+#define MAX_SPD_SIZE                 (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
+#define SPD_PAGE_ADDRESS_0           (0x6C)
+#define SPD_PAGE_ADDRESS_1           (0x6E)
+#define SPD_DDR3_SDRAM_TYPE_OFFSET   (0x02)
+#define SPD_DDR3_SDRAM_TYPE_NUMBER   (0x0B)
+#define SPD_DDR4_SDRAM_TYPE_NUMBER   (0x0C)
+#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
+#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
+#define XMP_ID_STRING                (0x4A0C)
+#define SPD3_MANUF_START             (117)
+#define SPD3_MANUF_END               (127)
+#define SPD4_MANUF_START             (320)
+#define SPD4_MANUF_END               (328)
+#define SPDLP_MANUF_START            (320)
+#define SPDLP_MANUF_END              (328)
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] = {
+  {   0,               1,             (1 << SpdCold),},
+  {   2,               2,             (1 << SpdCold) | (1 << SpdFast),},
+  {   3,              41,             (1 << SpdCold),},
+  {  60,              63,             (1 << SpdCold),},
+  { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+  { 128,             145,             (1 << SpdCold),},
+  {  39,              59,             (1 << SpdCold),},
+  {  64,             125,             (1 << SpdCold),},
+  { 176,             179,             (1 << SpdCold),},
+  { 180,             184,             (1 << SpdCold),},
+  { 185,             215,             (1 << SpdCold),},
+  { 220,             250,             (1 << SpdCold),},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] = {
+  {   0,               1,             (1 << SpdCold),},
+  {   2,               2,             (1 << SpdCold) | (1 << SpdFast),},
+  {   3,              40,             (1 << SpdCold),},
+  { 117,             131,             (1 << SpdCold),},
+  { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+  { 329,             348,             (1 << SpdCold),},
+  {  32,             119,             (1 << SpdCold),},
+  { 126,             255,             (1 << SpdCold),},
+  { 349,             383,             (1 << SpdCold),},
+  { 384,             387,             (1 << SpdCold),},
+  { 388,             389,             (1 << SpdCold),},
+  { 393,             431,             (1 << SpdCold),},
+  { 440,             478,             (1 << SpdCold),},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] = {
+  {   0,               1,               (1 << SpdCold),},
+  {   2,               2,               (1 << SpdCold) | (1 << SpdFast),},
+  {   3,              32,               (1 << SpdCold),},
+  { 120,             130,               (1 << SpdCold),},
+  { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+  { 329,             348,               (1 << SpdCold),},
+  {  31,             121,               (1 << SpdCold),},
+  { 126,             255,               (1 << SpdCold),},
+  { 349,             383,               (1 << SpdCold),},
+  { 384,             387,               (1 << SpdCold),},
+  { 388,             389,               (1 << SpdCold),},
+  { 393,             431,               (1 << SpdCold),},
+  { 440,             478,               (1 << SpdCold),},
+};
+
+
+/**
+  Update Spd Data
+
+  @param[in][out] FspmUpd              Pointer to FSP UPD Data.
+  @param[in]      MemConfigNoCrc       Pointer to Mem Config No Crc.
+  @param[in]      MiscPeiPreMemConfig  Pointer to Misc Config.
+
+  @retval         EFI_SUCCESS          The function completes successfully
+  @retval         Other                The function fail
+**/
+VOID
+EFIAPI
+InternalUpdateSpdInfo (
+  IN OUT FSPM_UPD               *FspmUpd,
+  IN MEMORY_CONFIG_NO_CRC       *MemConfigNoCrc,
+  IN SA_MISC_PEI_PREMEM_CONFIG  *MiscPeiPreMemConfig
+  )
+{
+
+  DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n"));
+  if ((FspmUpd == NULL) || (MemConfigNoCrc == NULL) || (MiscPeiPreMemConfig == NULL)) {
+    DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n"));
+    DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n"));
+    return;
+  }
+
+  //
+  // Update MemorySpdPtrXX if SpdAddressTable is zero
+  //
+  if (MiscPeiPreMemConfig->SpdAddressTable[0] == 0x0) {
+    FspmUpd->FspmConfig.MemorySpdPtr00 = (UINT32)MemConfigNoCrc->SpdData->SpdData;
+  } else {
+    FspmUpd->FspmConfig.SpdAddressTable[0] = MiscPeiPreMemConfig->SpdAddressTable[0];
+  }
+
+  if (MiscPeiPreMemConfig->SpdAddressTable[1] == 0x0) {
+    FspmUpd->FspmConfig.MemorySpdPtr01 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * SA_MC_MAX_SPD_SIZE);
+  } else {
+    FspmUpd->FspmConfig.SpdAddressTable[1] = MiscPeiPreMemConfig->SpdAddressTable[1];
+  }
+
+  if (MiscPeiPreMemConfig->SpdAddressTable[2] == 0x0) {
+    FspmUpd->FspmConfig.MemorySpdPtr10 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * SA_MC_MAX_SPD_SIZE);
+  } else {
+    FspmUpd->FspmConfig.SpdAddressTable[2] = MiscPeiPreMemConfig->SpdAddressTable[2];
+  }
+
+  if (MiscPeiPreMemConfig->SpdAddressTable[3] == 0x0) {
+    FspmUpd->FspmConfig.MemorySpdPtr11 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * SA_MC_MAX_SPD_SIZE);
+  } else {
+    FspmUpd->FspmConfig.SpdAddressTable[3] = MiscPeiPreMemConfig->SpdAddressTable[3];
+  }
+
+  DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n"));
+}
+
+/**
+  PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+  @param[in] NameGuid              - File GUID
+  @param[out] Address              - Pointer to the File Address
+  @param[out] Size                 - Pointer to File Size
+
+  @retval EFI_SUCCESS                Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+  IN CONST  EFI_GUID        NameGuid,
+  OUT VOID                  **Address,
+  OUT UINT32               *Size
+  )
+{
+  EFI_STATUS  Status;
+  EFI_PEI_FIRMWARE_VOLUME_PPI          *FvPpi;
+  EFI_FV_FILE_INFO                     FvFileInfo;
+  PEI_CORE_INSTANCE                    *PrivateData;
+  UINTN                                CurrentFv;
+  PEI_CORE_FV_HANDLE                   *CoreFvHandle;
+  EFI_PEI_FILE_HANDLE                  VbtFileHandle;
+  EFI_GUID                             *VbtGuid;
+  EFI_COMMON_SECTION_HEADER            *Section;
+  CONST EFI_PEI_SERVICES               **PeiServices;
+
+  PeiServices = GetPeiServicesTablePointer ();
+
+  PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+
+  Status = PeiServicesLocatePpi (
+            &gEfiFirmwareFileSystem2Guid,
+            0,
+            NULL,
+            (VOID **) &FvPpi
+            );
+  ASSERT_EFI_ERROR (Status);
+
+  CurrentFv = PrivateData->CurrentPeimFvCount;
+  CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
+
+  Status = FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &VbtFileHandle);
+  if (!EFI_ERROR(Status) && VbtFileHandle != NULL) {
+
+  DEBUG ((DEBUG_INFO, "Find SectionByType \n"));
+
+    Status = FvPpi->FindSectionByType (FvPpi, EFI_SECTION_RAW, VbtFileHandle, (VOID **) &VbtGuid);
+    if (!EFI_ERROR (Status)) {
+
+    DEBUG ((DEBUG_INFO, "GetFileInfo \n"));
+
+      Status = FvPpi->GetFileInfo (FvPpi, VbtFileHandle, &FvFileInfo);
+      Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+      if (IS_SECTION2 (Section)) {
+        ASSERT (SECTION2_SIZE (Section) > 0x00FFFFFF);
+        *Size = SECTION2_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+        *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+      } else {
+        *Size = SECTION_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+        *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+      }
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Performs FSP SA PEI Policy initialization in pre-memory.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                  Status;
+  SA_MISC_PEI_PREMEM_CONFIG   *MiscPeiPreMemConfig;
+  MEMORY_CONFIGURATION        *MemConfig;
+  MEMORY_CONFIG_NO_CRC        *MemConfigNoCrc;
+  SI_PREMEM_POLICY_PPI        *SiPreMemPolicyPpi;
+  PCIE_PEI_PREMEM_CONFIG      *PciePeiPreMemConfig;
+  SWITCHABLE_GRAPHICS_CONFIG  *SgGpioData;
+  GRAPHICS_PEI_PREMEM_CONFIG  *GtPreMemConfig;
+  OVERCLOCKING_PREMEM_CONFIG  *OcPreMemConfig;
+  VTD_CONFIG                  *Vtd;
+  IPU_PREMEM_CONFIG           *IpuPreMemPolicy;
+  UINT8                       Index;
+  VOID                        *Buffer;
+
+  SiPreMemPolicyPpi   = NULL;
+  MiscPeiPreMemConfig = NULL;
+  MemConfig           = NULL;
+  MemConfigNoCrc      = NULL;
+  PciePeiPreMemConfig = NULL;
+  SgGpioData          = NULL;
+  GtPreMemConfig      = NULL;
+  OcPreMemConfig      = NULL;
+  Vtd                 = NULL;
+  IpuPreMemPolicy     = NULL;
+
+
+
+  //
+  // Locate SiPreMemPolicyPpi
+  //
+  Status = PeiServicesLocatePpi(
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPreMemPolicyPpi
+             );
+  ASSERT_EFI_ERROR (Status);
+  if ((Status == EFI_SUCCESS) && (SiPreMemPolicyPpi != NULL)) {
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy);
+    ASSERT_EFI_ERROR (Status);
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig);
+    ASSERT_EFI_ERROR (Status);
+
+  }
+
+  DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
+  }
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
+  }
+
+  DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
+  }
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
+  }
+
+  //
+  // Update UPD:MemorySpdPtrXX and SpdAddressTable
+  //
+  InternalUpdateSpdInfo (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig);
+
+  //
+  // Update UPD:MemorySpdDataLen
+  //
+  FspmUpd->FspmConfig.MemorySpdDataLen = SA_MC_MAX_SPD_SIZE;
+
+  if (MemConfigNoCrc != NULL) {
+    //
+    // Update UPD:PlatformMemorySize
+    //
+    //
+    // @todo: This value is used since #183932. Revisit.
+    //
+    FspmUpd->FspmConfig.PlatformMemorySize  = MemConfigNoCrc->PlatformMemorySize;
+    FspmUpd->FspmConfig.CleanMemory         = (UINT8) MemConfigNoCrc->CleanMemory;
+    FspmUpd->FspmConfig.MemTestOnWarmBoot   = (UINT8) MemConfigNoCrc->MemTestOnWarmBoot;
+  }
+
+  if (MemConfig != NULL) {
+    //
+    // Update UPD:DqPinsInterleaved
+    //
+    FspmUpd->FspmConfig.DqPinsInterleaved     = (UINT8) MemConfig->DqPinsInterleaved;
+
+    FspmUpd->FspmConfig.ProbelessTrace        = MemConfig->ProbelessTrace;
+    FspmUpd->FspmConfig.GdxcIotSize           = MemConfig->GdxcIotSize;
+    FspmUpd->FspmConfig.GdxcMotSize           = MemConfig->GdxcMotSize;
+    FspmUpd->FspmConfig.DualDimmPerChannelBoardType =(UINT8) MemConfig->DualDimmPerChannelBoardType;
+    FspmUpd->FspmConfig.Ddr4MixedUDimm2DpcLimit     =(UINT8) MemConfig->Ddr4MixedUDimm2DpcLimit;
+    //
+    // Update UPD:CaVrefConfig
+    //
+    FspmUpd->FspmConfig.CaVrefConfig          = MemConfig->CaVrefConfig;
+    FspmUpd->FspmConfig.SaGv                  = MemConfig->SaGv;
+    FspmUpd->FspmConfig.FreqSaGvLow           = MemConfig->FreqSaGvLow;
+    FspmUpd->FspmConfig.RMT                   = (UINT8) MemConfig->RMT;
+    FspmUpd->FspmConfig.DdrFreqLimit          = MemConfig->DdrFreqLimit;
+
+    FspmUpd->FspmConfig.SpdProfileSelected    = MemConfig->SpdProfileSelected;
+    FspmUpd->FspmConfig.VddVoltage            = MemConfig->VddVoltage;
+    FspmUpd->FspmConfig.RefClk                = MemConfig->RefClk;
+    FspmUpd->FspmConfig.Ratio                 = MemConfig->Ratio;
+    FspmUpd->FspmConfig.OddRatioMode          = (UINT8) MemConfig->OddRatioMode;
+    FspmUpd->FspmConfig.tCL                   = (UINT8) MemConfig->tCL;
+    FspmUpd->FspmConfig.tCWL                  = (UINT8) MemConfig->tCWL;
+    FspmUpd->FspmConfig.tFAW                  = MemConfig->tFAW;
+    FspmUpd->FspmConfig.tRAS                  = MemConfig->tRAS;
+    FspmUpd->FspmConfig.tRCDtRP               = (UINT8) MemConfig->tRCDtRP;
+    FspmUpd->FspmConfig.tREFI                 = MemConfig->tREFI;
+    FspmUpd->FspmConfig.tRFC                  = MemConfig->tRFC;
+    FspmUpd->FspmConfig.tRRD                  = (UINT8) MemConfig->tRRD;
+    FspmUpd->FspmConfig.tRTP                  = (UINT8) MemConfig->tRTP;
+    FspmUpd->FspmConfig.tWR                   = (UINT8) MemConfig->tWR;
+    FspmUpd->FspmConfig.tWTR                  = (UINT8) MemConfig->tWTR;
+    FspmUpd->FspmConfig.NModeSupport          = MemConfig->NModeSupport;
+    FspmUpd->FspmConfig.DllBwEn0              = MemConfig->DllBwEn0;
+    FspmUpd->FspmConfig.DllBwEn1              = MemConfig->DllBwEn1;
+    FspmUpd->FspmConfig.DllBwEn2              = MemConfig->DllBwEn2;
+    FspmUpd->FspmConfig.DllBwEn3              = MemConfig->DllBwEn3;
+    FspmUpd->FspmConfig.MrcSafeConfig         = (UINT8) MemConfig->MrcSafeConfig; // Typecasting as MrcSafeConfig is of UINT32 in MEMORY_CONFIGURATION
+    FspmUpd->FspmConfig.LpDdrDqDqsReTraining  = (UINT8) MemConfig->Lp4DqsOscEn;
+    FspmUpd->FspmConfig.RmtPerTask            = (UINT8) MemConfig->RmtPerTask;
+    FspmUpd->FspmConfig.TrainTrace            = (UINT8) MemConfig->TrainTrace;
+    FspmUpd->FspmConfig.ScramblerSupport      = (UINT8) MemConfig->ScramblerSupport;
+    FspmUpd->FspmConfig.SafeMode              = (UINT8) MemConfig->SafeMode;
+
+    //
+    // Update UPD:SmramMask and DisableDimmChannel
+    //
+    FspmUpd->FspmConfig.SmramMask               = MemConfig->SmramMask;
+    FspmUpd->FspmConfig.DisableDimmChannel0     = MemConfig->DisableDimmChannel[0];
+    FspmUpd->FspmConfig.DisableDimmChannel1     = MemConfig->DisableDimmChannel[1];
+    FspmUpd->FspmConfig.HobBufferSize           = MemConfig->HobBufferSize;
+
+    FspmUpd->FspmConfig.ECT                     = (UINT8) MemConfig->ECT;
+    FspmUpd->FspmConfig.SOT                     = (UINT8) MemConfig->SOT;
+    FspmUpd->FspmConfig.ERDMPRTC2D              = (UINT8) MemConfig->ERDMPRTC2D;
+    FspmUpd->FspmConfig.RDMPRT                  = (UINT8) MemConfig->RDMPRT;
+    FspmUpd->FspmConfig.RCVET                   = (UINT8) MemConfig->RCVET;
+    FspmUpd->FspmConfig.JWRL                    = (UINT8) MemConfig->JWRL;
+    FspmUpd->FspmConfig.EWRTC2D                 = (UINT8) MemConfig->EWRTC2D;
+    FspmUpd->FspmConfig.ERDTC2D                 = (UINT8) MemConfig->ERDTC2D;
+    FspmUpd->FspmConfig.WRTC1D                  = (UINT8) MemConfig->WRTC1D;
+    FspmUpd->FspmConfig.WRVC1D                  = (UINT8) MemConfig->WRVC1D;
+    FspmUpd->FspmConfig.RDTC1D                  = (UINT8) MemConfig->RDTC1D;
+    FspmUpd->FspmConfig.DIMMODTT                = (UINT8) MemConfig->DIMMODTT;
+    FspmUpd->FspmConfig.DIMMRONT                = (UINT8) MemConfig->DIMMRONT;
+    FspmUpd->FspmConfig.WRSRT                   = (UINT8) MemConfig->WRSRT;
+    FspmUpd->FspmConfig.RDODTT                  = (UINT8) MemConfig->RDODTT;
+    FspmUpd->FspmConfig.RDEQT                   = (UINT8) MemConfig->RDEQT;
+    FspmUpd->FspmConfig.RDAPT                   = (UINT8) MemConfig->RDAPT;
+    FspmUpd->FspmConfig.WRTC2D                  = (UINT8) MemConfig->WRTC2D;
+    FspmUpd->FspmConfig.RDTC2D                  = (UINT8) MemConfig->RDTC2D;
+    FspmUpd->FspmConfig.WRVC2D                  = (UINT8) MemConfig->WRVC2D;
+    FspmUpd->FspmConfig.RDVC2D                  = (UINT8) MemConfig->RDVC2D;
+    FspmUpd->FspmConfig.CMDVC                   = (UINT8) MemConfig->CMDVC;
+    FspmUpd->FspmConfig.LCT                     = (UINT8) MemConfig->LCT;
+    FspmUpd->FspmConfig.RTL                     = (UINT8) MemConfig->RTL;
+    FspmUpd->FspmConfig.TAT                     = (UINT8) MemConfig->TAT;
+    FspmUpd->FspmConfig.RCVENC1D                = (UINT8) MemConfig->RCVENC1D;
+    FspmUpd->FspmConfig.RMT                     = (UINT8) MemConfig->RMT;
+    FspmUpd->FspmConfig.MEMTST                  = (UINT8) MemConfig->MEMTST;
+    FspmUpd->FspmConfig.ALIASCHK                = (UINT8) MemConfig->ALIASCHK;
+    FspmUpd->FspmConfig.RMC                     = (UINT8) MemConfig->RMC;
+    FspmUpd->FspmConfig.WRDSUDT                 = (UINT8) MemConfig->WRDSUDT;
+    FspmUpd->FspmConfig.EnBER                   = (UINT8) MemConfig->EnBER;
+    FspmUpd->FspmConfig.EccSupport              = (UINT8) MemConfig->EccSupport;
+    FspmUpd->FspmConfig.RemapEnable             = (UINT8) MemConfig->RemapEnable;
+    FspmUpd->FspmConfig.ScramblerSupport        = (UINT8) MemConfig->ScramblerSupport;
+    FspmUpd->FspmConfig.MrcFastBoot             = (UINT8) MemConfig->MrcFastBoot;
+    FspmUpd->FspmConfig.RankInterleave          = (UINT8) MemConfig->RankInterleave;
+    FspmUpd->FspmConfig.EnhancedInterleave      = (UINT8) MemConfig->EnhancedInterleave;
+    FspmUpd->FspmConfig.MemoryTrace             = (UINT8) MemConfig->MemoryTrace;
+    FspmUpd->FspmConfig.ChHashEnable            = (UINT8) MemConfig->ChHashEnable;
+    FspmUpd->FspmConfig.EnableExtts             = (UINT8) MemConfig->EnableExtts;
+    FspmUpd->FspmConfig.EnableCltm              = (UINT8) MemConfig->EnableCltm;
+    FspmUpd->FspmConfig.EnableOltm              = (UINT8) MemConfig->EnableOltm;
+    FspmUpd->FspmConfig.EnablePwrDn             = (UINT8) MemConfig->EnablePwrDn;
+    FspmUpd->FspmConfig.EnablePwrDnLpddr        = (UINT8) MemConfig->EnablePwrDnLpddr;
+    FspmUpd->FspmConfig.UserPowerWeightsEn      = (UINT8) MemConfig->UserPowerWeightsEn;
+    FspmUpd->FspmConfig.RaplLim2Lock            = (UINT8) MemConfig->RaplLim2Lock;
+    FspmUpd->FspmConfig.RaplLim2Ena             = (UINT8) MemConfig->RaplLim2Ena;
+    FspmUpd->FspmConfig.RaplLim1Ena             = (UINT8) MemConfig->RaplLim1Ena;
+    FspmUpd->FspmConfig.SrefCfgEna              = (UINT8) MemConfig->SrefCfgEna;
+    FspmUpd->FspmConfig.ThrtCkeMinDefeatLpddr   = (UINT8) MemConfig->ThrtCkeMinDefeatLpddr;
+    FspmUpd->FspmConfig.ThrtCkeMinDefeat        = (UINT8) MemConfig->ThrtCkeMinDefeat;
+    FspmUpd->FspmConfig.RhPrevention            = (UINT8) MemConfig->RhPrevention;
+    FspmUpd->FspmConfig.ExitOnFailure           = (UINT8) MemConfig->ExitOnFailure;
+    FspmUpd->FspmConfig.DdrThermalSensor        = (UINT8) MemConfig->DdrThermalSensor;
+    FspmUpd->FspmConfig.Ddr4DdpSharedClock      = (UINT8) MemConfig->Ddr4DdpSharedClock;
+    FspmUpd->FspmConfig.Ddr4DdpSharedZq         = (UINT8) MemConfig->SharedZqPin;
+    FspmUpd->FspmConfig.BClkFrequency           = MemConfig->BClkFrequency;
+    FspmUpd->FspmConfig.ChHashInterleaveBit     = MemConfig->ChHashInterleaveBit;
+    FspmUpd->FspmConfig.ChHashMask              = MemConfig->ChHashMask;
+    FspmUpd->FspmConfig.EnergyScaleFact         = MemConfig->EnergyScaleFact;
+    FspmUpd->FspmConfig.Idd3n                   = MemConfig->Idd3n;
+    FspmUpd->FspmConfig.Idd3p                   = MemConfig->Idd3p;
+    FspmUpd->FspmConfig.CMDSR                   = (UINT8) MemConfig->CMDSR;
+    FspmUpd->FspmConfig.CMDDSEQ                 = (UINT8) MemConfig->CMDDSEQ;
+    FspmUpd->FspmConfig.CMDNORM                 = (UINT8) MemConfig->CMDNORM;
+    FspmUpd->FspmConfig.EWRDSEQ                 = (UINT8) MemConfig->EWRDSEQ;
+    FspmUpd->FspmConfig.FreqSaGvLow             = MemConfig->FreqSaGvLow;
+    FspmUpd->FspmConfig.RhActProbability        = MemConfig->RhActProbability;
+    FspmUpd->FspmConfig.RaplLim2WindX           = MemConfig->RaplLim2WindX;
+    FspmUpd->FspmConfig.RaplLim2WindY           = MemConfig->RaplLim2WindY;
+    FspmUpd->FspmConfig.RaplLim1WindX           = MemConfig->RaplLim1WindX;
+    FspmUpd->FspmConfig.RaplLim1WindY           = MemConfig->RaplLim1WindY;
+    FspmUpd->FspmConfig.RaplLim2Pwr             = MemConfig->RaplLim2Pwr;
+    FspmUpd->FspmConfig.RaplLim1Pwr             = MemConfig->RaplLim1Pwr;
+    FspmUpd->FspmConfig.WarmThresholdCh0Dimm0   = MemConfig->WarmThresholdCh0Dimm0;
+    FspmUpd->FspmConfig.WarmThresholdCh0Dimm1   = MemConfig->WarmThresholdCh0Dimm1;
+    FspmUpd->FspmConfig.WarmThresholdCh1Dimm0   = MemConfig->WarmThresholdCh1Dimm0;
+    FspmUpd->FspmConfig.WarmThresholdCh1Dimm1   = MemConfig->WarmThresholdCh1Dimm1;
+    FspmUpd->FspmConfig.HotThresholdCh0Dimm0    = MemConfig->HotThresholdCh0Dimm0;
+    FspmUpd->FspmConfig.HotThresholdCh0Dimm1    = MemConfig->HotThresholdCh0Dimm1;
+    FspmUpd->FspmConfig.HotThresholdCh1Dimm0    = MemConfig->HotThresholdCh1Dimm0;
+    FspmUpd->FspmConfig.HotThresholdCh1Dimm1    = MemConfig->HotThresholdCh1Dimm1;
+    FspmUpd->FspmConfig.WarmBudgetCh0Dimm0      = MemConfig->WarmBudgetCh0Dimm0;
+    FspmUpd->FspmConfig.WarmBudgetCh0Dimm1      = MemConfig->WarmBudgetCh0Dimm1;
+    FspmUpd->FspmConfig.WarmBudgetCh1Dimm0      = MemConfig->WarmBudgetCh1Dimm0;
+    FspmUpd->FspmConfig.WarmBudgetCh1Dimm1      = MemConfig->WarmBudgetCh1Dimm1;
+    FspmUpd->FspmConfig.HotBudgetCh0Dimm0       = MemConfig->HotBudgetCh0Dimm0;
+    FspmUpd->FspmConfig.HotBudgetCh0Dimm1       = MemConfig->HotBudgetCh0Dimm1;
+    FspmUpd->FspmConfig.HotBudgetCh1Dimm0       = MemConfig->HotBudgetCh1Dimm0;
+    FspmUpd->FspmConfig.HotBudgetCh1Dimm1       = MemConfig->HotBudgetCh1Dimm1;
+    FspmUpd->FspmConfig.IdleEnergyCh0Dimm0      = MemConfig->IdleEnergyCh0Dimm0;
+    FspmUpd->FspmConfig.IdleEnergyCh0Dimm1      = MemConfig->IdleEnergyCh0Dimm1;
+    FspmUpd->FspmConfig.IdleEnergyCh1Dimm0      = MemConfig->IdleEnergyCh1Dimm0;
+    FspmUpd->FspmConfig.IdleEnergyCh1Dimm1      = MemConfig->IdleEnergyCh1Dimm1;
+    FspmUpd->FspmConfig.PdEnergyCh0Dimm0        = MemConfig->PdEnergyCh0Dimm0;
+    FspmUpd->FspmConfig.PdEnergyCh0Dimm1        = MemConfig->PdEnergyCh0Dimm1;
+    FspmUpd->FspmConfig.PdEnergyCh1Dimm0        = MemConfig->PdEnergyCh1Dimm0;
+    FspmUpd->FspmConfig.PdEnergyCh1Dimm1        = MemConfig->PdEnergyCh1Dimm1;
+    FspmUpd->FspmConfig.ActEnergyCh0Dimm0       = MemConfig->ActEnergyCh0Dimm0;
+    FspmUpd->FspmConfig.ActEnergyCh0Dimm1       = MemConfig->ActEnergyCh0Dimm1;
+    FspmUpd->FspmConfig.ActEnergyCh1Dimm0       = MemConfig->ActEnergyCh1Dimm0;
+    FspmUpd->FspmConfig.ActEnergyCh1Dimm1       = MemConfig->ActEnergyCh1Dimm1;
+    FspmUpd->FspmConfig.RdEnergyCh0Dimm0        = MemConfig->RdEnergyCh0Dimm0;
+    FspmUpd->FspmConfig.RdEnergyCh0Dimm1        = MemConfig->RdEnergyCh0Dimm1;
+    FspmUpd->FspmConfig.RdEnergyCh1Dimm0        = MemConfig->RdEnergyCh1Dimm0;
+    FspmUpd->FspmConfig.RdEnergyCh1Dimm1        = MemConfig->RdEnergyCh1Dimm1;
+    FspmUpd->FspmConfig.WrEnergyCh0Dimm0        = MemConfig->WrEnergyCh0Dimm0;
+    FspmUpd->FspmConfig.WrEnergyCh0Dimm1        = MemConfig->WrEnergyCh0Dimm1;
+    FspmUpd->FspmConfig.WrEnergyCh1Dimm0        = MemConfig->WrEnergyCh1Dimm0;
+    FspmUpd->FspmConfig.WrEnergyCh1Dimm1        = MemConfig->WrEnergyCh1Dimm1;
+    FspmUpd->FspmConfig.ThrtCkeMinTmr           = MemConfig->ThrtCkeMinTmr;
+    FspmUpd->FspmConfig.CkeRankMapping          = MemConfig->CkeRankMapping;
+    FspmUpd->FspmConfig.CaVrefConfig            = MemConfig->CaVrefConfig;
+    FspmUpd->FspmConfig.RaplPwrFlCh1            = MemConfig->RaplPwrFlCh1;
+    FspmUpd->FspmConfig.RaplPwrFlCh0            = MemConfig->RaplPwrFlCh0;
+    FspmUpd->FspmConfig.EnCmdRate               = MemConfig->EnCmdRate;
+    FspmUpd->FspmConfig.Refresh2X               = MemConfig->Refresh2X;
+    FspmUpd->FspmConfig.EpgEnable               = MemConfig->EpgEnable;
+    FspmUpd->FspmConfig.RhSolution              = MemConfig->RhSolution;
+    FspmUpd->FspmConfig.UserThresholdEnable     = MemConfig->UserThresholdEnable;
+    FspmUpd->FspmConfig.UserBudgetEnable        = MemConfig->UserBudgetEnable;
+    FspmUpd->FspmConfig.TsodTcritMax            = MemConfig->TsodTcritMax;
+    FspmUpd->FspmConfig.TsodEventMode           = MemConfig->TsodEventMode;
+    FspmUpd->FspmConfig.TsodEventPolarity       = MemConfig->TsodEventPolarity;
+    FspmUpd->FspmConfig.TsodCriticalEventOnly   = MemConfig->TsodCriticalEventOnly;
+    FspmUpd->FspmConfig.TsodEventOutputControl  = MemConfig->TsodEventOutputControl;
+    FspmUpd->FspmConfig.TsodAlarmwindowLockBit  = MemConfig->TsodAlarmwindowLockBit;
+    FspmUpd->FspmConfig.TsodCriticaltripLockBit = MemConfig->TsodCriticaltripLockBit;
+    FspmUpd->FspmConfig.TsodShutdownMode        = MemConfig->TsodShutdownMode;
+    FspmUpd->FspmConfig.TsodThigMax             = MemConfig->TsodThigMax;
+    FspmUpd->FspmConfig.TsodManualEnable        = MemConfig->TsodManualEnable;
+    FspmUpd->FspmConfig.IsvtIoPort              = MemConfig->IsvtIoPort;
+    FspmUpd->FspmConfig.ForceOltmOrRefresh2x    = MemConfig->ForceOltmOrRefresh2x;
+    FspmUpd->FspmConfig.PwdwnIdleCounter        = MemConfig->PwdwnIdleCounter;
+    FspmUpd->FspmConfig.CmdRanksTerminated      = MemConfig->CmdRanksTerminated;
+    FspmUpd->FspmConfig.GdxcEnable              = MemConfig->GdxcEnable;
+    FspmUpd->FspmConfig.RMTLoopCount            = MemConfig->RMTLoopCount;
+
+    // DDR4 Memory Timings
+    FspmUpd->FspmTestConfig.tRRD_L = (UINT8) MemConfig->tRRD_L;
+    FspmUpd->FspmTestConfig.tRRD_S = (UINT8) MemConfig->tRRD_S;
+    FspmUpd->FspmTestConfig.tWTR_L = (UINT8) MemConfig->tWTR_L;
+    FspmUpd->FspmTestConfig.tWTR_S = (UINT8) MemConfig->tWTR_S;
+
+    // TurnAround Timing
+    // Read-to-Read
+    FspmUpd->FspmTestConfig.tRd2RdSG = MemConfig->tRd2RdSG;
+    FspmUpd->FspmTestConfig.tRd2RdDG = MemConfig->tRd2RdDG;
+    FspmUpd->FspmTestConfig.tRd2RdDR = MemConfig->tRd2RdDR;
+    FspmUpd->FspmTestConfig.tRd2RdDD = MemConfig->tRd2RdDD;
+    // Write-to-Read
+    FspmUpd->FspmTestConfig.tWr2RdSG = MemConfig->tWr2RdSG;
+    FspmUpd->FspmTestConfig.tWr2RdDG = MemConfig->tWr2RdDG;
+    FspmUpd->FspmTestConfig.tWr2RdDR = MemConfig->tWr2RdDR;
+    FspmUpd->FspmTestConfig.tWr2RdDD = MemConfig->tWr2RdDD;
+    // Write-to-Write
+    FspmUpd->FspmTestConfig.tWr2WrSG = MemConfig->tWr2WrSG;
+    FspmUpd->FspmTestConfig.tWr2WrDG = MemConfig->tWr2WrDG;
+    FspmUpd->FspmTestConfig.tWr2WrDR = MemConfig->tWr2WrDR;
+    FspmUpd->FspmTestConfig.tWr2WrDD = MemConfig->tWr2WrDD;
+    // Read-to-Write
+    FspmUpd->FspmTestConfig.tRd2WrSG = MemConfig->tRd2WrSG;
+    FspmUpd->FspmTestConfig.tRd2WrDG = MemConfig->tRd2WrDG;
+    FspmUpd->FspmTestConfig.tRd2WrDR = MemConfig->tRd2WrDR;
+    FspmUpd->FspmTestConfig.tRd2WrDD = MemConfig->tRd2WrDD;
+  }
+
+  if (MiscPeiPreMemConfig != NULL) {
+    FspmUpd->FspmConfig.IedSize               = MiscPeiPreMemConfig->IedSize;
+    FspmUpd->FspmConfig.UserBd                = MiscPeiPreMemConfig->UserBd;
+    FspmUpd->FspmConfig.SgDelayAfterPwrEn     = MiscPeiPreMemConfig->SgDelayAfterPwrEn;
+    FspmUpd->FspmConfig.SgDelayAfterHoldReset = MiscPeiPreMemConfig->SgDelayAfterHoldReset;
+    FspmUpd->FspmConfig.MmioSize              = MiscPeiPreMemConfig->MmioSize;
+    FspmUpd->FspmConfig.MmioSizeAdjustment    = MiscPeiPreMemConfig->MmioSizeAdjustment;
+    FspmUpd->FspmConfig.TsegSize              = MiscPeiPreMemConfig->TsegSize;
+
+    FspmUpd->FspmTestConfig.SkipExtGfxScan           = (UINT8) MiscPeiPreMemConfig->SkipExtGfxScan;
+    FspmUpd->FspmTestConfig.BdatEnable               = (UINT8) MiscPeiPreMemConfig->BdatEnable;
+    FspmUpd->FspmTestConfig.BdatTestType             = (UINT8) MiscPeiPreMemConfig->BdatTestType;
+    FspmUpd->FspmTestConfig.ScanExtGfxForLegacyOpRom = (UINT8) MiscPeiPreMemConfig->ScanExtGfxForLegacyOpRom;
+    FspmUpd->FspmTestConfig.LockPTMregs              = (UINT8) MiscPeiPreMemConfig->LockPTMregs;
+  }
+
+  if (Vtd != NULL) {
+    FspmUpd->FspmConfig.X2ApicOptOut = (UINT8) Vtd->X2ApicOptOut;
+    FspmUpd->FspmConfig.VtdBaseAddress[0] = Vtd->BaseAddress[0];
+    FspmUpd->FspmConfig.VtdBaseAddress[1] = Vtd->BaseAddress[1];
+    FspmUpd->FspmConfig.VtdBaseAddress[2] = Vtd->BaseAddress[2];
+    FspmUpd->FspmTestConfig.VtdDisable = (UINT8) Vtd->VtdDisable;
+  }
+
+  if (PciePeiPreMemConfig != NULL) {
+    FspmUpd->FspmConfig.DmiGen3ProgramStaticEq = (UINT8) PciePeiPreMemConfig->DmiGen3ProgramStaticEq;
+    FspmUpd->FspmConfig.Peg0Enable = (UINT8) PciePeiPreMemConfig->Peg0Enable;
+    FspmUpd->FspmConfig.Peg1Enable = (UINT8) PciePeiPreMemConfig->Peg1Enable;
+    FspmUpd->FspmConfig.Peg2Enable = (UINT8) PciePeiPreMemConfig->Peg2Enable;
+    FspmUpd->FspmConfig.Peg3Enable = (UINT8) PciePeiPreMemConfig->Peg3Enable;
+    FspmUpd->FspmConfig.Peg0MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg0MaxLinkSpeed;
+    FspmUpd->FspmConfig.Peg1MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg1MaxLinkSpeed;
+    FspmUpd->FspmConfig.Peg2MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg2MaxLinkSpeed;
+    FspmUpd->FspmConfig.Peg3MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg3MaxLinkSpeed;
+    FspmUpd->FspmConfig.Peg0MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg0MaxLinkWidth;
+    FspmUpd->FspmConfig.Peg1MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg1MaxLinkWidth;
+    FspmUpd->FspmConfig.Peg2MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg2MaxLinkWidth;
+    FspmUpd->FspmConfig.Peg3MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg3MaxLinkWidth;
+    FspmUpd->FspmConfig.Peg0PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg0PowerDownUnusedLanes;
+    FspmUpd->FspmConfig.Peg1PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg1PowerDownUnusedLanes;
+    FspmUpd->FspmConfig.Peg2PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg2PowerDownUnusedLanes;
+    FspmUpd->FspmConfig.Peg3PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg3PowerDownUnusedLanes;
+    FspmUpd->FspmConfig.InitPcieAspmAfterOprom = (UINT8) PciePeiPreMemConfig->InitPcieAspmAfterOprom;
+    FspmUpd->FspmConfig.PegDisableSpreadSpectrumClocking = (UINT8) PciePeiPreMemConfig->PegDisableSpreadSpectrumClocking;
+    for (Index = 0; Index < SA_DMI_MAX_LANE; Index++) {
+      FspmUpd->FspmConfig.DmiGen3RootPortPreset[Index] = PciePeiPreMemConfig->DmiGen3RootPortPreset[Index];
+      FspmUpd->FspmConfig.DmiGen3EndPointPreset[Index] = PciePeiPreMemConfig->DmiGen3EndPointPreset[Index];
+      FspmUpd->FspmConfig.DmiGen3EndPointHint[Index] = PciePeiPreMemConfig->DmiGen3EndPointHint[Index];
+    }
+    for (Index = 0; Index < SA_DMI_MAX_BUNDLE; Index++) {
+      FspmUpd->FspmConfig.DmiGen3RxCtlePeaking[Index] = PciePeiPreMemConfig->DmiGen3RxCtlePeaking[Index];
+    }
+    for (Index = 0; Index < SA_PEG_MAX_BUNDLE ; Index++) {
+      FspmUpd->FspmConfig.PegGen3RxCtlePeaking[Index] = PciePeiPreMemConfig->PegGen3RxCtlePeaking[Index];
+    }
+    FspmUpd->FspmConfig.PegDataPtr = (UINT32) PciePeiPreMemConfig->PegDataPtr;
+    CopyMem((VOID *)FspmUpd->FspmConfig.PegGpioData, &PciePeiPreMemConfig->PegGpioData, sizeof (PEG_GPIO_DATA));
+    FspmUpd->FspmConfig.DmiDeEmphasis = PciePeiPreMemConfig->DmiDeEmphasis;
+
+    for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
+      FspmUpd->FspmConfig.PegRootPortHPE[Index] = PciePeiPreMemConfig->PegRootPortHPE[Index];
+    }
+    FspmUpd->FspmTestConfig.DmiMaxLinkSpeed     = (UINT8) PciePeiPreMemConfig->DmiMaxLinkSpeed;
+    FspmUpd->FspmTestConfig.DmiGen3EqPh2Enable  = (UINT8) PciePeiPreMemConfig->DmiGen3EqPh2Enable;
+    FspmUpd->FspmTestConfig.DmiGen3EqPh3Method  = (UINT8) PciePeiPreMemConfig->DmiGen3EqPh3Method;
+    FspmUpd->FspmTestConfig.Peg0Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg0Gen3EqPh2Enable;
+    FspmUpd->FspmTestConfig.Peg1Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg1Gen3EqPh2Enable;
+    FspmUpd->FspmTestConfig.Peg2Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg2Gen3EqPh2Enable;
+    FspmUpd->FspmTestConfig.Peg3Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg3Gen3EqPh2Enable;
+    FspmUpd->FspmTestConfig.Peg0Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg0Gen3EqPh3Method;
+    FspmUpd->FspmTestConfig.Peg1Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg1Gen3EqPh3Method;
+    FspmUpd->FspmTestConfig.Peg2Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg2Gen3EqPh3Method;
+    FspmUpd->FspmTestConfig.Peg3Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg3Gen3EqPh3Method;
+    FspmUpd->FspmTestConfig.PegGen3ProgramStaticEq = (UINT8) PciePeiPreMemConfig->PegGen3ProgramStaticEq;
+    FspmUpd->FspmTestConfig.Gen3SwEqAlwaysAttempt = (UINT8) PciePeiPreMemConfig->Gen3SwEqAlwaysAttempt;
+    FspmUpd->FspmTestConfig.Gen3SwEqNumberOfPresets = (UINT8) PciePeiPreMemConfig->Gen3SwEqNumberOfPresets;
+    FspmUpd->FspmTestConfig.Gen3SwEqEnableVocTest = (UINT8) PciePeiPreMemConfig->Gen3SwEqEnableVocTest;
+    FspmUpd->FspmTestConfig.PegRxCemTestingMode = (UINT8) PciePeiPreMemConfig->PegRxCemTestingMode;
+    FspmUpd->FspmTestConfig.PegRxCemLoopbackLane = (UINT8) PciePeiPreMemConfig->PegRxCemLoopbackLane;
+    FspmUpd->FspmTestConfig.PegGenerateBdatMarginTable = (UINT8) PciePeiPreMemConfig->PegGenerateBdatMarginTable;
+    FspmUpd->FspmTestConfig.PegRxCemNonProtocolAwareness = (UINT8) PciePeiPreMemConfig->PegRxCemNonProtocolAwareness;
+    FspmUpd->FspmTestConfig.PegGen3RxCtleOverride = (UINT8) PciePeiPreMemConfig->PegGen3RxCtleOverride;
+    for (Index = 0; Index < SA_PEG_MAX_LANE; Index++) {
+      FspmUpd->FspmTestConfig.PegGen3RootPortPreset[Index] = PciePeiPreMemConfig->PegGen3RootPortPreset[Index];
+      FspmUpd->FspmTestConfig.PegGen3EndPointPreset[Index] = PciePeiPreMemConfig->PegGen3EndPointPreset[Index];
+      FspmUpd->FspmTestConfig.PegGen3EndPointHint[Index] = PciePeiPreMemConfig->PegGen3EndPointHint[Index];
+    }
+    FspmUpd->FspmTestConfig.Gen3SwEqJitterDwellTime = PciePeiPreMemConfig->Gen3SwEqJitterDwellTime;
+    FspmUpd->FspmTestConfig.Gen3SwEqJitterErrorTarget = PciePeiPreMemConfig->Gen3SwEqJitterErrorTarget;
+    FspmUpd->FspmTestConfig.Gen3SwEqVocDwellTime = PciePeiPreMemConfig->Gen3SwEqVocDwellTime;
+    FspmUpd->FspmTestConfig.Gen3SwEqVocErrorTarget = PciePeiPreMemConfig->Gen3SwEqVocErrorTarget;
+  }
+
+  if (GtPreMemConfig != NULL) {
+    FspmUpd->FspmConfig.PrimaryDisplay = (UINT8) GtPreMemConfig->PrimaryDisplay;
+    FspmUpd->FspmConfig.InternalGfx = (UINT8) GtPreMemConfig->InternalGraphics;
+    FspmUpd->FspmConfig.IgdDvmt50PreAlloc = (UINT8) GtPreMemConfig->IgdDvmt50PreAlloc;
+    FspmUpd->FspmConfig.ApertureSize = (UINT8) GtPreMemConfig->ApertureSize;
+    FspmUpd->FspmConfig.GttMmAdr = GtPreMemConfig->GttMmAdr;
+    FspmUpd->FspmConfig.GmAdr = GtPreMemConfig->GmAdr;
+    FspmUpd->FspmConfig.GttSize = GtPreMemConfig->GttSize;
+    FspmUpd->FspmConfig.PsmiRegionSize = (UINT8) GtPreMemConfig->PsmiRegionSize;
+    FspmUpd->FspmConfig.GtPsmiSupport = (UINT8)GtPreMemConfig->GtPsmiSupport;
+    FspmUpd->FspmTestConfig.PanelPowerEnable = (UINT8) GtPreMemConfig->PanelPowerEnable;
+    FspmUpd->FspmTestConfig.DeltaT12PowerCycleDelayPreMem = (UINT16) GtPreMemConfig->DeltaT12PowerCycleDelayPreMem;
+  }
+
+  if (SgGpioData != NULL) {
+    CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie0Gpio, &SgGpioData->SaRtd3Pcie0Gpio, sizeof (SA_PCIE_RTD3_GPIO));
+    CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie1Gpio, &SgGpioData->SaRtd3Pcie1Gpio, sizeof (SA_PCIE_RTD3_GPIO));
+    CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie2Gpio, &SgGpioData->SaRtd3Pcie2Gpio, sizeof (SA_PCIE_RTD3_GPIO));
+    FspmUpd->FspmConfig.RootPortIndex = SgGpioData->RootPortIndex;
+  }
+
+  if (IpuPreMemPolicy != NULL) {
+    FspmUpd->FspmConfig.SaIpuEnable = (UINT8) IpuPreMemPolicy->SaIpuEnable;
+    FspmUpd->FspmConfig.SaIpuImrConfiguration = (UINT8) IpuPreMemPolicy->SaIpuImrConfiguration;
+  }
+
+  if (OcPreMemConfig != NULL) {
+    FspmUpd->FspmConfig.SaOcSupport = (UINT8) OcPreMemConfig->OcSupport;
+    FspmUpd->FspmConfig.RealtimeMemoryTiming = (UINT8) OcPreMemConfig->RealtimeMemoryTiming;
+    FspmUpd->FspmConfig.GtVoltageMode = (UINT8) OcPreMemConfig->GtVoltageMode;
+    FspmUpd->FspmConfig.GtMaxOcRatio = OcPreMemConfig->GtMaxOcRatio;
+    FspmUpd->FspmConfig.GtVoltageOffset = OcPreMemConfig->GtVoltageOffset;
+    FspmUpd->FspmConfig.GtVoltageOverride = OcPreMemConfig->GtVoltageOverride;
+    FspmUpd->FspmConfig.GtExtraTurboVoltage = OcPreMemConfig->GtExtraTurboVoltage;
+    FspmUpd->FspmConfig.SaVoltageOffset = OcPreMemConfig->SaVoltageOffset;
+    FspmUpd->FspmConfig.GtusMaxOcRatio = OcPreMemConfig->GtusMaxOcRatio;
+    FspmUpd->FspmConfig.GtusVoltageMode = (UINT8) OcPreMemConfig->GtusVoltageMode;
+    FspmUpd->FspmConfig.GtusVoltageOffset = OcPreMemConfig->GtusVoltageOffset;
+    FspmUpd->FspmConfig.GtusVoltageOverride = OcPreMemConfig->GtusVoltageOverride;
+    FspmUpd->FspmConfig.GtusExtraTurboVoltage = OcPreMemConfig->GtusExtraTurboVoltage;
+  }
+
+
+
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Performs FSP SA PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  EFI_STATUS                Status;
+  SI_POLICY_PPI             *SiPolicyPpi;
+  SA_MISC_PEI_CONFIG        *MiscPeiConfig;
+  GRAPHICS_PEI_CONFIG       *GtConfig;
+  PCIE_PEI_CONFIG           *PciePeiConfig;
+  GNA_CONFIG                *GnaConfig;
+  UINT8                     Index;
+  EFI_BOOT_MODE             BootMode;
+
+  MiscPeiConfig = NULL;
+  GtConfig      = NULL;
+  PciePeiConfig = NULL;
+  GnaConfig     = NULL;
+
+  //
+  // @todo This could be cleared up after FSP provides ExitBootServices NotifyPhase.
+  //
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Locate SiPolicyPpi
+  //
+  SiPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi(
+             &gSiPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **)&SiPolicyPpi
+             );
+  if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) {
+    MiscPeiConfig = NULL;
+    Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, (VOID *) &MiscPeiConfig);
+    ASSERT_EFI_ERROR (Status);
+
+    GtConfig = NULL;
+    Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+    ASSERT_EFI_ERROR (Status);
+
+    GnaConfig = NULL;
+    Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID *) &GnaConfig);
+    ASSERT_EFI_ERROR (Status);
+
+    PciePeiConfig = NULL;
+    Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, (VOID *) &PciePeiConfig);
+    ASSERT_EFI_ERROR (Status);
+
+  }
+
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n"));
+
+
+  if (MiscPeiConfig != NULL) {
+    FspsUpd->FspsConfig.Device4Enable = (UINT8) MiscPeiConfig->Device4Enable;
+    FspsUpd->FspsConfig.CridEnable = (UINT8) MiscPeiConfig->CridEnable;
+    FspsUpd->FspsTestConfig.ChapDeviceEnable = (UINT8) MiscPeiConfig->ChapDeviceEnable;
+    FspsUpd->FspsTestConfig.SkipPamLock = (UINT8) MiscPeiConfig->SkipPamLock;
+    FspsUpd->FspsTestConfig.EdramTestMode = (UINT8) MiscPeiConfig->EdramTestMode;
+  }
+
+  if (PciePeiConfig != NULL) {
+    FspsUpd->FspsConfig.DmiAspm = (UINT8) PciePeiConfig->DmiAspm;
+    FspsUpd->FspsTestConfig.DmiExtSync = (UINT8) PciePeiConfig->DmiExtSync;
+    FspsUpd->FspsTestConfig.DmiIot = (UINT8) PciePeiConfig->DmiIot;
+    for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
+      FspsUpd->FspsConfig.PegDeEmphasis[Index] = PciePeiConfig->PegDeEmphasis[Index];
+      FspsUpd->FspsConfig.PegSlotPowerLimitValue[Index] = PciePeiConfig->PegSlotPowerLimitValue[Index];
+      FspsUpd->FspsConfig.PegSlotPowerLimitScale[Index] = PciePeiConfig->PegSlotPowerLimitScale[Index];
+      FspsUpd->FspsConfig.PegPhysicalSlotNumber[Index] = PciePeiConfig->PegPhysicalSlotNumber[Index];
+      FspsUpd->FspsTestConfig.PegMaxPayload[Index] = PciePeiConfig->PegMaxPayload[Index];
+    }
+  }
+
+  if (GtConfig != NULL) {
+    FspsUpd->FspsConfig.PavpEnable = (UINT8) GtConfig->PavpEnable;
+    FspsUpd->FspsConfig.CdClock = (UINT8) GtConfig->CdClock;
+    FspsUpd->FspsTestConfig.RenderStandby = (UINT8) GtConfig->RenderStandby;
+    FspsUpd->FspsTestConfig.PmSupport = (UINT8) GtConfig->PmSupport;
+    FspsUpd->FspsTestConfig.CdynmaxClampEnable = (UINT8) GtConfig->CdynmaxClampEnable;
+    FspsUpd->FspsTestConfig.GtFreqMax = (UINT8) GtConfig->GtFreqMax;
+    FspsUpd->FspsTestConfig.DisableTurboGt = (UINT8) GtConfig->DisableTurboGt;
+    FspsUpd->FspsConfig.SkipS3CdClockInit = (UINT8)GtConfig->SkipS3CdClockInit;
+
+    //
+    // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled as default.
+    //
+    FspsUpd->FspsConfig.PeiGraphicsPeimInit = (UINT8) GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validation we still need to enable both Enable/Disable Cases
+
+    //
+    // Update UPD: VBT & LogoPtr
+    //
+    if (BootMode == BOOT_ON_S3_RESUME) {
+      FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) NULL;
+    } else {
+      FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) GtConfig->GraphicsConfigPtr;
+    }
+    DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
+
+    FspsUpd->FspsConfig.LogoPtr  = (UINT32) GtConfig->LogoPtr;
+    FspsUpd->FspsConfig.LogoSize = GtConfig->LogoSize;
+    DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+    DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+    FspsUpd->FspsConfig.BltBufferAddress  = (UINT32) GtConfig->BltBufferAddress;
+    FspsUpd->FspsConfig.BltBufferSize     = (UINT32) GtConfig->BltBufferSize;
+
+    //
+    // Update DDI/DDC configuration
+    //
+    FspsUpd->FspsConfig.DdiPortEdp = GtConfig->DdiConfiguration.DdiPortEdp;
+    FspsUpd->FspsConfig.DdiPortBHpd = GtConfig->DdiConfiguration.DdiPortBHpd;
+    FspsUpd->FspsConfig.DdiPortCHpd = GtConfig->DdiConfiguration.DdiPortCHpd;
+    FspsUpd->FspsConfig.DdiPortDHpd = GtConfig->DdiConfiguration.DdiPortDHpd;
+    FspsUpd->FspsConfig.DdiPortFHpd = GtConfig->DdiConfiguration.DdiPortFHpd;
+    FspsUpd->FspsConfig.DdiPortBDdc = GtConfig->DdiConfiguration.DdiPortBDdc;
+    FspsUpd->FspsConfig.DdiPortCDdc = GtConfig->DdiConfiguration.DdiPortCDdc;
+    FspsUpd->FspsConfig.DdiPortDDdc = GtConfig->DdiConfiguration.DdiPortDDdc;
+    FspsUpd->FspsConfig.DdiPortFDdc = GtConfig->DdiConfiguration.DdiPortFDdc;
+
+  }
+
+  if (GnaConfig != NULL) {
+    FspsUpd->FspsConfig.GnaEnable = (UINT8) GnaConfig->GnaEnable;
+#ifdef TESTMENU_FLAG
+#endif // TESTMENU_FLAG
+  }
+
+
+  return EFI_SUCCESS;
+}
+

+ 70 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c

@@ -0,0 +1,70 @@
+/** @file
+  Implementation of Fsp Security Policy Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+
+/**
+  Performs FSP Security PEI Policy initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                    Status;
+  SI_PREMEM_POLICY_PPI          *SiPreMemPolicyPpi;
+
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem Start\n"));
+
+  //
+  // Locate SiPreMemPolicyPpi
+  //
+  SiPreMemPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPreMemPolicyPpi
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem End\n"));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Performs FSP Security PEI Policy post memory initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSecurityPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+
+  return EFI_SUCCESS;
+}
+

+ 96 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c

@@ -0,0 +1,96 @@
+/** @file
+  Implementation of Fsp SI Policy Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  Performs FSP SI PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInitPreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                Status;
+  SI_PREMEM_POLICY_PPI      *SiPreMemPolicyPpi;
+
+  //
+  // Locate SiPreMemPolicyPpi
+  //
+  SiPreMemPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPreMemPolicyPpi
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Performs FSP SI PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  EFI_STATUS                   Status;
+  SI_POLICY_PPI                *SiPolicy;
+  SI_CONFIG                    *SiConfig;
+
+  //
+  // Locate SiPolicyPpi
+  //
+  SiPolicy = NULL;
+  Status = PeiServicesLocatePpi (
+             &gSiPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **) &SiPolicy
+             );
+  if (EFI_ERROR (Status)) {
+    return EFI_NOT_FOUND;
+  }
+
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &SiConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Update SiConfig policies
+  //
+  FspsUpd->FspsConfig.SiCsmFlag                = (UINT8)SiConfig->CsmFlag;
+  FspsUpd->FspsConfig.SiSsidTablePtr           = (UINT32)(UINTN)SiConfig->SsidTablePtr;
+  FspsUpd->FspsConfig.SiNumberOfSsidTableEntry = (UINT16)SiConfig->NumberOfSsidTableEntry;
+  FspsUpd->FspsConfig.TraceHubMemBase          =  SiConfig->TraceHubMemBase;
+
+  return EFI_SUCCESS;
+}
+
+
+

+ 100 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c

@@ -0,0 +1,100 @@
+/** @file
+  Implementation of Fsp Misc UPD Initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <PchAccess.h>
+
+#include "PeiMiscPolicyUpdate.h"
+
+/**
+  Performs FSP Misc UPD initialization.
+
+  @param[in,out]    FspmUpd                 Pointer to FSPM_UPD Data.
+
+  @retval           EFI_SUCCESS             FSP UPD Data is updated.
+  @retval           EFI_NOT_FOUND           An instance of gEfiPeiReadOnlyVariable2PpiGuid
+                                            could not be located.
+  @retval           EFI_OUT_OF_RESOURCES    Insufficent resources to allocate a memory buffer.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  EFI_STATUS                        Status;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *VariableServices;
+  UINTN                             VariableSize;
+  VOID                              *MemorySavedData;
+
+  Status = PeiServicesLocatePpi (
+             &gEfiPeiReadOnlyVariable2PpiGuid,
+             0,
+             NULL,
+             (VOID **) &VariableServices
+             );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  VariableSize = 0;
+  MemorySavedData = NULL;
+  Status = VariableServices->GetVariable (
+                               VariableServices,
+                               L"MemoryConfig",
+                               &gFspNonVolatileStorageHobGuid,
+                               NULL,
+                               &VariableSize,
+                               MemorySavedData
+                               );
+  if (Status == EFI_BUFFER_TOO_SMALL) {
+    MemorySavedData = AllocatePool (VariableSize);
+    if (MemorySavedData == NULL) {
+      ASSERT (MemorySavedData != NULL);
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));
+    Status = VariableServices->GetVariable (
+                                 VariableServices,
+                                 L"MemoryConfig",
+                                 &gFspNonVolatileStorageHobGuid,
+                                 NULL,
+                                 &VariableSize,
+                                 MemorySavedData
+                                 );
+    if (Status == EFI_SUCCESS) {
+      FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+    } else {
+      DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMemoryConfigVariableGuid, Status = %r\n", Status));
+      ASSERT_EFI_ERROR (Status);
+    }
+  }
+  FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+
+  return EFI_SUCCESS;
+}
+
+

+ 124 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c

@@ -0,0 +1,124 @@
+/** @file
+  Provide FSP wrapper platform related function.
+
+`  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/SiliconPolicyUpdateLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include "PeiMiscPolicyUpdate.h"
+
+/**
+  Performs FSP PCH PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+VOID
+InternalPrintVariableData (
+  IN UINT8   *Data8,
+  IN UINTN   DataSize
+  )
+{
+  UINTN      Index;
+
+  for (Index = 0; Index < DataSize; Index++) {
+    if (Index % 0x10 == 0) {
+      DEBUG ((DEBUG_INFO, "\n%08X:", Index));
+    }
+    DEBUG ((DEBUG_INFO, " %02X", *Data8++));
+  }
+  DEBUG ((DEBUG_INFO, "\n"));
+}
+
+/**
+  Performs silicon pre-mem policy update.
+
+  The meaning of Policy is defined by silicon code.
+  It could be the raw data, a handle, a PPI, etc.
+
+  The input Policy must be returned by SiliconPolicyDonePreMem().
+
+  1) In FSP path, the input Policy should be FspmUpd.
+  A platform may use this API to update the FSPM UPD policy initialized
+  by the silicon module or the default UPD data.
+  The output of FSPM UPD data from this API is the final UPD data.
+
+  2) In non-FSP path, the board may use additional way to get
+  the silicon policy data field based upon the input Policy.
+
+  @param[in, out] Policy       Pointer to policy.
+
+  @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+  IN OUT VOID    *FspmUpd
+  )
+{
+  FSPM_UPD              *FspmUpdDataPtr;
+
+  FspmUpdDataPtr = FspmUpd;
+
+  PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
+  InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD));
+
+  return FspmUpd;
+}
+
+/**
+  Performs silicon post-mem policy update.
+
+  The meaning of Policy is defined by silicon code.
+  It could be the raw data, a handle, a PPI, etc.
+
+  The input Policy must be returned by SiliconPolicyDonePostMem().
+
+  1) In FSP path, the input Policy should be FspsUpd.
+  A platform may use this API to update the FSPS UPD policy initialized
+  by the silicon module or the default UPD data.
+  The output of FSPS UPD data from this API is the final UPD data.
+
+  2) In non-FSP path, the board may use additional way to get
+  the silicon policy data field based upon the input Policy.
+
+  @param[in, out] Policy       Pointer to policy.
+
+  @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+  IN OUT VOID    *FspsUpd
+  )
+{
+  FSPS_UPD              *FspsUpdDataPtr;
+
+  FspsUpdDataPtr = FspsUpd;
+
+  PeiFspPchPolicyUpdate (FspsUpd);
+  InternalPrintVariableData ((VOID * )FspsUpdDataPtr, sizeof (FSPS_UPD));
+
+  return FspsUpd;
+}

+ 25 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h

@@ -0,0 +1,25 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_MISC_POLICY_UPDATE_H_
+#define _PEI_MISC_POLICY_UPDATE_H_
+
+#include <FspmUpd.h>
+
+/**
+  Performs FSP Misc UPD initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  );
+
+#endif

+ 60 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c

@@ -0,0 +1,60 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+#include <PcieDeviceOverrideTable.h>
+
+/**
+  Performs FSP PCH PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
+
+  AddPlatformVerbTables (
+    PchHdaCodecPlatformOnboard,
+    &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum),
+    &(FspsUpd->FspsConfig.PchHdaVerbTablePtr)
+    );
+
+DEBUG_CODE_BEGIN();
+if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
+    FspsUpd->FspsConfig.SerialIoUartMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) {
+    FspsUpd->FspsConfig.SerialIoUartMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoHidden;
+  }
+DEBUG_CODE_END();
+
+  return EFI_SUCCESS;
+}
+
+

+ 27 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h

@@ -0,0 +1,27 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/MmPciLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#endif
+

+ 39 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c

@@ -0,0 +1,39 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <PchHsioPtssTables.h>
+#include <Library/DebugLib.h>
+
+/**
+  Performs FSP PCH PEI Policy pre mem initialization.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  return EFI_SUCCESS;
+}
+
+

+ 85 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c

@@ -0,0 +1,85 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/PeiLib.h>
+
+/**
+  Performs FSP SA PEI Policy initialization.
+
+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+  IN OUT FSPS_UPD    *FspsUpd
+  )
+{
+  VOID                            *Buffer;
+  VOID                            *MemBuffer;
+  UINT32                          Size;
+
+  DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+    FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
+
+    Size   = 0;
+    Buffer = NULL;
+    PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
+    if (Buffer == NULL) {
+      DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
+    } else {
+      MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+      if ((MemBuffer != NULL) && (Buffer != NULL)) {
+        CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+        FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer;
+      } else {
+        DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+        FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
+      }
+    }
+    DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
+    DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+
+    Size   = 0;
+    Buffer = NULL;
+    PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
+    if (Buffer == NULL) {
+      DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+    } else {
+      MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+      if ((MemBuffer != NULL) && (Buffer != NULL)) {
+        CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+        FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
+        FspsUpd->FspsConfig.LogoSize = Size;
+      } else {
+        DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+        FspsUpd->FspsConfig.LogoPtr = 0;
+        FspsUpd->FspsConfig.LogoSize = 0;
+      }
+    }
+    DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+    DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+  return EFI_SUCCESS;
+}
+
+

+ 30 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h

@@ -0,0 +1,30 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <SaPolicyCommon.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <CpuAccess.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+extern EFI_GUID gTianoLogoGuid;
+
+#endif
+
+

+ 87 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c

@@ -0,0 +1,87 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+
+
+/**
+  Performs FSP SA PEI Policy initialization in pre-memory.
+
+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.
+
+  @retval          EFI_SUCCESS         FSP UPD Data is updated.
+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.
+  @retval          Other               FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+  IN OUT FSPM_UPD    *FspmUpd
+  )
+{
+  VOID                        *Buffer;
+
+  //
+  // If SpdAddressTable are not all 0, it means DIMM slots implemented and
+  // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPolicyInitPreMem.
+  //
+  // If SpdAddressTable all 0, this is memory down design and hardcoded SpdData
+  // should be applied to MemorySpdPtr*.
+  //
+  if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8 (PcdMrcSpdAddressTable1) == 0)
+      && (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8 (PcdMrcSpdAddressTable3) == 0)) {
+    DEBUG ((DEBUG_INFO, "Overriding SPD data for down memory.\n"));
+    CopyMem (
+      (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00,
+      (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
+      PcdGet16 (PcdMrcSpdDataSize)
+      );
+    CopyMem (
+      (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10,
+      (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
+      PcdGet16 (PcdMrcSpdDataSize)
+      );
+  }
+
+  DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
+  }
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
+    CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
+  }
+
+  DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
+  }
+  Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+  if (Buffer) {
+    CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
+  }
+  return EFI_SUCCESS;
+}
+
+

+ 140 - 0
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf

@@ -0,0 +1,140 @@
+## @file
+#  Provide FSP wrapper platform related function.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SiliconPolicyUpdateLibFsp
+  FILE_GUID                      = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+  PeiFspPolicyUpdateLib.c
+  PeiPchPolicyUpdatePreMem.c
+  PeiPchPolicyUpdate.c
+  PeiSaPolicyUpdatePreMem.c
+  PeiSaPolicyUpdate.c
+  PeiFspMiscUpdUpdateLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+#                              this module.
+#
+################################################################################
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses.IA32]
+  FspWrapperApiLib
+  OcWdtLib
+  PchResetLib
+  FspWrapperPlatformLib
+  BaseMemoryLib
+  CpuPlatformLib
+  DebugLib
+  HdaVerbTableLib
+  HobLib
+  IoLib
+  PcdLib
+  PostCodeLib
+  SmbusLib
+  ConfigBlockLib
+  PeiSaPolicyLib
+  PchGbeLib
+  PchInfoLib
+  PchHsioLib
+  PchPcieRpLib
+  MemoryAllocationLib
+  DebugPrintErrorLevelLib
+  SiPolicyLib
+  PchGbeLib
+  TimerLib
+  GpioLib
+  PeiLib
+
+[Pcd]
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
+
+
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress         ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable           ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber                ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi                      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit    ## CONSUMES
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
+
+  # SPD Address Table
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+[Guids]
+  gFspNonVolatileStorageHobGuid                 ## CONSUMES
+  gTianoLogoGuid                                ## CONSUMES
+  gEfiMemoryOverwriteControlDataGuid
+
+[Depex]
+  gEdkiiVTdInfoPpiGuid

+ 394 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/AcpiTimerLib.c

@@ -0,0 +1,394 @@
+/** @file
+  ACPI Timer implements one instance of Timer Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <IndustryStandard/Acpi.h>
+//
+// OVERRIDE: OverrideBegin
+//
+#include <Register/Cpuid.h>
+//
+// OVERRIDE: OverrideEnd
+//
+
+
+/**
+  Internal function to retrieves the 64-bit frequency in Hz.
+
+  Internal function to retrieves the 64-bit frequency in Hz.
+
+  @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+  VOID
+  );
+
+/**
+  The constructor function enables ACPI IO space.
+
+  If ACPI I/O space not enabled, this function will enable it.
+  It will always return RETURN_SUCCESS.
+
+  @retval EFI_SUCCESS   The constructor always returns RETURN_SUCCESS.
+
+**/
+RETURN_STATUS
+EFIAPI
+AcpiTimerLibConstructor (
+  VOID
+  )
+{
+  UINTN   Bus;
+  UINTN   Device;
+  UINTN   Function;
+  UINTN   EnableRegister;
+  UINT8   EnableMask;
+
+  //
+  // ASSERT for the invalid PCD values. They must be configured to the real value.
+  //
+  ASSERT (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) != 0xFFFF);
+  ASSERT (PcdGet16 (PcdAcpiIoPortBaseAddress)      != 0xFFFF);
+
+  //
+  // If the register offset to the BAR for the ACPI I/O Port Base Address is 0x0000, then
+  // no PCI register programming is required to enable access to the the ACPI registers
+  // specified by PcdAcpiIoPortBaseAddress
+  //
+  if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) == 0x0000) {
+    return RETURN_SUCCESS;
+  }
+
+  //
+  // ASSERT for the invalid PCD values. They must be configured to the real value.
+  //
+  ASSERT (PcdGet8  (PcdAcpiIoPciDeviceNumber)   != 0xFF);
+  ASSERT (PcdGet8  (PcdAcpiIoPciFunctionNumber) != 0xFF);
+  ASSERT (PcdGet16 (PcdAcpiIoPciEnableRegisterOffset) != 0xFFFF);
+
+  //
+  // Retrieve the PCD values for the PCI configuration space required to program the ACPI I/O Port Base Address
+  //
+  Bus            = PcdGet8  (PcdAcpiIoPciBusNumber);
+  Device         = PcdGet8  (PcdAcpiIoPciDeviceNumber);
+  Function       = PcdGet8  (PcdAcpiIoPciFunctionNumber);
+  EnableRegister = PcdGet16 (PcdAcpiIoPciEnableRegisterOffset);
+  EnableMask     = PcdGet8  (PcdAcpiIoBarEnableMask);
+
+  //
+  // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.
+  //
+  if ((PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister)) & EnableMask) != EnableMask) {
+    PciWrite16 (
+      PCI_LIB_ADDRESS (Bus, Device, Function, PcdGet16 (PcdAcpiIoPciBarRegisterOffset)),
+      PcdGet16 (PcdAcpiIoPortBaseAddress)
+      );
+    PciOr8 (
+      PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister),
+      EnableMask
+      );
+  }
+
+  return RETURN_SUCCESS;
+}
+
+/**
+  Internal function to retrieve the ACPI I/O Port Base Address.
+
+  Internal function to retrieve the ACPI I/O Port Base Address.
+
+  @return The 16-bit ACPI I/O Port Base Address.
+
+**/
+UINT16
+InternalAcpiGetAcpiTimerIoPort (
+  VOID
+  )
+{
+  UINT16  Port;
+
+  Port = PcdGet16 (PcdAcpiIoPortBaseAddress);
+
+  //
+  // If the register offset to the BAR for the ACPI I/O Port Base Address is not 0x0000, then
+  // read the PCI register for the ACPI BAR value in case the BAR has been programmed to a
+  // value other than PcdAcpiIoPortBaseAddress
+  //
+  if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) != 0x0000) {
+    Port = PciRead16 (PCI_LIB_ADDRESS (
+                        PcdGet8  (PcdAcpiIoPciBusNumber),
+                        PcdGet8  (PcdAcpiIoPciDeviceNumber),
+                        PcdGet8  (PcdAcpiIoPciFunctionNumber),
+                        PcdGet16 (PcdAcpiIoPciBarRegisterOffset)
+                        ));
+  }
+
+  return (Port & PcdGet16 (PcdAcpiIoPortBaseAddressMask)) + PcdGet16 (PcdAcpiPm1TmrOffset);
+}
+
+/**
+  Stalls the CPU for at least the given number of ticks.
+
+  Stalls the CPU for at least the given number of ticks. It's invoked by
+  MicroSecondDelay() and NanoSecondDelay().
+
+  @param  Delay     A period of time to delay in ticks.
+
+**/
+VOID
+InternalAcpiDelay (
+  IN UINT32  Delay
+  )
+{
+  UINT16   Port;
+  UINT32   Ticks;
+  UINT32   Times;
+
+  Port   = InternalAcpiGetAcpiTimerIoPort ();
+  Times  = Delay >> 22;
+  Delay &= BIT22 - 1;
+  do {
+    //
+    // The target timer count is calculated here
+    //
+    Ticks = IoBitFieldRead32 (Port, 0, 23) + Delay;
+    Delay = BIT22;
+    //
+    // Wait until time out
+    // Delay >= 2^23 could not be handled by this function
+    // Timer wrap-arounds are handled correctly by this function
+    //
+    while (((Ticks - IoBitFieldRead32 (Port, 0, 23)) & BIT23) == 0) {
+      CpuPause ();
+    }
+  } while (Times-- > 0);
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to delay.
+
+  @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+  IN UINTN  MicroSeconds
+  )
+{
+  InternalAcpiDelay (
+    (UINT32)DivU64x32 (
+              MultU64x32 (
+                MicroSeconds,
+                ACPI_TIMER_FREQUENCY
+                ),
+              1000000u
+              )
+    );
+  return MicroSeconds;
+}
+
+/**
+  Stalls the CPU for at least the given number of nanoseconds.
+
+  Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+  @param  NanoSeconds The minimum number of nanoseconds to delay.
+
+  @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+  IN UINTN  NanoSeconds
+  )
+{
+  InternalAcpiDelay (
+    (UINT32)DivU64x32 (
+              MultU64x32 (
+                NanoSeconds,
+                ACPI_TIMER_FREQUENCY
+                ),
+              1000000000u
+              )
+    );
+  return NanoSeconds;
+}
+
+/**
+  Retrieves the current value of a 64-bit free running performance counter.
+
+  Retrieves the current value of a 64-bit free running performance counter. The
+  counter can either count up by 1 or count down by 1. If the physical
+  performance counter counts by a larger increment, then the counter values
+  must be translated. The properties of the counter can be retrieved from
+  GetPerformanceCounterProperties().
+
+  @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+  VOID
+  )
+{
+  return AsmReadTsc ();
+}
+
+/**
+  Retrieves the 64-bit frequency in Hz and the range of performance counter
+  values.
+
+  If StartValue is not NULL, then the value that the performance counter starts
+  with immediately after is it rolls over is returned in StartValue. If
+  EndValue is not NULL, then the value that the performance counter end with
+  immediately before it rolls over is returned in EndValue. The 64-bit
+  frequency of the performance counter in Hz is always returned. If StartValue
+  is less than EndValue, then the performance counter counts up. If StartValue
+  is greater than EndValue, then the performance counter counts down. For
+  example, a 64-bit free running counter that counts up would have a StartValue
+  of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+  that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+  @param  StartValue  The value the performance counter starts with when it
+                      rolls over.
+  @param  EndValue    The value that the performance counter ends with before
+                      it rolls over.
+
+  @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+  OUT UINT64  *StartValue,  OPTIONAL
+  OUT UINT64  *EndValue     OPTIONAL
+  )
+{
+  if (StartValue != NULL) {
+    *StartValue = 0;
+  }
+
+  if (EndValue != NULL) {
+    *EndValue = 0xffffffffffffffffULL;
+  }
+  return InternalGetPerformanceCounterFrequency ();
+}
+
+/**
+  Converts elapsed ticks of performance counter to time in nanoseconds.
+
+  This function converts the elapsed ticks of running performance counter to
+  time value in unit of nanoseconds.
+
+  @param  Ticks     The number of elapsed ticks of running performance counter.
+
+  @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+  IN UINT64  Ticks
+  )
+{
+  UINT64  Frequency;
+  UINT64  NanoSeconds;
+  UINT64  Remainder;
+  INTN    Shift;
+  Frequency = GetPerformanceCounterProperties (NULL, NULL);
+
+  //
+  //          Ticks
+  // Time = --------- x 1,000,000,000
+  //        Frequency
+  //
+  NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);
+
+  //
+  // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
+  // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
+  // i.e. highest bit set in Remainder should <= 33.
+  //
+  Shift = MAX (0, HighBitSet64 (Remainder) - 33);
+  Remainder = RShiftU64 (Remainder, (UINTN) Shift);
+  Frequency = RShiftU64 (Frequency, (UINTN) Shift);
+  NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
+
+  return NanoSeconds;
+}
+
+//
+// OVERRIDE: OverrideBegin
+//
+/**
+  Calculate TSC frequency.
+
+  The TSC counting frequency is determined by using CPUID leaf 0x15 that is the preferred
+  method for Skylake and beyond.  Frequency in MHz = Core XTAL frequency * EBX/EAX.
+  In newer flavors of the CPU, core xtal frequency is returned in ECX (or 0 if not
+  supported).  If ECX is 0, 24MHz is assumed.
+  @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalCalculateTscFrequency (
+  VOID
+  )
+{
+  UINT64      TscFrequency;
+  UINT64      CoreXtalFrequency;
+  UINT32      RegEax;
+  UINT32      RegEbx;
+  UINT32      RegEcx;
+
+  //
+  // Use CPUID leaf 0x15.
+  // TSC frequency = (Core Xtal Frequency) * EBX/EAX.  EBX returns 0 if not
+  // supported. ECX, if non zero, provides Core Xtal Frequency in hertz
+  // (SDM Dec 2016).
+  //
+  AsmCpuid (CPUID_TIME_STAMP_COUNTER, &RegEax, &RegEbx, &RegEcx, NULL);
+  ASSERT (RegEbx != 0);
+
+  //
+  // If core xtal frequency (ECX) returns 0, it is safe to use 24MHz for post
+  // Skylake client CPU's.
+  //
+  if (RegEcx == 0) {
+    CoreXtalFrequency = 24000000ul;
+  } else {
+    CoreXtalFrequency = (UINT64)RegEcx;
+  }
+
+  //
+  // Calculate frequency.  For integer division, round up/down result
+  // correctly by adding denominator/2 to the numerator prior to division.
+  //
+  TscFrequency = DivU64x32 (MultU64x32 (CoreXtalFrequency, RegEbx) + (UINT64)(RegEax >> 1), RegEax);
+
+  return TscFrequency;
+}
+//
+// OVERRIDE: OverrideEnd
+//
+

+ 48 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c

@@ -0,0 +1,48 @@
+/** @file
+  ACPI Timer implements one instance of Timer Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+
+/**
+  Calculate TSC frequency.
+
+  The TSC counting frequency is determined by comparing how far it counts
+  during a 101.4 us period as determined by the ACPI timer.
+  The ACPI timer is used because it counts at a known frequency.
+  The TSC is sampled, followed by waiting 363 counts of the ACPI timer,
+  or 101.4 us. The TSC is then sampled again. The difference multiplied by
+  9861 is the TSC frequency. There will be a small error because of the
+  overhead of reading the ACPI timer. An attempt is made to determine and
+  compensate for this error.
+
+  @return The number of TSC counts per second.
+
+**/
+UINT64
+InternalCalculateTscFrequency (
+  VOID
+  );
+
+/**
+  Internal function to retrieves the 64-bit frequency in Hz.
+
+  Internal function to retrieves the 64-bit frequency in Hz.
+
+  @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+  VOID
+  )
+{
+  return InternalCalculateTscFrequency ();
+}
+

+ 54 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf

@@ -0,0 +1,54 @@
+## @file
+#  Base ACPI Timer Library
+#
+#  Provides basic timer support using the ACPI timer hardware.  The performance
+#  counter features are provided by the processors time stamp counter.
+#
+#  Note: The implementation uses the lower 24-bits of the ACPI timer and
+#  is compatible with both 24-bit and 32-bit ACPI timers.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = BaseAcpiTimerLib
+  FILE_GUID                      = 564DE85F-049E-4481-BF7A-CA04D2788CF9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = TimerLib|SEC PEI_CORE PEIM
+  CONSTRUCTOR                    = AcpiTimerLibConstructor
+  MODULE_UNI_FILE                = BaseAcpiTimerLib.uni
+
+[Sources]
+  AcpiTimerLib.c
+  BaseAcpiTimerLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  PcAtChipsetPkg/PcAtChipsetPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec      ## OVERRIDE
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  PciLib
+  IoLib
+  DebugLib
+
+[Pcd]
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber             ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber          ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber        ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset  ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask            ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset     ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress          ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset               ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask      ## CONSUMES
+

+ 15 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.uni

@@ -0,0 +1,15 @@
+/** @file
+  Base ACPI Timer Library
+  Provides basic timer support using the ACPI timer hardware.  The performance
+  counter features are provided by the processors time stamp counter.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#string STR_MODULE_ABSTRACT             #language en-US "ACPI Timer Library"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Provides basic timer support using the ACPI timer hardware."
+
+

+ 308 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c

@@ -0,0 +1,308 @@
+/** @file
+  Support for IO expander TCA6424.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioExpanderLib.h>
+#include <Library/I2cAccessLib.h>
+
+//
+// Addresses of registers inside expander
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mInputRegister[3]    = {0x0,0x1,0x2};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mOutputRegister[3]   = {0x4,0x5,0x6};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mConfigRegister[3]   = {0xC,0xD,0xE};
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8  mPolarityRegister[3] = {0x8,0x9,0xA};
+
+#define PCH_SERIAL_IO_I2C4                 4
+#define TCA6424_I2C_ADDRESS 0x22
+#define PINS_PER_REGISTER                  8
+#define GPIO_EXP_PIN_DIRECTION_OUT         1
+#define GPIO_EXP_PIN_DIRECTION_IN          0
+#define GPIO_EXP_PIN_POLARITY_NORMAL       0
+#define GPIO_EXP_PIN_POLARITY_INVERTED     1
+#define GPIO_EXP_SET_OUTPUT                0
+#define GPIO_EXP_SET_DIR                   1
+#define GPIO_EXP_GET_INPUT                 2
+#define GPIO_EXP_SET_POLARITY              3
+#define AUTO_INCREMENT 0x80
+
+/**
+  Returns the Controller on which GPIO expander is present.
+
+  This function returns the Controller value
+
+  @param[out] Controller              Pointer to a Controller value on
+                                      which I2C expander is configured.
+
+  @retval     EFI_SUCCESS              non.
+**/
+EFI_STATUS
+GpioExpGetController (
+  OUT UINT8 *Controller
+  )
+{
+  *Controller = PCH_SERIAL_IO_I2C4;
+  return EFI_SUCCESS;
+}
+
+/**
+  Returns the data from register value giving in the input.
+
+  This function is to get the data from the Expander
+  Registers by following the I2C Protocol communication
+
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+
+  @retval     UINT8      Value returned from the register
+**/
+UINT8
+GpioExpGetRegister (
+  IN UINTN Bar0,
+  IN UINT8 Address,
+  IN UINT8 Register
+  )
+{
+  UINT8 WriBuf[1];
+  UINT8 ReBuf[1] = {0};
+
+  WriBuf[0] = Register;
+  I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf, WAIT_1_SECOND);
+
+  return ReBuf[0];
+}
+/**
+  Set the input register to a give value mentioned in the function.
+
+  This function is to Programm the data value to the Expander
+  Register by following the I2C Protocol communication.
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+  @param[in]  Value      Value to set in the mentioned the register
+**/
+VOID
+GpioExpSetRegister (
+  IN UINTN Bar0,
+  IN UINT8 Address,
+  IN UINT8 Register,
+  IN UINT8 Value
+  )
+{
+  UINT8 WriBuf[2];
+
+  WriBuf[0] = Register;
+  WriBuf[1] = Value;
+
+  I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL, WAIT_1_SECOND);
+}
+/**
+  Set the input register to a give value mentioned in the function.
+
+  This function is to update the status of the Gpio Expander
+  pin based on the input Operation value of the caller.This
+  function calculates the exact address of the register with
+  the help of the Register Bank
+
+  @param[in]  Controller  SerialIo Controller value
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+  @param[in]  Operation   Type of operation (Setoutput/Setdirection
+                          /Getinput/Setpolarity)
+  @retval     UINT8       Final Value returned from the register
+**/
+UINT8
+GpioExpDecodeRegAccess (
+  IN UINT8 Controller,
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value,
+  IN UINT8 Operation
+  )
+{
+  UINT8* RegisterBank;
+  UINT8 OldValue;
+  UINT8 NewValue;
+  UINT8 RegisterAddress;
+  UINT8 PinNumber;
+  UINT8 ReturnValue = 0;
+
+  DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", Controller, Expander, Pin, Value, Operation));
+  ASSERT(Controller<6);
+  ASSERT(Expander<2);
+  ASSERT(Pin<24);
+  ASSERT(Value<2);
+  ASSERT(Operation<4);
+  //
+  // Find the register Address value based on the OPeration
+  //
+  switch(Operation) {
+    case GPIO_EXP_SET_OUTPUT:
+      RegisterBank = mOutputRegister;
+      break;
+    case GPIO_EXP_SET_DIR:
+      RegisterBank = mConfigRegister;
+      break;
+    case GPIO_EXP_GET_INPUT:
+      RegisterBank = mInputRegister;
+      break;
+    case GPIO_EXP_SET_POLARITY:
+      RegisterBank = mPolarityRegister;
+      break;
+    default:
+      ASSERT(FALSE);
+      return 0;
+    }
+  //
+  // Each bit of register represents each Pin
+  // calaulate the register address and Pinnumber(offset with in register)
+  //
+  if (Pin >= 24) {
+    //
+    // Avoid out-of-bound usage of RegisterBank
+    //
+    return 0;
+  }
+
+  RegisterAddress = RegisterBank[(Pin/PINS_PER_REGISTER)];
+  PinNumber = Pin%PINS_PER_REGISTER;
+
+  OldValue = GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander, RegisterAddress);
+  //
+  // If it to get the data ,just returned otherwise mark the input value and write the register
+  //
+  if (Operation == GPIO_EXP_GET_INPUT) {
+    ReturnValue = 0x1 & (OldValue>>PinNumber);
+  } else {
+    NewValue = OldValue;
+    NewValue &= ~(BIT0<<PinNumber);
+    NewValue |= (Value<<PinNumber);
+    if(NewValue!=OldValue) {
+      GpioExpSetRegister(FindSerialIoBar(Controller, 0), Expander, RegisterAddress, NewValue);
+    }
+  }
+  return ReturnValue;
+}
+/**
+  Set the Output value for the given Expander Gpio pin.
+
+  This function is to Set the Output value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetOutput (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  )
+{
+  UINT8 Controller;
+  if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+    GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_OUTPUT);
+  }
+}
+/**
+  Set the Direction value for the given Expander Gpio pin.
+
+  This function is to Set the direction value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+**/
+VOID
+GpioExpSetDirection (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  )
+{
+
+  UINT8 Controller;
+  if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+    GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_DIR);
+  }
+}
+
+
+/**
+  Get the input value for the given Expander Gpio pin.
+
+  This function is to get the input value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+
+  @retval     UINT8       Final Value returned from the register
+**/
+UINT8
+GpioExpGetInput (
+  IN UINT8 Expander,
+  IN UINT8 Pin
+  )
+{
+  UINT8 Controller;
+  if(!EFI_ERROR(GpioExpGetController(&Controller))) {
+    return GpioExpDecodeRegAccess(Controller,Expander,Pin,0,GPIO_EXP_GET_INPUT);
+  }
+  return 0;
+}
+
+/**
+  Configures all registers of a single IO Expander in one go.
+
+  @param[in]  Expander    Expander number (0/1)
+  @param[in]  Direction   Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
+  @param[in]  Polarity    Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
+  @param[in]  Output      Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
+
+**/
+VOID
+GpioExpBulkConfig (
+  IN UINT8  Expander,
+  IN UINT32 Direction,
+  IN UINT32 Polarity,
+  IN UINT32 Output
+  )
+{
+  UINT8 WriteBuf[4];
+  UINT8 Controller;
+
+  GpioExpGetController(&Controller);
+
+  WriteBuf[0] = mOutputRegister[0] + AUTO_INCREMENT;
+  WriteBuf[1] = Output & 0xFF;
+  WriteBuf[2] = (Output>>8) & 0xFF;
+  WriteBuf[3] = (Output>>16) & 0xFF;
+  I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+  WriteBuf[0] = mPolarityRegister[0] + AUTO_INCREMENT;
+  WriteBuf[1] = Polarity & 0xFF;
+  WriteBuf[2] = (Polarity>>8) & 0xFF;
+  WriteBuf[3] = (Polarity>>16) & 0xFF;
+  I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+  WriteBuf[0] = mConfigRegister[0] + AUTO_INCREMENT;
+  WriteBuf[1] = Direction & 0xFF;
+  WriteBuf[2] = (Direction>>8) & 0xFF;
+  WriteBuf[3] = (Direction>>16) & 0xFF;
+  I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND);
+
+}
+
+

+ 36 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf

@@ -0,0 +1,36 @@
+## @file
+# Library producing Gpio Expander functionality.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = BaseGpioExpanderLib
+  FILE_GUID                      = D10AE2A4-782E-427E-92FB-BB74505ED329
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = GpioExpanderLib
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  DebugLib
+  TimerLib
+  PchSerialIoLib
+  I2cAccessLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  BaseGpioExpanderLib.c
+

+ 2053 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c

@@ -0,0 +1,2053 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Ppi/SiPolicy.h>
+
+HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio = HDAUDIO_VERB_TABLE_INIT (
+  //
+  //  VerbTable: CFL Display Audio Codec
+  //  Revision ID = 0xFF
+  //  Codec Vendor: 0x8086280B
+  //
+  0x8086, 0x280B,
+  0xFF, 0xFF,
+  //
+  // Display Audio Verb Table
+  //
+  // For GEN9, the Vendor Node ID is 08h
+  // Port to be exposed to the inbox driver in the vanilla mode: PORT C - BIT[7:6] = 01b
+  0x00878140,
+  // Pin Widget 5 - PORT B - Configuration Default: 0x18560010
+  0x00571C10,
+  0x00571D00,
+  0x00571E56,
+  0x00571F18,
+  // Pin Widget 6 - PORT C - Configuration Default: 0x18560020
+  0x00671C20,
+  0x00671D00,
+  0x00671E56,
+  0x00671F18,
+  // Pin Widget 7 - PORT D - Configuration Default: 0x18560030
+  0x00771C30,
+  0x00771D00,
+  0x00771E56,
+  0x00771F18,
+  // Disable the third converter and third Pin (NID 08h)
+  0x00878140
+);
+
+//
+//codecs verb tables
+//
+HDAUDIO_VERB_TABLE HdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
+  //
+  //  VerbTable: (Realtek ALC700)
+  //  Revision ID = 0xff
+  //  Codec Verb Table
+  //  Codec Address: CAd value (0/1/2)
+  //  Codec Vendor: 0x10EC0700
+  //
+  0x10EC, 0x0700,
+  0xFF, 0xFF,
+  //===================================================================================================
+  //
+  //                               Realtek Semiconductor Corp.
+  //
+  //===================================================================================================
+
+  //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+  //Realtek HD Audio Codec : ALC700
+  //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+  //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+  //The number of verb command block : 17
+
+  //    NID 0x12 : 0x411111F0
+  //    NID 0x13 : 0x40000000
+  //    NID 0x14 : 0x411111F0
+  //    NID 0x15 : 0x411111F0
+  //    NID 0x16 : 0x411111F0
+  //    NID 0x17 : 0x90170110
+  //    NID 0x18 : 0x411111F0
+  //    NID 0x19 : 0x04A11030
+  //    NID 0x1A : 0x411111F0
+  //    NID 0x1B : 0x411111F0
+  //    NID 0x1D : 0x40622005
+  //    NID 0x1E : 0x411111F0
+  //    NID 0x1F : 0x411111F0
+  //    NID 0x21 : 0x04211020
+  //    NID 0x29 : 0x411111F0
+
+  //===== HDA Codec Subsystem ID Verb-table =====
+  //HDA Codec Subsystem ID  : 0x10EC10F2
+  0x001720F2,
+  0x00172110,
+  0x001722EC,
+  0x00172310,
+
+  //===== Pin Widget Verb-table =====
+  //Widget node 0x01 :
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  //Pin widget 0x12 - DMIC
+  0x01271C00,
+  0x01271D00,
+  0x01271E00,
+  0x01271F40,
+  //Pin widget 0x13 - DMIC
+  0x01371C00,
+  0x01371D00,
+  0x01371E00,
+  0x01371F40,
+  //Pin widget 0x14 - FRONT (Port-D)
+  0x01471CF0,
+  0x01471D11,
+  0x01471E11,
+  0x01471F41,
+  //Pin widget 0x15 - I2S-OUT
+  0x01571CF0,
+  0x01571D11,
+  0x01571E11,
+  0x01571F41,
+  //Pin widget 0x16 - LINE3 (Port-B)
+  0x01671CF0,
+  0x01671D11,
+  0x01671E11,
+  0x01671F41,
+  //Pin widget 0x17 - I2S-OUT
+  0x01771C10,
+  0x01771D01,
+  0x01771E17,
+  0x01771F90,
+  //Pin widget 0x18 - I2S-IN
+  0x01871CF0,
+  0x01871D11,
+  0x01871E11,
+  0x01871F41,
+  //Pin widget 0x19 - MIC2 (Port-F)
+  0x01971C30,
+  0x01971D10,
+  0x01971EA1,
+  0x01971F04,
+  //Pin widget 0x1A - LINE1 (Port-C)
+  0x01A71CF0,
+  0x01A71D11,
+  0x01A71E11,
+  0x01A71F41,
+  //Pin widget 0x1B - LINE2 (Port-E)
+  0x01B71CF0,
+  0x01B71D11,
+  0x01B71E11,
+  0x01B71F41,
+  //Pin widget 0x1D - PC-BEEP
+  0x01D71C05,
+  0x01D71D20,
+  0x01D71E62,
+  0x01D71F40,
+  //Pin widget 0x1E - S/PDIF-OUT
+  0x01E71CF0,
+  0x01E71D11,
+  0x01E71E11,
+  0x01E71F41,
+  //Pin widget 0x1F - S/PDIF-IN
+  0x01F71CF0,
+  0x01F71D11,
+  0x01F71E11,
+  0x01F71F41,
+  //Pin widget 0x21 - HP-OUT (Port-I)
+  0x02171C20,
+  0x02171D10,
+  0x02171E21,
+  0x02171F04,
+  //Pin widget 0x29 - I2S-IN
+  0x02971CF0,
+  0x02971D11,
+  0x02971E11,
+  0x02971F41,
+  //Widget node 0x20 :
+  0x02050045,
+  0x02045289,
+  0x0205004A,
+  0x0204201B,
+  //Widget node 0x20 - 1 :
+  0x05850000,
+  0x05843888,
+  0x0205006F,
+  0x02042C0B,
+
+
+  //Widget node 0X20 for ALC1305   20160603 update
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040000,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040004,
+  0x02050028,
+  0x02040600,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FFD0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040080,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040880,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003A,
+  0x02050028,
+  0x02040DFE,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x0204005D,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x02040442,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040005,
+  0x02050028,
+  0x02040880,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040006,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040008,
+  0x02050028,
+  0x0204B000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204002E,
+  0x02050028,
+  0x02040800,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400C3,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x0204D4A0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400CC,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x0204400A,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400C1,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x02040320,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040039,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003B,
+  0x02050028,
+  0x0204FFFF,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FC20,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003A,
+  0x02050028,
+  0x02041DFE,
+  0x02050029,
+  0x0204B024,
+  //
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C0,
+  0x02050028,
+  0x020401FA,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C1,
+  0x02050028,
+  0x0204DE23,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C2,
+  0x02050028,
+  0x02041C00,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C3,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C4,
+  0x02050028,
+  0x02040200,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C5,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C6,
+  0x02050028,
+  0x020403F5,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C7,
+  0x02050028,
+  0x0204AF1B,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C8,
+  0x02050028,
+  0x02041E0A,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C9,
+  0x02050028,
+  0x0204368E,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CA,
+  0x02050028,
+  0x020401FA,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CB,
+  0x02050028,
+  0x0204DE23,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CC,
+  0x02050028,
+  0x02041C00,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CD,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CE,
+  0x02050028,
+  0x02040200,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CF,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D0,
+  0x02050028,
+  0x020403F5,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D1,
+  0x02050028,
+  0x0204AF1B,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D2,
+  0x02050028,
+  0x02041E0A,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D3,
+  0x02050028,
+  0x0204368E,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040040,
+  0x02050028,
+  0x0204800F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040062,
+  0x02050028,
+  0x02048000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040063,
+  0x02050028,
+  0x02044848,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040064,
+  0x02050028,
+  0x02040800,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040065,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040066,
+  0x02050028,
+  0x02044004,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040067,
+  0x02050028,
+  0x02040802,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040068,
+  0x02050028,
+  0x0204890F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040069,
+  0x02050028,
+  0x0204E021,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040070,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040071,
+  0x02050000,
+  0x02043330,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040072,
+  0x02050000,
+  0x02043333,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040073,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040074,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040075,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040076,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040050,
+  0x02050028,
+  0x020402EC,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040051,
+  0x02050028,
+  0x02044909,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040052,
+  0x02050028,
+  0x020440B0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040046,
+  0x02050028,
+  0x0204C22E,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040047,
+  0x02050028,
+  0x02040C00,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040048,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040049,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204004A,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204004B,
+  0x02050028,
+  0x02041C00,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x02040090,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x0204721F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204009E,
+  0x02050028,
+  0x02040001,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040004,
+  0x02050028,
+  0x02040500,
+  0x02050029,
+  0x0204B024
+); // HdaVerbTableAlc700
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc701 = HDAUDIO_VERB_TABLE_INIT (
+  //
+  //  VerbTable: (Realtek ALC701)
+  //  Revision ID = 0xff
+  //  Codec Verb Table
+  //  Codec Address: CAd value (0/1/2)
+  //  Codec Vendor: 0x10EC0701
+  //
+  0x10EC, 0x0701,
+  0xFF, 0xFF,
+  //===================================================================================================
+  //
+  //                               Realtek Semiconductor Corp.
+  //
+  //===================================================================================================
+
+  //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+  //Realtek HD Audio Codec : ALC701
+  //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+  //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124
+  //The number of verb command block : 17
+
+  //    NID 0x12 : 0x411111F0
+  //    NID 0x13 : 0x40000000
+  //    NID 0x14 : 0x411111F0
+  //    NID 0x15 : 0x411111F0
+  //    NID 0x16 : 0x411111F0
+  //    NID 0x17 : 0x90170110
+  //    NID 0x18 : 0x411111F0
+  //    NID 0x19 : 0x04A11030
+  //    NID 0x1A : 0x411111F0
+  //    NID 0x1B : 0x411111F0
+  //    NID 0x1D : 0x40610041
+  //    NID 0x1E : 0x411111F0
+  //    NID 0x1F : 0x411111F0
+  //    NID 0x21 : 0x04211020
+  //    NID 0x29 : 0x411111F0
+
+
+  //===== HDA Codec Subsystem ID Verb-table =====
+  //HDA Codec Subsystem ID  : 0x10EC1124
+  0x00172024,
+  0x00172111,
+  0x001722EC,
+  0x00172310,
+  //===== Pin Widget Verb-table =====
+  //Widget node 0x01 :
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  //Pin widget 0x12 - DMIC
+  0x01271C00,
+  0x01271D00,
+  0x01271E00,
+  0x01271F40,
+  //Pin widget 0x13 - DMIC
+  0x01371C00,
+  0x01371D00,
+  0x01371E00,
+  0x01371F40,
+  //Pin widget 0x14 - FRONT (Port-D)
+  0x01471CF0,
+  0x01471D11,
+  0x01471E11,
+  0x01471F41,
+  //Pin widget 0x15 - I2S-OUT
+  0x01571CF0,
+  0x01571D11,
+  0x01571E11,
+  0x01571F41,
+  //Pin widget 0x16 - LINE3 (Port-B)
+  0x01671CF0,
+  0x01671D11,
+  0x01671E11,
+  0x01671F41,
+  //Pin widget 0x17 - I2S-OUT
+  0x01771C10,
+  0x01771D01,
+  0x01771E17,
+  0x01771F90,
+  //Pin widget 0x18 - I2S-IN
+  0x01871CF0,
+  0x01871D11,
+  0x01871E11,
+  0x01871F41,
+  //Pin widget 0x19 - MIC2 (Port-F)
+  0x01971C30,
+  0x01971D10,
+  0x01971EA1,
+  0x01971F04,
+  //Pin widget 0x1A - LINE1 (Port-C)
+  0x01A71CF0,
+  0x01A71D11,
+  0x01A71E11,
+  0x01A71F41,
+  //Pin widget 0x1B - LINE2 (Port-E)
+  0x01B71CF0,
+  0x01B71D11,
+  0x01B71E11,
+  0x01B71F41,
+  //Pin widget 0x1D - PC-BEEP
+  0x01D71C41,
+  0x01D71D00,
+  0x01D71E61,
+  0x01D71F40,
+  //Pin widget 0x1E - S/PDIF-OUT
+  0x01E71CF0,
+  0x01E71D11,
+  0x01E71E11,
+  0x01E71F41,
+  //Pin widget 0x1F - S/PDIF-IN
+  0x01F71CF0,
+  0x01F71D11,
+  0x01F71E11,
+  0x01F71F41,
+  //Pin widget 0x21 - HP-OUT (Port-I)
+  0x02171C20,
+  0x02171D10,
+  0x02171E21,
+  0x02171F04,
+  //Pin widget 0x29 - I2S-IN
+  0x02971CF0,
+  0x02971D11,
+  0x02971E11,
+  0x02971F41,
+  //Widget node 0x20 :
+  0x02050045,
+  0x02045289,
+  0x0205004A,
+  0x0204201B,
+  //Widget node 0x20 - 1 :
+  0x05850000,
+  0x05843888,
+  0x0205006F,
+  0x02042C0B
+); // HdaVerbTableAlc701
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc274 = HDAUDIO_VERB_TABLE_INIT (
+  //
+  //  VerbTable: (Realtek ALC274)
+  //  Revision ID = 0xff
+  //  Codec Verb Table
+  //  Codec Address: CAd value (0/1/2)
+  //  Codec Vendor: 0x10EC0274
+  //
+  0x10EC, 0x0274,
+  0xFF, 0xFF,
+  //===================================================================================================
+  //
+  //                               Realtek Semiconductor Corp.
+  //
+  //===================================================================================================
+
+  //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+  //Realtek HD Audio Codec : ALC274
+  //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+  //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6
+  //The number of verb command block : 16
+
+  //    NID 0x12 : 0x40000000
+  //    NID 0x13 : 0x411111F0
+  //    NID 0x14 : 0x411111F0
+  //    NID 0x15 : 0x411111F0
+  //    NID 0x16 : 0x411111F0
+  //    NID 0x17 : 0x411111F0
+  //    NID 0x18 : 0x411111F0
+  //    NID 0x19 : 0x04A11020
+  //    NID 0x1A : 0x411111F0
+  //    NID 0x1B : 0x411111F0
+  //    NID 0x1D : 0x40451B05
+  //    NID 0x1E : 0x411111F0
+  //    NID 0x1F : 0x411111F0
+  //    NID 0x21 : 0x04211010
+
+
+  //===== HDA Codec Subsystem ID Verb-table =====
+  //,DA Codec Subsystem ID  : 0x10EC10F6
+  0x001720F6,
+  0x00172110,
+  0x001722EC,
+  0x00172310,
+
+  //===== Pin Widget Verb-table =====
+  //Widget node 0x01 :
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  //Pin widget 0x12 - DMIC
+  0x01271C00,
+  0x01271D00,
+  0x01271E00,
+  0x01271F40,
+  //Pin widget 0x13 - DMIC
+  0x01371CF0,
+  0x01371D11,
+  0x01371E11,
+  0x01371F41,
+  //Pin widget 0x14 - NPC
+  0x01471CF0,
+  0x01471D11,
+  0x01471E11,
+  0x01471F41,
+  //Pin widget 0x15 - I2S_OUT2
+  0x01571CF0,
+  0x01571D11,
+  0x01571E11,
+  0x01571F41,
+  //Pin widget 0x16 - LINE3 (Port-B)
+  0x01671CF0,
+  0x01671D11,
+  0x01671E11,
+  0x01671F41,
+  //Pin widget 0x17 - I2S_OUT1
+  0x01771CF0,
+  0x01771D11,
+  0x01771E11,
+  0x01771F41,
+  //Pin widget 0x18 - I2S_IN
+  0x01871CF0,
+  0x01871D11,
+  0x01871E11,
+  0x01871F41,
+  //Pin widget 0x19 - MIC2 (Port-F)
+  0x01971C20,
+  0x01971D10,
+  0x01971EA1,
+  0x01971F04,
+  //Pin widget 0x1A - LINE1 (Port-C)
+  0x01A71CF0,
+  0x01A71D11,
+  0x01A71E11,
+  0x01A71F41,
+  //Pin widget 0x1B - LINE2 (Port-E)
+  0x01B71CF0,
+  0x01B71D11,
+  0x01B71E11,
+  0x01B71F41,
+  //Pin widget 0x1D - PC-BEEP
+  0x01D71C05,
+  0x01D71D1B,
+  0x01D71E45,
+  0x01D71F40,
+  //Pin widget 0x1E - S/PDIF-OUT
+  0x01E71CF0,
+  0x01E71D11,
+  0x01E71E11,
+  0x01E71F41,
+  //Pin widget 0x1F - S/PDIF-IN
+  0x01F71CF0,
+  0x01F71D11,
+  0x01F71E11,
+  0x01F71F41,
+  //Pin widget 0x21 - HP-OUT (Port-I)
+  0x02171C10,
+  0x02171D10,
+  0x02171E21,
+  0x02171F04,
+  //Widget node 0x20 :
+  0x02050045,
+  0x02045289,
+  0x0205006F,
+  0x02042C0B,
+  //Widget node 0x20 - 1 :
+  0x02050035,
+  0x02048968,
+  0x05B50001,
+  0x05B48540,
+  //Widget node 0x20 - 2 :
+  0x05850000,
+  0x05843888,
+  0x05850000,
+  0x05843888,
+  //Widget node 0x20 - 3 :
+  0x0205004A,
+  0x0204201B,
+  0x0205004A,
+  0x0204201B
+); //HdaVerbTableAlc274
+
+//
+// WHL codecs verb tables
+//
+HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
+  //
+  //  VerbTable: (Realtek ALC700) WHL RVP
+  //  Revision ID = 0xff
+  //  Codec Verb Table for WHL PCH boards
+  //  Codec Address: CAd value (0/1/2)
+  //  Codec Vendor: 0x10EC0700
+  //
+  0x10EC, 0x0700,
+  0xFF, 0xFF,
+  //===================================================================================================
+  //
+  //                               Realtek Semiconductor Corp.
+  //
+  //===================================================================================================
+
+  //Realtek High Definition Audio Configuration - Version : 5.0.3.1
+  //Realtek HD Audio Codec : ALC700
+  //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+  //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+  //The number of verb command block : 17
+
+  //    NID 0x12 : 0x411111F0
+  //    NID 0x13 : 0x40000000
+  //    NID 0x14 : 0x411111F0
+  //    NID 0x15 : 0x411111F0
+  //    NID 0x16 : 0x411111F0
+  //    NID 0x17 : 0x90170110
+  //    NID 0x18 : 0x411111F0
+  //    NID 0x19 : 0x02A19040
+  //    NID 0x1A : 0x411111F0
+  //    NID 0x1B : 0x411111F0
+  //    NID 0x1D : 0x40638029
+  //    NID 0x1E : 0x411111F0
+  //    NID 0x1F : 0x411111F0
+  //    NID 0x21 : 0x02211020
+  //    NID 0x29 : 0x411111F0
+
+  //===== HDA Codec Subsystem ID Verb-table =====
+  //HDA Codec Subsystem ID  : 0x10EC10F2
+  0x001720F2,
+  0x00172110,
+  0x001722EC,
+  0x00172310,
+
+  //===== Pin Widget Verb-table =====
+  //Widget node 0x01 :
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  0x0017FF00,
+  //Pin widget 0x12 - DMIC
+  0x01271CF0,
+  0x01271D11,
+  0x01271E11,
+  0x01271F41,
+  //Pin widget 0x13 - DMIC
+  0x01371C00,
+  0x01371D00,
+  0x01371E00,
+  0x01371F40,
+  //Pin widget 0x14 - FRONT (Port-D)
+  0x01471CF0,
+  0x01471D11,
+  0x01471E11,
+  0x01471F41,
+  //Pin widget 0x15 - I2S-OUT
+  0x01571CF0,
+  0x01571D11,
+  0x01571E11,
+  0x01571F41,
+  //Pin widget 0x16 - LINE3 (Port-B)
+  0x01671CF0,
+  0x01671D11,
+  0x01671E11,
+  0x01671F41,
+  //Pin widget 0x17 - I2S-OUT
+  0x01771C10,
+  0x01771D01,
+  0x01771E17,
+  0x01771F90,
+  //Pin widget 0x18 - I2S-IN
+  0x01871CF0,
+  0x01871D11,
+  0x01871E11,
+  0x01871F41,
+  //Pin widget 0x19 - MIC2 (Port-F)
+  0x01971C40,
+  0x01971D90,
+  0x01971EA1,
+  0x01971F02,
+  //Pin widget 0x1A - LINE1 (Port-C)
+  0x01A71CF0,
+  0x01A71D11,
+  0x01A71E11,
+  0x01A71F41,
+  //Pin widget 0x1B - LINE2 (Port-E)
+  0x01B71CF0,
+  0x01B71D11,
+  0x01B71E11,
+  0x01B71F41,
+  //Pin widget 0x1D - PC-BEEP
+  0x01D71C29,
+  0x01D71D80,
+  0x01D71E63,
+  0x01D71F40,
+  //Pin widget 0x1E - S/PDIF-OUT
+  0x01E71CF0,
+  0x01E71D11,
+  0x01E71E11,
+  0x01E71F41,
+  //Pin widget 0x1F - S/PDIF-IN
+  0x01F71CF0,
+  0x01F71D11,
+  0x01F71E11,
+  0x01F71F41,
+  //Pin widget 0x21 - HP-OUT (Port-I)
+  0x02171C20,
+  0x02171D10,
+  0x02171E21,
+  0x02171F02,
+  //Pin widget 0x29 - I2S-IN
+  0x02971CF0,
+  0x02971D11,
+  0x02971E11,
+  0x02971F41,
+  //Widget node 0x20 - 0  FAKE JD unplug
+  0x02050008,
+  0x0204A80F,
+  0x02050008,
+  0x0204A80F,
+
+  //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700  bypass DAC02 DRE(NID5B bit14)
+  0x05B50010,
+  0x05B45C1D,
+  0x0205006F,
+  0x02040F8B,   //Zeek, 0F8Bh
+
+  //Widget node 0x20 -2:
+  0x02050045,
+  0x02045089,
+  0x0205004A,
+  0x0204201B,
+
+  //Widget node 0x20 - 3   From JD detect
+  0x02050008,
+  0x0204A807,
+  0x02050008,
+  0x0204A807,
+
+  //Widget node 0x20 - 4  Pull high ALC700 GPIO5 for AMP1305 PD pin and enable I2S BCLK first
+  0x02050090,
+  0x02040424,
+  0x00171620,
+  0x00171720,
+
+  0x00171520,
+  0x01770740,
+  0x01770740,
+  0x01770740,
+
+  //Widget node 0x20 for ALC1305   20181105 update   2W/4ohm to remove ALC1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040000,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400CF,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x02045548,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003F,
+  0x02050028,
+  0x02041000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040004,
+  0x02050028,
+  0x02040600,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FFD0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040080,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040880,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003A,
+  0x02050028,
+  0x02040DFE,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x0204005D,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x02040442,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040005,
+  0x02050028,
+  0x02040880,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040006,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040008,
+  0x02050028,
+  0x0204B000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204002E,
+  0x02050028,
+  0x02040800,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400C3,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x0204D4A0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400CC,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x0204400A,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x020400C1,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x02040320,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040039,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003B,
+  0x02050028,
+  0x0204FFFF,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FC20,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x02040006,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x020400C0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FCA0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FCE0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FCF0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040080,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040880,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040880,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FCE0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FCA0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003C,
+  0x02050028,
+  0x0204FC20,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x02040006,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040080,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C0,
+  0x02050028,
+  0x020401F0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C1,
+  0x02050028,
+  0x0204C1C7,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C2,
+  0x02050028,
+  0x02041C00,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C3,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C4,
+  0x02050028,
+  0x02040200,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C5,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C6,
+  0x02050028,
+  0x020403E1,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C7,
+  0x02050028,
+  0x02040F5A,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C8,
+  0x02050028,
+  0x02041E1E,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400C9,
+  0x02050028,
+  0x0204083F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CA,
+  0x02050028,
+  0x020401F0,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CB,
+  0x02050028,
+  0x0204C1C7,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CC,
+  0x02050028,
+  0x02041C00,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CD,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CE,
+  0x02050028,
+  0x02040200,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400CF,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D0,
+  0x02050028,
+  0x020403E1,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D1,
+  0x02050028,
+  0x02040F5A,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D2,
+  0x02050028,
+  0x02041E1E,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x020400D3,
+  0x02050028,
+  0x0204083F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040062,
+  0x02050028,
+  0x02048000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040063,
+  0x02050028,
+  0x02045F5F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040064,
+  0x02050028,
+  0x02042000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040065,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040066,
+  0x02050028,
+  0x02044004,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040067,
+  0x02050028,
+  0x02040802,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040068,
+  0x02050028,
+  0x0204890F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040069,
+  0x02050028,
+  0x0204E021,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040070,
+  0x02050028,
+  0x02048012,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040071,
+  0x02050028,
+  0x02043450,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040072,
+  0x02050028,
+  0x02040123,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040073,
+  0x02050028,
+  0x02044543,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040074,
+  0x02050028,
+  0x02042100,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040075,
+  0x02050028,
+  0x02044321,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040076,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040050,
+  0x02050028,
+  0x02048200,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040051,
+  0x02050028,
+  0x02040707,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040052,
+  0x02050028,
+  0x02044090,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006A,
+  0x02050028,
+  0x02040090,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204006C,
+  0x02050028,
+  0x0204721F,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040012,
+  0x02050028,
+  0x0204DFDF,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204009E,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040004,
+  0x02050028,
+  0x02040500,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040060,
+  0x02050028,
+  0x0204E213,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003A,
+  0x02050028,
+  0x02041DFE,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204003F,
+  0x02050028,
+  0x02043000,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040040,
+  0x02050028,
+  0x0204000C,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x02040046,
+  0x02050028,
+  0x0204422E,
+  0x02050029,
+  0x0204B024,
+
+  0x02050024,
+  0x02040010,
+  0x02050026,
+  0x0204004B,
+  0x02050028,
+  0x02040000,
+  0x02050029,
+  0x0204B024
+); // WhlHdaVerbTableAlc700

+ 137 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c

@@ -0,0 +1,137 @@
+/** @file
+  This file is SampleCode of the library for Intel HD Audio Verb Table configuration.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <ConfigBlock.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc274;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc700;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc701;
+extern HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700;
+
+/**
+  Add verb table helper function.
+  This function calculates verbtable number and shows verb table information.
+
+  @param[in,out] VerbTableEntryNum      Input current VerbTable number and output the number after adding new table
+  @param[in,out] VerbTableArray         Pointer to array of VerbTable
+  @param[in]     VerbTable              VerbTable which is going to add into array
+**/
+STATIC
+VOID
+InternalAddVerbTable (
+  IN OUT  UINT8                   *VerbTableEntryNum,
+  IN OUT  UINT32                  *VerbTableArray,
+  IN      HDAUDIO_VERB_TABLE      *VerbTable
+  )
+{
+  if (VerbTable == NULL) {
+    DEBUG ((DEBUG_INFO, "InternalAddVerbTable wrong input: VerbTable == NULL\n"));
+    return;
+  }
+
+  VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable;
+  *VerbTableEntryNum += 1;
+
+  DEBUG ((DEBUG_INFO,
+    "HDA: Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n",
+    VerbTable->Header.VendorId,
+    VerbTable->Header.DeviceId,
+    VerbTable->Header.DataDwords)
+    );
+}
+
+/**
+  Add verb table function.
+  This function update the verb table number and verb table ptr of policy.
+
+  @param[in]  HdAudioConfig            HD Audio config block
+  @param[out] VerbTableEntryNum        Number of verb table entries
+  @param[out] HdaVerbTablePtr          Pointer to the verb table
+**/
+VOID
+AddPlatformVerbTables (
+  IN   UINT8              CodecType,
+  OUT  UINT8              *VerbTableEntryNum,
+  OUT  UINT32             *HdaVerbTablePtr
+  )
+{
+  UINT8                   VerbTableEntries;
+  UINT32                  VerbTableArray[6];
+  UINT32                  *VerbTablePtr;
+
+  VerbTableEntries = 0;
+
+  InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable));
+
+  if (CodecType == PchHdaCodecPlatformOnboard) {
+    DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));
+    InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable));
+    InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2));
+  } else {
+    DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));
+    InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1));
+    InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2));
+    InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3));
+  }
+
+  *VerbTableEntryNum = VerbTableEntries;
+
+  VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntries);
+  CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntries);
+  *HdaVerbTablePtr = (UINT32) VerbTablePtr;
+}
+
+/**
+  HDA VerbTable init function for PEI post memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+HdaVerbTableInit (
+  IN UINT16 BoardId
+  )
+{
+  HDAUDIO_VERB_TABLE *VerbTable;
+  HDAUDIO_VERB_TABLE *VerbTable2;
+
+  VerbTable = NULL;
+  VerbTable2 = NULL;
+
+  switch (BoardId) {
+
+    case BoardIdCometLakeULpddr3Rvp:
+      VerbTable = &WhlHdaVerbTableAlc700;
+      break;
+
+    default:
+      DEBUG ((DEBUG_INFO, "HDA: Init default verb tables (Realtek ALC700 and ALC701)\n"));
+      VerbTable = &HdaVerbTableAlc700;
+      VerbTable2 = &HdaVerbTableAlc701;
+      break;
+  }
+
+  PcdSet32S (PcdHdaVerbTable, (UINT32) VerbTable);
+  PcdSet32S (PcdHdaVerbTable2, (UINT32) VerbTable2);
+  PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINT32) &HdaVerbTableDisplayAudio);
+
+  // Codecs - Realtek ALC700, ALC701, ALC274 (external - connected via HDA header)
+  PcdSet32S (PcdCommonHdaVerbTable1, (UINT32) &HdaVerbTableAlc700);
+  PcdSet32S (PcdCommonHdaVerbTable2, (UINT32) &HdaVerbTableAlc701);
+  PcdSet32S (PcdCommonHdaVerbTable3, (UINT32) &HdaVerbTableAlc274);
+
+  return EFI_SUCCESS;
+}

+ 69 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf

@@ -0,0 +1,69 @@
+## @file
+#  PEI Intel HD Audio Verb Table library.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiHdaVerbTableLib
+  FILE_GUID                      = 821486A2-CF3B-4D24-BC45-AFE40D9737EB
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = HdaVerbTableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+  PeiHdaVerbTableLib.c
+  PchHdaVerbTables.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+#                              this module.
+#
+################################################################################
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  MemoryAllocationLib
+  PcdLib
+
+[Pcd]
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable    ## CONSUMES

+ 115 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.c

@@ -0,0 +1,115 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/I2cAccessLib.h>
+
+EFI_STATUS
+I2cWriteRead (
+  IN UINTN  MmioBase,
+  IN UINT8  SlaveAddress,
+  IN UINT8  WriteLength,
+  IN UINT8  *WriteBuffer,
+  IN UINT8  ReadLength,
+  IN UINT8  *ReadBuffer,
+  IN UINT64  TimeBudget
+  //TODO: add Speed parameter
+  )
+{
+  UINT8 ReadsNeeded = ReadLength;
+  UINT64 CutOffTime;
+
+  if ((WriteLength == 0 && ReadLength == 0) ||
+      (WriteLength != 0 && WriteBuffer == NULL) ||
+      (ReadLength != 0 && ReadBuffer == NULL) ) {
+    DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Sanity checks to verify the I2C controller is alive
+  // Conveniently, ICON register's values of 0 or FFFFFFFF indicate
+  // I2c controller is out-of-order: either disabled, in D3 or in reset.
+  //
+  if (MmioRead32(MmioBase+R_IC_CON) == 0xFFFFFFFF || MmioRead32(MmioBase+R_IC_CON) == 0x0) {
+    DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n"));
+    return EFI_DEVICE_ERROR;
+  }
+
+  MmioWrite32(MmioBase+R_IC_ENABLE, 0x0);
+  MmioRead32(MmioBase+0x40);
+  MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
+  MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C);
+  //
+  // Set I2C Bus Speed at 400 kHz for GPIO Expander
+  //
+  MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128);
+  MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160);
+  MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress);
+  MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | V_IC_SPEED_FAST | B_IC_RESTART_EN | B_IC_SLAVE_DISABLE );
+  MmioWrite32(MmioBase+R_IC_ENABLE, 0x1);
+  CutOffTime = AsmReadTsc() + TimeBudget;
+
+  while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==0 ) {
+    if (AsmReadTsc() > CutOffTime) {
+      DEBUG ((DEBUG_ERROR, "I2cWR timeout\n"));
+      return EFI_TIMEOUT;
+    }
+  }
+
+  while(1) {
+    if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) {
+      DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason = 0x%08x\n",MmioRead32(MmioBase+R_IC_TX_ABRT_SOURCE)));
+      MmioRead32(MmioBase+R_IC_CLR_TX_ABRT);
+      MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+      while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
+      return EFI_DEVICE_ERROR;
+    }
+    if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) {
+      if (WriteLength > 1) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
+        WriteBuffer++;
+        WriteLength--;
+      } else if (WriteLength==1 && ReadLength != 0) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer);
+        WriteBuffer++;
+        WriteLength--;
+      } else if (WriteLength==1 && ReadLength == 0) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | B_IC_CMD_STOP);
+        WriteBuffer++;
+        WriteLength--;
+      } else if (ReadLength > 1) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ);
+        ReadLength--;
+      } else if (ReadLength == 1) {
+        MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ|B_IC_CMD_STOP);
+        ReadLength--;
+      }
+    }
+
+    if (ReadsNeeded) {
+      if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) {
+        *ReadBuffer = (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD);
+        ReadBuffer++;
+        ReadsNeeded--;
+      }
+    }
+    if (WriteLength==0 && ReadsNeeded==0 && !(MmioRead32(MmioBase+R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) {
+      MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+      while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
+      DEBUG ((DEBUG_INFO, "I2cWR success\n"));
+      return EFI_SUCCESS;
+    }
+    if (AsmReadTsc() > CutOffTime) {
+      MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE);
+      while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)==1 ) {}
+      DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n"));
+      return EFI_TIMEOUT;
+    }
+
+  }
+}
+
+

+ 39 - 0
Platform/Intel/CometlakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf

@@ -0,0 +1,39 @@
+## @file
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiI2cAccessLib
+  FILE_GUID                      = 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = BASE
+  LIBRARY_CLASS                  = PeiI2cAccessLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  TimerLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  SecurityPkg/SecurityPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiI2cAccessLib.c
+

+ 88 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeCpuPolicyUpdate.c

@@ -0,0 +1,88 @@
+/** @file
+  This file is the library for CPU DXE Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DxeCpuPolicyUpdateLib.h>
+
+/**
+  This function prints the CPU DXE phase policy.
+
+  @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+  IN  DXE_CPU_POLICY_PROTOCOL  *DxeCpuPolicy
+  )
+{
+  DEBUG_CODE_BEGIN ();
+  DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print BEGIN -----------------\n"));
+  DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision));
+  ASSERT (DxeCpuPolicy->Revision == DXE_CPU_POLICY_PROTOCOL_REVISION);
+  DEBUG ((DEBUG_INFO, "\n------------------------ CPU_DXE_CONFIG -----------------\n"));
+  DEBUG ((DEBUG_INFO, "EnableDts : %x\n", DxeCpuPolicy->EnableDts));
+  DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print END -----------------\n"));
+  DEBUG_CODE_END ();
+}
+
+/**
+  Get data for CPU policy from setup options.
+
+  @param[in] DxeCpuPolicy              The pointer to get CPU Policy protocol instance
+
+  @retval EFI_SUCCESS                  Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+  IN OUT  DXE_CPU_POLICY_PROTOCOL  *DxeCpuPolicy
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  CpuInstallPolicyProtocol installs CPU Policy.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @param[in] ImageHandle                Image handle of this driver.
+  @param[in] DxeCpuPolicy               The pointer to CPU Policy Protocol instance
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+  IN  EFI_HANDLE                  ImageHandle,
+  IN  DXE_CPU_POLICY_PROTOCOL     *DxeCpuPolicy
+  )
+{
+  EFI_STATUS            Status;
+
+  ///
+  /// Print CPU DXE Policy
+  ///
+  CpuDxePrintPolicyProtocol(DxeCpuPolicy);
+
+  ///
+  /// Install the DXE_CPU_POLICY_PROTOCOL interface
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gDxeCpuPolicyProtocolGuid,
+                  DxeCpuPolicy,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+

+ 105 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.c

@@ -0,0 +1,105 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "DxeMePolicyUpdate.h"
+
+//
+// Record version
+//
+#define RECORD_REVISION_1              0x01
+#define MAX_FW_UPDATE_BIOS_SELECTIONS  2
+
+//
+// Function implementations executed during policy initialization phase
+//
+
+/**
+  Update the ME Policy Library
+
+  @param[in, out] DxeMePolicy           The pointer to get ME Policy protocol instance
+
+  @retval EFI_SUCCESS                   Initialization complete.
+  @retval EFI_UNSUPPORTED               The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES          Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR              Device error, driver exits abnormally.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeMePolicy (
+  IN OUT  ME_POLICY_PROTOCOL            *DxeMePolicy
+  )
+{
+  EFI_STATUS              Status;
+  EFI_EVENT               EndOfDxeEvent;
+
+  DEBUG ((DEBUG_INFO, "UpdateDxeMePolicy\n"));
+  UpdateMePolicyFromSetup (DxeMePolicy);
+  UpdateMePolicyFromMeSetup (DxeMePolicy);
+
+  //
+  // Register End of DXE event
+  //
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_NOTIFY,
+                  UpdateMeSetupCallback,
+                  NULL,
+                  &gEfiEndOfDxeEventGroupGuid,
+                  &EndOfDxeEvent
+                  );
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
+
+/**
+  Update ME Policy while MePlatformProtocol is installed.
+
+  @param[in] MePolicyInstance     Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromMeSetup (
+  IN ME_POLICY_PROTOCOL           *MePolicyInstance
+  )
+{
+
+}
+
+/**
+  Update ME Policy if Setup variable exists.
+
+  @param[in, out] MePolicyInstance     Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromSetup (
+  IN OUT ME_POLICY_PROTOCOL     *MePolicyInstance
+  )
+{
+
+}
+
+/**
+  Functions performs HECI exchange with FW to update MePolicy settings.
+
+  @param[in] Event         A pointer to the Event that triggered the callback.
+  @param[in] Context       A pointer to private data registered with the callback function.
+
+**/
+VOID
+EFIAPI
+UpdateMeSetupCallback (
+  IN  EFI_EVENT                   Event,
+  IN  VOID                        *Context
+  )
+{
+  gBS->CloseEvent (Event);
+
+  return;
+}
+
+

+ 90 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.h

@@ -0,0 +1,90 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_ME_POLICY_UPDATE_H_
+#define _DXE_ME_POLICY_UPDATE_H_
+
+#include <PiDxe.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Guid/EventGroup.h>
+#include <IndustryStandard/Acpi10.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/MePolicy.h>
+#include <Library/HobLib.h>
+#include <ConfigBlock/MePeiConfig.h>
+
+#define PLATFORM_BOOT_TABLE_PTR_TYPE   0x1001
+#define PLATFORM_BOOT_RECORD_TYPE      0x1022
+//
+// Timeout values based on HPET
+//
+#define HECI_MSG_DELAY                 2000000  ///< show warning msg and stay for 2 seconds.
+#define CONVERSION_MULTIPLIER          1000000  ///< msec to nanosec multiplier
+#define PLATFORM_BOOT_TABLE_SIGNATURE  SIGNATURE_32 ('P', 'B', 'P', 'T')
+
+//
+// Platform Boot Performance Table Record
+//
+
+typedef struct {
+  UINT16 Type;
+  UINT8  Length;
+  UINT8  Revision;
+  UINT32 Reserved;
+  UINT64 TimestampDelta1;
+  UINT64 TimestampDelta2;
+  UINT64 TimestampDelta3;
+} PLATFORM_BOOT_TABLE_RECORD;
+
+//
+// Platform boot Performance Table
+//
+
+typedef struct {
+  EFI_ACPI_COMMON_HEADER     Header;
+  PLATFORM_BOOT_TABLE_RECORD PlatformBoot;
+} PLATFORM_BOOT_PERFORMANCE_TABLE;
+
+/**
+  Update ME Policy while MePlatformProtocol is installed.
+
+  @param[in] MePolicyInstance     Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromMeSetup (
+  IN ME_POLICY_PROTOCOL           *MePolicyInstance
+  );
+
+/**
+  Update ME Policy if Setup variable exists.
+
+  @param[in, out] MePolicyInstance     Instance of ME Policy Protocol
+
+**/
+VOID
+UpdateMePolicyFromSetup (
+  IN OUT ME_POLICY_PROTOCOL     *MePolicyInstance
+  );
+
+/**
+  Functions performs HECI exchange with FW to update MePolicy settings.
+
+  @param[in] Event         A pointer to the Event that triggered the callback.
+  @param[in] Context       A pointer to private data registered with the callback function.
+
+**/
+VOID
+EFIAPI
+UpdateMeSetupCallback (
+  IN  EFI_EVENT                       Event,
+  IN  VOID                            *Context
+  );
+
+#endif
+

+ 40 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxePchPolicyUpdate.c

@@ -0,0 +1,40 @@
+/** @file
+  This file is the library for PCH DXE Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiDxe.h>
+#include <PchAccess.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/PchPolicy.h>
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  Get data for PCH policy from setup options.
+
+  @param[in] PchPolicy                 The pointer to get PCH Policy protocol instance
+
+  @retval EFI_SUCCESS                  Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxePchPolicy (
+  IN OUT  PCH_POLICY_PROTOCOL    *PchPolicy
+  )
+{
+  EFI_STATUS              Status;
+  PCH_HDAUDIO_DXE_CONFIG  *HdAudioDxeConfig;
+
+  Status = GetConfigBlock ((VOID *)PchPolicy, &gHdAudioDxeConfigGuid, (VOID *)&HdAudioDxeConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+

+ 59 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf

@@ -0,0 +1,59 @@
+## @file
+#  Component description file for DXE DxePolicyUpdateLib Library
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = DxePolicyUpdateLib
+  FILE_GUID                      = 690B3786-D215-4ABB-9EF2-7A80128560E0
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = DxePolicyUpdateLib|DXE_DRIVER
+
+#
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
+#
+
+[Sources]
+  DxeMePolicyUpdate.c
+  DxeSaPolicyUpdate.c
+  DxePchPolicyUpdate.c
+  DxeCpuPolicyUpdate.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  BaseLib
+  BaseMemoryLib
+  PcdLib
+  DebugLib
+  IoLib
+  CpuPlatformLib
+  HobLib
+  ConfigBlockLib
+  PciSegmentLib
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress  ## CONSUMES
+
+[Guids]
+  gEfiGlobalVariableGuid                        ## CONSUMES
+  gEfiEndOfDxeEventGroupGuid                    ## CONSUMES
+  gMeInfoSetupGuid                              ## PRODUCES
+  gMePolicyHobGuid                              ## CONSUMES
+  gCpuSetupVariableGuid                         ## CONSUMES
+  gPchSetupVariableGuid                         ## CONSUMES
+

+ 58 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.c

@@ -0,0 +1,58 @@
+/** @file
+  This file is the library for SA DXE Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <DxeSaPolicyUpdate.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  Get data for platform policy from setup options.
+
+  @param[in] SaPolicy                  The pointer to get SA Policy protocol instance
+
+  @retval EFI_SUCCESS                  Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+  IN OUT  SA_POLICY_PROTOCOL    *SaPolicy
+  )
+{
+  EFI_STATUS                Status;
+  GRAPHICS_DXE_CONFIG       *GraphicsDxeConfig;
+  PCIE_DXE_CONFIG           *PcieDxeConfig;
+  MISC_DXE_CONFIG           *MiscDxeConfig;
+  MEMORY_DXE_CONFIG         *MemoryDxeConfig;
+
+  GraphicsDxeConfig = NULL;
+  PcieDxeConfig = NULL;
+  MiscDxeConfig = NULL;
+  MemoryDxeConfig = NULL;
+  //
+  // Get requisite IP Config Blocks which needs to be used here
+  //
+  Status = GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID *)&PcieDxeConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *)SaPolicy, &gMemoryDxeConfigGuid, (VOID *)&MemoryDxeConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  PcieDxeConfig->PegAspmL0s[0] = 3;
+  PcieDxeConfig->PegAspmL0s[1] = 3;
+  PcieDxeConfig->PegAspmL0s[2] = 3;
+
+  return EFI_SUCCESS;
+}
+
+

+ 25 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.h

@@ -0,0 +1,25 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_SA_POLICY_UPDATE_H_
+#define _DXE_SA_POLICY_UPDATE_H_
+
+#include <PiDxe.h>
+#include <CpuRegs.h>
+#include <PchAccess.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/SaPolicy.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+
+#endif
+

+ 37 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiCpuPolicyInit.h

@@ -0,0 +1,37 @@
+/** @file
+  Header file for the PeiCpuPolicyInit.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CPU_POLICY_INIT_H_
+#define _PEI_CPU_POLICY_INIT_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/CpuPolicyLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+
+/**
+  This function performs CPU PEI Policy initialization in PreMem.
+
+  @param[in, out] SiPreMemPolicyPpi  The Si Pre-Mem Policy PPI instance
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+  IN OUT  SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+  );
+#endif
+

+ 23 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiMePolicyInit.h

@@ -0,0 +1,23 @@
+/** @file
+  Header file for the PeiMePolicyInit
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_ME_POLICY_INIT_H_
+#define _PEI_ME_POLICY_INIT_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiMePolicyLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+
+#endif // _PEI_ME_POLICY_INIT_H_
+

+ 65 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInit.c

@@ -0,0 +1,65 @@
+/** @file
+  This file is SampleCode for Intel PEI Platform Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyInit.h"
+
+/**
+  Initialize Intel PEI Platform Policy
+
+  @param[in] PeiServices            General purpose services available to every PEIM.
+  @param[in] FirmwareConfiguration  It uses to skip specific policy init that depends
+                                    on the 'FirmwareConfiguration' varaible.
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+  IN UINT8                     FirmwareConfiguration
+  )
+{
+  EFI_STATUS                   Status;
+  SI_POLICY_PPI                *SiPolicyPpi;
+
+  //
+  // Call SiCreateConfigBlocks to initialize Silicon Policy structure
+  // and get all Intel default policy settings.
+  //
+  Status = SiCreateConfigBlocks (&SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR(Status)) {
+    return;
+  }
+
+  if (PcdGetBool (PcdDumpDefaultSiliconPolicy)) {
+    DEBUG ((DEBUG_INFO, "Dump Default Silicon Policy...\n"));
+    DumpSiPolicy (SiPolicyPpi);
+  }
+
+  //
+  // Update policy by board configuration
+  //
+  UpdatePeiSiPolicyBoardConfig (SiPolicyPpi);
+  UpdatePeiPchPolicyBoardConfig (SiPolicyPpi);
+  UpdatePeiSaPolicyBoardConfig (SiPolicyPpi);
+  UpdatePeiCpuPolicyBoardConfig (SiPolicyPpi);
+  UpdatePeiMePolicyBoardConfig (SiPolicyPpi);
+
+  UpdatePeiSiPolicy(SiPolicyPpi);
+  UpdatePeiPchPolicy(SiPolicyPpi);
+  UpdatePeiSaPolicy(SiPolicyPpi);
+  UpdatePeiCpuPolicy(SiPolicyPpi);
+  UpdatePeiMePolicy(SiPolicyPpi);
+
+  //
+  // Install SiPolicyPpi.
+  // While installed, RC assumes the Policy is ready and finalized. So please
+  // update and override any setting before calling this function.
+  //
+  Status = SiInstallPolicyPpi (SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+}
+

+ 23 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInit.h

@@ -0,0 +1,23 @@
+/** @file
+  Header file for the PolicyInitPei PEIM.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_INIT_H_
+#define _PEI_POLICY_INIT_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include "PeiCpuPolicyInit.h"
+#include "PeiMePolicyInit.h"
+#include "PeiSaPolicyInit.h"
+#include "PeiSiPolicyInit.h"
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#endif
+

+ 62 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf

@@ -0,0 +1,62 @@
+## @file
+# Component description file for PeiPolicyInit library.
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiPolicyInitLib
+  FILE_GUID                      = B494DF39-A5F8-48A1-B2D0-EF523AD91C55
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiPolicyInitLib
+
+[LibraryClasses]
+  BaseMemoryLib
+  BaseLib
+  CpuPlatformLib
+  DebugLib
+  DebugPrintErrorLevelLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  PeiServicesLib
+  PeiPolicyBoardConfigLib
+  PeiPolicyUpdateLib
+  PostCodeLib
+  SmbusLib
+  ConfigBlockLib
+  SiPolicyLib
+  TimerLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress  ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy ## CONSUMES
+
+
+[Sources]
+  PeiPolicyInitPreMem.c
+  PeiPolicyInit.c
+  PeiPolicyInit.h
+  PeiCpuPolicyInit.h
+  PeiMePolicyInit.h
+  PeiSaPolicyInit.c
+  PeiSaPolicyInit.h
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid               ## CONSUMES
+  gSiPolicyPpiGuid                              ## CONSUMES
+  gSiPreMemPolicyPpiGuid                        ## CONSUMES
+

+ 60 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiPolicyInitPreMem.c

@@ -0,0 +1,60 @@
+/** @file
+  This file is SampleCode for Intel PEI Platform Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyInit.h"
+
+/**
+  Initialize Intel PEI Platform Policy
+
+  @param[in]  FirmwareConfiguration  It uses to skip specific policy init that depends
+                                     on the 'FirmwareConfiguration' varaible.
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+  IN UINT8                     FirmwareConfiguration
+  )
+{
+  EFI_STATUS                   Status;
+  SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi;
+
+  DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n"));
+  //
+  // Call SiCreatePreMemConfigBlocks to initialize platform policy structure
+  // and get all intel default policy settings.
+  //
+  Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Update policy by board configuration
+  //
+  UpdatePeiPchPolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+  UpdatePeiMePolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+  UpdatePeiSaPolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+  UpdatePeiCpuPolicyBoardConfigPreMem (SiPreMemPolicyPpi);
+
+  //
+  // Update and override all platform related and customized settings below.
+  //
+  UpdatePeiPchPolicyPreMem (SiPreMemPolicyPpi);
+  UpdatePeiMePolicyPreMem (SiPreMemPolicyPpi);
+  UpdatePeiSaPolicyPreMem (SiPreMemPolicyPpi);
+  UpdatePeiCpuPolicyPreMem (SiPreMemPolicyPpi);
+
+  //
+  // Install SiPreMemPolicyPpi.
+  // While installed, RC assumes the Policy is ready and finalized. So please
+  // update and override any setting before calling this function.
+  //
+  Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n"));
+}
+

+ 114 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiSaPolicyInit.c

@@ -0,0 +1,114 @@
+/** @file
+  This file is SampleCode for Intel SA PEI Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyInit.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+  PcieCardResetWorkAround performs PCIe Card reset on root port
+
+  @param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI
+
+  @retval EFI_SUCCESS              The policy is installed and initialized.
+**/
+EFI_STATUS
+  PcieCardResetWorkAround (
+  IN OUT   SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi
+  )
+{
+  EFI_STATUS                      Status;
+  SA_MISC_PEI_PREMEM_CONFIG       *MiscPeiPreMemConfig;
+  SWITCHABLE_GRAPHICS_CONFIG      *SgGpioData;
+
+  Status = GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *)&MiscPeiPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *)&SgGpioData);
+  ASSERT_EFI_ERROR(Status);
+
+  if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport != NotSupported) {
+    ///
+    /// dGPU is present.
+    ///      If PCIe Mode or SG Muxless
+    ///              Power on MXM
+    ///              Configure GPIOs to drive MXM in PCIe mode or SG Muxless
+    ///      else
+    ///              Do Nothing
+    ///
+    if ((MiscPeiPreMemConfig->SgMode == SgModeMuxless) ||
+        (MiscPeiPreMemConfig->SgMode == SgModeDgpu)) {
+      DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n"));
+      ///
+      ///  Drive DGPU HOLD RST Enable to make sure we hold reset
+      ///
+      PcieGpioWrite (
+        SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
+        SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
+        GP_ENABLE
+        );
+      ///
+      /// wait 100ms
+      ///
+      MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STALL_ONE_MILLI_SECOND);
+
+      ///
+      /// Drive DGPU PWR EN to Power On MXM
+      ///
+      PcieGpioWrite (
+        SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo,
+        SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active,
+        GP_ENABLE
+        );
+      ///
+      /// wait 300ms
+      ///
+      MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * STALL_ONE_MILLI_SECOND);
+
+      ///
+      /// Drive DGPU HOLD RST Disabled to remove reset
+      ///
+      PcieGpioWrite (
+        SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
+        SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
+        GP_DISABLE
+        );
+      ///
+      /// wait 100ms
+      ///
+      MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STALL_ONE_MILLI_SECOND);
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  PCIe GPIO Write
+
+  @param[in] Gpio        - GPIO Number
+  @param[in] Active      - GPIO Active Information; High/Low
+  @param[in] Level       - Write GPIO value (0/1)
+
+**/
+VOID
+PcieGpioWrite (
+  IN  UINT32                Gpio,
+  IN  BOOLEAN               Active,
+  IN  BOOLEAN               Level
+  )
+{
+  EFI_STATUS  Status;
+
+  if (Active == 0) {
+    Level = (~Level) & 0x1;
+  }
+  Status = GpioSetOutputValue(Gpio, (UINT32)Level);
+  if (Status != EFI_SUCCESS) {
+    return;
+  }
+}
+

+ 58 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiSaPolicyInit.h

@@ -0,0 +1,58 @@
+/** @file
+  Header file for the SaPolicyInitPei PEIM.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SA_POLICY_INIT_PEI_H_
+#define _SA_POLICY_INIT_PEI_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Ppi/SiPolicy.h>
+#include <SaPolicyCommon.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+#include <Library/TimerLib.h>
+#include <Library/GpioLib.h>
+
+//
+// Functions
+//
+/**
+PCIe GPIO Write
+
+@param[in] Gpio        - GPIO Number
+@param[in] Active      - GPIO Active Information; High/Low
+@param[in] Level       - Write GPIO value (0/1)
+
+**/
+VOID
+PcieGpioWrite(
+IN       UINT32                       Gpio,
+IN       BOOLEAN                      Active,
+IN       BOOLEAN                      Level
+);
+
+/**
+PcieCardResetWorkAround performs PCIe Card reset on root port
+
+@param[in out] SiPreMemPolicyPpi       - SI_PREMEM_POLICY_PPI
+
+@retval EFI_SUCCESS              The policy is installed and initialized.
+**/
+EFI_STATUS
+PcieCardResetWorkAround(
+IN OUT   SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi
+);
+#endif
+

+ 22 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/PeiSiPolicyInit.h

@@ -0,0 +1,22 @@
+/** @file
+  Header file for the PeiSiPolicyInit
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SI_POLICY_INIT_PEI_H_
+#define _SI_POLICY_INIT_PEI_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <FirwmareConfigurations.h>
+
+#endif // _SI_POLICY_INIT_PEI_H_
+

+ 80 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c

@@ -0,0 +1,80 @@
+/** @file
+  CPU PEI Policy Update & initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/CpuPlatformLib.h>
+
+/**
+  This function performs CPU PEI Policy initialization.
+
+  @param[in] SiPolicyPpi           The SI Policy PPI instance
+
+  @retval EFI_SUCCESS              The PPI is installed and initialized.
+  @retval EFI ERRORS               The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES     Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+  IN OUT  SI_POLICY_PPI   *SiPolicyPpi
+  )
+{
+  EFI_STATUS                       Status;
+  CPU_CONFIG                       *CpuConfig;
+  CPU_POWER_MGMT_BASIC_CONFIG      *CpuPowerMgmtBasicConfig;
+  SI_PREMEM_POLICY_PPI             *SiPreMemPolicyPpi;
+  CPU_POWER_MGMT_CUSTOM_CONFIG     *CpuPowerMgmtCustomConfig;
+  CPU_POWER_MGMT_TEST_CONFIG      *CpuPowerMgmtTestConfig;
+  CPU_TEST_CONFIG                 *CpuTestConfig;
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtCustomConfigGuid, (VOID *)&CpuPowerMgmtCustomConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *)SiPolicyPpi, &gCpuTestConfigGuid, (VOID *)&CpuTestConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = PeiServicesLocatePpi (
+                &gSiPreMemPolicyPpiGuid,
+                0,
+                NULL,
+                (VOID **) &SiPreMemPolicyPpi
+                );
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtTestConfigGuid, (VOID *)&CpuPowerMgmtTestConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  //
+  // Init Power Management Policy Variables
+  //
+  CpuPowerMgmtBasicConfig->HwpInterruptControl = 1;
+  CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio = 0x4;
+  CpuPowerMgmtBasicConfig->OneCoreRatioLimit = 0x22;
+  CpuPowerMgmtBasicConfig->TwoCoreRatioLimit = 0x22;
+  CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit = 0x22;
+  CpuPowerMgmtBasicConfig->FourCoreRatioLimit = 0x22;
+  CpuPowerMgmtBasicConfig->FiveCoreRatioLimit = 0;
+  CpuPowerMgmtBasicConfig->SixCoreRatioLimit = 0;
+  CpuPowerMgmtBasicConfig->SevenCoreRatioLimit = 0;
+  CpuPowerMgmtBasicConfig->EightCoreRatioLimit = 0;
+  CpuPowerMgmtBasicConfig->Hwp = 0x1;
+  CpuTestConfig->CpuWakeUpTimer = 1;
+  CpuPowerMgmtTestConfig->AutoThermalReporting = 0;
+
+  return EFI_SUCCESS;
+}
+

+ 32 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h

@@ -0,0 +1,32 @@
+/** @file
+  Header file for PEI CpuPolicyUpdate.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <PchAccess.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuAccess.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+#endif
+

+ 108 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c

@@ -0,0 +1,108 @@
+/** @file
+  This file is SampleCode of the library for Intel CPU PEI Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SpiLib.h>
+
+/**
+  Check on the processor if SGX is supported.
+
+  @retval True if SGX supported or FALSE if not
+**/
+BOOLEAN
+IsSgxCapSupported (
+  VOID
+  )
+{
+  EFI_CPUID_REGISTER CpuidRegs;
+
+  ///
+  /// Processor support SGX feature by reading CPUID.(EAX=7,ECX=0):EBX[2]
+  ///
+  AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEax,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx);
+
+  ///
+  /// SGX feature is supported only on WHL and later,
+  /// with CPUID.(EAX=7,ECX=0):EBX[2]=1
+  /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] == 1
+  ///
+  if ((CpuidRegs.RegEbx & BIT2) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BIT12)) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+/**
+  This function performs CPU PEI Policy initialization in Pre-memory.
+
+  @param[in] SiPreMemPolicyPpi     The SI Pre-Mem Policy PPI instance
+
+  @retval EFI_SUCCESS              The PPI is installed and initialized.
+  @retval EFI ERRORS               The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES     Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+  IN OUT  SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+  )
+{
+  EFI_STATUS                      Status;
+  EFI_BOOT_MODE                   BootMode;
+  CPU_CONFIG_LIB_PREMEM_CONFIG    *CpuConfigLibPreMemConfig;
+  CPU_OVERCLOCKING_PREMEM_CONFIG  *CpuOverClockingPreMemConfig;
+  UINT32                          PchSpiBar0;
+  UINT32                          MaxLogicProcessors;
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclockingPreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  DEBUG ((DEBUG_INFO, "UpdatePeiCpuPolicyPreMem Start\n"));
+
+  //
+  // Get current boot mode
+  //
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  SpiServiceInit ();
+
+  PchSpiBar0 = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (
+                                   DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+                                   DEFAULT_PCI_BUS_NUMBER_PCH,
+                                   PCI_DEVICE_NUMBER_PCH_SPI,
+                                   PCI_FUNCTION_NUMBER_PCH_SPI,
+                                   R_SPI_CFG_BAR0
+                                   ));
+  PchSpiBar0 &= ~(B_SPI_CFG_BAR0_MASK);
+
+  if (PchSpiBar0 == 0) {
+    DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
+    ASSERT (FALSE);
+  }
+
+  CpuConfigLibPreMemConfig->PeciC10Reset = 0;
+  CpuConfigLibPreMemConfig->CpuRatio = 0;
+  ///
+  /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical processors enabled
+  /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+  ///
+  MaxLogicProcessors = (UINT32) (AsmReadMsr64 (MSR_CORE_THREAD_COUNT) & B_THREAD_COUNT_MASK);
+  DEBUG ((DEBUG_INFO, "MaxLogicProcessors = %d\n", MaxLogicProcessors));
+  PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+
+  return EFI_SUCCESS;
+}
+

+ 49 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c

@@ -0,0 +1,49 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiMePolicyUpdate.h"
+#include <ConfigBlock/MePeiConfig.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PmcLib.h>
+
+/**
+  Update the ME Policy Library
+
+  @param[in, out] SiPolicyPpi     The pointer to SiPolicyPpi
+
+  @retval EFI_SUCCESS             Update complete.
+**/
+EFI_STATUS
+UpdatePeiMePolicy (
+  IN OUT SI_POLICY_PPI            *SiPolicyPpi
+  )
+{
+  EFI_STATUS                      Status;
+  ME_PEI_CONFIG                   *MePeiConfig;
+
+  DEBUG ((DEBUG_INFO, "UpdatePeiMePolicy\n"));
+
+  Status = EFI_SUCCESS;
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (!PmcIsRtcBatteryGood ()) {
+    //
+    // For non coin battery design, this can be skipped.
+    //
+    MePeiConfig->MeUnconfigOnRtcClear   = 2;
+  }
+
+  return Status;
+}
+
+

+ 14 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.h

@@ -0,0 +1,14 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_ME_POLICY_UPDATE_H_
+#define _PEI_ME_POLICY_UPDATE_H_
+
+#include <Library/DebugLib.h>
+#include <Ppi/SiPolicy.h>
+
+#endif
+

+ 32 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c

@@ -0,0 +1,32 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiMePolicyUpdate.h"
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  Update the ME Policy Library
+
+  @param[in] SiPreMemPolicyPpi  The pointer to SiPreMemPolicyPpi
+
+  @retval EFI_SUCCESS           Update complete.
+**/
+EFI_STATUS
+UpdatePeiMePolicyPreMem (
+  IN OUT SI_PREMEM_POLICY_PPI     *SiPreMemPolicyPpi
+  )
+{
+  EFI_STATUS                      Status;
+
+  DEBUG ((DEBUG_INFO, "UpdatePeiMePolicyPreMem\n"));
+
+  Status = EFI_SUCCESS;
+
+  return Status;
+}
+

+ 518 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c

@@ -0,0 +1,518 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/SataLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Ppi/Spi.h>
+#include <GpioConfig.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+#include <PlatformBoardConfig.h>
+#include <Library/CnviLib.h>
+#include <Register/PchRegsLpcCnl.h>
+#include <PcieDeviceOverrideTable.h>
+#include <Library/ConfigBlockLib.h>
+
+VOID
+UpdatePcieClockInfo (
+  PCH_PCIE_CONFIG  *PcieRpConfig,
+  UINTN            Index,
+  UINT64           Data
+  )
+{
+  PCD64_BLOB Pcd64;
+
+  Pcd64.Blob = Data;
+  DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
+
+  PcieRpConfig->PcieClock[Index].Usage = (UINT8)Pcd64.PcieClock.ClockUsage;
+  if (Pcd64.PcieClock.ClkReqSupported) {
+    PcieRpConfig->PcieClock[Index].ClkReq = (UINT8)Index;
+  } else {
+    PcieRpConfig->PcieClock[Index].ClkReq = 0xFF;
+  }
+}
+
+/**
+  This is helper function for getting I2C Pads Internal Termination settings from Pcd
+
+  @param[in]  Index            I2C Controller Index
+**/
+UINT8
+GetSerialIoI2cPadsTerminationFromPcd (
+  IN UINT8 Index
+)
+{
+  switch (Index) {
+    case 0:
+      return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+    case 1:
+      return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+    case 2:
+      return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+    case 3:
+      return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+    case 4:
+      return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+    case 5:
+      return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+    default:
+      ASSERT (FALSE); // Invalid I2C Controller Index
+  }
+  return 0;
+}
+/**
+  This is a helper function for updating USB Policy according to Blob data
+
+  @param[in]  UsbConfig        Pointer to USB_CONFIG data buffer
+  @param[in]  PortIndex        USB Port index
+  @param[in]  Data32           Blob containing USB2 Afe (PCD32_BLOB) data
+**/
+VOID
+UpdateUsb20AfePolicy (
+  IN USB_CONFIG                 *UsbConfig,
+  IN UINT8                      PortIndex,
+  UINT32                        Data32
+)
+{
+  PCD32_BLOB Pcd32;
+  Pcd32.Blob = Data32;
+
+  if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset != 0) {
+    UsbConfig->PortUsb20[PortIndex].Afe.Petxiset     = Pcd32.Info.Petxiset;
+    UsbConfig->PortUsb20[PortIndex].Afe.Txiset       = Pcd32.Info.Txiset;
+    UsbConfig->PortUsb20[PortIndex].Afe.Predeemp     = Pcd32.Info.Predeemp;
+    UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit    = Pcd32.Info.Pehalfbit;
+  }
+}
+
+/**
+  This function updates USB Policy per port OC Pin number
+
+  @param[in]  PchUsbConfig     Pointer to USB_CONFIG data buffer
+  @param[in]  PortIndex        USB Port index
+  @param[in]  Pin              OverCurrent pin number
+**/
+VOID
+UpdateUsb20OverCurrentPolicy (
+  IN USB_CONFIG                 *UsbConfig,
+  IN UINT8                      PortIndex,
+  UINT8                         Pin
+)
+{
+  if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
+    UsbConfig->PortUsb20[PortIndex].OverCurrentPin = Pin;
+  } else {
+    if (PortIndex >= MAX_USB2_PORTS) {
+      DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number %d is not a valid USB2 port number\n", PortIndex));
+    } else {
+      DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurrent pin specified USB2 port %d\n", PortIndex));
+    }
+  }
+}
+
+/**
+  This function updates USB Policy per port OC Pin number
+
+  @param[in]  PchUsbConfig     Pointer to USB_CONFIG data buffer
+  @param[in]  PortIndex        USB Port index
+  @param[in]  Pin              OverCurrent pin number
+**/
+VOID
+UpdateUsb30OverCurrentPolicy (
+  IN USB_CONFIG                 *UsbConfig,
+  IN UINT8                      PortIndex,
+  UINT8                         Pin
+)
+{
+  if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
+    UsbConfig->PortUsb30[PortIndex].OverCurrentPin = Pin;
+  } else {
+    if (PortIndex >= MAX_USB2_PORTS) {
+      DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number %d is not a valid USB3 port number\n", PortIndex));
+    } else {
+      DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurrent pin specified USB3 port %d\n", PortIndex));
+    }
+  }
+}
+
+/**
+  This function performs PCH USB Platform Policy initialization
+
+  @param[in] PchUsbConfig         Pointer to USB_CONFIG data buffer
+  @param[in] PchSetup             Pointer to PCH_SETUP data buffer
+**/
+VOID
+UpdatePchUsbConfig (
+  IN USB_CONFIG                *UsbConfig
+  )
+{
+  UINTN              PortIndex;
+
+  UsbConfig->OverCurrentEnable = TRUE;
+
+  for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) {
+      UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
+  }
+  for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
+      UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
+  }
+
+  UsbConfig->XdciConfig.Enable = FALSE;
+
+
+  //
+  // USB2 AFE settings.
+  //
+  UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe));
+  UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe));
+  UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe));
+  UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe));
+  UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe));
+  UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe));
+  UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe));
+  UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe));
+
+  //
+  // Platform Board programming per the layout of each port.
+  //
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrentPinPort0));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrentPinPort1));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrentPinPort2));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrentPinPort3));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrentPinPort4));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrentPinPort5));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrentPinPort6));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrentPinPort7));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrentPinPort8));
+  UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrentPinPort9));
+  UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrentPinPort10));
+  UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrentPinPort11));
+  UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrentPinPort12));
+  UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrentPinPort13));
+  UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrentPinPort14));
+  UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrentPinPort15));
+
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrentPinPort0));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrentPinPort1));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrentPinPort2));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrentPinPort3));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrentPinPort4));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrentPinPort5));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrentPinPort6));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrentPinPort7));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrentPinPort8));
+  UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrentPinPort9));
+
+}
+
+/**
+  Return if input ImageGuid belongs to system FMP GUID list.
+
+  @param[in] ImageGuid A pointer to GUID
+
+  @retval TRUE  ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeIdGuid
+  @retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTypeIdGuid
+**/
+BOOLEAN
+IsSystemFmpGuid (
+  IN GUID   *ImageGuid
+  )
+{
+  GUID      *Guid;
+  UINTN     Count;
+  UINTN     Index;
+
+  Guid = PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid);
+  Count = PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID);
+
+  for (Index = 0; Index < Count; Index++, Guid++) {
+    if (CompareGuid (ImageGuid, Guid)) {
+      return TRUE;
+    }
+  }
+
+  return FALSE;
+}
+
+/**
+  This function performs PCH PEI Policy initialization.
+
+  @param[in, out] SiPolicy        The SI Policy PPI instance
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+  IN OUT      SI_POLICY_PPI     *SiPolicy
+  )
+{
+  EFI_STATUS                      Status;
+  UINT8                           Index;
+  DMI_HW_WIDTH_CONTROL            *DmiHaAWC;
+  PCH_GENERAL_CONFIG              *PchGeneralConfig;
+  PCH_PCIE_CONFIG                 *PcieRpConfig;
+  PCH_SATA_CONFIG                 *SataConfig;
+  PCH_IOAPIC_CONFIG               *IoApicConfig;
+  PCH_DMI_CONFIG                  *DmiConfig;
+  PCH_FLASH_PROTECTION_CONFIG     *FlashProtectionConfig;
+  PCH_HDAUDIO_CONFIG              *HdAudioConfig;
+  PCH_INTERRUPT_CONFIG            *InterruptConfig;
+  PCH_ISH_CONFIG                  *IshConfig;
+  PCH_LAN_CONFIG                  *LanConfig;
+  PCH_LOCK_DOWN_CONFIG            *LockDownConfig;
+  PCH_PM_CONFIG                   *PmConfig;
+  PCH_SCS_CONFIG                  *ScsConfig;
+  PCH_SERIAL_IO_CONFIG            *SerialIoConfig;
+  PCH_LPC_SIRQ_CONFIG             *SerialIrqConfig;
+  PCH_THERMAL_CONFIG              *ThermalConfig;
+  USB_CONFIG                      *UsbConfig;
+  PCH_ESPI_CONFIG                 *EspiConfig;
+  PCH_CNVI_CONFIG                 *CnviConfig;
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
+
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &ThermalConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *) &EspiConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PeiServicesLocatePpi (
+                &gSiPreMemPolicyPpiGuid,
+                0,
+                NULL,
+                (VOID **) &SiPreMemPolicyPpi
+                );
+  ASSERT_EFI_ERROR (Status);
+
+  DmiConfig->PwrOptEnable = TRUE;
+  PmConfig->PchSlpS3MinAssert = 0;
+  PmConfig->PchSlpS4MinAssert = 0;
+  PmConfig->PchSlpSusMinAssert = 0;
+  PmConfig->PchSlpAMinAssert = 0;
+
+  SataConfig->ThermalThrottling.P1T3M = 3;
+  SataConfig->ThermalThrottling.P1T2M = 2;
+  SataConfig->ThermalThrottling.P1T1M = 1;
+  SataConfig->ThermalThrottling.P0T3M = 3;
+  SataConfig->ThermalThrottling.P0T2M = 2;
+  SataConfig->ThermalThrottling.P0T1M = 1;
+
+  UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64  (PcdPcieClock0));
+  UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64  (PcdPcieClock1));
+  UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64  (PcdPcieClock2));
+  UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64  (PcdPcieClock3));
+  UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64  (PcdPcieClock4));
+  UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64  (PcdPcieClock5));
+  UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64  (PcdPcieClock6));
+  UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64  (PcdPcieClock7));
+  UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64  (PcdPcieClock8));
+  UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64  (PcdPcieClock9));
+  UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10));
+  UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11));
+  UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12));
+  UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13));
+  UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14));
+  UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15));
+
+  PcieRpConfig->PcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
+  PcieRpConfig->RootPort[0].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[1].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[2].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[3].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[4].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[5].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[6].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[7].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[8].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[9].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[10].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[11].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[12].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[13].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[14].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[15].ClkReqDetect = TRUE;
+  PcieRpConfig->RootPort[0].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[1].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[2].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[3].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[4].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[5].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[6].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[7].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[8].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[9].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[10].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[11].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[12].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[13].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[14].AdvancedErrorReporting = TRUE;
+  PcieRpConfig->RootPort[15].AdvancedErrorReporting = TRUE;
+
+  //
+  // Install HDA Link/iDisplay Codec Verb Table
+  //
+  AddPlatformVerbTables (
+    PchHdaCodecPlatformOnboard,
+    &(HdAudioConfig->VerbTableEntryNum),
+    &(HdAudioConfig->VerbTablePtr)
+    );
+
+  LockDownConfig->BiosLock = FALSE;
+  LockDownConfig->BiosInterface = FALSE;
+
+  //
+  // IOAPIC Config
+  //
+//  IoApicConfig->IoApicEntry24_119     = PchSetup.PchIoApic24119Entries;
+  //
+  // To support SLP_S0, it's required to disable 8254 timer.
+  // Note that CSM may require this option to be disabled for correct operation.
+  // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail while using 8254 timer.
+  // For some OS environment that it needs to set 8254CGE in late state it should
+  // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in SMM later.
+  // This is also required during S3 resume.
+  //
+  // The Enable8254ClockGatingOnS3 is only applicable when Enable8254ClockGating is disabled.
+  // If Enable8254ClockGating is enabled, RC will do 8254 CGE programming on S3 as well.
+  // else, RC will do the programming on S3 when Enable8254ClockGatingOnS3 is enabled.
+  // This avoids the SMI requirement for the programming.
+  //
+  // If S0ix is not enabled, then disable 8254CGE for leagcy boot case.
+  //
+  IoApicConfig->Enable8254ClockGating     = FALSE;
+  IoApicConfig->Enable8254ClockGatingOnS3 = FALSE;
+
+  //
+  // SerialIo Config
+  //
+  SerialIoConfig->DevMode[0] = 1;
+  SerialIoConfig->DevMode[1] = 1;
+  SerialIoConfig->DevMode[2] = 0;
+  SerialIoConfig->DevMode[3] = 0;
+  SerialIoConfig->DevMode[4] = 1;
+  SerialIoConfig->DevMode[5] = 0;
+  SerialIoConfig->DevMode[6] = 0;
+  SerialIoConfig->DevMode[7] = 0;
+  SerialIoConfig->DevMode[8] = 0;
+  SerialIoConfig->DevMode[9] = 0;
+  SerialIoConfig->DevMode[10] = 0;
+  SerialIoConfig->DevMode[11] = 3;
+
+  SerialIoConfig->Uart0PinMuxing = 1;
+  SerialIoConfig->SpiCsPolarity[0] = 1;
+  SerialIoConfig->SpiCsPolarity[1] = 0;
+  SerialIoConfig->SpiCsPolarity[2] = 0;
+
+  SerialIoConfig->UartHwFlowCtrl[0] = 1;
+  SerialIoConfig->UartHwFlowCtrl[1] = 1;
+  SerialIoConfig->UartHwFlowCtrl[2] = 1;
+  //
+  // I2C4 and I2C5 don't exist in SPT-H chipset
+  //
+  if (IsPchH ()) {
+    SerialIoConfig->DevMode[PchSerialIoIndexI2C4] = PchSerialIoDisabled;
+    SerialIoConfig->DevMode[PchSerialIoIndexI2C5] = PchSerialIoDisabled;
+  }
+
+  for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+    SerialIoConfig->I2cPadsTermination[Index] = GetSerialIoI2cPadsTerminationFromPcd (Index);
+  }
+
+  PmConfig->SlpS0Override                         = 2; //PchSetup.SlpS0Override;
+  PmConfig->SlpS0DisQForDebug                     = 3;  //PchSetup.SlpS0DisQForDebug;
+  PmConfig->SlpS0Vm075VSupport                    = 1; // PcdGetBool(PcdSlpS0Vm075VSupport);
+  PmConfig->CpuC10GatePinEnable                   = 1;
+
+  //
+  // Thermal Config
+  //
+  ThermalConfig->TsmicLock           = TRUE;
+  ThermalConfig->PchHotEnable        = PcdGetBool (PcdPchThermalHotEnable);
+
+  DmiHaAWC = &ThermalConfig->DmiHaAWC;
+  DmiHaAWC->TS3TW = 0;
+  DmiHaAWC->TS2TW = 1;
+  DmiHaAWC->TS1TW = 2;
+  DmiHaAWC->TS0TW = 3;
+  //
+  // Update Pch Usb Config
+  //
+  UpdatePchUsbConfig (
+    UsbConfig
+    );
+
+  ScsConfig->ScsUfsEnabled = 0;
+  ScsConfig->ScsEmmcHs400Enabled = 1;
+  ScsConfig->ScsEmmcHs400TuningRequired = TRUE;
+
+  IshConfig->I2c0GpioAssign = 1;
+  IshConfig->I2c1GpioAssign = 1;
+  IshConfig->Gp0GpioAssign = 1;
+  IshConfig->Gp1GpioAssign = 1;
+  IshConfig->Gp2GpioAssign = 1;
+  IshConfig->Gp3GpioAssign = 1;
+  IshConfig->Gp4GpioAssign = 1;
+  IshConfig->Gp5GpioAssign = 1;
+  IshConfig->Gp6GpioAssign = 1;
+
+  return Status;
+}

+ 24 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h

@@ -0,0 +1,24 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PlatformBoardConfig.h>
+
+#endif
+

+ 114 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c

@@ -0,0 +1,114 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/SataLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchPolicyLib.h>
+#include <Library/ConfigBlockLib.h>
+
+//
+// Sawtooth Peak
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = {
+  DIMM_SMB_SPD_P0C0D0_STP,
+  DIMM_SMB_SPD_P0C0D1_STP,
+  DIMM_SMB_SPD_P0C1D0_STP,
+  DIMM_SMB_SPD_P0C1D1_STP
+};
+
+
+/**
+  This function performs PCH PEI Policy initialization.
+
+  @param[in, out] SiPreMemPolicy  The SI PREMEM Policy PPI instance
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+  IN OUT   SI_PREMEM_POLICY_PPI  *SiPreMemPolicy
+  )
+{
+  EFI_STATUS                      Status;
+  UINT8                           *SmBusReservedTable;
+  UINT8                           SmBusReservedNum;
+
+  PCH_GENERAL_PREMEM_CONFIG       *PchGeneralPreMemConfig;
+  PCH_TRACE_HUB_PREMEM_CONFIG     *PchTraceHubPreMemConfig;
+  PCH_SMBUS_PREMEM_CONFIG         *SmbusPreMemConfig;
+  PCH_LPC_PREMEM_CONFIG           *LpcPreMemConfig;
+  PCH_WDT_PREMEM_CONFIG           *WatchDogPreMemConfig;
+  PCH_DCI_PREMEM_CONFIG           *DciPreMemConfig;
+  PCH_PCIE_RP_PREMEM_CONFIG       *PcieRpPreMemConfig;
+  PCH_HDAUDIO_PREMEM_CONFIG       *HdaPreMemConfig;
+  PCH_ISH_PREMEM_CONFIG           *IshPreMemConfig;
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemConfigGuid, (VOID *) &PchTraceHubPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConfigGuid, (VOID *) &WatchDogPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGuid, (VOID *) &IshPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  DciPreMemConfig->DciUsb3TypecUfpDbg = 2;
+  PchTraceHubPreMemConfig->MemReg0Size = 3;
+  PchTraceHubPreMemConfig->MemReg1Size = 3;
+  //
+  // SMBUS
+  //
+  SmbusPreMemConfig->Enable = TRUE;
+  SmbusPreMemConfig->SmbAlertEnable = PcdGetBool (PcdSmbusAlertEnable);
+  //
+  // SMBUS reserved addresses
+  //
+  SmBusReservedTable = NULL;
+  SmBusReservedNum   = 0;
+  SmbusPreMemConfig->SmbusIoBase = PcdGet16 (PcdSmbusBaseAddress);
+  SmBusReservedTable = mSmbusSTPRsvdAddresses;
+  SmBusReservedNum   = sizeof (mSmbusSTPRsvdAddresses);
+
+  if (SmBusReservedTable != NULL) {
+    SmbusPreMemConfig->NumRsvdSmbusAddresses = SmBusReservedNum;
+    CopyMem (
+      SmbusPreMemConfig->RsvdSmbusAddressTable,
+      SmBusReservedTable,
+      SmBusReservedNum
+      );
+  }
+
+  return Status;
+}
+

+ 273 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf

@@ -0,0 +1,273 @@
+## @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+#
+#  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiPolicyUpdateLib
+  FILE_GUID                      = 6EA9585C-3C15-47DA-9FFC-25E9E4EA4D0C
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+  HobLib
+  BaseCryptLib
+  CpuPlatformLib
+  IoLib
+  PeiSaPolicyLib
+  ConfigBlockLib
+  PchGbeLib
+  PchInfoLib
+  PchPcieRpLib
+  HdaVerbTableLib
+  MemoryAllocationLib
+  PeiServicesTablePointerLib
+  PcdLib
+  Tpm2CommandLib
+  Tpm12CommandLib
+  Tpm2DeviceLib
+  Tpm12DeviceLib
+  PmcLib
+  SataLib
+  PchInfoLib
+  PciSegmentLib
+  SiPolicyLib
+  PeiServicesLib
+  SpiLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  CometlakeOpenBoardPkg/OpenBoardPkg.dec
+  CoffeelakeSiliconPkg/SiPkg.dec
+  SecurityPkg/SecurityPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[FixedPcd]
+  gSiPkgTokenSpaceGuid.PcdTsegSize                             ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize          ## CONSUMES
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress  ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength     ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdMchBaseAddress             ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress           ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable    ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber         ## CONSUMES
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid   ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress    ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress     ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdGttMmAddress      ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress      ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress  ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit       ## CONSUMES
+
+  # SA Misc Config
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd                   ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap                   ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram              ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize          ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize                 ## CONSUMES
+
+  # Display DDI
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize       ## CONSUMES
+
+  # PEG Reset By GPIO
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive            ## CONSUMES
+
+  # PCIE RTD3 GPIO
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev                    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc                   ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex                  ## CONSUMES
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive           ## CONSUMES
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive           ## CONSUMES
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive           ## CONSUMES
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo         ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo           ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive           ## CONSUMES
+
+  # SPD Address Table
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3            ## CONSUMES
+
+  # CA Vref Configuration
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig                ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent              ## CONSUMES
+
+  # PCIe Clock Info
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9                     ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10                    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11                    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12                    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13                    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14                    ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15                    ## CONSUMES
+
+  # USB 2.0 Port AFE
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe                 ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe                 ## CONSUMES
+
+  # USB 2.0 Port Over Current Pin
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14      ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15      ## CONSUMES
+
+  # USB 3.0 Port Over Current Pin
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8       ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9       ## CONSUMES
+
+  # Pch SerialIo I2c Pads Termination
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent
+
+  gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable               ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable                  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl          ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport             ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable            ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable  ## CONSUMES
+  gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable  ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid   ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber           ## CONSUMES
+
+[FixedPcd]
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize  ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize      ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize     ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize       ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize       ## CONSUMES
+
+[Sources]
+  PeiPchPolicyUpdatePreMem.c
+  PeiPchPolicyUpdate.c
+  PeiCpuPolicyUpdatePreMem.c
+  PeiCpuPolicyUpdate.c
+  PeiMePolicyUpdatePreMem.c
+  PeiMePolicyUpdate.c
+  PeiSaPolicyUpdate.c
+  PeiSaPolicyUpdatePreMem.c
+  PeiSiPolicyUpdate.c
+
+[Ppis]
+  gWdtPpiGuid                                   ## CONSUMES
+  gPchSpiPpiGuid                                ## CONSUMES
+  gSiPolicyPpiGuid                              ## CONSUMES
+  gSiPreMemPolicyPpiGuid                        ## CONSUMES
+  gPeiTbtPolicyPpiGuid                          ## CONSUMES
+
+[Guids]
+  gTianoLogoGuid                                ## CONSUMES
+  gSiConfigGuid                                 ## CONSUMES

+ 243 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c

@@ -0,0 +1,243 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Protocol/GraphicsOutput.h>
+#include <IndustryStandard/Bmp.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <Platform.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+  UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+  @param[in out] SiPolicyPpi     - SI_POLICY PPI
+
+  @retval EFI_SUCCESS              The policy is installed and initialized.
+**/
+EFI_STATUS
+UpdatePeiSaPolicy (
+  IN OUT   SI_POLICY_PPI      *SiPolicyPpi
+  )
+{
+  EFI_STATUS                      Status;
+  EFI_GUID                        FileGuid;
+  VOID                            *Buffer;
+  UINT8                           SaDisplayConfigTable[9] = {0};
+  VOID                            *MemBuffer;
+  BMP_IMAGE_HEADER                *BmpHeader;
+  UINT64                          BltBufferSize;
+  UINT32                          Size;
+  GRAPHICS_PEI_CONFIG             *GtConfig;
+  GNA_CONFIG                      *GnaConfig;
+  WDT_PPI                         *gWdtPei;
+  PCIE_PEI_CONFIG                 *PciePeiConfig;
+  SA_MISC_PEI_CONFIG              *MiscPeiConfig;
+  EFI_BOOT_MODE                   BootMode;
+
+  DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+  Size = 0;
+  MemBuffer = NULL;
+  BmpHeader = NULL;
+  BltBufferSize = 0;
+  GtConfig = NULL;
+  GnaConfig = NULL;
+
+  Status = GetConfigBlock((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID *)&GnaConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, (VOID *)&PciePeiConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, (VOID *)&MiscPeiConfig);
+  ASSERT_EFI_ERROR (Status);
+
+
+  //
+  // Locate WDT_PPI (ICC WDT PPI)
+  //
+  gWdtPei = NULL;
+  Status = PeiServicesLocatePpi(
+             &gWdtPpiGuid,
+             0,
+             NULL,
+             (VOID **) &gWdtPei
+             );
+
+  Status = PeiServicesGetBootMode(&BootMode);
+  ASSERT_EFI_ERROR(Status);
+
+  if (!EFI_ERROR (Status)) {
+    Buffer = NULL;
+
+    CopyMem(&FileGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(FileGuid));
+    PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+    if (Buffer == NULL) {
+      DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+    }
+
+    MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+    if ((MemBuffer != NULL) && (Buffer != NULL)) {
+      CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+      GtConfig->GraphicsConfigPtr = MemBuffer;
+    } else {
+      DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+      GtConfig->GraphicsConfigPtr = NULL;
+    }
+
+    GtConfig->PeiGraphicsPeimInit = 1;
+
+    DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
+    DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+
+    PeiGetSectionFromFv (gTianoLogoGuid, &Buffer, &Size);
+    if (Buffer == NULL) {
+      DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+    }
+
+    MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+    if ((MemBuffer != NULL) && (Buffer != NULL)) {
+      CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+      GtConfig->LogoPtr = MemBuffer;
+      GtConfig->LogoSize = Size;
+
+      //
+      // Calculate the BltBuffer needed size.
+      //
+      BmpHeader = (BMP_IMAGE_HEADER *) GtConfig->LogoPtr;
+
+      if (BmpHeader->CharB == 'B' && BmpHeader->CharM == 'M') {
+        BltBufferSize = MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpHeader->PixelHeight);
+        if (BltBufferSize < DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
+          BltBufferSize = MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
+          GtConfig->BltBufferSize    = (UINT32) BltBufferSize;
+          GtConfig->BltBufferAddress = (VOID *) AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)GtConfig->BltBufferSize));
+        } else {
+          DEBUG ((DEBUG_ERROR, "Blt Buffer Size overflow.\n"));
+          ASSERT (FALSE);
+        }
+      } else {
+        DEBUG ((DEBUG_ERROR, "Wrong Bmp Image Header.\n"));
+        ASSERT (FALSE);
+      }
+
+    } else {
+      DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+      GtConfig->LogoPtr = NULL;
+      GtConfig->LogoSize = 0;
+    }
+
+    DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoPtr));
+    DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtConfig->LogoSize));
+
+    //
+    // Display DDI Initialization ( default Native GPIO as per board during AUTO case)
+    //
+    if (PcdGet32 (PcdSaDisplayConfigTable) != 0) {
+      CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+      GtConfig->DdiConfiguration.DdiPortEdp     = SaDisplayConfigTable[0];
+      GtConfig->DdiConfiguration.DdiPortBHpd    = SaDisplayConfigTable[1];
+      GtConfig->DdiConfiguration.DdiPortCHpd    = SaDisplayConfigTable[2];
+      GtConfig->DdiConfiguration.DdiPortDHpd    = SaDisplayConfigTable[3];
+      GtConfig->DdiConfiguration.DdiPortFHpd    = SaDisplayConfigTable[4];
+      GtConfig->DdiConfiguration.DdiPortBDdc    = SaDisplayConfigTable[5];
+      GtConfig->DdiConfiguration.DdiPortCDdc    = SaDisplayConfigTable[6];
+      GtConfig->DdiConfiguration.DdiPortDDdc    = SaDisplayConfigTable[7];
+      GtConfig->DdiConfiguration.DdiPortFDdc    = SaDisplayConfigTable[8];
+    }
+  }
+
+  PciePeiConfig->DmiAspm = 0x3;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+  @param[in] NameGuid              - File GUID
+  @param[out] Address              - Pointer to the File Address
+  @param[out] Size                 - Pointer to File Size
+
+  @retval EFI_SUCCESS                Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+  IN CONST  EFI_GUID        NameGuid,
+  OUT VOID                  **Address,
+  OUT UINT32                *Size
+  )
+{
+  EFI_STATUS                           Status;
+  EFI_PEI_FIRMWARE_VOLUME_PPI          *FvPpi;
+  EFI_FV_FILE_INFO                     FvFileInfo;
+  PEI_CORE_INSTANCE                    *PrivateData;
+  UINTN                                CurrentFv;
+  PEI_CORE_FV_HANDLE                   *CoreFvHandle;
+  EFI_PEI_FILE_HANDLE                  VbtFileHandle;
+  EFI_GUID                             *VbtGuid;
+  EFI_COMMON_SECTION_HEADER            *Section;
+  CONST EFI_PEI_SERVICES               **PeiServices;
+
+  PeiServices = GetPeiServicesTablePointer();
+
+  PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+
+  Status = PeiServicesLocatePpi(
+             &gEfiFirmwareFileSystem2Guid,
+             0,
+             NULL,
+             (VOID **)&FvPpi
+             );
+  ASSERT_EFI_ERROR(Status);
+
+  CurrentFv = PrivateData->CurrentPeimFvCount;
+  CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
+
+  Status = FvPpi->FindFileByName(FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &VbtFileHandle);
+  if (!EFI_ERROR(Status) && VbtFileHandle != NULL) {
+
+    DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+    Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, VbtFileHandle, (VOID **)&VbtGuid);
+    if (!EFI_ERROR(Status)) {
+
+      DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+      Status = FvPpi->GetFileInfo(FvPpi, VbtFileHandle, &FvFileInfo);
+      Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+      if (IS_SECTION2(Section)) {
+        ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+        *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+        *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+      } else {
+        *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+        *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+      }
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+

+ 53 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h

@@ -0,0 +1,53 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PlatformBoardId.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <CpuAccess.h>
+
+#define WDT_TIMEOUT 60
+
+// BClk Frequency Limitations (in Hz)
+#define BCLK_MAX                538000000
+#define BCLK_100                100000000
+#define BCLK_GRANULARITY        1000000
+#define BCLK_100_KHZ            100000
+
+
+/**
+  PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+  @param[in] NameGuid              - File GUID
+  @param[out] Address              - Pointer to the File Address
+  @param[out] Size                 - Pointer to File Size
+
+  @retval EFI_SUCCESS                Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+  IN CONST  EFI_GUID        NameGuid,
+  OUT VOID                  **Address,
+  OUT UINT32               *Size
+  );
+
+#endif
+
+

+ 213 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c

@@ -0,0 +1,213 @@
+/** @file
+  Platform Stage System Agent initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Register/Cpuid.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <Platform.h>
+#include <PlatformBoardConfig.h>
+#include <Library/SiPolicyLib.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <Library/ConfigBlockLib.h>
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+  { EfiACPIReclaimMemory,   FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) },  // ASL
+  { EfiACPIMemoryNVS,       FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) },      // ACPI NVS (including S3 related)
+  { EfiReservedMemoryType,  FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) },     // BIOS Reserved (including S3 related)
+  { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) },       // Runtime Service Data
+  { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) },       // Runtime Service Code
+  { EfiMaxMemoryType, 0 }
+};
+
+/**
+  UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+  @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI
+
+  @retval EFI_SUCCESS              The policy is installed and initialized.
+**/
+EFI_STATUS
+UpdatePeiSaPolicyPreMem (
+  IN OUT   SI_PREMEM_POLICY_PPI      *SiPreMemPolicyPpi
+  )
+{
+  EFI_STATUS                      Status;
+  SA_MISC_PEI_PREMEM_CONFIG       *MiscPeiPreMemConfig = NULL;
+  MEMORY_CONFIG_NO_CRC            *MemConfigNoCrc = NULL;
+  SA_MEMORY_RCOMP                 *RcompData;
+  WDT_PPI                         *gWdtPei;
+  UINT8                           Index;
+  UINTN                           DataSize;
+  EFI_MEMORY_TYPE_INFORMATION     MemoryData[EfiMaxMemoryType + 1];
+  EFI_BOOT_MODE                   BootMode;
+  UINT32                          TraceHubTotalMemSize;
+  GRAPHICS_PEI_PREMEM_CONFIG      *GtPreMemConfig = NULL;
+  MEMORY_CONFIGURATION            *MemConfig = NULL;
+  PCIE_PEI_PREMEM_CONFIG          *PciePeiPreMemConfig = NULL;
+  SWITCHABLE_GRAPHICS_CONFIG      *SgGpioData = NULL;
+  IPU_PREMEM_CONFIG               *IpuPreMemPolicy = NULL;
+  OVERCLOCKING_PREMEM_CONFIG      *OcPreMemConfig = NULL;
+  VTD_CONFIG                      *Vtd = NULL;
+  UINT32                          ProcessorTraceTotalMemSize;
+
+  TraceHubTotalMemSize = 0;
+  ProcessorTraceTotalMemSize = 0;
+
+  DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdatePeiSaPolicyPreMem\n"));
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *)&Vtd);
+  ASSERT_EFI_ERROR(Status);
+
+  RcompData = MemConfigNoCrc->RcompData;
+
+  //
+  // Locate WDT_PPI (ICC WDT PPI)
+  //
+  gWdtPei = NULL;
+  Status = PeiServicesLocatePpi(
+             &gWdtPpiGuid,
+             0,
+             NULL,
+             (VOID **) &gWdtPei
+             );
+
+  Status = PeiServicesGetBootMode(&BootMode);
+  ASSERT_EFI_ERROR(Status);
+
+  MiscPeiPreMemConfig->S3DataPtr = NULL;
+  MiscPeiPreMemConfig->UserBd = 0; // It's a CRB mobile board by default (btCRBMB)
+
+  PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform));
+  MiscPeiPreMemConfig->SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
+  MiscPeiPreMemConfig->SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
+  MiscPeiPreMemConfig->SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
+  MiscPeiPreMemConfig->SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
+  MemConfig->CaVrefConfig                 = PcdGet8 (PcdMrcCaVrefConfig);
+  MemConfig->DualDimmPerChannelBoardType  = PcdGetBool (PcdDualDimmPerChannelBoardType);
+  if (PcdGet32 (PcdMrcRcompResistor)) {
+    CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor), sizeof (RcompData->RcompResistor));
+  }
+  if (PcdGet32 (PcdMrcRcompTarget)) {
+    CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget), sizeof (RcompData->RcompTarget));
+  }
+  if (PcdGet32 (PcdMrcDqByteMap)) {
+    CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX * 2);
+  }
+  if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+    CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO_ECC);
+  }
+  if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+    MemConfig->DqPinsInterleaved = PcdGetBool (PcdMrcDqPinsInterleaved);
+  }
+  if (PcdGet32 (PcdMrcSpdData)) {
+    CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+    CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+  }
+
+  MiscPeiPreMemConfig->MchBar   = (UINTN) PcdGet64 (PcdMchBaseAddress);
+  MiscPeiPreMemConfig->DmiBar   = (UINTN) PcdGet64 (PcdDmiBaseAddress);
+  MiscPeiPreMemConfig->EpBar    = (UINTN) PcdGet64 (PcdEpBaseAddress);
+  MiscPeiPreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
+  MiscPeiPreMemConfig->SmbusBar = PcdGet16(PcdSmbusBaseAddress);
+  MiscPeiPreMemConfig->TsegSize = PcdGet32(PcdTsegSize);
+  MiscPeiPreMemConfig->UserBd   = PcdGet8 (PcdSaMiscUserBd);
+  MiscPeiPreMemConfig->MmioSizeAdjustment = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
+  if (PcdGetBool (PcdPegGpioResetControl)) {
+    PciePeiPreMemConfig->PegGpioData.GpioSupport = PcdGetBool (PcdPegGpioResetSupoort);
+  } else {
+
+  }
+  PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad = PcdGet32 (PcdPeg0ResetGpioPad);
+  PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active  = PcdGetBool (PcdPeg0ResetGpioActive);
+
+  PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad = PcdGet32 (PcdPeg3ResetGpioPad);
+  PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active  = PcdGetBool (PcdPeg3ResetGpioActive);
+
+  MemConfig->CkeRankMapping = 0xAA;
+  ///
+  /// Initialize the VTD Configuration
+  ///
+  Vtd->VtdDisable = 0;
+
+  MemConfig->RMT = 1;
+  MemConfig->UserPowerWeightsEn = 0;
+  MemConfig->RaplLim2WindY = 0x0A;
+  MemConfig->ExitOnFailure = 1;
+
+  MemConfigNoCrc->PlatformMemorySize = PEI_MIN_MEMORY_SIZE + TraceHubTotalMemSize + ProcessorTraceTotalMemSize;
+  DataSize = sizeof (mDefaultMemoryTypeInformation);
+  CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
+
+  if (BootMode != BOOT_IN_RECOVERY_MODE) {
+    for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+      MemConfigNoCrc->PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+    }
+
+    OcPreMemConfig->GtMaxOcRatio = 0;
+    OcPreMemConfig->GtVoltageMode = 0;
+    OcPreMemConfig->GtVoltageOverride = 0;
+    OcPreMemConfig->GtExtraTurboVoltage = 0;
+    OcPreMemConfig->GtVoltageOffset = 0;
+    OcPreMemConfig->SaVoltageOffset = 0;
+    OcPreMemConfig->GtusMaxOcRatio = 0;
+    OcPreMemConfig->GtusVoltageMode = 0;
+    OcPreMemConfig->GtusVoltageOverride = 0;
+    OcPreMemConfig->GtusExtraTurboVoltage = 0;
+    OcPreMemConfig->GtusVoltageOffset = 0;
+
+    ///
+    /// Build the GUID'd HOB for DXE
+    ///
+    BuildGuidDataHob (
+      &gEfiMemoryTypeInformationGuid,
+      MemoryData,
+      DataSize
+      );
+  }
+
+  return EFI_SUCCESS;
+}
+
+

+ 169 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c

@@ -0,0 +1,169 @@
+/** @file
+  This file is SampleCode of the library for Intel Silicon PEI
+  Platform Policy initialization.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSiPolicyUpdate.h"
+#include <MeChipset.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ConfigBlockLib.h>
+
+STATIC SVID_SID_INIT_ENTRY mCdfSsidTablePtr[] = {
+  //
+  // SA Device(s)
+  //
+  {{{PCI_SVID_OFFSET,    SA_MC_FUN,        SA_MC_DEV,        SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM,  SA_PEG0_DEV_NUM,  SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM,  SA_PEG1_DEV_NUM,  SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM,  SA_PEG2_DEV_NUM,  SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    SA_IGD_FUN_0,     SA_IGD_DEV,       SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    SA_IPU_FUN_NUM,   SA_IPU_DEV_NUM,   SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    SA_GNA_FUN_NUM,   SA_GNA_DEV_NUM,   SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  //
+  // PCH Device(s)
+  //
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_LPC,               PCI_DEVICE_NUMBER_PCH_LPC,           DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_P2SB,              PCI_DEVICE_NUMBER_PCH_P2SB,          DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_PMC,               PCI_DEVICE_NUMBER_PCH_PMC,           DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_HDA,               PCI_DEVICE_NUMBER_PCH_HDA,           DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1,        PCI_DEVICE_NUMBER_CDF_PCH_SATA_1,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2,        PCI_DEVICE_NUMBER_CDF_PCH_SATA_2,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3,        PCI_DEVICE_NUMBER_CDF_PCH_SATA_3,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_SMBUS,             PCI_DEVICE_NUMBER_PCH_SMBUS,         DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_SPI,               PCI_DEVICE_NUMBER_PCH_SPI,           DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_TRACE_HUB,         PCI_DEVICE_NUMBER_PCH_TRACE_HUB,     DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_XHCI,              PCI_DEVICE_NUMBER_PCH_XHCI,          DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_XDCI,              PCI_DEVICE_NUMBER_PCH_XDCI,          DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_THERMAL,           PCI_DEVICE_NUMBER_PCH_THERMAL,       DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+};
+
+STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[] = {
+  //
+  // SA Device(s)
+  //
+  {{{PCI_SVID_OFFSET,    SA_MC_FUN,        SA_MC_DEV,        SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM,  SA_PEG0_DEV_NUM,  SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM,  SA_PEG1_DEV_NUM,  SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM,  SA_PEG2_DEV_NUM,  SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    SA_IGD_FUN_0,     SA_IGD_DEV,       SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    SA_IPU_FUN_NUM,   SA_IPU_DEV_NUM,   SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    SA_GNA_FUN_NUM,   SA_GNA_DEV_NUM,   SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
+  //
+  // PCH Device(s)
+  //
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_LPC,     PCI_DEVICE_NUMBER_PCH_LPC,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_P2SB,    PCI_DEVICE_NUMBER_PCH_P2SB,   DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_PMC,     PCI_DEVICE_NUMBER_PCH_PMC,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_HDA,     PCI_DEVICE_NUMBER_PCH_HDA,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_SATA,    PCI_DEVICE_NUMBER_PCH_SATA,   DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_SMBUS,   PCI_DEVICE_NUMBER_PCH_SMBUS,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_SPI,     PCI_DEVICE_NUMBER_PCH_SPI,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  //
+  // Skip PCH LAN controller
+  // PCH LAN SVID/SID may be loaded automatically from the NVM Word 0Ch/0Bh upon power up or reset
+  // depending on the "Load Subsystem ID" bit field in NVM word 0Ah
+  //
+  //{{{PCI_SVID_OFFSET,    PCI_FUNCTION_NUMBER_PCH_LAN,     PCI_DEVICE_NUMBER_PCH_LAN,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_TRACE_HUB,       PCI_DEVICE_NUMBER_PCH_TRACE_HUB,        DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0,   DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1,   DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD, PCI_DEVICE_NUMBER_PCH_CNL_SCS_SDCARD, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_XHCI,       PCI_DEVICE_NUMBER_PCH_XHCI,       DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_XDCI,       PCI_DEVICE_NUMBER_PCH_XDCI,       DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_THERMAL,    PCI_DEVICE_NUMBER_PCH_THERMAL,    DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_ISH,               PCI_DEVICE_NUMBER_PCH_ISH,           DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9,  PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{R_PCH_PCIE_CFG_SVID,  PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4,  PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4,  DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  //
+  // ME Device(s)
+  //
+  {{{PCI_SVID_OFFSET,  HECI_FUNCTION_NUMBER,  ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  HECI2_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  IDER_FUNCTION_NUMBER,  ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  SOL_FUNCTION_NUMBER,   ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  HECI3_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
+  {{{PCI_SVID_OFFSET,  HECI4_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}
+};
+
+/**
+  This function performs Silicon PEI Policy initialization.
+
+  @param[in] SiPolicy  The Silicon Policy PPI instance
+
+  @retval EFI_SUCCESS  The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicy (
+  IN OUT SI_POLICY_PPI *SiPolicy
+  )
+{
+  EFI_STATUS                         Status;
+  SI_CONFIG                          *SiConfig;
+
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &SiConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  SiConfig->CsmFlag       = 0;
+
+  if (IsCdfPch ()) {
+    SiConfig->SsidTablePtr = (UINT32*)(UINTN) mCdfSsidTablePtr;
+    SiConfig->NumberOfSsidTableEntry = (sizeof (mCdfSsidTablePtr) / sizeof (SVID_SID_INIT_ENTRY));
+  } else {
+    SiConfig->SsidTablePtr = (UINT32*)(UINTN) mSsidTablePtr;
+    SiConfig->NumberOfSsidTableEntry = (sizeof (mSsidTablePtr) / sizeof (SVID_SID_INIT_ENTRY));
+  }
+  return EFI_SUCCESS;
+}
+
+

+ 18 - 0
Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h

@@ -0,0 +1,18 @@
+/** @file
+   Header file for PEI SiPolicyUpdate.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_H_
+#define _PEI_SI_POLICY_UPDATE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/SiPolicy.h>
+
+#endif
+