PeiDTbtInitLib.c 19 KB

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  1. /** @file
  2. Thunderbolt(TM) Pei Library
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Library/PeiServicesLib.h>
  7. #include <Library/MemoryAllocationLib.h>
  8. #include <Library/BaseMemoryLib.h>
  9. #include <Library/DebugLib.h>
  10. #include <Library/GpioLib.h>
  11. #include <GpioPinsSklLp.h>
  12. #include <GpioPinsSklH.h>
  13. #include <Library/TimerLib.h>
  14. #include <Library/IoLib.h>
  15. #include <Library/MmPciLib.h>
  16. #include <Library/HobLib.h>
  17. #include <Library/PcdLib.h>
  18. #include <Library/GpioExpanderLib.h>
  19. #include <Ppi/ReadOnlyVariable2.h>
  20. #include <Base.h>
  21. #include <Library/TbtCommonLib.h>
  22. #include <TbtBoardInfo.h>
  23. #include <IndustryStandard/Pci22.h>
  24. #include <Library/PchCycleDecodingLib.h>
  25. #include <Ppi/PeiTbtPolicy.h>
  26. #include <Library/PciSegmentLib.h>
  27. #include <Library/PeiTbtPolicyLib.h>
  28. #include <Library/PchPmcLib.h>
  29. #include <Private/Library/PeiDTbtInitLib.h>
  30. /**
  31. Is host router (For dTBT) or End Point (For iTBT) present before sleep
  32. @param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER
  33. @param[in] Controller - Controller begin offset of CMOS
  34. @Retval TRUE There is a TBT HostRouter presented before sleep
  35. @Retval FALSE There is no TBT HostRouter presented before sleep
  36. BOOLEAN
  37. IsHostRouterPresentBeforeSleep(
  38. IN UINT8 ControllerType,
  39. IN UINT8 Controller
  40. )
  41. {
  42. UINT8 SavedState;
  43. SavedState = (UINT8)GetTbtHostRouterStatus();
  44. if (ControllerType == DTBT_CONTROLLER){
  45. return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) == (DTBT_SAVE_STATE_OFFSET << Controller));
  46. } else {
  47. if (ControllerType == ITBT_CONTROLLER) {
  48. return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) == (ITBT_SAVE_STATE_OFFSET << Controller));
  49. }
  50. }
  51. return 0;
  52. }
  53. **/
  54. /**
  55. Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode with PreBootAclEnable
  56. @param[in] Bus Bus number for Host Router (DTBT)
  57. @param[in] Device Device number for Host Router (DTBT)
  58. @param[in] Function Function number for Host Router (DTBT)
  59. @param[in] Timeout Time out with 100 ms garnularity
  60. @Retval true if command executes succesfully
  61. **/
  62. BOOLEAN
  63. TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(
  64. IN UINT8 Bus,
  65. IN UINT8 Device,
  66. IN UINT8 Function,
  67. IN UINT32 Timeout
  68. )
  69. {
  70. UINT64 Pcie2Tbt;
  71. UINT64 Tbt2Pcie;
  72. UINT32 RegisterValue;
  73. BOOLEAN ReturnFlag;
  74. UINT32 Command;
  75. GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
  76. GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
  77. // If PreBootAcl is Enable, we need to enable DATA bit while sending SX EXIT MAIL BOX Command
  78. Command = (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED;
  79. PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
  80. ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
  81. PciSegmentWrite32(Pcie2Tbt, 0);
  82. return ReturnFlag;
  83. }
  84. /**
  85. Set the Sleep Mode if the HR is up.
  86. @param[in] Bus Bus number for Host Router (DTBT)
  87. @param[in] Device Device number for Host Router (DTBT)
  88. @param[in] Function Function number for Host Router (DTBT)
  89. **/
  90. VOID
  91. TbtSetSxMode(
  92. IN UINT8 Bus,
  93. IN UINT8 Device,
  94. IN UINT8 Function,
  95. IN UINT8 TbtBootOn
  96. )
  97. {
  98. UINT64 TbtUsDevId;
  99. UINT64 Tbt2Pcie;
  100. UINT32 RegVal;
  101. UINT32 MaxLoopCount;
  102. UINTN Delay;
  103. UINT8 RetCode;
  104. EFI_BOOT_MODE BootMode;
  105. EFI_STATUS Status;
  106. TbtUsDevId = PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0);
  107. GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
  108. MaxLoopCount = TBT_5S_TIMEOUT; // Wait 5 sec
  109. Delay = 100 * 1000;
  110. RetCode = 0x62;
  111. Status = PeiServicesGetBootMode(&BootMode);
  112. ASSERT_EFI_ERROR(Status);
  113. if ((BootMode == BOOT_ON_S4_RESUME) && (TbtBootOn == 2)) {
  114. MaxLoopCount = TBT_3S_TIMEOUT;
  115. if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Function, MaxLoopCount)) {
  116. //
  117. // Nothing to wait, HR is not responsive
  118. //
  119. return;
  120. }
  121. }
  122. else {
  123. if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device, Function, MaxLoopCount)) {
  124. //
  125. // Nothing to wait, HR is not responsive
  126. //
  127. return;
  128. }
  129. }
  130. DEBUG((DEBUG_INFO, "Wait for Dev ID != 0xFF\n"));
  131. while (MaxLoopCount-- > 0) {
  132. //
  133. // Check what HR still here
  134. //
  135. RegVal = PciSegmentRead32(Tbt2Pcie);
  136. if (0xFFFFFFFF == RegVal) {
  137. RetCode = 0x6F;
  138. break;
  139. }
  140. //
  141. // Check completion of TBT link
  142. //
  143. RegVal = PciSegmentRead32(TbtUsDevId);
  144. if (0xFFFFFFFF != RegVal) {
  145. RetCode = 0x61;
  146. break;
  147. }
  148. MicroSecondDelay(Delay);
  149. }
  150. DEBUG((DEBUG_INFO, "Return code = 0x%x\n", RetCode));
  151. }
  152. /**
  153. set tPCH25 Timing to 10 ms for DTBT.
  154. @param[in] PEI_TBT_POLICY PeiTbtConfig
  155. @retval EFI_SUCCESS The function completes successfully
  156. @retval EFI_UNSUPPORTED dTBT is not supported.
  157. **/
  158. EFI_STATUS
  159. EFIAPI
  160. DTbtSetTPch25Timing (
  161. IN PEI_TBT_POLICY *PeiTbtConfig
  162. )
  163. {
  164. DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n"));
  165. UINT32 PchPwrmBase;
  166. //
  167. //During boot, reboot and wake tPCH25 Timing should be set to 10 ms
  168. //
  169. MmioOr32 (
  170. (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG),
  171. (BIT0 | BIT1)
  172. );
  173. DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n"));
  174. return EFI_SUCCESS;
  175. }
  176. /**
  177. Do ForcePower for DTBT Controller
  178. @param[in] PEI_TBT_POLICY PeiTbtConfig
  179. @retval EFI_SUCCESS The function completes successfully
  180. @retval EFI_UNSUPPORTED dTBT is not supported.
  181. **/
  182. EFI_STATUS
  183. EFIAPI
  184. DTbtForcePower (
  185. IN PEI_TBT_POLICY *PeiTbtConfig
  186. )
  187. {
  188. DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n"));
  189. if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) {
  190. DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad = %x \n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
  191. ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel);
  192. DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n"));
  193. MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly * 1000);
  194. DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower = 0x%x ms \n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
  195. }
  196. DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n"));
  197. return EFI_SUCCESS;
  198. }
  199. /**
  200. Clear VGA Registers for DTBT.
  201. @param[in] PEI_TBT_POLICY PeiTbtConfig
  202. @retval EFI_SUCCESS The function completes successfully
  203. @retval EFI_UNSUPPORTED dTBT is not supported.
  204. **/
  205. EFI_STATUS
  206. EFIAPI
  207. DTbtClearVgaRegisters (
  208. IN PEI_TBT_POLICY *PeiTbtConfig
  209. )
  210. {
  211. UINTN RpDev;
  212. UINTN RpFunc;
  213. EFI_STATUS Status;
  214. UINT64 BridngeBaseAddress;
  215. UINT16 Data16;
  216. DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n"));
  217. Status = EFI_SUCCESS;
  218. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  219. ASSERT_EFI_ERROR(Status);
  220. //
  221. // VGA Enable and VGA 16-bit decode registers of Bridge control register of Root port where
  222. // Host router resides should be cleaned
  223. //
  224. BridngeBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UINT32)RpFunc, 0);
  225. Data16 = PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSET);
  226. Data16 &= (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16));
  227. PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSET, Data16);
  228. DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n"));
  229. return Status;
  230. }
  231. /**
  232. Exectue Mail box command "Boot On".
  233. @param[in] PEI_TBT_POLICY PeiTbtConfig
  234. @retval EFI_SUCCESS The function completes successfully
  235. @retval EFI_UNSUPPORTED dTBT is not supported.
  236. **/
  237. EFI_STATUS
  238. EFIAPI
  239. DTbtBootOn(
  240. IN PEI_TBT_POLICY *PeiTbtConfig
  241. )
  242. {
  243. EFI_STATUS Status;
  244. UINT32 OrgBusNumberConfiguration;
  245. UINTN RpDev;
  246. UINTN RpFunc;
  247. DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n"));
  248. Status = EFI_SUCCESS;
  249. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  250. ASSERT_EFI_ERROR(Status);
  251. OrgBusNumberConfiguration = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
  252. //
  253. // Set Sec/Sub buses to 0xF0
  254. //
  255. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
  256. //
  257. //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we need to do the below:
  258. //Bios should send "Boot On" message through PCIE2TBT register
  259. //The Boot On command as described above would include the command and acknowledge from FW (with the default timeout in BIOS),
  260. //once the Boot On command is completed it is guaranteed that the AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
  261. //next step from BIOS is enumeration using SMI
  262. //
  263. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
  264. //
  265. // Exectue Mail box command "Boot On / Pre-Boot ACL"
  266. //
  267. //Command may be executed only during boot/reboot and not during Sx exit flow
  268. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 1) {
  269. if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_TIMEOUT)) {
  270. //
  271. // Nothing to wait, HR is not responsive
  272. //
  273. DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Boot On message sent failed \n"));
  274. }
  275. }
  276. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2) {
  277. if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_3S_TIMEOUT)) {
  278. //
  279. // Nothing to wait, HR is not responsive
  280. //
  281. DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Pre-Boot ACL message sent failed \n"));
  282. }
  283. }
  284. }
  285. //
  286. // Reset Sec/Sub buses to original value
  287. //
  288. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
  289. DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n"));
  290. return Status;
  291. }
  292. /**
  293. Exectue Mail box command "USB On".
  294. @param[in] PEI_TBT_POLICY PeiTbtConfig
  295. @retval EFI_SUCCESS The function completes successfully
  296. @retval EFI_UNSUPPORTED dTBT is not supported.
  297. **/
  298. EFI_STATUS
  299. EFIAPI
  300. DTbtUsbOn(
  301. IN PEI_TBT_POLICY *PeiTbtConfig
  302. )
  303. {
  304. EFI_STATUS Status;
  305. UINTN RpDev;
  306. UINTN RpFunc;
  307. UINT32 OrgBusNumberConfiguration;
  308. UINT64 TbtBaseAddress;
  309. UINT32 MaxWaitIter;
  310. UINT32 RegVal;
  311. EFI_BOOT_MODE BootMode;
  312. DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n"));
  313. Status = EFI_SUCCESS;
  314. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  315. ASSERT_EFI_ERROR(Status);
  316. OrgBusNumberConfiguration = PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
  317. //
  318. // Set Sec/Sub buses to 0xF0
  319. //
  320. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
  321. //
  322. //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup we need to do the below:
  323. //Bios should send "Usb On" message through PCIE2TBT register
  324. //The Usb On command as described above would include the command and acknowledge from FW (with the default timeout in BIOS),
  325. //once the Usb On command is completed it is guaranteed that the AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
  326. //next step from BIOS is enumeration using SMI
  327. //
  328. if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) {
  329. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
  330. MaxWaitIter = 50; // Wait 5 sec
  331. TbtBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0);
  332. //
  333. // Driver clears the PCIe2TBT Valid bit to support two consicutive mailbox commands
  334. //
  335. PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0);
  336. DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R = 0x%lx \n", TbtBaseAddress + PCIE2TBT_DTBT_R));
  337. while (MaxWaitIter-- > 0) {
  338. RegVal = PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R);
  339. if (0xFFFFFFFF == RegVal) {
  340. //
  341. // Device is not here return now
  342. //
  343. DEBUG((DEBUG_INFO, "TBT device is not present \n"));
  344. break;
  345. }
  346. if (!(RegVal & TBT2PCIE_DON_R)) {
  347. break;
  348. }
  349. MicroSecondDelay(100 * 1000);
  350. }
  351. }
  352. Status = PeiServicesGetBootMode(&BootMode);
  353. ASSERT_EFI_ERROR(Status);
  354. //
  355. // Exectue Mail box command "Usb On"
  356. //
  357. //Command may be executed only during boot/reboot and not during S3 exit flow
  358. //In case of S4 Exit send USB ON cmd only if Host Router was inactive/not present during S4 entry
  359. if ((BootMode == BOOT_ON_S4_RESUME) ) {
  360. // USB_ON cmd not required
  361. } else {
  362. if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_TIMEOUT)) {
  363. //
  364. // Nothing to wait, HR is not responsive
  365. //
  366. DEBUG((DEBUG_INFO, "<TbtPei> TbtBootSupport - Usb On message sent failed \n"));
  367. }
  368. }
  369. }
  370. //
  371. // Reset Sec/Sub buses to original value
  372. //
  373. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
  374. DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n"));
  375. return Status;
  376. }
  377. /**
  378. Exectue Mail box command "Sx Exit".
  379. @param[in] PEI_TBT_POLICY PeiTbtConfig
  380. @retval EFI_SUCCESS The function completes successfully
  381. @retval EFI_UNSUPPORTED dTBT is not supported.
  382. **/
  383. EFI_STATUS
  384. EFIAPI
  385. DTbtSxExitFlow(
  386. IN PEI_TBT_POLICY *PeiTbtConfig
  387. )
  388. {
  389. EFI_STATUS Status;
  390. UINT32 OrgBusNumberConfiguration;
  391. UINTN RpDev;
  392. UINTN RpFunc;
  393. UINT32 Count;
  394. DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n"));
  395. Status = EFI_SUCCESS;
  396. Count = 0;
  397. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  398. ASSERT_EFI_ERROR(Status);
  399. OrgBusNumberConfiguration = PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
  400. //
  401. // Set Sec/Sub buses to 0xF0
  402. //
  403. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
  404. if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2)) {
  405. //
  406. // WA: When system with TBT 3.1 device, resume SX system need to wait device ready. In document that maximum time out should be 500ms.
  407. //
  408. while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0, 0x08)) == 0xffffffff) { //End Device will be with Device Number 0x0, Function Number 0x0.
  409. MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec
  410. Count++;
  411. if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S board.
  412. break;
  413. }
  414. }
  415. //
  416. // Upon wake, if BIOS saved pre-Sx Host Router state as active (system went to sleep with
  417. // attached devices), BIOS should:
  418. // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
  419. // 2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
  420. // 3. Continue regular wake flow.
  421. //
  422. //
  423. // Exectue Mail box command and perform "wait for fast link bring-up" loop
  424. //
  425. TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn);
  426. }
  427. //
  428. // Reset Sec/Sub buses to original value
  429. //
  430. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
  431. DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n"));
  432. return Status;
  433. }
  434. /**
  435. Initialize Thunderbolt(TM)
  436. @retval EFI_SUCCESS The function completes successfully
  437. @retval others
  438. **/
  439. EFI_STATUS
  440. EFIAPI
  441. TbtInit (
  442. VOID
  443. )
  444. {
  445. EFI_STATUS Status;
  446. PEI_TBT_POLICY *PeiTbtConfig;
  447. //
  448. // Get the TBT Policy
  449. //
  450. Status = PeiServicesLocatePpi (
  451. &gPeiTbtPolicyPpiGuid,
  452. 0,
  453. NULL,
  454. (VOID **) &PeiTbtConfig
  455. );
  456. if (EFI_ERROR(Status)) {
  457. DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
  458. }
  459. ASSERT_EFI_ERROR (Status);
  460. //
  461. // Exectue Mail box command "Boot On"
  462. //
  463. Status = DTbtBootOn (PeiTbtConfig);
  464. //
  465. // Exectue Mail box command "Usb On"
  466. //
  467. Status = DTbtUsbOn (PeiTbtConfig);
  468. //
  469. //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register should be
  470. //set to 11b - 10 ms (default value is 0b - 10 us)
  471. //
  472. Status = DTbtSetTPch25Timing (PeiTbtConfig);
  473. //
  474. // Configure Tbt Force Power
  475. //
  476. Status = DTbtForcePower (PeiTbtConfig);
  477. //
  478. // VGA Enable and VGA 16-bit decode registers of Bridge control register of Root port where
  479. // Host router resides should be cleaned
  480. //
  481. Status = DTbtClearVgaRegisters (PeiTbtConfig);
  482. //
  483. // Upon wake, if BIOS saved pre-Sx Host Router state as active (system went to sleep with
  484. // attached devices), BIOS should:
  485. // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
  486. // 2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
  487. // 3. Continue regular wake flow.
  488. //
  489. Status = DTbtSxExitFlow (PeiTbtConfig);
  490. return EFI_SUCCESS;
  491. }