PeiSaPolicyUpdatePreMem.c 2.9 KB

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  1. /** @file
  2. Do Platform Stage System Agent initialization.
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiSaPolicyUpdate.h"
  7. #include <CpuRegs.h>
  8. #include <Library/CpuPlatformLib.h>
  9. #include <Guid/MemoryTypeInformation.h>
  10. #include <Guid/MemoryOverwriteControl.h>
  11. #include <Library/HobLib.h>
  12. #include <PchAccess.h>
  13. #include <SaAccess.h>
  14. #include <Library/BaseMemoryLib.h>
  15. #include <Library/MemoryAllocationLib.h>
  16. #include <Library/PeiSaPolicyLib.h>
  17. #include <Library/GpioLib.h>
  18. #include <GpioPinsSklH.h>
  19. /**
  20. Performs FSP SA PEI Policy initialization in pre-memory.
  21. @param[in][out] FspmUpd Pointer to FSP UPD Data.
  22. @retval EFI_SUCCESS FSP UPD Data is updated.
  23. @retval EFI_NOT_FOUND Fail to locate required PPI.
  24. @retval Other FSP UPD Data update process fail.
  25. **/
  26. EFI_STATUS
  27. EFIAPI
  28. PeiFspSaPolicyUpdatePreMem (
  29. IN OUT FSPM_UPD *FspmUpd
  30. )
  31. {
  32. VOID *Buffer;
  33. //
  34. // If SpdAddressTable are not all 0, it means DIMM slots implemented and
  35. // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPolicyInitPreMem.
  36. //
  37. // If SpdAddressTable all 0, this is memory down design and hardcoded SpdData
  38. // should be applied to MemorySpdPtr*.
  39. //
  40. if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8 (PcdMrcSpdAddressTable1) == 0)
  41. && (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8 (PcdMrcSpdAddressTable3) == 0)) {
  42. DEBUG ((DEBUG_INFO, "Overriding SPD data for down memory.\n"));
  43. CopyMem (
  44. (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00,
  45. (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
  46. PcdGet16 (PcdMrcSpdDataSize)
  47. );
  48. CopyMem (
  49. (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10,
  50. (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
  51. PcdGet16 (PcdMrcSpdDataSize)
  52. );
  53. }
  54. DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
  55. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
  56. if (Buffer) {
  57. CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
  58. CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
  59. }
  60. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
  61. if (Buffer) {
  62. CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
  63. CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
  64. }
  65. DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
  66. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
  67. if (Buffer) {
  68. CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
  69. }
  70. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
  71. if (Buffer) {
  72. CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
  73. }
  74. return EFI_SUCCESS;
  75. }