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CometlakeOpenBoardPkg: Add package and headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Create the CometlakeOpenBoardPkg to provide board support code. The
package may support Cometlake boards. The package serves as a board
support package in the EDK II Minimum Platform design. Silicon support
for this package is provided in CometLakeFspBinPkg in the FSP repository
and CoffeelakeSiliconPkg in the edk2-platforms repository.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Kathappan Esakkithevar 4 years ago
parent
commit
6f00e4731a
45 changed files with 5246 additions and 0 deletions
  1. 43 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeCheckIommuSupportLib.h
  2. 49 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h
  3. 131 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtSecurityLib.h
  4. 21 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiCheckIommuSupportLib.h
  5. 43 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h
  6. 61 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtTaskDispatchLib.h
  7. 261 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h
  8. 31 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h
  9. 130 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h
  10. 51 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h
  11. 36 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/DisableBmeProtocol.h
  12. 137 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h
  13. 50 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h
  14. 23 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
  15. 68 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAreaDef.h
  16. 84 0
      Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h
  17. 112 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
  18. 118 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
  19. 51 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
  20. 57 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
  21. 20 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h
  22. 1766 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
  23. 68 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
  24. 75 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpdateLib.h
  25. 27 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpdateLib.h
  26. 25 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpdateLib.h
  27. 30 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardConfigLib.h
  28. 25 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdateLib.h
  29. 29 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h
  30. 46 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflictLib.h
  31. 123 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.h
  32. 48 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.h
  33. 34 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
  34. 40 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h
  35. 141 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h
  36. 38 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h
  37. 23 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h
  38. 51 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
  39. 106 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
  40. 33 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
  41. 29 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
  42. 47 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
  43. 144 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
  44. 157 0
      Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
  45. 564 0
      Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec

+ 43 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeCheckIommuSupportLib.h

@@ -0,0 +1,43 @@
+/** @file
+  Header file for the DxeCheckIommuSupport library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+#define _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
+/**
+  Detect ME FW and Board Type and return the result via IommuSkuCheck.
+
+  IommuSkuCheck
+  BIT0: Indicate system has a Corporate CSME firmware
+  BIT1: Indicate BIOS is running on a CML RVP
+  BIT2: Indicate BIOS is running on a CFL-H RVP
+  BIT3: Indicate BIOS is running on a CFL-S 8+2 RVP
+
+  @retval Return 0 means not support, otherwise value is defined by IommuSkuCheck
+**/
+UINT8
+DetectMeAndBoard (
+  VOID
+  );
+
+/**
+  DxeCheckIommuSupport
+
+  Only WHL/CFL-H/CFL-S 8+2 Crop SKUs support Iommu.
+  This function will save sku information to PcdIommuSkuCheck.
+  BIOS will use PcdIommuSkuCheck and other factors to set PcdVTdPolicyPropertyMask on the next boot in PEI phase
+
+  This function might perform a system reset.
+**/
+EFI_STATUS
+EFIAPI
+DxeCheckIommuSupport (
+  VOID
+  );
+#endif // _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+

+ 49 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h

@@ -0,0 +1,49 @@
+/** @file
+  Prototype of the DxeTbtPolicyLib library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_LIB_H_
+#define _DXE_TBT_POLICY_LIB_H_
+
+
+/**
+  Install TBT Policy.
+
+  @param[in] ImageHandle                Image handle of this driver.
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallTbtPolicy (
+  IN  EFI_HANDLE                    ImageHandle
+  );
+
+/**
+  Update Tbt Policy Callback.
+
+  @param[in] Event         A pointer to the Event that triggered the callback.
+  @param[in] Context       A pointer to private data registered with the callback function.
+
+**/
+VOID
+EFIAPI
+UpdateTbtPolicyCallback (
+  VOID
+  );
+
+/**
+  Print DXE TBT Policy
+**/
+VOID
+TbtPrintDxePolicyConfig (
+  VOID
+  );
+#endif // _DXE_TBT_POLICY_LIB_H_
+

+ 131 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtSecurityLib.h

@@ -0,0 +1,131 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_SECURITY_LIB_H_
+#define _TBT_SECURITY_LIB_H_
+
+#include <Protocol/Tcg2Protocol.h>
+#include <Protocol/AcpiTable.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/AslUpdateLib.h>
+#include <Library/UefiLib.h>
+#include <Uefi.h>
+#include <SetupVariable.h>
+#include <OemSetup.h>
+#include <DmaRemappingTable.h>
+#include <PcieRegs.h>
+#include <Tcg2ConfigNvData.h>
+#include <TbtPolicyCommonDefinition.h>
+#include <Library/TbtCommonLib.h>
+
+#define TBT_SECURITY_EVENT_STRING                 "DMA Protection Disabled"
+#define TBT_SECURITY_EVENT_STRING_LEN             (sizeof (TBT_SECURITY_EVENT_STRING) - 1)
+
+#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING      "Security Level is Downgraded to 0"
+#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN  (sizeof (TBT_SECURITY_LEVEL_DOWNGRADED_STRING) - 1)
+
+#define GET_TBT_SECURITY_MODE    0
+#define SET_TBT_SECURITY_MODE    1
+
+typedef struct {
+  UINT8       EnableVtd;
+  BOOLEAN     SLDowngrade;
+} PCR7_DATA;
+
+/**
+  TBT Security ExtendPCR7 CallBackFunction
+  If the firmware/BIOS has an option to enable and disable DMA protections via a VT-d switch in BIOS options, then the shipping configuration must be with VT-d protection enabled.
+  On every boot where VT-d/DMA protection is disabled, or will be disabled, or configured to a lower security state, and a platform has a TPM enabled, then the platform SHALL extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA.
+  The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement in the event log using the string "DMA Protection Disabled" for the Event Data.
+  Measure and log launch of TBT Security, and extend the measurement result into a specific PCR.
+  Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement in the event log using the string "DMA Protection Disabled" for the Event Data.
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+VOID
+EFIAPI
+ExtendPCR7CallBackFunction (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  );
+
+/**
+  TBT Security DisableBme CallBackFunction
+
+  BIOS will disable BME and tear down the Thunderbolt DMAR tables at ExitBootServices
+  in order to hand off security of TBT hierarchies to the OS.
+  The BIOS is expected to either: Disable BME from power on till the OS starts configuring the devices and enabling BME Enable BME only for devices that can be protected by VT-d in preboot environment,
+  but disable BME and tear down any Thunderbolt DMAR tables at ExitBootServices()
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+VOID
+EFIAPI
+TbtDisableBmeCallBackFunction (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  );
+
+/**
+  TBT Security SetDmarOptIn CallBackFunction
+
+  A new security feature will be supported to protect against Physical DMA attacks over Thunderbolt connects.
+  In order to do this, they need a new flag added to the DMAR tables that a DMA is only permitted into RMRR at ExitBootServices().  With this flag available, OS can then Bug Check if any DMA is requested outside of the RMRR before OS supported device drivers are started.
+  ReadyToBoot callback routine to update DMAR BIT2
+  Bit definition: DMA_CONTROL_GUARANTEE
+  If Set, the platform supports blocking all DMA outside of the regions defined in the RMRR structures from ExitBootServices() until OS supported device drivers are started.
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+VOID
+EFIAPI
+SetDmarOptInCallBackFunction (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  );
+
+
+/**
+  The function install DisableBme protocol for TBT Shell validation
+**/
+VOID
+InstallDisableBmeProtocol (
+  VOID
+  );
+
+/**
+  Get or set Thunderbolt(TM) security mode
+
+  @param[in]  DelayTime           - The delay time after do ForcePwr
+  @param[in]  SecurityMode        - TBT Security Level
+  @param[in]  Gpio3ForcePwrEn     - Force GPIO to power on or not
+  @param[in]  DTbtController      - Enable/Disable DTbtController
+  @param[in]  MaxControllerNumber - Number of contorller
+  @param[in]  Action              - 0 = get, 1 = set
+
+  @retval                         - Return security level
+**/
+UINT8
+EFIAPI
+GetSetSecurityMode (
+  IN UINTN                       DelayTime,
+  IN UINT8                       SecurityMode,
+  IN UINT8                       Gpio3ForcePwrEn,
+  IN UINT8                       *DTbtController,
+  IN UINT8                       MaxControllerNumber,
+  IN UINT8                       Action
+);
+#endif
+

+ 21 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiCheckIommuSupportLib.h

@@ -0,0 +1,21 @@
+/** @file
+  Header file for the PeiCheckIommuSupport library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+#define _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
+/**
+  Check Iommu Ability base on SKU type, CSME FW type, Vtd and setup options.
+**/
+VOID
+PeiCheckIommuSupport (
+  VOID
+  );
+
+#endif // _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+

+ 43 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h

@@ -0,0 +1,43 @@
+/** @file
+  Prototype of the PeiTbtPolicyLib library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_LIB_H_
+#define _PEI_TBT_POLICY_LIB_H_
+
+/**
+  Install Tbt Policy
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallPeiTbtPolicy (
+  VOID
+  );
+
+/**
+  Update PEI TBT Policy Callback
+**/
+VOID
+EFIAPI
+UpdatePeiTbtPolicyCallback (
+  VOID
+  );
+
+/**
+  Print PEI TBT Policy
+**/
+VOID
+EFIAPI
+TbtPrintPeiPolicyConfig (
+  VOID
+  );
+#endif // _DXE_TBT_POLICY_LIB_H_
+

+ 61 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtTaskDispatchLib.h

@@ -0,0 +1,61 @@
+/** @file
+  PEI TBT Task Dispatch library Header file
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_TBT_TASK_DISPATCH_LIB_H__
+#define __PEI_TBT_TASK_DISPATCH_LIB_H__
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/PeiTbtPolicy.h>
+
+typedef
+EFI_STATUS
+(EFIAPI *TBT_TASK) (
+  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+typedef enum {
+  TBT_NULL,                ///< All policy flags turned off.
+  TBT_NORMAL   = (1 << 0), ///< Execute TBT function on cold reset.
+  TBT_S3       = (1 << 1), ///< Execute TBT function on S3 exit.
+  TBT_S4       = (1 << 2), ///< Execute TBT function on S4 exit.
+  TBT_ALL      = MAX_UINTN ///< Execute TBT function always.
+} TBT_BOOT_MODE;
+
+typedef struct {
+  TBT_TASK      TbtTask;         ///< Ptr to function to execute, with parameter list.
+  TBT_BOOT_MODE TbtBootModeFlag; ///< Call table base on TbtBootModeFlag
+  CHAR8         *String;         ///< Output string describing this task.
+} TBT_CALL_TABLE_ENTRY;
+
+/**
+  Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE
+**/
+TBT_BOOT_MODE
+TbtGetBootMode (
+  VOID
+);
+
+/**
+  TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY
+
+  @param[in] TBT_CALL_TABLE_ENTRY   TbtCallTable
+
+**/
+VOID
+TbtTaskDistpach (
+  IN TBT_CALL_TABLE_ENTRY *TbtCallTable
+);
+#endif
+

+ 261 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h

@@ -0,0 +1,261 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_COMMON_LIB_H_
+#define _TBT_COMMON_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+
+#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_RP     0 // @todo : Update when once finalized
+#define DEFAULT_PCI_BUS_NUMBER_ITBT_RP         0
+#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_RP      0x07
+
+#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0   0
+#define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0       0
+#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0    0x0D
+#define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0  0x02
+
+#define DTBT_CONTROLLER                   0x00
+#define DTBT_TYPE_PCH                     0x01
+#define DTBT_TYPE_PEG                     0x02
+#define ITBT_CONTROLLER                   0x80
+#define TBT2PCIE_ITBT_R                   0xEC
+#define PCIE2TBT_ITBT_R                   0xF0
+#define TBT2PCIE_DTBT_R                   0x548
+#define PCIE2TBT_DTBT_R                   0x54C
+
+#define INVALID_RP_CONTROLLER_TYPE        0xFF
+
+//
+//  Thunderbolt FW OS capability
+//
+#define NO_OS_NATIVE_SUPPORT    0
+#define OS_NATIVE_SUPPORT_ONLY  1
+#define OS_NATIVE_SUPPORT_RTD3  2
+
+#define ITBT_SAVE_STATE_OFFSET  BIT4 // Bits 4-7 is for ITBT (HIA0/1/2/Reserved)
+#define DTBT_SAVE_STATE_OFFSET  BIT0 // Bits 0-3 is for DTBT (only bit 0 is in use)
+/**
+Get Tbt2Pcie Register Offset
+
+@param[in]  Type      ITBT (0x80) or DTBT (0x00)
+@retval     Register  Register Variable
+**/
+
+#define GET_TBT2PCIE_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function, RegisterAddress) \
+  if (Type == ITBT_CONTROLLER) { \
+    RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_ITBT_R); \
+  } else { \
+    RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_DTBT_R); \
+  }
+
+/**
+Get Pcie2Tbt Register Offset
+
+@param[in]  Type      ITBT (0x80) or DTBT (0x00)
+@retval     Register  Register Variable
+**/
+
+#define GET_PCIE2TBT_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function, RegisterAddress) \
+  if (Type == ITBT_CONTROLLER) { \
+    RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_ITBT_R); \
+  } else { \
+    RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_DTBT_R); \
+  }
+
+#define PCIE2TBT_VLD_B                    BIT0
+#define TBT2PCIE_DON_R                    BIT0
+#define TBT_MAIL_BOX_DELAY                (100*1000)
+#define TBT_5S_TIMEOUT                    50
+#define TBT_1S_TIMEOUT                    10
+#define TBT_3S_TIMEOUT                    30
+
+#define PCIE2TBT_GO2SX                    (0x02 << 1)
+#define PCIE2TBT_GO2SX_NO_WAKE            (0x03 << 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED    (0x04 << 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
+#define PCIE2TBT_OS_UP                    (0x06 << 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL       (0x08 << 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL       (0x09 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_ENTER       (0x10 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_EXIT        (0x11 << 1)
+#define PCIE2TBT_BOOT_ON                  (0x18 << 1)
+#define PCIE2TBT_BOOT_OFF                 (0x19 << 1)
+#define PCIE2TBT_USB_ON                   (0x19 << 1)
+#define PCIE2TBT_GET_ENUMERATION_METHOD   (0x1A << 1)
+#define PCIE2TBT_SET_ENUMERATION_METHOD   (0x1B << 1)
+#define PCIE2TBT_POWER_CYCLE              (0x1C << 1)
+#define PCIE2TBT_PREBOOTACL               (0x1E << 1)
+#define CONNECT_TOPOLOGY_COMMAND          (0x1F << 1)
+
+#define RESET_HR_BIT                      BIT0
+#define ENUMERATE_HR_BIT                  BIT1
+#ifndef AUTO
+#define AUTO                              0x0
+#endif
+
+//
+//Thunder Bolt Device IDs
+//
+
+//
+// Alpine Ridge HR device IDs
+//
+#define AR_HR_2C  0x1576
+#define AR_HR_4C  0x1578
+#define AR_XHC    0x15B5
+#define AR_XHC_4C 0x15B6
+#define AR_HR_LP  0x15C0
+//
+// Alpine Ridge C0 HR device IDs
+//
+#define AR_HR_C0_2C  0x15DA
+#define AR_HR_C0_4C  0x15D3
+//
+// Titan Ridge HR device IDs
+//
+#define TR_HR_2C  0x15E7
+#define TR_HR_4C  0x15EA
+//
+//End of Thunderbolt(TM) Device IDs
+//
+
+typedef struct _DEV_ID {
+  UINT8 Segment;
+  UINT8 Bus;
+  UINT8 Dev;
+  UINT8 Fun;
+} DEV_ID;
+
+//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
+//@todo should refactor this to only be present in that driver
+//@todo also definitions like this should never be in a .h file anyway
+//@todo this is a quick hack to get things compiling for now
+#ifdef __GNUC__
+#pragma GCC diagnostic warning "-Wunused-variable"
+#endif
+
+/**
+Based on the Security Mode Selection, BIOS drives FORCE_PWR.
+
+@param[in]  GpioNumber
+@param[in]  Value
+**/
+VOID
+ForceDtbtPower(
+  IN  UINT32         GpioNumber,
+  IN  BOOLEAN        Value
+);
+
+/**
+  Get Security Level.
+  @param[in]  Type      ITBT (0x80) or DTBT (0x00)
+  @param[in]  Bus       Bus number for HIA (ITBT) or Host Router (DTBT)
+  @param[in]  Device    Device number for HIA (ITBT) or Host Router (DTBT)
+  @param[in]  Function  Function number for HIA (ITBT) or Host Router (DTBT)
+  @param[in]  Timeout   Time out with 100 ms garnularity
+**/
+UINT8
+GetSecLevel (
+  IN    BOOLEAN                 Type,
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT8                   Command,
+  IN    UINT32                  Timeout
+  );
+
+/**
+  Set Security Level.
+  @param[in]  Data      Security State
+  @param[in]  Type      ITBT (0x80) or DTBT (0x00)
+  @param[in]  Bus       Bus number for HIA (ITBT) or Host Router (DTBT)
+  @param[in]  Device    Device number for HIA (ITBT) or Host Router (DTBT)
+  @param[in]  Function  Function number for HIA (ITBT) or Host Router (DTBT)
+  @param[in]  Timeout   Time out with 100 ms garnularity
+**/
+BOOLEAN
+SetSecLevel (
+  IN    UINT8                   Data,
+  IN    BOOLEAN                 Type,
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT8                   Command,
+  IN    UINT32                  Timeout
+  );
+
+/**
+Execute TBT Mail Box Command
+
+@param[in]  Command   TBT Command
+@param[in]  Type      ITBT (0x80) or DTBT (0x00)
+@param[in]  Bus       Bus number for HIA (ITBT) or Host Router (DTBT)
+@param[in]  Device    Device number for HIA (ITBT) or Host Router (DTBT)
+@param[in]  Function  Function number for HIA (ITBT) or Host Router (DTBT)
+@param[in]  Timeout   Time out with 100 ms garnularity
+@Retval     true      if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtCommand(
+  IN    UINT8                   Command,
+  IN    BOOLEAN                 Type,
+  IN    UINT8                   Bus,
+  IN    UINT8                   Device,
+  IN    UINT8                   Function,
+  IN    UINT32                  Timeout
+);
+/**
+  Check connected TBT controller is supported or not by DeviceID
+
+  @param[in]  DeviceID              DeviceID of of TBT controller
+
+
+  @retval     TRUE                  Valid DeviceID
+  @retval     FALSE                 Invalid DeviceID
+**/
+
+BOOLEAN
+IsTbtHostRouter (
+  IN    UINT16  DeviceID
+  );
+
+/**
+  Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
+
+  @param[in]  RpNumber              Root port physical number. (0-based)
+  @param[out] RpDev                 Return corresponding root port device number.
+  @param[out] RpFun                 Return corresponding root port function number.
+
+  @retval     EFI_SUCCESS           Root port device and function is retrieved
+**/
+EFI_STATUS
+EFIAPI
+GetDTbtRpDevFun(
+  IN  BOOLEAN Type,
+  IN  UINTN   RpNumber,
+  OUT UINTN   *RpDev,
+  OUT UINTN   *RpFunc
+  );
+
+/**
+  Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
+  @param[in]  CommandOffsetAddress      Tbt2Pcie Register Address
+  @param[in]  TimeOut                   Time out with 100 ms garnularity
+  @param[in]  Tbt2PcieDone              Wait condition (wait for Bit to Clear/Set)
+  @param[out] *Tbt2PcieValue Function   Register value
+**/
+BOOLEAN
+InternalWaitforCommandCompletion (
+  IN  UINT64   CommandOffsetAddress,
+  IN  UINT32   TimeOut,
+  IN  BOOLEAN  Tbt2PcieDone,
+  OUT UINT32   *Tbt2PcieValue
+  );
+
+#endif
+

+ 31 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h

@@ -0,0 +1,31 @@
+/** @file
+TBT PEI Policy
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_H_
+#define _PEI_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define PEI_TBT_POLICY_REVISION 1
+
+/**
+ TBT PEI configuration\n
+  <b>Revision 1</b>:
+  - Initial version.
+**/
+typedef struct _PEI_TBT_POLICY {
+  DTBT_COMMON_CONFIG     DTbtCommonConfig;                                  ///< dTbt Common Configuration
+  DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]; ///< dTbt Controller Configuration
+} PEI_TBT_POLICY;
+
+#pragma pack(pop)
+
+#endif
+

+ 130 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h

@@ -0,0 +1,130 @@
+/** @file
+  PEI DTBT Init Dispatch library Header file
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_DTBT_INIT_LIB_H__
+#define __PEI_DTBT_INIT_LIB_H__
+
+#include <Private/Library/PeiTbtCommonInitLib.h>
+#include <Library/PeiTbtTaskDispatchLib.h>
+
+extern TBT_CALL_TABLE_ENTRY DTbtCallTable[];
+
+/**
+  Get Thunderbolt(TM) (TBT) PEI Policy Data.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtGetPeiTbtPolicyData (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Toggle related GPIO pin for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtToggleGPIO (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  set tPCH25 Timing to 10 ms for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSetTPch25Timing (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Do ForcePower for DTBT Controller
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtForcePower (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Clear VGA Registers for DTBT.
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtClearVgaRegisters (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Exectue Mail box command "Boot On".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtBootOn (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Exectue Mail box command "USB On".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtUsbOn (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+/**
+  Exectue Mail box command "Sx Exit".
+
+  @param[in]  PEI_TBT_POLICY   PeiTbtConfig
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     EFI_UNSUPPORTED  dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSxExitFlow (
+  IN  PEI_TBT_POLICY  *PeiTbtConfig
+);
+
+#endif
+

+ 51 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h

@@ -0,0 +1,51 @@
+/** @file
+  PEI TBT Common Init Dispatch library Header file
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_TBT_COMMON_INIT_LIB_H__
+#define __PEI_TBT_COMMON_INIT_LIB_H__
+
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiTbtTaskDispatchLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TbtCommonLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/PmcLib.h>
+#include <PlatformNvRamHookLib.h>
+
+BOOLEAN
+IsHostRouterPresentBeforeSleep(
+IN  UINT8        ControllerType,
+IN  UINT8        Controller
+);
+
+VOID
+TbtSetSxMode(
+IN    BOOLEAN                 Type,
+IN    UINT8                   Bus,
+IN    UINT8                   Device,
+IN    UINT8                   Function,
+IN    UINT8                   TbtBootOn
+);
+
+VOID
+TbtClearVgaRegisters(
+IN    UINTN                   Segment,
+IN    UINTN                   Bus,
+IN    UINTN                   Device,
+IN    UINTN                   Function
+);
+
+#endif
+

+ 36 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/DisableBmeProtocol.h

@@ -0,0 +1,36 @@
+/** @file
+  Definitions for DisableBmeProtocol
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DISABLE_TBT_BME_PROTOCOL_H_
+#define _DISABLE_TBT_BME_PROTOCOL_H_
+
+typedef struct EFI_DISABLE_BME_PROTOCOL EFI_DISABLE_TBT_BME_PROTOCOL;
+
+/**
+  This is for disable TBT BME bit under shell environment
+
+  @param[in] Event     - A pointer to the Event that triggered the callback.
+  @param[in] Context   - A pointer to private data registered with the callback function.
+**/
+typedef
+VOID
+(EFIAPI *DISABLE_BUS_MASTER_ENABLE) (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context
+  );
+
+
+struct EFI_DISABLE_BME_PROTOCOL {
+  DISABLE_BUS_MASTER_ENABLE DisableBme;
+};
+
+extern EFI_GUID gDxeDisableTbtBmeProtocolGuid;
+
+
+#endif
+

+ 137 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h

@@ -0,0 +1,137 @@
+/** @file
+TBT DXE Policy
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_H_
+#define _DXE_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define DXE_TBT_POLICY_REVISION 1
+
+//
+// TBT Common Data Structure
+//
+typedef struct _TBT_COMMON_CONFIG{
+  /**
+    TBT Security Level
+    <b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
+  **/
+  UINT32   SecurityMode      : 3;
+  /**
+    BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH GPIOs
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   Gpio5Filter       : 1;
+  /**
+     WA for TR A0 OS_UP Command, it is only needed for TR A0 stepping
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TrA0OsupWa        : 1;
+  /**
+    Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtWakeupSupport  : 1;
+  /**
+    SMI TBT enumeration
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtHotSMI         : 1;
+  /**
+    Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtHotNotify      : 1;
+  /**
+    CLK REQ for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtSetClkReq      : 1;
+  /**
+    ASPM setting for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
+  **/
+  UINT32   TbtAspm           : 2;
+  /**
+    L1 SubState for for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: L1.1, 2: L1.1 & L1.2
+  **/
+  UINT32   TbtL1SubStates    : 2;
+  /**
+    LTR for for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtLtr            : 1;
+  /**
+    PTM for for all the PCIe device in TBT daisy chain.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtPtm            : 1;
+  /**
+    TBT Dynamic AC/DC L1.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtAcDcSwitch     : 1;
+  /**
+    TBT RTD3 Support.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   Rtd3Tbt           : 1;
+  /**
+    TBT ClkReq for RTD3 Flow.
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   Rtd3TbtClkReq     : 1;
+  /**
+    TBT Win10support for Tbt FW execution mode.
+    <b>0: Disabled</b>, 1: Native, 2: Native + RTD3
+  **/
+  UINT32   Win10Support      : 2;
+  /**
+    TbtVtdBaseSecurity
+    <b>0: Disabled</b>, 1: Enabled
+  **/
+  UINT32   TbtVtdBaseSecurity: 1;
+  /**
+    Control Iommu behavior in pre-boot
+    <b>0: Disabled Iommu</b>, 1: Enable Iommu, Disable exception list, 2: Enable Iommu, Enable exception list
+  **/
+  UINT32   ControlIommu      : 3;
+  UINT32   Rsvd0             : 8; ///< Reserved bits
+  UINT16   Rtd3TbtClkReqDelay;
+  UINT16   Rtd3TbtOffDelay;
+} TBT_COMMON_CONFIG;
+
+//
+// dTBT Resource Data Structure
+//
+typedef struct _DTBT_RESOURCE_CONFIG{
+  UINT8  DTbtPcieExtraBusRsvd;     ///< Preserve Bus resource for PCIe RP that connect to dTBT Host Router
+  UINT16 DTbtPcieMemRsvd;          ///< Preserve MEM resource for PCIe RP that connect to dTBT Host Router
+  UINT8  DTbtPcieMemAddrRngMax;    ///< Alignment of Preserve MEM resource for PCIe RP that connect to dTBT Host Router
+  UINT16 DTbtPciePMemRsvd;         ///< Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
+  UINT8  DTbtPciePMemAddrRngMax;   ///< Alignment of Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
+  UINT8  Reserved[1];      ///< Reserved for DWORD alignment
+} DTBT_RESOURCE_CONFIG;
+
+/**
+ TBT DXE configuration\n
+  <b>Revision 1</b>:
+  - Initial version.
+**/
+typedef struct _DXE_TBT_POLICY_PROTOCOL {
+  TBT_COMMON_CONFIG      TbtCommonConfig;                                  ///< Tbt Common Information
+  DTBT_RESOURCE_CONFIG   DTbtResourceConfig[MAX_DTBT_CONTROLLER_NUMBER];   ///< dTbt Resource Configuration
+} DXE_TBT_POLICY_PROTOCOL;
+
+#pragma pack(pop)
+
+#endif
+

+ 50 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h

@@ -0,0 +1,50 @@
+/** @file
+  This file defines the TBT NVS Area Protocol.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_NVS_AREA_H_
+#define _TBT_NVS_AREA_H_
+
+//
+// Platform NVS Area definition
+//
+#include <TbtNvsAreaDef.h>
+
+//
+// Includes
+//
+#define TBT_NVS_DEVICE_ENABLE 1
+#define TBT_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL;
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gTbtNvsAreaProtocolGuid;
+
+/**
+ Making any TBT_NVS_AREA structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+  <b>Revision 1</b>:   - Initial version.\n
+  <b>Revision 2</b>:   - Adding TBT NVS AREA Revision, Deprecated DTbtControllerEn0, DTbtControllerEn1.\n
+**/
+#define TBT_NVS_AREA_REVISION       2
+
+//
+// Platform NVS Area Protocol
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL {
+  TBT_NVS_AREA     *Area;
+} TBT_NVS_AREA_PROTOCOL;
+
+#endif // _TBT_NVS_AREA_H_
+

+ 23 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h

@@ -0,0 +1,23 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_INFO_GUID_H_
+#define _TBT_INFO_GUID_H_
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(1)
+//
+// TBT Info HOB
+//
+typedef struct _TBT_INFO_HOB {
+  EFI_HOB_GUID_TYPE      EfiHobGuidType;
+  DTBT_COMMON_CONFIG     DTbtCommonConfig;                                  ///< dTbt Common Configuration
+  DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]; ///< dTbt Controller Configuration
+} TBT_INFO_HOB;
+#pragma pack()
+
+#endif
+

+ 68 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAreaDef.h

@@ -0,0 +1,68 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+  //
+  // Define TBT NVS Area operation region.
+  //
+
+#ifndef _TBT_NVS_AREA_DEF_H_
+#define _TBT_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+  UINT8    ThunderboltSmiFunction;                  ///< Offset 0       Thunderbolt(TM) SMI Function Number
+  UINT8    ThunderboltHotSmi;                       ///< Offset 1       SMI on Hot Plug for TBT devices
+  UINT8    TbtWin10Support;                         ///< Offset 2       TbtWin10Support
+  UINT8    TbtGpioFilter;                           ///< Offset 3       Gpio filter to detect USB Hotplug event
+  UINT8    ThunderboltHotNotify;                    ///< Offset 4       Notify on Hot Plug for TBT devices
+  UINT8    TbtSelector;                             ///< Offset 5       Thunderbolt(TM) Root port selector
+  UINT8    WAKFinished;                             ///< Offset 6       WAK Finished
+  UINT8    DiscreteTbtSupport;                      ///< Offset 7       Thunderbolt(TM) support
+  UINT8    TbtAcpiRemovalSupport;                   ///< Offset 8       TbtAcpiRemovalSupport
+  UINT32   TbtFrcPwrEn;                             ///< Offset 9       TbtFrcPwrEn
+  UINT32   TbtFrcPwrGpioNo0;                        ///< Offset 13      TbtFrcPwrGpioNo
+  UINT8    TbtFrcPwrGpioLevel0;                     ///< Offset 17      TbtFrcPwrGpioLevel
+  UINT32   TbtCioPlugEventGpioNo0;                  ///< Offset 18      TbtCioPlugEventGpioNo
+  UINT32   TbtPcieRstGpioNo0;                       ///< Offset 22      TbtPcieRstGpioNo
+  UINT8    TbtPcieRstGpioLevel0;                    ///< Offset 26      TbtPcieRstGpioLevel
+  UINT8    CurrentDiscreteTbtRootPort;              ///< Offset 27      Current Port that has plug event
+  UINT8    RootportSelected0;                       ///< Offset 28      Root port Selected by the User
+  UINT8    RootportSelected0Type;                   ///< Offset 29      Root port Type
+  UINT8    RootportSelected1;                       ///< Offset 30      Root port Selected by the User
+  UINT8    RootportSelected1Type;                   ///< Offset 31      Root port Type
+  UINT8    RootportEnabled0;                        ///< Offset 32      Root port Enabled by the User
+  UINT8    RootportEnabled1;                        ///< Offset 33      Root port Enabled by the User
+  UINT32   TbtFrcPwrGpioNo1;                        ///< Offset 34      TbtFrcPwrGpioNo
+  UINT8    TbtFrcPwrGpioLevel1;                     ///< Offset 38      TbtFrcPwrGpioLevel
+  UINT32   TbtCioPlugEventGpioNo1;                  ///< Offset 39      TbtCioPlugEventGpioNo
+  UINT32   TbtPcieRstGpioNo1;                       ///< Offset 43      TbtPcieRstGpioNo
+  UINT8    TbtPcieRstGpioLevel1;                    ///< Offset 47      TbtPcieRstGpioLevel
+  UINT8    TBtCommonGpioSupport;                    ///< Offset 48      Set if Single GPIO is used for Multi/Different Controller Hot plug support
+  UINT8    CurrentDiscreteTbtRootPortType;          ///< Offset 49      Root Port type for which SCI Triggered
+  UINT8    TrOsup;                                  ///< Offset 50      Titan Ridge Osup command
+  UINT8    TbtAcDcSwitch;                           ///< Offset 51      TBT Dynamic AcDc L1
+  UINT8    DTbtControllerEn0;                       ///< Offset 52      DTbtController0 is enabled or not.  @deprecated since revision 2
+  UINT8    DTbtControllerEn1;                       ///< Offset 53      DTbtController1 is enabled or not.  @deprecated since revision 2
+  UINT8    TbtAspm;                                 ///< Offset 54      ASPM setting for all the PCIe device in TBT daisy chain.
+  UINT8    TbtL1SubStates;                          ///< Offset 55      L1 SubState for for all the PCIe device in TBT daisy chain.
+  UINT8    TbtSetClkReq;                            ///< Offset 56      CLK REQ for all the PCIe device in TBT daisy chain.
+  UINT8    TbtLtr;                                  ///< Offset 57      LTR for for all the PCIe device in TBT daisy chain.
+  UINT8    TbtPtm;                                  ///< Offset 58      PTM for for all the PCIe device in TBT daisy chain.
+  UINT8    TbtWakeupSupport;                        ///< Offset 59      Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+  UINT16   Rtd3TbtOffDelay;                         ///< Offset 60      Rtd3TbtOffDelay TBT RTD3 Off Delay
+  UINT8    TbtSxWakeSwitchLogicEnable;              ///< Offset 62      TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB at Sx entry point. HW logic is required.
+  UINT8    Rtd3TbtSupport;                          ///< Offset 63      Enable Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
+  UINT8    Rtd3TbtClkReq;                           ///< Offset 64      Enable TBT RTD3 CLKREQ mask.
+  UINT16   Rtd3TbtClkReqDelay;                      ///< Offset 65      TBT RTD3 CLKREQ mask delay.
+  //
+  // Revision Field:
+  //
+  UINT8    TbtRevision;                             ///< Offset 67      Revison of TbtNvsArea
+} TBT_NVS_AREA;
+
+#pragma pack(pop)
+#endif
+

+ 84 - 0
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h

@@ -0,0 +1,84 @@
+/** @file
+TBT Policy Common definition.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_POLICY_COMMON_H_
+#define _TBT_POLICY_COMMON_H_
+
+#include <Library/GpioLib.h>
+#include <IndustryStandard/Pci22.h>
+
+#define MAX_DTBT_CONTROLLER_NUMBER 2
+
+#define TYPE_PCIE           0x01
+#define TYPE_PEG            0x02
+
+#pragma pack(push, 1)
+
+//
+// dTBT Force Power GPIO Data Structure
+//
+typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
+  GPIO_PAD       GpioPad;                 ///< GPIO Pad Number
+  BOOLEAN        GpioLevel;               ///< 0 = Active Low; 1 = Active High
+  UINT8          Reserved[3];             ///< Reserved for DWORD alignment
+} DTBT_FORCE_POWER_GPIO_CONFIG;
+
+//
+// dTBT CIO Plug Event GPIO Data Structure
+//
+typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
+  GPIO_PAD       GpioPad;                 ///< GPIO Pad Number
+  UINT32         AcpiGpeSignature;        ///< AcpiPlatform driver will change the XTBT method to the _Lxx or _Exx that we assign in this item.
+  BOOLEAN        AcpiGpeSignaturePorting; ///< 0 = No porting required(for 2-tier GPI GPE event architecture), 1 = Porting required(for 1-tier GPI GPE event architecture)
+  UINT8          Reserved[3];             ///< Reserved for DWORD alignment
+} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
+
+//
+// dTBT PCIE Reset GPIO Data Structure
+//
+typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
+  GPIO_PAD       GpioPad;                 ///< GPIO Pad Number
+  BOOLEAN        GpioLevel;               ///< 0 = Active Low; 1 = Active High
+  UINT8          Reserved[3];             ///< Reserved for DWORD alignment
+} DTBT_PCIE_RESET_GPIO_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_CONTROLLER_CONFIG {
+  UINT8                           DTbtControllerEn; ///< Enable/Disable DTbtController.
+  UINT8                           Type;             ///< 01-Pcie RP, 02- PEG,Reserved. <Specific according to Board Design>
+  UINT8                           PcieRpNumber;     ///< RP Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific according to Board Design>
+  DTBT_FORCE_POWER_GPIO_CONFIG    ForcePwrGpio;     ///< The GPIO pin that can force dTBT Power On. <Specific according to Board Design>
+  DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that can generate Hot-Plug event. <Specific according to Board Design>
+  DTBT_PCIE_RESET_GPIO_CONFIG     PcieRstGpio;      ///< The GPIO pin that is use to perform Reset when platform enters to Sx, it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO <Specific according to Board Design>
+  GPIO_PAD                        PdResetGpioPad;   ///< PD HRESET GPIO Pad Number
+  GPIO_PAD                        PdSxEntryGpioPad; ///< PD SX Entry GPIO Pad Number
+  GPIO_PAD                        PdSxAckGpioPad;   ///< PD SX Ack GPIO Pad Number
+  UINT8                           Reserved[1];      ///< Reserved for DWORD alignment
+} DTBT_CONTROLLER_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_COMMON_CONFIG {
+  UINT8            TbtBootOn;                    ///< Send BootOn Mailbox command when TbtBootOn is enabled.
+  UINT8            TbtUsbOn;                     ///< Send UsbOn Mailbox command when TbtBootOn is enabled.
+  UINT8            Gpio3ForcePwr;                ///< Force GPIO to power on or not
+  UINT16           Gpio3ForcePwrDly;             ///< The delay time after do ForcePwr
+  BOOLEAN          DTbtSharedGpioConfiguration;  ///< Multiple DTBT controllers share the same GPIO pin <Specific according to Board Design>
+  BOOLEAN          PcieRstSupport;               ///< 0 = Not Support, 1 = Supported. it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO
+  UINT8            SecurityMode;                 ///< 0: SL0 No Security, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
+  UINT8            ControlIommu;                 ///< Control Iommu behavior in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable exception list, 2: Enable Iommu, Enable exception list
+  UINT8            Reserved[3];                  ///< Reserved for DWORD alignment
+} DTBT_COMMON_CONFIG;
+
+#pragma pack(pop)
+
+#endif
+

+ 112 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl

@@ -0,0 +1,112 @@
+/** @file
+  ACPI DSDT table
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+  // Define a Global region of ACPI NVS Region that may be used for any
+  // type of implementation.  The starting offset and size will be fixed
+  // up by the System BIOS during POST.  Note that the Size must be a word
+  // in size to be fixed up correctly.
+
+  OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
+  Field(GNVS,AnyAcc,Lock,Preserve)
+  {
+  //
+  // Miscellaneous Dynamic Registers:
+  //
+  Offset(0),      OSYS, 16, // Offset(0),     Operating System
+  Offset(2),      SMIF, 8,  // Offset(2),     SMI Function Call (ASL to SMI via I/O Trap)
+  Offset(3),      P80D, 32, // Offset(3),     Port 80 Debug Port Value
+  Offset(7),      PWRS, 8,  // Offset(7),     Power State (AC Mode = 1)
+  //
+  // Thermal Policy Registers:
+  //
+  Offset(8),      DTSE, 8,  // Offset(8),    Digital Thermal Sensor Enable
+  Offset(9),      DTSF, 8,  // Offset(9),    DTS SMI Function Call
+  //
+  // CPU Identification Registers:
+  //
+  Offset(10),     APIC, 8,  // Offset(10),    APIC Enabled by SBIOS (APIC Enabled = 1)
+  Offset(11),     TCNT, 8,  // Offset(11),    Number of Enabled Threads
+  //
+  // PCIe Hot Plug
+  //
+  Offset(12),     OSCC, 8,  // Offset(12),    PCIE OSC Control
+  Offset(13),     NEXP, 8,  // Offset(13),    Native PCIE Setup Value
+  //
+  // Global Variables
+  //
+  Offset(14),     DSEN, 8,  // Offset(14),    _DOS Display Support Flag.
+  Offset(15),     GPIC, 8,  // Offset(15),    Global IOAPIC/8259 Interrupt Mode Flag.
+  Offset(16),     L01C, 8,  // Offset(16),    Global L01 Counter.
+  Offset(17),     LTR1, 8,  // Offset(17),    Latency Tolerance Reporting Enable
+  Offset(18),     LTR2, 8,  // Offset(18),    Latency Tolerance Reporting Enable
+  Offset(19),     LTR3, 8,  // Offset(19),    Latency Tolerance Reporting Enable
+  Offset(20),     LTR4, 8,  // Offset(20),    Latency Tolerance Reporting Enable
+  Offset(21),     LTR5, 8,  // Offset(21),    Latency Tolerance Reporting Enable
+  Offset(22),     LTR6, 8,  // Offset(22),    Latency Tolerance Reporting Enable
+  Offset(23),     LTR7, 8,  // Offset(23),    Latency Tolerance Reporting Enable
+  Offset(24),     LTR8, 8,  // Offset(24),    Latency Tolerance Reporting Enable
+  Offset(25),     LTR9, 8,  // Offset(25),    Latency Tolerance Reporting Enable
+  Offset(26),     LTRA, 8,  // Offset(26),    Latency Tolerance Reporting Enable
+  Offset(27),     LTRB, 8,  // Offset(27),    Latency Tolerance Reporting Enable
+  Offset(28),     LTRC, 8,  // Offset(28),    Latency Tolerance Reporting Enable
+  Offset(29),     LTRD, 8,  // Offset(29),    Latency Tolerance Reporting Enable
+  Offset(30),     LTRE, 8,  // Offset(30),    Latency Tolerance Reporting Enable
+  Offset(31),     LTRF, 8,  // Offset(31),    Latency Tolerance Reporting Enable
+  Offset(32),     LTRG, 8,  // Offset(32),    Latency Tolerance Reporting Enable
+  Offset(33),     LTRH, 8,  // Offset(33),    Latency Tolerance Reporting Enable
+  Offset(34),     LTRI, 8,  // Offset(34),    Latency Tolerance Reporting Enable
+  Offset(35),     LTRJ, 8,  // Offset(35),    Latency Tolerance Reporting Enable
+  Offset(36),     LTRK, 8,  // Offset(36),    Latency Tolerance Reporting Enable
+  Offset(37),     LTRL, 8,  // Offset(37),    Latency Tolerance Reporting Enable
+  Offset(38),     LTRM, 8,  // Offset(38),    Latency Tolerance Reporting Enable
+  Offset(39),     LTRN, 8,  // Offset(39),    Latency Tolerance Reporting Enable
+  Offset(40),     LTRO, 8,  // Offset(40),    Latency Tolerance Reporting Enable
+  Offset(41),     OBF1, 8,  // Offset(41),    Optimized Buffer Flush and Fill
+  Offset(42),     OBF2, 8,  // Offset(42),    Optimized Buffer Flush and Fill
+  Offset(43),     OBF3, 8,  // Offset(43),    Optimized Buffer Flush and Fill
+  Offset(44),     OBF4, 8,  // Offset(44),    Optimized Buffer Flush and Fill
+  Offset(45),     OBF5, 8,  // Offset(45),    Optimized Buffer Flush and Fill
+  Offset(46),     OBF6, 8,  // Offset(46),    Optimized Buffer Flush and Fill
+  Offset(47),     OBF7, 8,  // Offset(47),    Optimized Buffer Flush and Fill
+  Offset(48),     OBF8, 8,  // Offset(48),    Optimized Buffer Flush and Fill
+  Offset(49),     OBF9, 8,  // Offset(49),    Optimized Buffer Flush and Fill
+  Offset(50),     OBFA, 8,  // Offset(50),    Optimized Buffer Flush and Fill
+  Offset(51),     OBFB, 8,  // Offset(51),    Optimized Buffer Flush and Fill
+  Offset(52),     OBFC, 8,  // Offset(52),    Optimized Buffer Flush and Fill
+  Offset(53),     OBFD, 8,  // Offset(53),    Optimized Buffer Flush and Fill
+  Offset(54),     OBFE, 8,  // Offset(54),    Optimized Buffer Flush and Fill
+  Offset(55),     OBFF, 8,  // Offset(55),    Optimized Buffer Flush and Fill
+  Offset(56),     OBFG, 8,  // Offset(56),    Optimized Buffer Flush and Fill
+  Offset(57),     OBFH, 8,  // Offset(57),    Optimized Buffer Flush and Fill
+  Offset(58),     OBFI, 8,  // Offset(58),    Optimized Buffer Flush and Fill
+  Offset(59),     OBFJ, 8,  // Offset(59),    Optimized Buffer Flush and Fill
+  Offset(60),     OBFK, 8,  // Offset(60),    Optimized Buffer Flush and Fill
+  Offset(61),     OBFL, 8,  // Offset(61),    Optimized Buffer Flush and Fill
+  Offset(62),     OBFM, 8,  // Offset(62),    Optimized Buffer Flush and Fill
+  Offset(63),     OBFN, 8,  // Offset(63),    Optimized Buffer Flush and Fill
+  Offset(64),     OBFO, 8,  // Offset(64),    Optimized Buffer Flush and Fill
+  Offset(65),     RTD3, 8,  // Offset(65),    Runtime D3 support.
+  Offset(66),     S0ID, 8,  // Offset(66),    Low Power S0 Idle Enable
+  Offset(67),     GBSX, 8,  // Offset(67),    Virtual GPIO button Notify Sleep State Change
+  Offset(68),     PSCP, 8,  // Offset(68),    P-state Capping
+  Offset(69),     P2ME, 8,  // Offset(69),    Ps2 Mouse Enable
+  Offset(70),     P2MK, 8,  // Offset(70),    Ps2 Keyboard and Mouse Enable
+  //
+  // Driver Mode
+  //
+  Offset(71),     GIRQ, 32, // Offset(71),    GPIO IRQ
+  Offset(75),     PLCS, 8,  // Offset(75),    set PL1 limit when entering CS
+  Offset(76),     PLVL, 16, // Offset(76),    PL1 limit value
+  Offset(78),     PB1E, 8,  // Offset(78),    10sec Power button support
+  Offset(79),     ECR1, 8,  // Offset(79),    Pci Delay Optimization Ecr
+  Offset(80),     TBTS, 8,  // Offset(80),    Thunderbolt(TM) support
+  Offset(81),     TNAT, 8,  // Offset(81),    TbtNativeOsHotPlug
+  Offset(82),     TBSE, 8,  // Offset(82),    Thunderbolt(TM) Root port selector
+  Offset(83),     TBS1, 8,  // Offset(83),    Thunderbolt(TM) Root port selector
+  }
+

+ 118 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h

@@ -0,0 +1,118 @@
+/** @file
+  ACPI DSDT table
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+  // Define a Global region of ACPI NVS Region that may be used for any
+  // type of implementation.  The starting offset and size will be fixed
+  // up by the System BIOS during POST.  Note that the Size must be a word
+  // in size to be fixed up correctly.
+
+
+#ifndef _GLOBAL_NVS_AREA_DEF_H_
+#define _GLOBAL_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Registers:
+  //
+  UINT16   OperatingSystem;                         ///< Offset 0       Operating System
+  UINT8    SmiFunction;                             ///< Offset 2       SMI Function Call (ASL to SMI via I/O Trap)
+  UINT32   Port80DebugValue;                        ///< Offset 3       Port 80 Debug Port Value
+  UINT8    PowerState;                              ///< Offset 7       Power State (AC Mode = 1)
+  //
+  // Thermal Policy Registers:
+  //
+  UINT8    EnableDigitalThermalSensor;              ///< Offset 8       Digital Thermal Sensor Enable
+  UINT8    DigitalThermalSensorSmiFunction;         ///< Offset 9       DTS SMI Function Call
+  //
+  // CPU Identification Registers:
+  //
+  UINT8    ApicEnable;                              ///< Offset 10      APIC Enabled by SBIOS (APIC Enabled = 1)
+  UINT8    ThreadCount;                             ///< Offset 11      Number of Enabled Threads
+  //
+  // PCIe Hot Plug
+  //
+  UINT8    PcieOSCControl;                          ///< Offset 12      PCIE OSC Control
+  UINT8    NativePCIESupport;                       ///< Offset 13      Native PCIE Setup Value
+  //
+  // Global Variables
+  //
+  UINT8    DisplaySupportFlag;                      ///< Offset 14      _DOS Display Support Flag.
+  UINT8    InterruptModeFlag;                       ///< Offset 15      Global IOAPIC/8259 Interrupt Mode Flag.
+  UINT8    L01Counter;                              ///< Offset 16      Global L01 Counter.
+  UINT8    LtrEnable[24];                           ///< Offset 17      Latency Tolerance Reporting Enable
+                                                    ///< Offset 18      Latency Tolerance Reporting Enable
+                                                    ///< Offset 19      Latency Tolerance Reporting Enable
+                                                    ///< Offset 20      Latency Tolerance Reporting Enable
+                                                    ///< Offset 21      Latency Tolerance Reporting Enable
+                                                    ///< Offset 22      Latency Tolerance Reporting Enable
+                                                    ///< Offset 23      Latency Tolerance Reporting Enable
+                                                    ///< Offset 24      Latency Tolerance Reporting Enable
+                                                    ///< Offset 25      Latency Tolerance Reporting Enable
+                                                    ///< Offset 26      Latency Tolerance Reporting Enable
+                                                    ///< Offset 27      Latency Tolerance Reporting Enable
+                                                    ///< Offset 28      Latency Tolerance Reporting Enable
+                                                    ///< Offset 29      Latency Tolerance Reporting Enable
+                                                    ///< Offset 30      Latency Tolerance Reporting Enable
+                                                    ///< Offset 31      Latency Tolerance Reporting Enable
+                                                    ///< Offset 32      Latency Tolerance Reporting Enable
+                                                    ///< Offset 33      Latency Tolerance Reporting Enable
+                                                    ///< Offset 34      Latency Tolerance Reporting Enable
+                                                    ///< Offset 35      Latency Tolerance Reporting Enable
+                                                    ///< Offset 36      Latency Tolerance Reporting Enable
+                                                    ///< Offset 37      Latency Tolerance Reporting Enable
+                                                    ///< Offset 38      Latency Tolerance Reporting Enable
+                                                    ///< Offset 39      Latency Tolerance Reporting Enable
+                                                    ///< Offset 40      Latency Tolerance Reporting Enable
+  UINT8    ObffEnable[24];                          ///< Offset 41      Optimized Buffer Flush and Fill
+                                                    ///< Offset 42      Optimized Buffer Flush and Fill
+                                                    ///< Offset 43      Optimized Buffer Flush and Fill
+                                                    ///< Offset 44      Optimized Buffer Flush and Fill
+                                                    ///< Offset 45      Optimized Buffer Flush and Fill
+                                                    ///< Offset 46      Optimized Buffer Flush and Fill
+                                                    ///< Offset 47      Optimized Buffer Flush and Fill
+                                                    ///< Offset 48      Optimized Buffer Flush and Fill
+                                                    ///< Offset 49      Optimized Buffer Flush and Fill
+                                                    ///< Offset 50      Optimized Buffer Flush and Fill
+                                                    ///< Offset 51      Optimized Buffer Flush and Fill
+                                                    ///< Offset 52      Optimized Buffer Flush and Fill
+                                                    ///< Offset 53      Optimized Buffer Flush and Fill
+                                                    ///< Offset 54      Optimized Buffer Flush and Fill
+                                                    ///< Offset 55      Optimized Buffer Flush and Fill
+                                                    ///< Offset 56      Optimized Buffer Flush and Fill
+                                                    ///< Offset 57      Optimized Buffer Flush and Fill
+                                                    ///< Offset 58      Optimized Buffer Flush and Fill
+                                                    ///< Offset 59      Optimized Buffer Flush and Fill
+                                                    ///< Offset 60      Optimized Buffer Flush and Fill
+                                                    ///< Offset 61      Optimized Buffer Flush and Fill
+                                                    ///< Offset 62      Optimized Buffer Flush and Fill
+                                                    ///< Offset 63      Optimized Buffer Flush and Fill
+                                                    ///< Offset 64      Optimized Buffer Flush and Fill
+  UINT8    Rtd3Support;                             ///< Offset 65      Runtime D3 support.
+  UINT8    LowPowerS0Idle;                          ///< Offset 66      Low Power S0 Idle Enable
+  UINT8    VirtualGpioButtonSxBitmask;              ///< Offset 67      Virtual GPIO button Notify Sleep State Change
+  UINT8    PstateCapping;                           ///< Offset 68      P-state Capping
+  UINT8    Ps2MouseEnable;                          ///< Offset 69      Ps2 Mouse Enable
+  UINT8    Ps2KbMsEnable;                           ///< Offset 70      Ps2 Keyboard and Mouse Enable
+  //
+  // Driver Mode
+  //
+  UINT32   GpioIrqRoute;                            ///< Offset 71      GPIO IRQ
+  UINT8    PL1LimitCS;                              ///< Offset 75      set PL1 limit when entering CS
+  UINT16   PL1LimitCSValue;                         ///< Offset 76      PL1 limit value
+  UINT8    TenSecondPowerButtonEnable;              ///< Offset 78      10sec Power button support
+  UINT8    PciDelayOptimizationEcr;                 ///< Offset 79      Pci Delay Optimization Ecr
+  UINT8    TbtSupport;                              ///< Offset 80      Thunderbolt(TM) support
+  UINT8    TbtNativeOsHotPlug;                      ///< Offset 81      TbtNativeOsHotPlug
+  UINT8    TbtSelector;                             ///< Offset 82      Thunderbolt(TM) Root port selector
+  UINT8    TbtSelector1;                            ///< Offset 83      Thunderbolt(TM) Root port selector
+} EFI_GLOBAL_NVS_AREA;
+
+#pragma pack(pop)
+#endif
+

+ 51 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h

@@ -0,0 +1,51 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ATTEMPT_USB_FIRST_H_
+#define _ATTEMPT_USB_FIRST_H_
+
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
+  UINT8 RevisonId;         // Structure Revision ID
+  UINT8 HotkeyTriggered;   // Hot key status
+} ATTEMPT_USB_FIRST_HOTKEY_INFO;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
+  UINT8 UsbBootPrior;
+} ATTEMPT_USB_FIRST_VARIABLE;
+#pragma pack()
+
+//
+// Volatile variable definition for Attempt USB first features
+//
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
+  UINT8 RevisonId;        // Structure Revision ID
+  UINT8 UsbFirstEnable;   // Attempt USB First is enabled or not
+} ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
+#pragma pack()
+
+//
+// Volatile variable definition for third party Default Enabling via UEFI Variable.
+//
+#pragma pack(1)
+typedef struct _ENABLE_CUSTOM_DEFAULTS{
+  UINT32 EnableCustomDefaults;
+} ENABLE_CUSTOM_DEFAULTS;
+#pragma pack()
+
+#define COENG_DEFAULTS_UNKNOWN   0
+#define COENG_DEFAULTS_SUPPORTED 1
+#define COENG_DEFAULTS_VAR_EXITS 2
+#define COENG_DEFAULTS_VAR_SET   4
+#define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED | COENG_DEFAULTS_VAR_EXITS |COENG_DEFAULTS_VAR_SET)
+
+extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
+extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
+#endif
+

+ 57 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h

@@ -0,0 +1,57 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPUSMM_H_
+#define _CPUSMM_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPUSMM_GUID { 0x90d93e09, 0x4e91, 0x4b3d, { 0x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81 }}
+#define CPUSMM_SETUP_NAME             L"CpuSmm"
+
+#pragma pack(1)
+typedef struct {
+  UINT8     CpuSmmMsrSaveStateEnable;
+  UINT8     CpuSmmCodeAccessCheckEnable;
+  UINT8     CpuSmmUseDelayIndication;
+  UINT8     CpuSmmUseBlockIndication;
+  UINT8     CpuSmmUseSmmEnableIndication;
+  UINT8     CpuSmmProcTraceEnable;
+} CPU_SMM;
+#pragma pack()
+
+#ifndef OFFSET_OF
+#ifdef __GNUC__
+#if __GNUC__ >= 4
+#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
+#endif
+#endif
+#endif
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
+#define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYPE##Field[(OFFSET_OF(TYPE, Field) == Offset) / (OFFSET_OF(TYPE, Field) == Offset)]
+
+//
+// If TpmSupport/MorStae isn't in this offset, build failure (0 size array or divided by 0) will be generated.
+// Platform DSC file maps the two field to HII PCD so the offset value is critical.
+//
+VERIFY_OFFSET (CPU_SMM, CpuSmmMsrSaveStateEnable, 0x0);
+VERIFY_OFFSET (CPU_SMM, CpuSmmCodeAccessCheckEnable, 0x1);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseDelayIndication, 0x2);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseBlockIndication, 0x3);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseSmmEnableIndication, 0x4);
+VERIFY_OFFSET (CPU_SMM, CpuSmmProcTraceEnable, 0x5);
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
+

+ 20 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h

@@ -0,0 +1,20 @@
+/** @file
+  This header file provides definitions of firmware configuration.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FIRMWARE_CONFIGURATION_H_
+#define _FIRMWARE_CONFIGURATION_H_
+
+typedef enum {
+  FwConfigDefault = 0,
+  FwConfigProduction,
+  FwConfigTest,
+  FwConfigMax
+} FW_CONFIG;
+
+#endif
+

+ 1766 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h

@@ -0,0 +1,1766 @@
+/** @file
+Header file for GOP Configuration Library
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GOP_CONFIG_LIB_H_
+#define _GOP_CONFIG_LIB_H_
+
+#include <Library/DebugLib.h>
+#include <Uefi/UefiBaseType.h>
+#pragma pack(1)
+#define GOP_CONFIG_VBT_REVISION 0xC1
+
+#define ChildStruct_MAX                       8         ///< Maximum number of child structures in VBT
+#define CompressionStruct_MAX                 2         ///< Maximum number of compression parameter structures in VBT.
+#define NO_DEVICE                             0x00      ///< Defines a null display class.
+#define DISPLAY_PORT_ONLY                     0x68C6    ///< Defines a display class of Integrated Display Port Only
+#define DISPLAY_PORT_HDMI_DVI_COMPATIBLE      0x60D6    ///< Defines a display class of Integrated DisplayPort with HDMI/DVI Compatible
+#define DISPLAY_PORT_DVI_COMPATIBLE           0x68D6    ///< Defines a display class of Integrated DisplayPort with DVI Compatible
+#define HDMI_DVI                              0x60D2    ///< Defines a display class of Integrated HDMI/DVI
+#define DVI_ONLY                              0x68D2    ///< Defines a display class of Integrated DVI Only
+#define MIPI_ONLY                             0x1400
+#define eDP_ONLY                              0x1806    ///< Defines a display class of eDP only
+#define AUX_CHANNEL_A                         0x40
+#define AUX_CHANNEL_B                         0x10
+#define AUX_CHANNEL_C                         0x20
+#define AUX_CHANNEL_D                         0x30
+#define NO_PORT                               0x00      ///< Defines a output port NA
+#define HDMI_B                                0x01      ///< Defines a output port HDMI-B
+#define HDMI_C                                0x02      ///< Defines a output port HDMI-C
+#define HDMI_D                                0x03      ///< Defines a output port HDMI-D
+#define HDMI_F                                0x0E      ///< Defines a output port HDMI-D
+#define DISPLAY_PORT_A                        0x0A      ///< Defines a output port DisplayPort A
+#define DISPLAY_PORT_B                        0x07      ///< Defines a output port DisplayPort B
+#define DISPLAY_PORT_C                        0x08      ///< Defines a output port DisplayPort C
+#define DISPLAY_PORT_D                        0x09      ///< Defines a output port DisplayPort D
+#define DISPLAY_PORT_E                        0x0B      ///< Defines a output port DisplayPort E
+#define DISPLAY_PORT_F                        0x0D      ///< Defines a output port DisplayPort F
+#define PORT_MIPI_A                           0x15      ///< Mipi Port A
+#define PORT_MIPI_C                           0x17      ///< Mipi Port C
+
+typedef struct {
+  UINT16  Dclk;                         // DClk in 10 KHz
+  UINT8   HActive;                      // HActive [7:0]
+  UINT8   HBlank;                       // HBlank [7:0]
+  UINT8   HA_HB_UpperNibble;            // Upper nibble = HActive [11:8]
+  UINT8   VActive;                      // VActive [7:0]
+  UINT8   VBlank;                       // VBlank [7:0]
+  UINT8   VA_VB_UpperNibble;            // Upper nibble = VActive [11:8]
+  UINT8   HSyncOffset;                  // HSync offset from blank start LSB
+  UINT8   HPulseWidth;                  // HSync Pulse Width, LSB
+  UINT8   VsyncOffset_VpulseWidth_LSB;  // Bits 7:4 = VSync offset [3:0]
+  UINT8   HSO_HSPW_V_High;              // Bits 7:6 = HSync Offset [9:8]
+  UINT8   HorImageSize;                 // Horizontal Image Size
+  UINT8   VerImageSize;                 // Vertical Image Size
+  UINT8   HIS_VIS_High;                 // UpperLmtH_V Upper limits of H. and V. image size
+  UINT8   HBorder;                      // Horizontal Border
+  UINT8   VBorder;                      // Vertical Border
+  UINT8   Flags;                        // Flags
+} DTD_STRUCTURE;                        // 18 Bytes
+
+typedef struct {
+  UINT16  XRes;
+  UINT16  YRes;
+  UINT32  SerialNo;
+  UINT8   Week;
+  UINT8   Year;
+} PID_DATA;                             // 10 Bytes
+
+//
+// VBT Header
+//
+/**
+  This structure defines the VBT Header.
+**/
+typedef struct {
+  UINT8   Product_String[20]; ///< "$VBT_Cannonlake" is the product string
+  UINT16  Version_Num;        ///< Defines the VBT Header version number.
+  UINT16  Header_Size;        ///< Defines the size of VBT Header.
+  UINT16  Table_Size;         ///< Defines the size of complete VBT.
+  UINT8   Checksum;           ///< Defines the checksum of entire VBT
+  UINT8   Reserved1;          ///< Reserved field 1 of 1 byte.
+  UINT32  Bios_Data_Offset;   ///< Defines the offset of VBT Data block.
+  UINT32  Aim_Data_Offset[4]; ///< 4 reserved pointers to VBT data blocks.
+} VBT_HEADER;
+
+/**
+  This structure defines the VBT BIOS Data Block Header
+**/
+typedef struct {
+  UINT8   BDB_Signature[16];  ///< Defines the Bios Data Block signature "BIOS_DATA_BLOCK".
+  UINT16  BDB_Version;        ///< Defines the VBT (data) version.
+  UINT16  BDB_Header_Size;    ///< Defines the size of VBT Bios data block header.
+  UINT16  BDB_Size;           ///< Defines the size of Bios data block.
+} VBT_BIOS_DATA_HEADER;
+
+/**
+  This structure defines the BMP Signon Message and Copyright Message Structure
+**/
+typedef struct {
+  UINT8   BlockId;            ///< Defines Block ID : 254
+  UINT16  BlockSize;          ///< Defines the size of BMP Signon block.
+
+  UINT16  Bmp_BIOS_Size;      ///< Defines the BIOS size 32k/48k/64k.
+  UINT8   BIOS_Type;          ///< Defines the type of BIOS desktop or mobile.
+  UINT8   RelStatus;          ///< Defines the release status of the current GOP driver.
+  UINT8   BIOS_HW;            ///< Defines the Hardware i.e. Cannonlake.
+  UINT8   INT_HW;             ///< Defines the integrated hardware supported eDP/HDMI/DP.
+  UINT8   Build_Number[4];    ///< Defines the build number string.
+  UINT8   SignOn[155];        ///< Defines the sign on message.
+  UINT8   CopyRight[61];      ///< Defines the copyright message.
+} BMP_STRUCTURE_SIGNON;
+
+/**
+  This structure defines the BMP General Bits
+**/
+typedef struct {
+  UINT16  bmp_BIOS_CS;          ///< Defines the start of BIOS code segment
+  UINT8   bmp_DOS_Boot_Mode;    ///< Defines the mode number to set when DOS is boot
+  UINT8   bmp_BW_Percent;       ///< Set percentage of total memory BW
+  UINT8   bmp_Popup_Mem_Size;   ///< Default Popup memory size in KB
+  UINT8   bmp_Resize_PCI_BIOS;  ///< BIOS size granularity in 0.5 KB
+  UINT8   Switch_CRT_To_DDC2;   ///< Obsolete field: Is the CRT already switched to DDC2
+  UINT8   bmp_Allow_Config;     ///< Bit 1 : 1, Enable aspect ratio for DOS
+                                ///< Bit 0 : 1, Allow boot to DVI even if it is not attached.
+} BMPGEN;
+
+/**
+  This structure defines Block 254 (BMP structure)
+**/
+typedef struct {
+  BMP_STRUCTURE_SIGNON    bmp_Signon_Message;   ///< Instance of signon and copyright message structure
+  BMPGEN                  bmp_General_Bytes;    ///< Instance of BMP General Bits structure.
+} BLOCK254_BMP_Structure;
+
+/**
+  This structure defines Block 1 (General Bytes Definitions)
+**/
+typedef struct {
+  UINT8   BlockId;        ///< Defines the Block ID (1)
+  UINT16  BlockSize;      ///< Defines the size of General bytes definition block.
+
+  /**
+  BMP General Bit Definitions 1\n
+  Bit 7 = DVO A color flip bit
+    = 0, No DVO A color flip
+    = 1, Flip DVO A color
+  Bits 6:4 = Clear screen (CLS) after Signon
+      = 000, No CLS
+      = 001, 0.5 sec pause and then CLS
+      = 010, 1.0 sec pause and then CLS
+      = 011, 1.5 sec pause and then CLS
+      = 100, 2.0 sec pause and then CLS
+      = 101, 2.5 sec pause and then CLS
+      = 110, 3.0 sec pause and then CLS
+      = 111, 3.5 sec pause and then CLS
+  Bit 3 = 1  Enable Display Signon
+  Bit 2 = 1  Enable Flex-aim Support
+  Bits 1:0 = Flat panel fitting enabling
+      = 00, Centering
+      = 01, Reserved
+      = 10, Aspect scaling
+      = 11, Fullscreen
+  **/
+  union {
+    UINT8  Value;
+    struct {
+      UINT8 PanelFitterEnabling:2;
+      UINT8 FlexAimSupportEnable:1;
+      UINT8 DisplaySignonEnable:1;
+      UINT8 ClearScreenTime:3;
+      UINT8 DvoAColorFlipEnable:1;
+    } Bits;
+  } bmp_Bits_1;
+
+  /**
+  BMP General Bit Definitions\n
+  Bit 7 = Hot plug support
+    = 0, Hot plug disabled
+    = 1, Hot plug enabled
+  Bit 6 = Dynamic CD clock feature
+    = 0, Dynamic CD clock feature is disabled
+    = 1, Dynamic CD clock feature is enabled
+  Bit 5 = Underscan support for VGA timings
+  Bit 4 = Disable SSC in Dual Display Twin Mode. (This field is obsolete now. Kept for VBIOS only.)
+    = 0, No
+    = 1, Yes
+  Bit 3 = LFP power state on override by 5f64h,08h
+    = 0, No Override
+    = 1, Override
+  Bit 2 = Internal LVDS SSC frequency. (This field is obsolete now. Kept for VBIOS only.)
+    = 0, 96/120MHz
+    = 1, 100MHz
+  Bit 1 = internal LVDS SSC (Spread Spectrum Clock) (This field is obsolete now. Kept for VBIOS only.)
+    = 0, Disabled
+    = 1, Enabled
+  Bit 0 = KvmrSessionEnable.
+    = 0, Disabled
+    = 1, Enabled
+  **/
+  union {
+    UINT8 Value;
+    struct {
+      UINT8 KvmrSessionEnable:1;
+      UINT8 Reserved_1:5;
+      UINT8 DynamicCdClockEnable:1;
+      UINT8 HotPlugEnable:1;
+    } Bits;
+  } bmp_Bits_2;
+
+  /**
+  BMP General Bit Definitions 3\n
+  Bit 7 = Ignore strap status
+      = 0 Do not ignore
+      = 1 Ignore
+  Bit 6 = Panel Timing algorithm
+      = 0 Preferred timings
+      = 1 Best fit timings
+  Bit 5 Copy iLFP DTD to SDVO LVDS DTD
+      = 0 Don't copy DTD
+      = 1 Copy DTD to
+  Bit 4 = VBIOS normal/extd. DT mode
+      = 0 Normal mode
+      = 1 DUAL mode
+  Bit 3 = FDI RX Polarity
+      = 0 Normal
+      = 1 Inverted
+  Bit 2 = Enable 180 Degree Rotation
+      = 0  Disable
+      = 1  Enable
+  Bit 1 = Single DVI-I connector for CRT and DVI display: Obsolete field
+      = 0 Disabled
+      = 1 Enabled
+  Bit 0 = Smooth Vision
+      = 0  Disabled
+      = 1  Enabled
+  **/
+  union {
+    UINT8 Value;
+    struct {
+      UINT8 Reserved1:1;
+      UINT8 SingleDviiCrtConnector:1;
+      UINT8 Enable180DegRotation:1;
+      UINT8 FdiRxPolarity:1;
+      UINT8 Reserved2:4;
+    } Bits;
+  } bmp_Bits_3;
+
+  UINT8   Reserved;     ///< Reserved field. It was Legacy_Monitor_Detect in previous platforms.
+
+  /**
+  Integrated display device support\n
+  Bits 7:6 = Reserved
+  Bit 5 = DP SSC Dongle Enable/Disable
+  Bit 4 = DP SSC Frequency. (This field is obsolete now. Kept for VBIOS only.)
+    = 0, 96 MHz
+    = 1, 100 MHz
+  Bit 3 = DP SSC Enable
+    = 0, Disable
+    = 1, Enable
+  Bit 2 = Integrated EFP support
+    = 0, Disable
+    = 1, Enable
+  Bit 1 = Integrated TV support. (This field is obsolete now. Kept for VBIOS only.)
+    = 0, Disable
+    = 1, Enable
+  Bit 0 = Integrated CRT support: Obsolete field
+    = 0, Disable
+    = 1, Enable
+  **/
+  union {
+    UINT8 Value;
+    struct {
+      UINT8 CrtSupported:1;
+      UINT8 TvSupported:1;
+      UINT8 EfpSupported:1;
+      UINT8 DpSscEnable:1;
+      UINT8 DpSscFrequency:1;
+      UINT8 DpDongleSscEnable:1;
+      UINT8 Reserved1:2;
+    } Bits;
+  } Int_Displays_Support;
+} VBT_GENERAL1_INFO;
+
+/**
+  This defines the Structure of PRD Boot Table Entry
+**/
+typedef struct {
+  UINT8 AttachBits;     ///< Bitmap representing the displays attached currently.
+  UINT8 BootDev_PipeA;  ///< Bitmap representing the display to boot on Pipe A.
+  UINT8 BootDev_PipeB;  ///< Bitmap representing the display to boot on Pipe B.
+} PRD_TABLE;
+
+/**
+  This defines the structure of Block 254 (PRD Boot Table/Child Device List)
+**/
+typedef struct {
+  UINT8     BlockId;    ///< Defines the Block ID (254)
+  UINT16    BlockSize;  ///< Defines the size of Block 254
+
+  PRD_TABLE PRDTable[16];                     ///< Defines the Child device list for enumerating child handles.
+  UINT16    PRD_Boot_Table_Number_Of_Entries; ///< Number of entries in child device list.
+} PRD_BOOT_TABLE;
+
+/**
+  This defines the Structure for a CHILD_STRUCT (used for all the displays).
+**/
+typedef struct {
+  UINT16  DeviceHandle;         ///< Unique ID indicating the group of display device (LFP/EFP1/EFP2/EFP3/EFP4).
+  UINT16  DeviceClass;          ///< Indicates the class of display device.
+  UINT8   I2CSpeed;             ///< Defines the I2C speed to be used for I2C transaction.
+  /**
+  Defines the DP on board redriver configuration.
+  BIT[7]    : Reserved
+  BIT[6]    : Is On Board DP Redriver Present
+          0 : No
+          1 : Yes
+  BIT[5:3]  : On Board Redriver VSwing Level
+          0 : Level 0
+          1 : Level 1
+          2 : Level 2
+          3 : Level 3
+     Others : Reserved
+  BIT[2:0]  : On Board Redriver PreEmph Level
+          0 : Level 0
+          1 : Level 1
+          2 : Level 2
+          3 : Level 3
+  Others    : Reserved
+  **/
+  union{
+  UINT8 Value;
+  struct {
+    UINT8 OnBoardPreEmphLevel:3;
+    UINT8 OnBoardVSwingLevel:3;
+    UINT8 OnBoardRedriverPresent:1;
+    UINT8 Reserved:1;
+    } Bits;
+  } DpOnBoardRedriver;
+
+  /**
+  Defines the DP on dock redriver configuration.
+  BIT[7]    : Reserved
+  BIT[6]    : Is On Dock DP Redriver Present
+          0 : No
+          1 : Yes
+  BIT[5:3]  : On Dock Redriver VSwing Level
+          0 : Level 0
+          1 : Level 1
+          2 : Level 2
+          3 : Level 3
+     Others : Reserved
+  BIT[2:0]  : On Dock Redriver PreEmph Level
+          0 : Level 0
+          1 : Level 1
+          2 : Level 2
+          3 : Level 3
+  Others    : Reserved
+  **/
+  union {
+  UINT8 Value;
+  struct {
+    UINT8 OnDockPreEmphLevel:3;
+    UINT8 OnDockVSwingLevel:3;
+    UINT8 OnDockRedriverPresent:1;
+    UINT8 Reserved:1;
+    } Bits;
+  } DpOnDockRedriver;
+
+  /**
+
+  Defines the HDMI level shifter configuration.
+  BIT[7:5]  : Hdmi Maximum data rate
+  BIT[4:0]  : Hdmi Level shifter value
+
+  **/
+  union{
+  UINT8 Value;
+  struct {
+    UINT8 HdmiLevelShifterValue:5;
+    UINT8 HdmiMaxDataRateBits:3;
+    } Bits;
+  } HdmiLevelShifterConfig;
+
+  UINT16  EFPDTDBufferPointer;  ///< Pointer to the DTD timing to be used in case of edidless EFP.
+
+  /**
+  Defines the first set of flags.
+  BIT[7-4]  : Reserved
+  BIT[3]    : Dual pipe ganged display support
+          0 : Display uses a single pipe/port
+          1 : Display uses two distinct pipes/ports.
+  BIT[2]    : Compression Method Select
+          0 : Compression using picture parameter set (PPS)
+          1 : Compression using Capability parameter set (CPS)
+  BIT[1]    : Compression enable/disable for this display.
+          0 : Disabled
+          1 : Enabled
+  BIT[0]    : EDID less EFP Enable
+          0 : Enable support for EDID less EFP.
+          1 : Disable support for EDID less EFP.
+  **/
+  union {
+  UINT8 Value;
+  struct {
+    UINT8 EdidlessEfpEnable:1;
+    UINT8 CompressionEnable:1;
+    UINT8 CompressionMethod:1;
+    UINT8 IsDualPortEnabled:1;
+    UINT8 Reserved:4;
+    } Bits;
+  } Flags0;
+
+  /**
+  Defines the compression index field for the display.
+  BITS[7-4]  : Reserved
+  BITS[3-0]  : Compression Structure index in the block 55.
+        0x0  : Index 0 in block 55
+        0x1  : Index 1 in block 55
+        0xF  : Not Applicable.
+      Others : Reserved
+  **/
+  union {
+  UINT8 Value;
+  struct {
+    UINT8 IndexInBlock55:4;
+    UINT8 Reserved:4;
+    } Bits;
+  } CompressionStructureIndex;
+
+  UINT8   SlaveDdiPort;         ///< The DVO port number of slave DDI to be used in case Flags0[3] = 1.
+
+  UINT8   Reserved_1;           ///< Reserved and might be used in other platforms.
+  UINT16  AddInOffset;          ///< Obsolete field.
+  UINT8   DVOPort;              ///< Specifies the port number of the display device represented in the device class.
+  UINT8   I2CBus;               ///< Specifies the GMBUS or I2C pin pair for add in card.
+  UINT8   SlaveAddr;            ///< Specifies the I2C address of the add in card.
+  UINT8   DDCBus;               ///< Specifies the GMBUS pin pair for EDID read.
+  UINT16  TimingInfoPtr;        ///< Pointer to the buffer where VBIOS stores the EDID of device.
+  UINT8   DVOCfg;               ///< Obsolete field.
+
+  /**
+  Flags 1\n
+  Bits 7:5  : Reserved
+  Bit 4     : HPD Sense Invert
+          0 : Invert not required (default)
+          1 : Invert required
+  Bit 3     : IBoost feature enable/disable.
+          0 : IBoost feature is disabled.
+          1 : IBoost feature is enabled.
+  Bit 2     : Hdmi 2.0 Motherboard Downsuppotred options
+          0 : Motherboard Down chip not supported
+          1 : Motherboard Down Chip Supported on the Board
+  Bit 1     : Lane Reversal feature.
+          0 : Disable
+          1 : Enable
+  Bit 0     : DP/HDMI routed to dock.
+          0 : Disable
+          1 : Enable
+  **/
+  union {
+  UINT8 Value;
+  struct {
+    UINT8 DockablePort:1;
+    UINT8 EnableLaneReversal:1;
+    UINT8 OnBoardLsPconDonglePresent:1;
+    UINT8 IBoostEnable:1;
+    UINT8 IsHpdInverted:1;
+    UINT8 Reserved:3;
+    } Bits;
+  } Flags_1;
+
+  UINT8   Compatibility;        ///< Compatibility is used in VBIOS only. It was used before device class was defined.
+  UINT8   AUX_Channel;          ///< Specifies the aux channel to be used for display port devices.
+  UINT8   Dongle_Detect;        ///< Indicates whether dongle detect is enabled or not.
+  UINT8   Capabilities;         ///< Bits 1-0 indicate pipe capabilities whether display can be used on one pipe or both the pipes.
+  UINT8   DVOWiring;            ///< Obsolete field.
+  UINT8   MipiBridgeType;       ///< MIPI bridge type
+  UINT16  DeviceClassExtension; ///< Obsolete.
+  UINT8   DVOFunction;          ///< Obsolete.
+
+  /**
+  Flags 2
+  Bits 7:4  : DP Port trace length from silicon to output port on the board
+          0 : Default RVP length
+          1 : Short trace length
+          2 : Long trace length
+  Bits 3:2  : Reserved
+  Bit 1     : Indicates whether this port is Thunderbolt port or not.
+          0 : No
+          1 : Yes
+  Bit 0     : DP 2 lane RCR# 1024829: USB type C to enable 2 lane DP display
+          0 : Disable
+          1 : Enable
+  **/
+  union {
+    UINT8   Value;
+    struct {
+      UINT8   UsbTypeCDongleEnabled:1;  ///< Indicates whether this port is USB type C.
+      UINT8   IsThunderboltPort:1;      ///< Indicates whether this port is Thunderbolt. (ICL+)
+      UINT8   Reserved:2;               ///< Reserved for future use.
+      UINT8   DpPortTraceLength:4;      ///< Dp port trace length from silicon to port.
+    } Bits;
+  } Flags_2;
+  UINT8   DP2XGpioIndex;        ///< GPIO index number for the USB type C.
+  UINT16  DP2XGpioNumber;       ///< GPIO number for USB type C.
+
+  /**
+  IBoost magnitude field.
+  Bits 7:4  : DP Boost magnitude
+          0 : 1
+          1 : 3
+          2 : 7
+     Others : Reserved for CML.
+  Bits 3:0  : HDMI Boost magnitude
+          0 : 1
+          1 : 3
+          2 : 7
+  Others : Reserved.
+  **/
+  union {
+    UINT8   Value;
+    struct {
+      UINT8   DpEdpBoostMagnitude:4;
+      UINT8   HdmiBoostMagnitude:4;
+    } Bits;
+  } BoostMagnitude;
+} CHILD_STRUCT;
+
+/**
+  This structure defines Block 2 (General Bytes Definitions)
+**/
+typedef struct {
+  UINT8         BlockId;          ///< Defines the Block ID : 2.
+  UINT16        BlockSize;        ///< Defines the size of VBT General Info 2 Block.
+
+  UINT8         bmp_CRT_DDC_GMBUS_Pin;  ///< Obsolete field: Selects the CRT DDC GMBUS pin pair.
+  UINT8         bmp_DPMS_Bits;          ///< BMP DPMS Bit Definitions.
+  UINT16        bmp_Boot_Dev_Bits;      ///< BMP Boot Device Bit Definitions.
+  UINT8         SizeChild_Struct;       ///< Size of the ChildStruc structure.
+
+  CHILD_STRUCT  Child_Struct[ChildStruct_MAX];  ///< This array defines all the supported child structures.
+} VBT_GENERAL2_INFO;
+
+/**
+  This defines the structure of Block 3 (Original Display Toggle List)
+**/
+typedef struct {
+  UINT8   BlockId;                ///< Defines the Block ID : 3
+  UINT16  BlockSize;              ///< Defines the size of Original Display Toggle List Block
+  UINT8   bmp_Display_Detect;     ///< Display must be attached or not
+} BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST;
+
+/**
+  This defines structure of a pointer table.
+**/
+typedef struct {
+  UINT16  Offset;       ///< Defines the offset of the table from start of BIOS Data block.
+  UINT16  Size;         ///< Defines the size of an entry of the table.
+} BMP_TABLE_PTR;
+
+/**
+  This structure defines Block 252 (SBIOS Hooks and BMP Table Pointers).
+**/
+typedef struct {
+  UINT8           BlockId;          ///< Defines the Block ID : 252.
+  UINT16          BlockSize;        ///< Defines the size of SBIOS Hooks block.
+  UINT8           SbiosHooks[18];   ///< This array defines a series of SBIOS hooks. Each entry represents one hook.
+  BMP_TABLE_PTR   BmpTablePtr[26];  ///< This array defines pointers to all the important tables in the VBT.
+} BLOCK252_SBIOS_Hook;
+
+/**
+  This defines the structure of MMIO boot table entry
+**/
+typedef struct {
+  UINT32  Register;   ///< Defines the MMIO offset of the register.
+  UINT32  Value;      ///< Defines the default value of the register.
+} MMIO_BOOT_TABLE;
+
+/**
+  This structure defines Block 6 (MMIO Register Block)
+**/
+typedef struct {
+  UINT8           BlockId;              ///< Defines the Block ID : 6
+  UINT16          BlockSize;            ///< Defines the size of MMIO Register Table block.
+  UINT16          RegTableId;           ///< Defines the ID for MMIO register table (0xFFFC).
+  UINT8           AccessFlag;           ///< Defines the flag for data access size (02 for 4 byte read/write).
+  MMIO_BOOT_TABLE MMIOBootTable[14];    ///< Array containing the MMIO register table.
+  UINT16          TableEnd;             ///< Special value describing End of table (0xFFFF).
+} BLOCK06_MMIO_REG_TABLE;
+
+/**
+  This structure defines Block 7 (IO SW Flag Register Table)
+**/
+typedef struct {
+  UINT8   BlockId;          ///< Defines Block ID (7).
+  UINT16  BlockSize;        ///< Defines the size of IO SW Flag register table block.
+  UINT16  RegTableId;       ///< Defines the ID for IO SW Flag register table (0xFFFE).
+  UINT8   GRIndexRegLsb;    ///< Defines the read/write size. Value is 0xCE meaning 1 byte without mask.
+  UINT8   IOSWFlagReg;      ///< Defines the offset for the IO SW Flag register.
+  UINT8   Value;            ///< Defines the data/value for the register.
+  UINT16  TableEnd;         ///< Special value describing the end of table (0xFFFF).
+} BLOCK07_IOSWFLAG_REG_TABLE;
+
+/**
+  This structure defines the entry of SWF table.
+**/
+typedef struct {
+  UINT32  Register;   ///< Defines the MMIO offset of the SWF register.
+  UINT32  Value;      ///< Defines the default value for the SWF register.
+} SWF_TABLE;
+
+/**
+  This defines the structure of Block 8 (MMIO SW Flag Block).
+**/
+typedef struct {
+  UINT8     BlockId;      ///< Defines the Block ID : 8.
+  UINT16    BlockSize;    ///< Defines the size of MMIO SWF register table block.
+  UINT16    RegTableId;   ///< Defines the ID for MMIO SWF register table (0xFFFC).
+  UINT8     AccessFlag;   ///< Defines the data access size. Value is 0x02 meaning 4 bytes read/write.
+  SWF_TABLE SWFTable[7];  ///< Array containing the MMIO SWF register table.
+  UINT16    TableEnd;     ///< Special value describing end of table (0xFFFF).
+} BLOCK08_MMIOSWFLAG_REG_TABLE;
+
+/**
+  This structure defines the PSR feature table entry.
+**/
+typedef struct {
+  UINT8   SRD_Enables;        ///< Defines PSR features such as full link enable/disable and whether aux is required to wake up.
+  UINT8   SRD_WaitTimes;      ///< Defines lines to wait before link standby and idle frames to wait before SRD enable.
+  UINT16  SRD_TP1_WakeupTime; ///< TP 1 wake up time in multiples of 100.
+  UINT16  SRD_TP2_WakeupTime; ///< TP2/TP3 wake up time in multiples of 100
+} PSR_FEATURE_TABLE;
+
+/**
+  This defines the structure of Block 9 (PSR Features Block)
+**/
+typedef struct {
+  UINT8             BlockId;              ///< Defines the block ID : 9
+  UINT16            BlockSize;            ///< Defines the size of PSR Feature block.
+  PSR_FEATURE_TABLE PSRFeatureTable[16];  ///< Array containing the PSR Feature table.
+} BLOCK09_PSR_FEATURE;
+
+/**
+  This structure defines an entry of Mode Removal table.
+**/
+typedef struct {
+  UINT16  XRes;         ///< X resolution of the mode.
+  UINT16  YRes;         ///< Y resolution of the mode.
+  UINT8   Bpp;          ///< Bits per pixel of the mode.
+  UINT16  RRate;        ///< Refresh rate of the mode.
+  UINT8   RFlags;       ///< Flags specifying display type and functional area where the mode is to be removed.
+  UINT16  PanelFlags;   ///< Applicable to LFP only. Indicates which LFP panels the mode is to be removed.
+} MODE_REMOVAL_TABLE_ENTRY;
+
+/**
+  This defines the structure of Block 10 (Mode Removal Block)
+**/
+typedef struct {
+  UINT8                     BlockId;              ///< Defines the Block ID : 10.
+  UINT16                    BlockSize;            ///< Defines the size of Mode Removal table block.
+  UINT8                     EntrySize;            ///< Defines the size of one entry of mode removal table.
+  MODE_REMOVAL_TABLE_ENTRY  ModeRemovalTable[20]; ///< Array containing the mode removal table.
+  UINT16                    Terminator;           ///< Special value indicating end of mode removal table (0xFFFF).
+} BLOCK10_MODE_REMOVAL_TABLE;
+
+/**
+  This defines the structure of Block 12 (Driver Features Data Block)
+**/
+typedef struct {
+  UINT8   BlockId;                  ///< Defines the unique Block ID : 12
+  UINT16  BlockSize;                ///< Defines the size of Driver features block.
+
+  /**
+  This field defines the various driver related bits:\n
+  Bit 7 = Use 00000110h ID for Primary LFP
+        = 0, No
+        = 1, Yes
+  Bit 6 = Enable/Disable Sprite in Clone Mode
+        = 0, Disable
+        = 1, Enable
+  Bit 5 = Driver INT 15h hook
+        = 0, Disable
+        = 1, Enable
+  Bit 4 = Dual View Zoom
+        = 0, Disable
+        = 1, Enable
+  Bit 3 = Hot Plug DVO
+        = 0, Disable
+        = 1, Enable
+  Bit 2 = Allow display switching when in Full Screen DOS.
+        = 0, Block Display Switching
+        = 1, Allow Display Switching
+  Bit 1 = Block display switching when DVD active
+        = 0, No Block Display Switching
+        = 1, Block Display Switching
+  Bit 0 = Boot device algorithm
+        = 0, OS Default
+        = 1, Driver Default
+  **/
+  UINT8   bmp_Driver_Bits;
+  UINT16  bmp_Driver_Boot_Mode_X;   ///< X resolution of driver boot mode.
+  UINT16  bmp_Driver_Boot_Mode_Y;   ///< Y resolution of driver boot mode.
+  UINT8   bmp_Driver_Boot_Mode_BPP; ///< Bits per pixel of driver boot mode.
+  UINT8   bmp_Driver_Boot_Mode_RR;  ///< Refresh rate of driver boot mode.
+
+  /**
+  This field defines the extended driver bits 1.\n
+  Bits [15:14] = Integrated HDMI configuration
+              = 00b,  No Integrated HDMI
+              = 01b,  Port-B Only
+              = 10b,  Port-C Only
+              = 11b,  Both Port-B and Port-C
+  Bits 13 = TV Hotplug
+  Bits [12:11]  = LFP configuration
+                = 00b,  No LVDS
+                = 01b,  Integrated LVDS
+                = 10b,  SDVO LVDS
+                = 11b,  eDP
+  Bit 10 = Obsolete field: CRT hotplug
+          = 0, Disabled
+          = 1, Enabled (Default)
+  Bit 9 = SDVO device power down
+        = 0, Disabled (Default)
+        = 1, Enabled
+  Bit 8 = Preserve Aspect Ratio
+        = 0, Disabled (Default)
+        = 1, Enabled
+  Bit 7 = Display "Maintain Aspect Scaling" via CUI
+        = 0, No
+        = 1, Yes (Default)
+  Bit 6 = Sprite Display Assignment when Overlay is Active in Clone Mode:
+        = 0, Secondary
+        = 1, Primary
+  Bit 5 = Default Power Scheme user interface
+        = 0, CUI
+        = 1, 3rd Party Application
+  Bit 4 = NT 4.0 Dual Display Clone Support
+        = 0, Disable
+        = 1, Enable
+  Bit 3 = Default Render Clock Frequency
+        = 0, High Frequency
+        = 1, Low Frequency
+  Bit 2 = Dual-Frequency Graphics Technology
+        = 0, No
+        = 1, Yes
+  Bit 1 = Selective Mode Pruning
+        = 0, No
+        = 1, Yes
+  Bit 0 = Enable LFP as primary
+        = 0, Disable
+        = 1, Enable
+**/
+  UINT16  bmp_Ext_Driver_Bits;
+
+  /**
+  This defines the driver flags related to CUI Hot key.\n
+  Bits [7:3] - Reserved
+  Bit 2 = Display Subsystem Enable/Disable
+        = 0, Enable (default Value)
+        = 1, Disable
+  Bit 1 = Embedded Platform
+        = 0, False
+        = 1, True
+  Bit 0 = Define CUI HotK Displays Statically
+        = 0, No
+        = 1, Yes
+  **/
+  UINT8   bmp_Display_Detect_CUIHotK;
+
+  UINT16  bmp_Legacy_CRT_Max_X;         ///< Obsolete field: Defines the legacy CRT X resolution for driver boot mode.
+  UINT16  bmp_Legacy_CRT_Max_Y;         ///< Obsolete field: Defines the legacy CRT Y resolution for driver boot mode.
+  UINT8   bmp_Legacy_CRT_Max_RR;        ///< Obsolete field: Defines the legacy CRT refresh rate for driver boot mode.
+
+  /**
+  This field defines the extended driver bits 2.\n
+  Bits [7:1] - Reserved
+  Bit 0 = Enable Internal Source Termination for HDMI
+        = 0, External Termination
+        = 1, Internal Termination
+  **/
+  UINT8   bmp_Ext2_Driver_Bits;
+
+  UINT8   bmp_VBT_Customization_Version;  ///< Defines the customized VBT version number.
+
+  /**
+  This field defines all the driver feature flags.\n
+  Bit 15 = PC Features Field's Validity
+         = 0, Invalid
+         = 1, Valid
+  Bit 14 = Hpd_wake - HPD events are routed to display driver when system is in S0ix/DC9
+         = 0, Disable
+         = 1, Enable
+  Bit 13 = Assertive Display Technology (ADT)
+         = 0, Disable
+         = 1, Enable
+  Bit 12 = Dynamic Media Refresh Rate Switching (DMRRS)
+         = 0, Disable
+         = 1, Enable
+  Bit 11 = Dynamic Frames Per Second (DFPS)
+         = 0, Disable
+         = 1, Enable
+  Bit 10 = Intermediate Pixel Storage (IPS)
+         = 0, Disable
+         = 1, Enable
+  Bit 9 = Panel Self Refresh (PSR)
+        = 0, Disable
+        = 1, Enable
+  Bit 8 = Intel Turbo Boost Technology
+        = 0, Disable
+        = 1, Enable
+  Bit 7 = Graphics Power Modulation Technology (GPMT)
+        = 0, Disable
+        = 1, Enable
+  Bit 6 = Graphics Render Standby (RS)
+        = 0, Disable
+        = 1, Enable
+  Bit 5 = Intel Display Refresh Rate Switching (DRRS)
+        = 0, Disable
+        = 1, Enable
+  Bit 4 = Intel Automatic Display Brightness (ADB)
+        = 0, Disable
+        = 1, Enable
+  Bit 3 = DxgkDDI Backlight Control (DxgkDdiBLC)
+        = 0, Disable
+        = 1, Enable
+  Bit 2 = Intel Display Power Saving Technology (DPST)
+        = 0, Disable
+        = 1, Enable
+  Bit 1 = Intel Smart 2D Display Technology (S2DDT)
+        = 0, Disable
+        = 1, Enable
+  Bit 0 = Intel Rapid Memory Power Management (RMPM)
+        = 0, Disable
+        = 1, Enable
+  **/
+  UINT16  bmp_Driver_Feature_Flags;
+} BLOCK12_DRIVER_FEATURES;
+
+/**
+  This defines the structure of Block 13 (Driver Persistence Options)
+**/
+typedef struct {
+  UINT8   BlockId;                ///< Defines the unique Block ID : 13
+  UINT16  BlockSize;              ///< Defines the size of Driver Persistence options block.
+
+  /**
+  Defines the various persistence options.\n
+  Bits [15:10] - Reserved
+  Bit 9 = Docking Persistence Algorithm
+        = 0, OS Default
+        = 1, Driver Default
+  Bit 8 = DVO Hot Plug Persistence on Mode
+  Bit 7 = EDID Persistence on Mode
+  Bit 6 = Hot Key Persistence on Mode
+        = 0, No
+        = 1, Yes
+  Bit 5 = Hot Key Persistence on RestorePipe
+        = 0, No
+        = 1, Yes
+  Bit 4 = Hot Key Persistence on RefreshRate
+        = 0, No
+        = 1, Yes
+  Bit 3 = Hot Key Persistence on MDS/Twin
+        = 0, No
+        = 1, Yes
+  Bit 2 = Power Management Persistence Algorithm
+        = 0, OS Default
+        = 1, Driver Default
+  Bit 1 = Lid Switch Persistence Algorithm
+        = 0, OS Default
+        = 1, Driver Default
+  Bit 0 = Hot Key Persistence Algorithm
+        = 0, OS Default
+        = 1, Driver Default
+  **/
+  UINT16  PersistenceAlgorithm;
+
+  UINT8   PersistMaxconfig;       ///< Maximum mode persistence configurations (10-200)
+} BLOCK13_DRIVER_PERSISTENCE;
+
+/**
+  This defines the structure of Block 17 (SV Bits)
+**/
+typedef struct {
+  UINT8   BlockId;      ///< Defnies the unique Block ID : 17
+  UINT16  BlockSize;    ///< Defines the size of SV Bits block.
+
+  /**
+  Bits [7:4] = Reserved
+    Bit3  = Allow VBlank/VblankScanline timeout hang
+          = 0, Disable
+          = 1, Enable
+    Bit2  = Special GMBus support
+          = 0, Disable
+          = 1, Enable
+    Bit1  = Skip program pipe timings when set VGA modes
+          = 0, Setmode skip DVO Update
+          = 1, Setmode updates DVO
+    Bit0  = Disable VGA fast arbiter
+          = 0, Enabled
+          = 1, Disabled
+  **/
+  UINT8   SvBits1;
+  UINT8   SvBits2;      ///< Reserved for future use.
+  UINT8   SvBits3;      ///< Reserved for future use.
+  UINT8   SvBits4;      ///< Reserved for future use.
+  UINT8   SvBits5;      ///< Reserved for future use.
+  UINT8   SvBits6;      ///< Reserved for future use.
+  UINT8   SvBits7;      ///< Reserved for future use.
+  UINT8   SvBits8;      ///< Reserved for future use.
+} BLOCK17_SV_BITS;
+
+/**
+  This defines the structure of Block 18 (Driver Rotation)
+**/
+typedef struct {
+  UINT8   BlockId;                    ///< Defines the unique Block ID : 18
+  UINT16  BlockSize;                  ///< Defines the size of Driver Rotation block.
+  UINT8   RotationFeatureSupport;     ///< Rotation feature support field used by driver.
+  UINT8   Reserved1;                  ///< Reserved for future use.
+  UINT16  Reserved2;                  ///< Reserved for future use.
+  UINT32  Reserved3;                  ///< Reserved for future use.
+  UINT32  Reserved4;                  ///< Reserved for future use.
+} BLOCK18_DRIVER_ROTATION;
+
+/**
+  This structure defines an entry of OEM mode table.
+**/
+typedef struct {
+  /**
+  Mode Flags:
+    Bits[7:3] = Reserved
+    Bit 2 = Enable/disable this OEM mode in GOP driver.
+    Bit 1 = Enable/disable this mode in Driver
+    Bit 0 = Enable/disable this mode in VBIOS
+  **/
+  UINT8   ModeFlags;
+
+  /**
+  Display Device Flags:
+    Bit 7 = LFP2
+    Bit 6 = EFP2
+    Bit 5 = EFP3
+    Bit 4 = EFP4
+    Bit 3 = LFP
+    Bit 2 = EFP
+    Bit 1 = Rsvd
+    Bit 0 = Rsvd
+  **/
+  UINT8   DisplayFlags;
+  UINT16  XRes;         ///< Defines the X resolution of the mode.
+  UINT16  YRes;         ///< Defines the Y resolution of the mode.
+
+  /**
+  Defines the bits per pixel of the mode.
+    Bit 7:3 = Reserved
+    Bit 2 = 32 BPP
+    Bit 1 = 16 BPP
+    Bit 0 = 8 BPP
+  **/
+  UINT8   Bpp;
+  UINT8   RRate;        ///< Defines the refresh rate of the mode.
+  DTD_STRUCTURE Dtd;    ///< Defines the 18 byte timing config for the mode.
+} OEM_MODE_ENTRY;
+
+/**
+  This defines the structure of Block 20 (OEM Mode Customization Block)
+**/
+typedef struct {
+  UINT8           BlockId;          ///< Defines the unique block ID : 20
+  UINT16          BlockSize;        ///< Defines the size of OEM customization block.
+  UINT8           NumOfEntry;       ///< Defines the number of entries in OEM Mode table.
+  UINT8           EntrySize;        ///< Defines the size of one entry of OEM Mode table.
+  OEM_MODE_ENTRY  OemModeTable[6];  ///< Array defining the OEM mode table.
+} BLOCK20_OEM_CUSTOMIZATION;
+
+/**
+  This defines the structure of Block 26 (TV options)
+**/
+typedef struct {
+  UINT8   BlockId;                  ///< Defines the unique Block ID : 26
+  UINT16  BlockSize;                ///< Defines the size of TV Options block.
+
+  /**
+  Defines the TV options:
+    Bit 15  = D-Conector Support
+            = 0, Disable
+            = 1, Enable
+    Bit 14 = Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected
+            = 0, Disable
+            = 1, Enable
+    Bit 13:12 Underscan/overscan for HDTV via DVI
+            = 00b, Enable Underscan and Overscan modes (Default)
+            = 01b, Enable only overscan modes
+            = 10b, Enable only underscan modes
+    Bits 11:2 = Reserved
+    Bit 1:0 = Underscan/overscan for HDTV via Component (YPrPb)
+            = 00b, Enable Underscan and Overscan modes (Default)
+            = 01b, Enable only overscan modes
+            = 10b, Enable only underscan modes
+  **/
+  UINT16  bmp_TV_Options_1;
+} BLOCK26_TV_OPTIONS;
+
+/**
+  This structure defines the eDP panel power sequencing parameters.
+**/
+typedef struct {
+  UINT16  T3;         ///< Panel Power-Up Delay.
+  UINT16  T8;         ///< Panel Power-On to backlight Enable Delay.
+  UINT16  T9;         ///< Backlight-Off to Power-Down Delay.
+  UINT16  T10;        ///< Power-Down Delay.
+  UINT16  T12;        ///< Power Cycle Delay.
+} EDP_PWR_SEQ;
+
+/**
+  This structure defines the PWM<-->Backlight delays for a single eDP panel.
+**/
+typedef struct {
+  UINT16  PwmOnToBacklightEnableDelay;      ///< PWM on to backight enable delay.
+  UINT16  BacklightDisableToPwmOffDelay;    ///< Backlight disable to PWM off delay.
+} EDP_PWM_BACKLIGHT_DELAYS;
+
+/**
+  This defines FLT parameters for a single eDP panel.
+  Bits[15:12] : VSwing level
+            0 : 0.4V (default)
+            1 : 0.6V
+            2 : 0.8V
+            3 : 1.2V
+       Others : Reserved
+  Bits[11:8]  : Pre-emphasis level
+            0 : no pre-emphasis (default)
+            1 : 3.5dB
+            2 : 6dB
+            3 : 9.5dB
+       Others : Reserved
+  Bits[7:4]   : Lane count (port width)
+            0 : x1 mode (default)
+            1 : x2 mode
+            2 : Reserved
+            3 : x4 mode
+       Others : Reserved
+  Bits[3:0]   : data rate
+            0 : 1.62 Gbps
+            1 : 2.7 Gbps
+            2 : 5.4 Gbps
+       Others : Reserved
+**/
+typedef union {
+  UINT16 Value;
+  struct {
+    UINT16 DataRate:4;
+    UINT16 LaneCount:4;
+    UINT16 PreEmphasisLevel:4;
+    UINT16 VSwingLevel:4;
+  } Bits;
+} EDP_FAST_LINK_TRAINING_PARAMS;
+
+/**
+  This defines Full link training parameters for a single eDP panel.
+  Bits[7:4] : VSwing level
+          0 : 0.4V (default)
+          1 : 0.6V
+          2 : 0.8V
+          3 : 1.2V
+     Others : Reserved
+  Bits[3:0] : Pre-emphasis level
+          0 : no pre-emphasis (default)
+          1 : 3.5dB
+          2 : 6dB
+          3 : 9.5dB
+     Others : Reserved
+**/
+typedef union {
+  UINT8   Value;
+  struct {
+    UINT8   PreEmphasisLevel:4;
+    UINT8   VSwingLevel:4;
+  } Bits;
+} EDP_FULL_LINK_TRAINING_PARAMS;
+
+/**
+  This defines the structure of Apical Parameters for a single eDP panel.
+**/
+typedef struct {
+  UINT32      PanelOui;             ///< Apical IP specific field for Panel OUI
+  UINT32      DPCDBaseAddress;      ///< Apical IP specific field for DPCD Base address
+  UINT32      DPCDIrdidixControl0;  ///< Apical IP specific field for DPCD Idridix Control 0
+  UINT32      DPCDOptionSelect;     ///< Apical IP specific field for DPCD option select
+  UINT32      DPCDBacklight;        ///< Apical IP specific field for DPCD backlight
+  UINT32      AmbientLight;         ///< Apical IP specific field for Ambient light
+  UINT32      BacklightScale;       ///< Apical IP specific field for backlight scale
+} EDP_APICAL_PARAMS;
+
+/**
+  This defines the structure of Block 27 (eDP Display Block)
+**/
+typedef struct {
+  UINT8       BlockId;            ///< Defines the unique Block ID : 27
+  UINT16      BlockSize;          ///< Defines the size of eDP display VBT block.
+
+  EDP_PWR_SEQ eDP_PWR_SEQ[16];    ///< Array defining the panel power sequencing for all 16 eDP panels.
+
+  /**
+  Defines the panel color depth in bits per pixel. 2 Bits for each Panel.
+    Bits[1:0] Panel color depth for Panel #1
+      = 00, 18bpp
+      = 01, 24bpp
+      = 10, 30bpp
+      = 11, 36bpp
+  **/
+  UINT32      eDP_Panel_Color_Depth;
+
+  /**
+    Array containing the FLT parameters of 16 eDP panels.
+  **/
+  EDP_FAST_LINK_TRAINING_PARAMS      eDP_Fast_Link_Training_Params[16];
+
+  /**
+  This field defines the eDP sDRRS MSA Timing Delay for all 16 eDP panels. 2 Bits for Each Panel.
+  Bits[1:0] for Panel #1
+    = 00, Line 1
+    = 01, Line 2
+    = 10, Line 3
+    = 11, Line 4
+  **/
+  UINT32      eDP_sDRRS_MSA_Delay;
+
+  /**
+  Defines the S3D feature enable/disable for all 16 eDP panels. 1 Bit for Each Panel.
+  Bits[0] for Panel #1
+    = 0, S3D disabled for this panel
+    = 1, S3D enabled for this panel
+  **/
+  UINT16      eDP_S3D_Feature;
+
+  /**
+  Defines the T3 optimization enable/disable for all 16 panels. 1 Bit for each panel.
+  Bits[0] = Panel #1
+    = 0, T3 optimization disabled for this panel
+    = 1, T3 optimization enabled for this panel
+  **/
+  UINT16      eDP_T3_Optmization;
+
+  /**
+  Defines the Edp vswing and pre-emphasis for all 16 panels. 4 Bits for Each Panel
+  Bits[3:0] = Panel #1
+    = 0, Use table 1 for this panel.
+    = 1, Use table 2 for this panel.
+  **/
+  UINT64       VswingPreEmphasisTableNum;
+
+  /**
+  Defines the Edp fast link training support on all 16 panels. 1 Bit for Each Panel
+  Bits[0] = Panel #1
+    = 0, FastLinkTraining feature is disabled for this panel
+    = 1, FastLinkTraining feature is enabled for this panel
+  **/
+  UINT16     EdpFastLinkTrainingSupportOnPanel;
+
+  /**
+  Defines whether the Set power state at DPCD 600h is to be done in eDP enable/disable sequence.
+  Bits[0] = Panel #1
+    = 0, Set power state at DPCD 600h feature is disabled for this panel
+    = 1, Set power state at DPCD 600h feature is enabled for this panel
+  **/
+  UINT16     SetPowerStateAtDPCD600h; //This is not used currently
+
+  /**
+    Array defining the PWM <--> Backlight related delays for 16 panels.
+  **/
+  EDP_PWM_BACKLIGHT_DELAYS eDP_Pwm_BackLight_Delays[16];
+
+  /**
+  Defines the Edp full link training support on all 16 panels. 1 Bit for Each Panel.
+  \verbatim
+  Bits[0] : Panel #1
+        0 : Initial vswing and pre-emphasis levels are not provided for Full link training
+        1 : Initial vswing and pre-emphasis levels are provided for Full link training
+  Bits 1 to 15 are for panel # 2 to 16.
+  \endverbatim
+  **/
+  UINT16     InitialFullLinkTrainingParamsProvidedInVbt;
+
+  /**
+    Array containing the initial Vswing and Pre-emphasis parameters for Full link training.
+  **/
+  EDP_FULL_LINK_TRAINING_PARAMS    eDP_Full_Link_Training_Params[16];
+
+  /**
+  Defines the Edp Apical assertive display IP support on all 16 panels. 1 Bit for Each Panel.
+  Bit 0   : Panel #1
+        0 : Apical assertive display IP is disabled for this panel.
+        1 : Apical assertive display IP is enabled for this panel.
+  Bits 1 to 15 are for panel # 2 to 16.
+  **/
+  UINT16                           IsApicalAssertiveDisplayIpEnable;
+
+  /**
+    Array containing the Apical parameters for all 16 panels
+  **/
+  EDP_APICAL_PARAMS                eDP_Apcial_Params[16];
+} BLOCK27_EDP_FEATURES;
+
+/**
+  This defines the structure of Block 28 (Edidless EFP support DTD timings)
+**/
+typedef struct {
+  UINT8                 BlockId;                    ///< Defines the unique Block ID : 28
+  UINT16                BlockSize;                  ///< Defines the size of Edidless EFP support block.
+  DTD_STRUCTURE         Edidless_EFP_DTD_Struc[4];  ///< Array defining the DTD timing for 3 EFP devices.
+} BLOCK28_EDIDLESS_EFP;
+
+/**
+This defines the structure of toggle list entry.
+**/
+typedef struct {
+  /**
+  Defines the display device selection for toggling
+  Bit 15 = EFP4.3 (Reserved for CML)
+  Bit 14 = EFP3.3
+  Bit 13 = EFP2.3
+  Bit 12 = EFP1.3
+  Bit 11 = EFP4.2 (Reserved for CML)
+  Bit 10 = EFP3.2
+  Bit 9  = EFP2.2
+  Bit 8  = EFP1.2
+  Bit 7  = LFP2
+  Bit 6  = EFP2
+  Bit 5  = EFP3
+  Bit 4  = EFP4
+  Bit 3  = LFP
+  Bit 2  = EFP
+  Bit 1  = TV
+  Bit 0  = CRT
+  **/
+  UINT16  DisplayDevice;
+} CNL_TOGGLE_LIST_ENTRY;
+
+/**
+  This defines the structure of Block 31 (Toggle Lists for Cannonlake)
+**/
+typedef struct {
+  UINT8                   BlockId;              ///< Defines the unique Block ID : 31
+  UINT16                  BlockSize;            ///< Defines the size of Toggle List Block.
+  UINT16                  NumOfEntry1;          ///< Defines the number of entries in toggle list 1.
+  UINT8                   EntrySize1;           ///< Defines the size of toggle list entry present in list 1.
+  CNL_TOGGLE_LIST_ENTRY   ToggleList1Entry[16]; ///< Array defining the toggle list 1.
+  UINT16                  NumOfEntry2;          ///< Defines the number of entries in toggle list 2.
+  UINT8                   EntrySize2;           ///< Defines the size of toggle list entry present in list 2.
+  CNL_TOGGLE_LIST_ENTRY   ToggleList2Entry[8];  ///< Array defining the toggle list 2.
+  UINT16                  NumOfEntry3;          ///< Defines the number of entries in toggle list 3.
+  UINT8                   EntrySize3;           ///< Defines the size of toggle list entry present in list 3.
+  CNL_TOGGLE_LIST_ENTRY   ToggleList3Entry[8];  ///< Array defining the toggle list 3.
+  UINT16                  NumOfEntry4;          ///< Defines the number of entries in toggle list 4.
+  UINT8                   EntrySize4;           ///< Defines the size of toggle list entry present in list 4.
+  CNL_TOGGLE_LIST_ENTRY   ToggleList4Entry[8];  ///< Array defining the toggle list 4.
+} BLOCK31_TOGGLE_LIST;
+
+/**
+  This defines the structure of Display device removal configuration entry.
+**/
+typedef struct {
+  /**
+  Defines the display device configuration to be removed.
+  Bit 15 = EFP4.3 (Reserved for CML)
+  Bit 14 = EFP3.3
+  Bit 13 = EFP2.3
+  Bit 12 = EFP1.3
+  Bit 11 = EFP4.2 (Reserved for CML)
+  Bit 10 = EFP3.2
+  Bit 9  = EFP2.2
+  Bit 8  = EFP1.2
+  Bit 7  = LFP2
+  Bit 6  = EFP2
+  Bit 5  = EFP3
+  Bit 4  = EFP4
+  Bit 3  = LFP
+  Bit 2  = EFP
+  Bit 1  = TV
+  Bit 0  = CRT
+  **/
+  UINT16  DisplayDeviceConfiguration;
+} CNL_DISPLAY_CONFIGURATION_ENTRY;
+
+/**
+  This defines the structure of Block 32 (Display removal configuration Block)
+**/
+typedef struct {
+  UINT8                                BlockId;       ///< Defines the unique Block ID = 32
+  UINT16                               BlockSize;     ///< Defines the size of Display removal configuration block.
+  UINT8                                NumOfEntry;    ///< Defines the number of entries in display removal configuraion table.
+  UINT8                                EntrySize;     ///< Defines the size of 1 entry in display removal configuration table.
+  CNL_DISPLAY_CONFIGURATION_ENTRY      RemoveDisplayConfiguration[15];    ///< Array defining the display removal configuration table.
+}BLOCK32_DISPLAY_CONFIGURATION_REMOVAL;
+
+/**
+  This defines the Local Flat panel basic details such as resolution and the various registers.
+**/
+typedef struct {
+  UINT16  XRes;                   ///< X resolution of the panel.
+  UINT16  YRes;                   ///< Y resolution of the panel.
+  UINT32  LVDSDigDisReg;          ///< MMIO offset of LFP digital display port register.
+  UINT32  LVDSDigDisVal;          ///< Value of LFP digital display port register.
+  UINT32  OnSeqDelayReg;          ///< MMIO offset of Panel power on sequencing delay register.
+  UINT32  OnSeqDelayVal;          ///< Value of Panel power on sequencing delay register.
+  UINT32  OffSeqDelayReg;         ///< MMIO offset of Panel power off sequencing delay register.
+  UINT32  OffSeqDelayVal;         ///< Value of Panel power off sequencing delay register.
+  UINT32  CycleDelay_RefDivReg;   ///< MMIO offset of Panel power cycle delay and reference divider register.
+  UINT32  CycleDelay_RefDivVal;   ///< Value of Panel power cycle delay and reference divider register.
+  UINT16  Terminate;              ///< Special value 0xFFFF indicating end of data.
+} FP_DATA;
+
+/**
+  This defines the structure consisting of all details for a single Local Flat panel.
+**/
+typedef struct {
+  FP_DATA       FP_Data;      ///< Instance of ::FP_DATA structure.
+  DTD_STRUCTURE DTD_Data;     ///< Instance of ::DTD_STRUCTURE which contains the DTD timings for the panel.
+  PID_DATA      PID_Data;     ///< Instance of ::PID_DATA structure which contains panel related information used by driver.
+} LVDS_FP_TABLE;
+
+/**
+  This structure defines all the details regarding Backlight control for LFP.
+**/
+typedef struct {
+  /**
+  Defines the backlight features for the panel.
+  Bits 7:6  = GMBus Speed:
+            = 00, 100 KHz
+            = 01, 50 KHz
+            = 10, 400 KHz
+            = 11, 1 MHz
+  Bits 5:3  = Inverter GPIO Pins
+            = 0, None
+            = 1, I2C GPIO pins
+            = 2, Analog CRT DDC pins
+            = 3, DVI/LVDS DDC GPIO pins
+            = 5, sDVO I2C GPIO pins
+  Bit 2     = Inverter Polarity (i2c & PWM)
+            = 0, Normal (0 = Minimum brightness)
+            = 1, Inverted (0 = Maximum brightness)
+  Bits 1:0  = BLC Inverter Type
+            = 00, None/External
+            = 01, i2c
+            = 10, PWM
+            = 11, Reserved
+  **/
+  UINT8   BLC_Ftr;
+
+  UINT16  PWM_Freq;       ///< PWM inverter frequency in KHz
+  UINT8   Min_Brightness; ///< Minimum brightness in the range 0-255
+  UINT8   I2C_Add;        ///< I2C Inverter Slave Address
+  UINT8   I2C_Command;    ///< I2C Inverter command code
+} BLC;
+
+/**
+  This defines the structure of Block 40 (LFP Features)
+**/
+typedef struct {
+  UINT8   BlockId;          ///< Defines the unique Block ID : 40
+  UINT16  BlockSize;        ///< Defines the size of LFP Features block.
+
+  UINT8   bmp_Panel_type;   ///< Defines the panel type of LFP.
+  UINT8   Skip1;            ///< Obsoleted.
+
+  /**
+  Capabilities byte:
+  Bit 15:7  = SW Workaround bits
+  Bit 6     = Panel EDID support
+            = 0, Disable
+            = 1, Enable
+  Bit 5     = Pixel dithering
+            = 0, Disable
+            = 1, Enable
+  Bit 4     = Panel Fitting ratio calc.
+            = 0 - Manual
+            = 1 - Automatic
+  Bit 3     = Panel Fitting Graphics mode
+            = 0, Bilinear
+            = 1, Enhanced
+  Bit 2     = Panel Fitting Text mode
+            = 0, Bilinear
+            = 1, Enhanced
+  Bit 1:0   = Panel Fitting Support
+            = 00, No panel fitting
+            = 01, Text panel fitting
+            = 10, GFX panel fitting
+            = 11, Text+GFX panel fitting
+  **/
+  UINT16  bmp_LVDS_Capabilities;
+
+  /**
+  Defines the channel type of LFP. 2 Bits for each Panel.
+  Bits [0:1] for Panel #1
+    = 00, Automatic (algorithm)
+    = 01, Single Channel
+    = 10, Dual Channel
+    = 11, Reserved
+  **/
+  UINT32  INT_LVDS_Panel_Channel_Bits;
+
+  UINT16  Enable_SSC_Bit;         ///< LVDS Spread Spectrum Clock
+  UINT16  SSC_Freq_Bit;           ///< LVDS Spread Spectrum Clock Frequency
+  UINT16  Disable_SSC_DDT_Bit;    ///< Disable SSC in Dual Display Twin
+
+  /**
+  Defines the panel color depth. 1 Bits for each Panel.
+  Bits[0] for Panel #01
+    = 0, 18bpp
+    = 1, 24bpp
+  **/
+  UINT16  INT_Panel_Color_Depth;
+
+  /**
+  Defines the Panel type. 2 Bits for each Panel.
+  Bits [0:1] for Panel #1
+    = 00, Static DRRS
+    = 01, D2PO
+    = 10, Seamless
+    = 11, Reserved
+  **/
+  UINT32  DPS_Panel_Type_Bits;
+
+  /**
+  Defines the type of backlight control for the LFP. 2 bits for each Panel.
+  Bits [0:1] for Panel #1
+    = 00, Default
+    = 01, CCFL backlight
+    = 10, LED backlight
+    = 11, Reserved
+  **/
+  UINT32  BLT_Control_Type_Bits;
+  /**
+  Defines the LFP power enable flag in S0 state for all 16 panels. 1 Bit for Each Panel.
+  Bits[0] : Panel #1
+        0 : Do not keep LCDVCC on during S0 state.
+        1 : Keep LCDVCC on during S0 state.
+  Bits 1 to 15 are for panel # 2 to 16.
+  **/
+  UINT16     LcdvccOnDuringS0State;
+} BLOCK40_LVDS_FEATURES;
+
+/**
+  This structure defines the second type of BMP table pointers.
+  This is used to store pointers to LFP Flat panel data, DTD and PID information.
+**/
+typedef struct {
+  UINT16  Offset;       ///< Offset of the table.
+  UINT8   Size;         ///< Size of the table.
+} BMP_TABLE_TYPE2_PTR;
+
+/**
+  This structure defines a set of 3 pointers for LFP display.
+  These pointers point to FP data, DTD and PID information respectively.
+**/
+typedef struct {
+  BMP_TABLE_TYPE2_PTR   FpTablePtr;   ///< Pointer to FP Data of the LFP panel.
+  BMP_TABLE_TYPE2_PTR   DtdTablePtr;  ///< Pointer to DTD of the LFP panel.
+  BMP_TABLE_TYPE2_PTR   PidTablePtr;  ///< Pointer to the PID data of the LFP panel.
+} LFP_TABLE_POINTERS;
+
+/**
+  This defines the structure of Block 41 (LFP Table Pointers for FPDATA, DTD and PID)
+**/
+typedef struct {
+  UINT8               BlockId;                  ///< Defines the unique Block ID:41
+  UINT16              BlockSize;                ///< Defines the size of LFP Table Pointer Block.
+  UINT8               NumOfEntries;             ///< Defines the number of entries in the Table.
+  LFP_TABLE_POINTERS  LfpTablePointers[16];     ///< Array of ::LFP_TABLE_POINTERS for all 16 panels.
+  UINT16              LfpPanelNameTableOffset;  ///< Offset of LFP panel names table.
+  UINT8               LfpPanelNameLength;       ///< Length of a single LFP panel's name.
+} BLOCK41_LFP_TABLE_POINTERS;
+
+/**
+  This defines the structure of Block 42 (Complete LFP Panel Information)
+**/
+typedef struct {
+  UINT8         BlockId;                ///< Defines the unique block ID : 42
+  UINT16        BlockSize;              ///< Defines the size of Complete LFP panel information for all 16 panels.
+  LVDS_FP_TABLE LVDS_FP_Table[16];      ///< Array of ::LVDS_FP_TABLE containing data of 16 panels.
+  UINT8         LFP_PANEL_NAMES[16][13];///< Array defining the panel names for all 16 panels.
+
+  /**
+  1 Bit for Each Panel
+  Bit0  = Scaling feature for panel 1.
+        = 0, Scaling feature is disabled for this panel.
+        = 1, Scaling feature is enabled for this panel.
+  **/
+  UINT16        EnableScaling; //This is not used currently
+
+  /**
+    Array defining DRRS minimum refresh rate. 1 Byte for Each Panel.
+  **/
+  UINT8         Seamless_DRRS_Min_RR[16];
+
+  /**
+    Array defining Pixel Overlap Count. 1 Byte for Each Panel.
+  **/
+  UINT8         PixelOverlapCount[16];
+} BLOCK42_LVDS_PANEL_INFO;
+
+typedef union {
+  /**
+  Backlight control parameters.\n
+  Bits 7:4  : PWM Controller Selection
+          0 : Controller 0
+          1 : Controller 1
+          2 : Controller 2
+          3 : Controller 3
+     Others : Reserved.
+  Bits 3:0  : PWM Source Selection
+          0 : PMIC PWM
+          1 : LPSS PWM
+          2 : DISPLAY PWM
+          3 : CABC PWM
+     Others : Reserved.
+  **/
+  UINT8 Value;
+  struct {
+    UINT8 PwmSourceSelection:4;
+    UINT8 PwmControllerSelection:4;
+  } Bits;
+} BKLT_CTRL_PARAMS;
+
+/**
+  This defines the structure of Block 43 (LFP Brightness Control)
+**/
+typedef struct {
+  UINT8             BlockId;                ///< Defines the unique Block ID : 43
+  UINT16            BlockSize;              ///< Defines the size of Brightness control block.
+
+  UINT8             SIZE_BLCStruc;          ///< Defines the size of single entry in Backlight control table for LFP.
+  BLC               BLC_Struct[16];         ///< Array defining the backlight control for 16 LFP panels.
+  UINT8             Post_Brightness[16];    ///< Array defining the initial brightness for all 16 panels.
+  BKLT_CTRL_PARAMS  Brightness_Control[16]; ///< Array defining the brightness control method for all 16 panels
+} BLOCK43_LVDS_BLC;
+
+/**
+  This defines the structure of Block 44 (LFP Power Conservation Features)
+**/
+typedef struct {
+  UINT8   BlockId;        ///< Defines the unique block ID : 44
+  UINT16  BlockSize;      ///< Defines the size of LFP Power Conservation Features block.
+  union {
+  /**
+  Bit[7]        : ALS Enable/Disable
+               0 - Disable
+               1 - Enable
+  Bit[6]        : Display LACE support
+               0 - Not supported
+               1 - Supported
+  Bit[5]        : Default Display LACE enabled status
+               0 - Disabled
+               1 - Enabled
+  Bit[4]        : Reserved
+  Bit[3:1]      : Power conservation preference level.
+                 4 is default in a range of 1 to 6.
+  Bit[0]        : Reserved
+  **/
+    UINT8  Value;
+    struct {
+      UINT8 Reserved:1;
+      UINT8 PwrConservation:3;
+      UINT8 Reserved_1:1;
+      UINT8 DefalutDisplayLaceEnable:1;
+      UINT8 DisplayLaceSupport:1;
+      UINT8 AlsEnable:1;
+    } Bits;
+  } LfpFeatureBits;
+
+  UINT16  AlsData[10];    ///< Defines the main ALS data.
+
+  union {
+  /**
+  Bit[7:3]      : Reserved
+  Bit[2:0]      : Aggressiveness Level Profile.
+            000 - Minimum
+            001 - Moderate
+            010 - High
+  **/
+    UINT8  Value;
+    struct {
+      UINT8 AggressionProfileLevel:3;
+      UINT8 Reserved:5;
+    } Bits;
+  } LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profile
+} BLOCK44_ALS;
+
+/**
+  This defines the structure of Black Frame Insertion table entry.
+**/
+typedef struct {
+  /**
+  BFI Features\n
+  Bit[7-2]  : Reserved\n
+  Bit[1]    : Enable Brightness control in CUI\n
+  Bit[0]    : Enable BFI in driver
+  **/
+  UINT8         EnableBits;
+  UINT8         BrightnessNonBFI;   ///< Brightness percentage in non BFI mode
+} BFI;
+
+/**
+  This defines the structure of Block 45 (Black Frame insertion Support for LFP)
+**/
+typedef struct {
+  UINT8              BlockId;         ///< Defines the unique Block ID : 45
+  UINT16             BlockSize;       ///< Defines the size of Black frame insertion support block.
+  UINT8              SIZE_BFIStruc;   ///< Defines the size of 1 entry of black frame data.
+  BFI                BFI_Struct[16];  ///< Array defining the data of black frame insertion for all 16 panels.
+} BLOCK45_BFI_SUPPORT;
+
+/**
+  This structure defines the chromaticity information for a single LFP panel.
+**/
+typedef struct {
+  /**
+  Defines the chromaticity feature enable bits
+  Bits 7:2  = Reserved
+  Bit 1     = Override EDID values for chromaticity if enabled, Instead Use VBT values
+            = 0, Disable, Use the EDID values
+            = 1, Enable, Use the values from the VBT
+  Bit 0     = Enable chromaticity feature. EDID values will be used when this feature is enabled.
+            = 0, Disable
+            = 1, Enable
+  **/
+  UINT8        EnableBits;
+
+  UINT8        Red_Green_1;   ///< Red/green chormaticity coordinates at EDID offset 19h
+  UINT8        Blue_White_1;  ///< Blue/white chromatiity coordinates at EDID offset 1Ah
+  UINT8        Red_X1;        ///< Red x coordinate at EDID offset 1Bh
+  UINT8        Red_Y1;        ///< Red x coordinate at EDID offset 1Ch
+  UINT8        Green_X1;      ///< Green x coordinate at EDID offset 1Dh
+  UINT8        Green_Y1;      ///< Green x coordinate at EDID offset 1Eh
+  UINT8        Blue_X1;       ///< Blue x coordinate at EDID offset 1Fh
+  UINT8        Blue_Y1;       ///< Blue x coordinate at EDID offset 20h
+  UINT8        White_X1;      ///< White x coordinate at EDID offset 21h
+  UINT8        White_Y1;      ///< White x coordinate at EDID offset 22h
+} CHROMATICITY;
+
+/**
+  This structure defines the Luminance information for a single LFP panel.
+**/
+typedef struct {
+  /**
+  Defines the chromaticity feature enable bits
+  Bits 7:2  : Reserved
+  Bit 1     : Enable Gamma feature.
+            : if enabled, use gamma values from this block.
+          0 : Disable
+          1 : Enable
+  Bit 0     : Enable Luminance feature.
+            : if enabled, use values from this block.
+          0 : Disable
+          1 : Enable
+  **/
+  UINT8        EnableBits;
+  /**
+    Luminance info (refer DisplayID 2.0)
+    2 byte value, encoded in IEEE 754 half-precision binary floating point format
+  **/
+  UINT16      MinLuminance;           ///< Native minimum luminance
+  UINT16      MaxFullFrameLuminance;  ///< Native maximum luminance (Full Frame)
+  UINT16      MaxLuminance;           ///< Native Maximum Luminance (1% Rectangular Coverage)
+  /**
+    Gamma EOTF
+    Gamma values range from 00h through FFh which will come from VBT.
+    Value shall define the gamma range, from 1.00 to 3.54.
+    Field Value = (Gamma (value from VBT) + 100) / 100
+
+    FFh = No gamma information shall be provided
+  **/
+  UINT8 Gamma;
+
+}LUMINANCE_AND_GAMMA;
+
+/**
+  This defines the structure of Block 46 (Chromaticity Support)
+**/
+typedef struct {
+  UINT8              BlockId;                 ///< Defines the unique Block ID : 46
+  UINT16             BlockSize;               ///< Defines the size of Chromaticity Block.
+  CHROMATICITY       Chromaticity_Struct[16]; ///< Defines the chromaticity information for all 16 panels.
+  LUMINANCE_AND_GAMMA  Luminance_Gamma_Struct[16];    ///< Defines the lumianance information for all 16 panels.
+} BLOCK46_CHROMATICITY_SUPPORT;
+
+/**
+  This defines the structure of Block 51 (Fixed Mode Set)
+**/
+typedef struct{
+  UINT8       BlockId;        ///< Defines the unique block ID : 51.
+  UINT16      BlockSize;      ///< Defines the size of Fixed mode set feature block.
+  UINT8       FeatureEnable;  ///< Whether the fixed mode set feature is enabled/disabled.
+  UINT32      XRes;           ///< X resolution of the fixed mode.
+  UINT32      YRes;           ///< Y resolution of the fixed mode.
+} BLOCK51_FIXED_MODE_SET;
+
+/**
+  This defines the Complete VBT Structure for generation purpose
+**/
+typedef struct {
+  VBT_HEADER                                VbtHeader;
+  VBT_BIOS_DATA_HEADER                      VbtBdbHeader;
+  BLOCK254_BMP_Structure                    Block254BMPStructure;
+  VBT_GENERAL1_INFO                         VbtGen1Info;
+  PRD_BOOT_TABLE                            PrdBootTable;
+  VBT_GENERAL2_INFO                         VbtGen2Info;
+  BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST      Block03OriginalDisplayToggleList;
+  BLOCK252_SBIOS_Hook                       Block252SbiosHook;
+  BLOCK06_MMIO_REG_TABLE                    Block06MmioRegTable;
+  BLOCK07_IOSWFLAG_REG_TABLE                Block07IoswflagRegTable;
+  BLOCK08_MMIOSWFLAG_REG_TABLE              Block08MmioswflagRegTable;
+  BLOCK09_PSR_FEATURE                       Block09PsrFeature;
+  BLOCK10_MODE_REMOVAL_TABLE                Block10ModeRemovalTable;
+  BLOCK12_DRIVER_FEATURES                   Block12DriverFeatures;
+  BLOCK13_DRIVER_PERSISTENCE                Block13DriverPersistence;
+  BLOCK17_SV_BITS                           Block17SvBits;
+  BLOCK18_DRIVER_ROTATION                   Block18DriverRotation;
+  BLOCK20_OEM_CUSTOMIZATION                 Block20OemCustomization;
+  BLOCK26_TV_OPTIONS                        Block26TVOptions;
+  BLOCK27_EDP_FEATURES                      Block27EDPFeatures;
+  BLOCK28_EDIDLESS_EFP                      Block28EdidlessEFP;
+  BLOCK31_TOGGLE_LIST                       Block31ToggleList;
+  BLOCK32_DISPLAY_CONFIGURATION_REMOVAL     Block32DisplayConfigurationRemoval;
+  BLOCK40_LVDS_FEATURES                     Block40LVDSFeatures;
+  BLOCK41_LFP_TABLE_POINTERS                Block41LfpTablePointers;
+  BLOCK42_LVDS_PANEL_INFO                   Block42LvdsPanelInfo;
+  BLOCK43_LVDS_BLC                          Block43LVDSBlc;
+  BLOCK44_ALS                               Block44Als;
+  BLOCK46_CHROMATICITY_SUPPORT              Block46ChromaticitySupport;
+  BLOCK51_FIXED_MODE_SET                    Block51FixedModeSet;
+} VBT_TABLE_DATA;
+
+#pragma pack()
+
+/**
+  This function will update the VBT checksum.
+
+  @param[in out] VbtPtr - Pointer to VBT table
+
+  @retval none
+**/
+VOID
+UpdateVbtChecksum(
+  VBT_TABLE_DATA *VbtPtr
+);
+
+/**
+  This function will update the VBT.
+
+  @param[in] VbtPtr - Pointer to VBT Table
+
+  @retval none
+**/
+VOID
+UpdateGopVbt (
+  IN  VBT_TABLE_DATA    *VbtPtr
+);
+#endif
+

+ 68 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h

@@ -0,0 +1,68 @@
+/** @file
+  GPIO definition table for CometlakeURvp
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IO_EXPANDER_H_
+#define _IO_EXPANDER_H_
+
+typedef struct {
+  UINT32 IoExpanderNumber   : 1;  // IO Expander Number (0/1)
+  UINT32 GpioPinNumber      : 5;  // GPIO Pin Number (0 to 23)
+  UINT32 GpioDirection      : 1;  // GPIO Pin Direction (Input/Output)
+  UINT32 GpioLevel          : 1;  // GPIO Pin Output Level (High/Low)
+  UINT32 GpioInversion     : 1;  // GPIO Pin Inversion (Enabled/Disabled)
+  UINT32 Reserved           : 23; // Reserved
+} IO_EXPANDER_GPIO_CONFIG;
+
+//CML PCH LP GPIO Expander Number
+#define IO_EXPANDER_0            0
+#define IO_EXPANDER_1            1
+
+//CML PCH LP GPIO Pin Mapping
+#define IO_EXPANDER_GPIO_0        0   // P00
+#define IO_EXPANDER_GPIO_1        1   // P01
+#define IO_EXPANDER_GPIO_2        2   // P02
+#define IO_EXPANDER_GPIO_3        3   // P03
+#define IO_EXPANDER_GPIO_4        4   // P04
+#define IO_EXPANDER_GPIO_5        5   // P05
+#define IO_EXPANDER_GPIO_6        6   // P06
+#define IO_EXPANDER_GPIO_7        7   // P07
+#define IO_EXPANDER_GPIO_8        8   // P10
+#define IO_EXPANDER_GPIO_9        9   // P11
+#define IO_EXPANDER_GPIO_10       10  // P12
+#define IO_EXPANDER_GPIO_11       11  // P13
+#define IO_EXPANDER_GPIO_12       12  // P14
+#define IO_EXPANDER_GPIO_13       13  // P15
+#define IO_EXPANDER_GPIO_14       14  // P16
+#define IO_EXPANDER_GPIO_15       15  // P17
+#define IO_EXPANDER_GPIO_16       16  // P20
+#define IO_EXPANDER_GPIO_17       17  // P21
+#define IO_EXPANDER_GPIO_18       18  // P22
+#define IO_EXPANDER_GPIO_19       19  // P23
+#define IO_EXPANDER_GPIO_20       20  // P24
+#define IO_EXPANDER_GPIO_21       21  // P25
+#define IO_EXPANDER_GPIO_22       22  // P26
+#define IO_EXPANDER_GPIO_23       23  // P27
+
+//CML PCH LP GPIO Expander GPIO Direction
+#define IO_EXPANDER_GPIO_OUTPUT   0
+#define IO_EXPANDER_GPIO_INPUT    1
+
+//CML PCH LP GPIO Expaner GPIO Output Level
+#define IO_EXPANDER_GPO_LEVEL_LOW    0
+#define IO_EXPANDER_GPO_LEVEL_HIGH   1
+
+//CML PCH LP GPIO Expaner GPIO Inversion Status
+#define IO_EXPANDER_GPI_INV_DISABLED  0
+#define IO_EXPANDER_GPI_INV_ENABLED   1
+#define IO_EXPANDER_GPIO_RESERVED     0x00
+
+//GPIO Table Terminator
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+#endif
+

+ 75 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpdateLib.h

@@ -0,0 +1,75 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_
+#define _DXE_CPU_POLICY_UPDATE_LIB_H_
+
+#include <PiDxe.h>
+#include <PchAccess.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/CpuPolicyProtocol.h>
+
+/**
+
+  This function prints the CPU DXE phase policy.
+
+  @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+  IN  DXE_CPU_POLICY_PROTOCOL  *DxeCpuPolicy
+  );
+
+/**
+
+Routine Description:
+
+  This function updates Dxe Cpu Policy Protocol
+
+Arguments:
+
+  @param[in] DxeCpuPolicy                 The Cpu Policy protocol instance
+
+Returns:
+
+  @retval EFI_SUCCESS                     Initialization complete.
+  @retval EFI_UNSUPPORTED                 The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES            Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR                Device error, driver exits abnormally.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+  IN OUT  DXE_CPU_POLICY_PROTOCOL  *DxeCpuPolicy
+  );
+
+/**
+
+  CpuInstallPolicyProtocol installs CPU Policy.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @param[in] ImageHandle                Image handle of this driver.
+  @param[in] DxeCpuPolicy               The pointer to CPU Policy Protocol instance
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+  IN  EFI_HANDLE                  ImageHandle,
+  IN  DXE_CPU_POLICY_PROTOCOL     *DxeCpuPolicy
+  );
+
+#endif
+

+ 27 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpdateLib.h

@@ -0,0 +1,27 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_ME_POLICY_UPDATE_LIB_H_
+#define _DXE_ME_POLICY_UPDATE_LIB_H_
+
+/**
+  Update the ME Policy Library
+
+  @param[in] DxeMePolicy                The pointer to get ME Policy protocol instance
+
+  @retval EFI_SUCCESS                   Initialization complete.
+  @retval EFI_UNSUPPORTED               The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES          Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR              Device error, driver exits abnormally.
+
+**/
+EFI_STATUS
+UpdateDxeMePolicy (
+  IN OUT  ME_POLICY_PROTOCOL      *DxeMePolicy
+  );
+
+#endif // _DXE_ME_POLICY_UPDATE_LIB_H_
+

+ 25 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpdateLib.h

@@ -0,0 +1,25 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_
+#define _DXE_PCH_POLICY_UPDATE_LIB_H_
+
+/**
+  Get data for platform policy from setup options.
+
+  @param[in] PchPolicy               The pointer to get PCH Policy protocol instance
+
+  @retval EFI_SUCCESS               Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxePchPolicy (
+  IN OUT  PCH_POLICY_PROTOCOL    *PchPolicy
+  );
+
+#endif
+

+ 30 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardConfigLib.h

@@ -0,0 +1,30 @@
+/** @file
+  Header file for the DxePolicyBoardConfig Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_
+#define _DXE_POLICY_BOARD_CONFIG_LIB_H_
+
+#include <Protocol/MePolicy.h>
+#include <Protocol/SaPolicy.h>
+
+/**
+  This function performs DXE SA Policy update by board configuration.
+
+  @param[in, out] DxeSaPolicy     DXE SA Policy
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicyBoardConfig (
+  IN OUT  SA_POLICY_PROTOCOL         *DxeSaPolicy
+  );
+
+#endif
+

+ 25 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdateLib.h

@@ -0,0 +1,25 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_SA_POLICY_UPDATE_LIB_H_
+#define _DXE_SA_POLICY_UPDATE_LIB_H_
+
+/**
+  Get data for platform policy from setup options.
+
+  @param[in] SaPolicy               The pointer to get SA Policy protocol instance
+
+  @retval EFI_SUCCESS               Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+  IN OUT  SA_POLICY_PROTOCOL    *SaPolicy
+  );
+
+#endif
+

+ 29 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h

@@ -0,0 +1,29 @@
+/** @file
+  Function prototype of FspPolicyInitLib.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSP_POLICY_INIT_LIB_H_
+#define _FSP_POLICY_INIT_LIB_H_
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+VOID
+EFIAPI
+FspPolicyInitPreMem (
+  IN FSPM_UPD           *FspmUpdDataPtr
+  );
+
+VOID
+EFIAPI
+FspPolicyInit (
+  IN OUT FSPS_UPD    *FspsUpd
+  );
+
+#endif // _FSP_POLICY_INIT_LIB_H_
+

+ 46 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflictLib.h

@@ -0,0 +1,46 @@
+/** @file
+  Header file for check Gpio PadMode conflict.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_CHECK_CONFLICT_LIB_H_
+#define _GPIO_CHECK_CONFLICT_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <GpioConfig.h>
+#include <Library/GpioLib.h>
+
+extern EFI_GUID gGpioCheckConflictHobGuid;
+
+typedef struct {
+  GPIO_PAD  GpioPad;
+  UINT32    GpioPadMode:5;
+  UINT32    Reserved:27;
+} GPIO_PAD_MODE_INFO;
+
+/**
+  Check Gpio PadMode conflict and report it.
+**/
+VOID
+GpioCheckConflict (
+  VOID
+  );
+
+/**
+  This libaray will create one Hob for each Gpio config table
+  without PadMode is GpioHardwareDefault
+
+  @param[in]  GpioDefinition    Point to Platform Gpio table
+  @param[in]  GpioTableCount    Number of Gpio table entries
+**/
+VOID
+CreateGpioCheckConflictHob (
+  IN GPIO_INIT_CONFIG          *GpioDefinition,
+  IN UINT16                    GpioTableCount
+  );
+
+#endif // _GPIO_CHECK_CONFLICT_LIB_H_
+

+ 123 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.h

@@ -0,0 +1,123 @@
+/** @file
+  Support for IO expander TCA6424.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_EXPANDER_LIB_H_
+#define _GPIO_EXPANDER_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+/**
+  Set the Direction value for the given Expander Gpio pin.
+
+  This function is to Set the direction value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+**/
+VOID
+GpioExpSetDirection (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Direction
+  );
+/**
+  Set the input value for the given Expander Gpio pin.
+
+  This function is to get the input value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetPolarity  (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Polarity
+  );
+/**
+  Set the Output value for the given Expander Gpio pin.
+
+  This function is to Set the Output value for the GPIO
+  Pin within the giving Expander.
+
+  @param[in]  Expander    Expander Value with in the Contoller
+  @param[in]  Pin         Pin with in the Expnader Value
+  @param[in]  Value       none
+
+**/
+VOID
+GpioExpSetOutput    (
+  IN UINT8 Expander,
+  IN UINT8 Pin,
+  IN UINT8 Value
+  );
+/**
+  Returns the data from register value giving in the input.
+
+  This function is to get the data from the Expander
+  Registers by following the I2C Protocol communication
+
+
+  @param[in]  Bar0       Bar address of the SerialIo Controller
+  @param[in]  Address    Expander Value with in the Contoller
+  @param[in]  Register   Address of Input/Output/Configure/Polarity
+                         registers with in the Expander
+
+  @retval     UINT8      Value returned from the register
+**/
+UINT8
+GpioExpGetInput     (
+  IN UINT8 Expander,
+  IN UINT8 Pin
+  );
+
+/**
+  Configures all registers of a single IO Expander in one go.
+
+  @param[in]  Expander    Expander number (0/1)
+  @param[in]  Direction   Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
+  @param[in]  Polarity    Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
+  @param[in]  Output      Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
+
+**/
+VOID
+GpioExpBulkConfig (
+  IN UINT8  Expander,
+  IN UINT32 Direction,
+  IN UINT32 Polarity,
+  IN UINT32 Output
+  );
+
+/**
+  Returns the Controller on which GPIO expander is present.
+
+  This function returns the Controller value
+
+  @param[out] Controller              Pointer to a Controller value on
+                                      which I2C expander is configured.
+
+  @retval     EFI_SUCCESS              non.
+**/
+EFI_STATUS
+GpioExpGetController (
+  OUT UINT8 *Controller
+  );
+
+#endif
+

+ 48 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.h

@@ -0,0 +1,48 @@
+/** @file
+
+  Header file for the Intel HD Audio Verb Table library.
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _HDA_VERB_TABLE_LIB_H_
+#define _HDA_VERB_TABLE_LIB_H_
+
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Library/BaseLib.h>
+
+enum HDAUDIO_CODEC_SELECT {
+  PchHdaCodecPlatformOnboard = 0,
+  PchHdaCodecExternalKit     = 1
+};
+
+/**
+  Add verb table function.
+  This function update the verb table number and verb table ptr of policy.
+
+  @param[in]  HdAudioConfig            HD Audio config block
+  @param[out] VerbTableEntryNum        Number of verb table entries
+  @param[out] HdaVerbTablePtr          Pointer to the verb table
+**/
+VOID
+AddPlatformVerbTables (
+  IN   UINT8              CodecType,
+  OUT  UINT8              *VerbTableEntryNum,
+  OUT  UINT32             *HdaVerbTablePtr
+  );
+
+/**
+  HDA VerbTable init function for PEI post memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+HdaVerbTableInit(
+  IN UINT16 BoardId
+  );
+
+#endif

+ 34 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h

@@ -0,0 +1,34 @@
+/** @file
+  Support for IO expander TCA6424.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _I2C_ACCESS_LIB_H_
+#define _I2C_ACCESS_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+#define WAIT_1_SECOND            1600000000 //1.6 * 10^9
+
+EFI_STATUS
+I2cWriteRead (
+  IN UINTN  MmioBase,
+  IN UINT8  SlaveAddress,
+  IN UINT8  WriteLength,
+  IN UINT8  *WriteBuffer,
+  IN UINT8  ReadLength,
+  IN UINT8  *ReadBuffer,
+  IN UINT64  TimeBudget
+  );
+
+#endif
+

+ 40 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h

@@ -0,0 +1,40 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED  1
+
+typedef struct {
+  UINT8   Register;
+  UINT32  Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+  PCH_GPIO_DEV Use_Sel;
+  PCH_GPIO_DEV Use_Sel2;
+  PCH_GPIO_DEV Use_Sel3;
+  PCH_GPIO_DEV Io_Sel;
+  PCH_GPIO_DEV Io_Sel2;
+  PCH_GPIO_DEV Io_Sel3;
+  PCH_GPIO_DEV Lvl;
+  PCH_GPIO_DEV Lvl2;
+  PCH_GPIO_DEV Lvl3;
+  PCH_GPIO_DEV Inv;
+  PCH_GPIO_DEV Blink;
+  PCH_GPIO_DEV Rst_Sel;
+  PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+

+ 141 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h

@@ -0,0 +1,141 @@
+/** @file
+  Header file for the PeiPolicyBoardConfig Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_
+#define _PEI_POLICY_BOARD_CONFIG_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+  This function performs PEI CPU Pre-Memory Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI PreMem Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+  IN OUT   SI_PREMEM_POLICY_PPI      *SiPreMemPolicyPpi
+  );
+
+/**
+  This function performs PEI ME Pre-Memory Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI PreMem Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+  IN OUT   SI_PREMEM_POLICY_PPI      *SiPreMemPolicyPpi
+  );
+
+/**
+  This function performs PEI PCH Pre-Memory Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI PreMem Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+  IN OUT   SI_PREMEM_POLICY_PPI      *SiPreMemPolicyPpi
+  );
+
+/**
+  This function performs PEI SA Pre-Memory Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI PreMem Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+  IN OUT   SI_PREMEM_POLICY_PPI      *SiPreMemPolicyPpi
+  );
+
+/**
+  This function performs PEI CPU Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfig (
+  IN OUT  SI_POLICY_PPI              *SiPolicyPpi
+  );
+
+/**
+  This function performs PEI ME Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+  IN OUT  SI_POLICY_PPI              *SiPolicyPpi
+  );
+
+/**
+  This function performs PEI PCH Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfig (
+  IN OUT  SI_POLICY_PPI              *SiPolicyPpi
+  );
+
+/**
+  This function performs PEI SA Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+  IN OUT  SI_POLICY_PPI              *SiPolicyPpi
+  );
+
+/**
+  This function performs PEI SI Policy update by board configuration.
+
+  @param[in, out] SiPolicy        The SI Policy PPI instance
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+  IN OUT  SI_POLICY_PPI              *SiPolicyPpi
+  );
+
+#endif
+

+ 38 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h

@@ -0,0 +1,38 @@
+/** @file
+  Header file for the PolicyInitPei Library.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _POLICY_INIT_PEI_LIB_H_
+#define _POLICY_INIT_PEI_LIB_H_
+
+/**
+  Initialize Intel PEI Platform Policy
+
+  @param[in]  FirmwareConfiguration  It uses to skip specific policy init that depends
+                                     on the 'FirmwareConfiguration' varaible.
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+  IN UINT8                     FirmwareConfiguration
+  );
+
+/**
+  Initialize Intel PEI Platform Policy
+
+  @param[in] PeiServices            General purpose services available to every PEIM.
+  @param[in] FirmwareConfiguration  It uses to skip specific policy init that depends
+                                    on the 'FirmwareConfiguration' varaible.
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+//  IN CONST EFI_PEI_SERVICES    **PeiServices,
+  IN UINT8                     FirmwareConfiguration
+  );
+#endif
+

+ 23 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h

@@ -0,0 +1,23 @@
+/** @file
+  Function prototype of PlatformInitLib.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INIT_LIB_H_
+#define _PLATFORM_INIT_LIB_H_
+
+VOID
+PlatformLateInit (
+  VOID
+  );
+
+VOID
+InitSerialPort (
+  VOID
+  );
+
+#endif // _PLATFORM_INIT_LIB_H_
+

+ 51 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h

@@ -0,0 +1,51 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef PCH_HSIO_PTSSTABLES_H_
+#define PCH_HSIO_PTSSTABLES_H_
+
+#include <PchAccess.h>
+
+///
+/// SATA PTSS Topology Types
+///
+typedef enum {
+  PchSataTopoUnknown = 0x00,
+  PchSataTopoIsata,
+  PchSataTopoDirectConnect,
+  PchSataTopoFlex,
+  PchSataTopoM2
+} PCH_SATA_TOPOLOGY;
+
+///
+/// PCIe PTSS Topology Types
+///
+typedef enum {
+  PchPcieTopoUnknown = 0x00,
+  PchPcieTopox1,
+  PchPcieTopox4,
+  PchPcieTopoSataE,
+  PchPcieTopoM2
+} PCH_PCIE_TOPOLOGY;
+
+///
+/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH.
+///
+typedef struct {
+  UINT8       LaneNum;
+  UINT8       PhyMode;
+  UINT16      Offset;
+  UINT32      Value;
+  UINT32      BitMask;
+} PCH_SBI_PTSS_HSIO_TABLE;
+
+typedef struct {
+  PCH_SBI_PTSS_HSIO_TABLE   PtssTable;
+  UINT16                    Topology;
+} HSIO_PTSS_TABLES;
+
+#endif // PCH_HSIO_PTSSTABLES_H_
+

+ 106 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h

@@ -0,0 +1,106 @@
+/** @file
+  PCIe Device Override Table
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_
+#define _PCIE_DEVICE_OVERRIDE_TABLE_H_
+
+#include <ConfigBlock/PcieRpConfig.h>
+#include <IndustryStandard/Pci22.h>
+
+#define PCI_CLASS_NETWORK             0x02
+#define PCI_CLASS_NETWORK_ETHERNET    0x00
+#define PCI_CLASS_NETWORK_OTHER       0x80
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
+  //
+  // Intel PRO/Wireless
+  //
+  { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel WiMAX/WiFi Link
+  //
+  { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Crane Peak WLAN NIC
+  //
+  { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Crane Peak w/BT WLAN NIC
+  //
+  { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Kelsey Peak WiFi, WiMax
+  //
+  { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 105
+  //
+  { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 135
+  //
+  { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 2200
+  //
+  { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 2230
+  //
+  { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel Centrino Wireless-N 6235
+  //
+  { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel CampPeak 2 Wifi
+  //
+  { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+  //
+  // Intel WilkinsPeak 1 Wifi
+  //
+  { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  //
+  // Intel Wilkins Peak 2 Wifi
+  //
+  { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+  //
+  // Intel Wilkins Peak PF Wifi
+  //
+  { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },
+
+  //
+  // End of Table
+  //
+  { 0 }
+};
+
+#endif

+ 33 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h

@@ -0,0 +1,33 @@
+/** @file
+  This header file provides platform specific definitions used
+  by other modules for platform specific initialization.
+  This is not suitable for consumption by ASL or VRF files.
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+//#include "CommonDefinitions.h"
+#include "PchAccess.h"
+#include "SaAccess.h"
+
+//
+// Need minimum of 48MB during PEI phase for IAG and some buffer for boot.
+//
+#define  PEI_MIN_MEMORY_SIZE               (10 * 0x800000 + 0x10000000)   // 80MB + 256MB
+#define  PEI_RECOVERY_MIN_MEMORY_SIZE      (10 * 0x800000 + 0x10000000)   // 80MB + 256MB
+
+#define FLASH_BLOCK_SIZE  0x10000
+
+#define CPU_EXTERNAL_CLOCK_FREQ  0x64
+#define CPU_FREQUENCY_MODE_100  0x64
+#define FREQUENCY_RESOLUTION_3182  0xc6e
+#define NDIVIDER_BASE_VALUE  0x19d
+#define MDIVIDER_VALUE_13  0xd
+
+#endif
+

+ 29 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h

@@ -0,0 +1,29 @@
+/** @file
+Defines Platform BoardIds
+
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+#define FlavorUnknown                       0x0
+#define FlavorMobile                        0x1
+#define FlavorDesktop                       0x2
+#define FlavorWorkstation                   0x3
+#define FlavorUpServer                      0x4
+#define FlavorEmbedded                      0x5
+#define FlavorPlatformMax                   0x6
+
+#define TypeUnknown                         0x0
+#define TypeTrad                            0x1
+#define TypeUltUlx                          0x2
+
+#define BoardIdCometLakeULpddr3Rvp          0x1
+
+#define BoardIdUnknown1                     0xffff
+
+#endif
+

+ 47 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h

@@ -0,0 +1,47 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+
+#define GLOBAL_NVS_AREA_REVISION       16
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#include <Acpi/GlobalNvsAreaDef.h>
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA     *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
+

+ 144 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h

@@ -0,0 +1,144 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SETUP__H__
+#define __SETUP__H__
+
+#ifndef MDEPKG_NDEBUG
+#define DEBUG_INTERFACE_FORM_ENABLE
+#endif // MDEPKG_NDEBUG
+//
+// Form class guid for the forms those will be showed on first front page.
+//
+#define FRONT_PAGE_GUID        { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a, 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } }
+//
+// Form class guid for the forms those will be showed on boot maintenance manager menu.
+//
+#define BOOT_MAINTENANCE_GUID  { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a, 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } }
+
+// VFR common Definitions
+#define INVENTORY(Name,Value) \
+    text \
+      help  = STRING_TOKEN(STR_EMPTY), \
+      text  = Name, \
+      text  = Value, \
+      flags = 0, \
+      key   = 0;
+
+#define SUBTITLE(Text) subtitle text = Text;
+#define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY))
+
+#define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\
+  grayoutif TRUE;\
+    oneof varid        = SETUP_DATA.InteractiveText,\
+      questionid       = Key,\
+      prompt           = CaptionToken,\
+      help             = HelpToken,\
+      option text      = ValueToken, value = 0, flags = INTERACTIVE | DEFAULT;\
+      refresh interval = 1 \
+    endoneof;\
+  endif;
+
+#define SUPPRESS_GRAYOUT_ENDIF endif; endif;
+#define DEFAULT_FLAG
+
+#define SYSTEM_ACCESS_KEY_ID            0xF000
+//
+// System Access defintions.
+//
+#define SYSTEM_ACCESS_GUID \
+ { 0xE770BB69, 0xBCB4, 0x4D04, { 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE, 0xAC }}
+
+#define SYSTEM_PASSWORD_ADMIN 0
+#define SYSTEM_PASSWORD_USER  1
+#define ADMIN_PW_CLEAR        0
+#define ADMIN_PW_SET          1
+
+
+typedef struct _SYSTEM_ACCESS
+{
+  //
+  // Passwords
+  //
+  UINT8       Access;
+} SYSTEM_ACCESS;
+
+//
+// Record the password status.
+//
+typedef struct {
+  UINT8   AdminName;
+  UINT8   UserName;
+} EFI_PASSWORD_STATUS;
+
+//
+// Config Data
+//
+typedef struct {
+  UINT8 SerialDebug;
+  UINT8 SerialDebugBaudRate;
+  UINT8 RamDebugInterface;
+  UINT8 UartDebugInterface;
+  UINT8 Usb3DebugInterface;
+  UINT8 SerialIoDebugInterface;
+  UINT8 TraceHubDebugInterface;
+} DEBUG_CONFIG_DATA;
+
+//
+// Config Data Hob
+//
+#define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA
+
+//
+// Secure Boot Data
+//
+typedef struct{
+  UINT8   SecureBoot;
+} SECURE_BOOT_VARIABLE;
+
+#pragma pack()
+
+//
+// Varstore statement
+// Setup is EfiVarStore that is related to EFI variable with attribute 0x07
+// (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS)
+//
+#define SETUP_DATA_VARSTORE\
+    efivarstore SETUP_DATA, varid = 1,\
+        attribute = 0x7, name = Setup, guid = SETUP_GUID;
+#define SA_SETUP_VARSTORE\
+    efivarstore SA_SETUP, varid = 2,\
+        attribute = 0x7, name = SaSetup, guid = SA_SETUP_GUID;
+#define CPU_SETUP_VARSTORE\
+    efivarstore CPU_SETUP, varid = 3,\
+        attribute = 0x7, name = CpuSetup, guid = CPU_SETUP_GUID;
+#define ME_SETUP_VARSTORE\
+    efivarstore ME_SETUP, varid = 4,\
+        attribute = 0x7, name = MeSetup, guid = ME_SETUP_GUID;
+#define PCH_SETUP_VARSTORE\
+    efivarstore PCH_SETUP, varid = 5,\
+        attribute = 0x7, name = PchSetup, guid = PCH_SETUP_GUID;
+#define SI_SETUP_VARSTORE\
+    efivarstore SI_SETUP, varid = 6,\
+        attribute = 0x7, name = SiSetup, guid = SI_SETUP_GUID;
+#ifdef DEBUG_INTERFACE_FORM_ENABLE
+#define DEBUG_CONFIG_DATA_ID            0xF001
+#define DEBUG_CONFIG_DATA_VARSTORE\
+    efivarstore DEBUG_CONFIG_DATA, varid = DEBUG_CONFIG_DATA_ID,\
+        attribute = 0x7, name = DebugConfigData, guid = DEBUG_CONFIG_GUID;
+#endif // DEBUG_INTERFACE_FORM_ENABLE
+#define SYSTEM_ACCESS_VARSTORE\
+    varstore SYSTEM_ACCESS, varid = SYSTEM_ACCESS_KEY_ID,\
+        name = SystemAccess, guid = SYSTEM_ACCESS_GUID;
+#define SYSTEM_PASSWORD_VARSTORE\
+    varstore EFI_PASSWORD_STATUS,\
+        name = PasswordStatus, guid = SYSTEM_ACCESS_GUID;
+
+#define BOOT_FLOW_CONDITION_RECOVERY   2
+#define BOOT_FLOW_CONDITION_FIRST_BOOT 4
+
+#endif
+

+ 157 - 0
Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h

@@ -0,0 +1,157 @@
+/** @file
+
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SIO_REG_H_
+#define _SIO_REG_H_
+
+#define REG_LOGICAL_DEVICE        0x07
+#define ACTIVATE                  0x30
+
+#define BASE_ADDRESS_HIGH0        0x60
+#define BASE_ADDRESS_LOW0         0x61
+#define BASE_ADDRESS_HIGH1        0x62
+#define BASE_ADDRESS_LOW1         0x63
+#define BASE_ADDRESS_HIGH2        0x64
+#define BASE_ADDRESS_LOW2         0x65
+#define BASE_ADDRESS_HIGH3        0x66
+#define BASE_ADDRESS_LOW3         0x67
+#define PRIMARY_INTERRUPT_SELECT  0x70
+#define WAKEUP_ON_IRQ_EN          0x70
+#define INTERRUPT_TYPE            0x71
+#define DMA_CHANNEL_SELECT0       0x74
+#define DMA_CHANNEL_SELECT1       0x75
+
+
+
+//
+//Port address for PILOT - III
+//
+#define PILOTIII_CHIP_ID         0x03
+#define PILOTIII_SIO_INDEX_PORT  0x04E
+#define PILOTIII_SIO_DATA_PORT   (PILOTIII_SIO_INDEX_PORT+1)
+
+#define PILOTIII_UNLOCK      0x5A
+#define PILOTIII_LOCK        0xA5
+
+//
+// logical device in PILOT-III
+//
+#define PILOTIII_SIO_PSR     0x00
+#define PILOTIII_SIO_COM2    0x01
+#define PILOTIII_SIO_COM1    0x02
+#define PILOTIII_SIO_SWCP    0x03
+#define PILOTIII_SIO_GPIO    0x04
+#define PILOTIII_SIO_WDT     0x05
+#define PILOTIII_SIO_KCS3    0x08
+#define PILOTIII_SIO_KCS4    0x09
+#define PILOTIII_SIO_KCS5    0x0A
+#define PILOTIII_SIO_BT      0x0B
+#define PILOTIII_SIO_SMIC    0x0C
+#define PILOTIII_SIO_MAILBOX 0x0D
+#define PILOTIII_SIO_RTC     0x0E
+#define PILOTIII_SIO_SPI     0x0F
+#define PILOTIII_SIO_TAP     0x10
+//
+// Regisgers for Pilot-III
+//
+#define PILOTIII_CHIP_ID_REG               0x20
+#define PILOTIII_LOGICAL_DEVICE            REG_LOGICAL_DEVICE
+#define PILOTIII_ACTIVATE                  ACTIVATE
+#define PILOTIII_BASE_ADDRESS_HIGH0        BASE_ADDRESS_HIGH0
+#define PILOTIII_BASE_ADDRESS_LOW0         BASE_ADDRESS_LOW0
+#define PILOTIII_BASE_ADDRESS_HIGH1        BASE_ADDRESS_HIGH1
+#define PILOTIII_BASE_ADDRESS_LOW1         BASE_ADDRESS_LOW1
+#define PILOTIII_PRIMARY_INTERRUPT_SELECT  PRIMARY_INTERRUPT_SELECT
+
+//
+// Port address for PC8374
+//
+#define PC8374_SIO_INDEX_PORT  0x02E
+#define PC8374_SIO_DATA_PORT   (PC8374_SIO_INDEX_PORT+1)
+
+//
+// Logical device in PC8374
+//
+#define PC8374_SIO_FLOPPY  0x00
+#define PC8374_SIO_PARA    0x01
+#define PC8374_SIO_COM2    0x02
+#define PC8374_SIO_COM1    0x03
+#define PC8374_SIO_MOUSE   0x05
+#define PC8374_SIO_KYBD    0x06
+#define PC8374_SIO_GPIO    0x07
+
+//
+// Registers specific for PC8374
+//
+#define PC8374_CLOCK_SELECT  0x2D
+#define PC8374_CLOCK_CONFIG  0x29
+
+//
+// Registers for PC8374
+//
+#define PC8374_LOGICAL_DEVICE            REG_LOGICAL_DEVICE
+#define PC8374_ACTIVATE                  ACTIVATE
+#define PC8374_BASE_ADDRESS_HIGH0        BASE_ADDRESS_HIGH0
+#define PC8374_BASE_ADDRESS_LOW0         BASE_ADDRESS_LOW0
+#define PC8374_PRIMARY_INTERRUPT_SELECT  PRIMARY_INTERRUPT_SELECT
+#define PC8374_DMA_CHANNEL_SELECT        DMA_CHANNEL_SELECT0
+
+#define PC87427_SERVERIO_CNF2           0x22
+
+
+//
+// Pilot III Mailbox Data Register definitions
+//
+#define MBDAT00_OFFSET                  0x00
+#define MBDAT01_OFFSET                  0x01
+#define MBDAT02_OFFSET                  0x02
+#define MBDAT03_OFFSET                  0x03
+#define MBDAT04_OFFSET                  0x04
+#define MBDAT05_OFFSET                  0x05
+#define MBDAT06_OFFSET                  0x06
+#define MBDAT07_OFFSET                  0x07
+#define MBDAT08_OFFSET                  0x08
+#define MBDAT09_OFFSET                  0x09
+#define MBDAT10_OFFSET                  0x0A
+#define MBDAT11_OFFSET                  0x0B
+#define MBDAT12_OFFSET                  0x0C
+#define MBDAT13_OFFSET                  0x0D
+#define MBDAT14_OFFSET                  0x0E
+#define MBDAT15_OFFSET                  0x0F
+#define MBST0_OFFSET                    0x10
+#define MBST1_OFFSET                    0x11
+#define MBBINT_OFFSET                   0x12
+
+//
+// Mailbox Bit definitions...
+//
+#define   MBBINT_MBBIST_BIT               0x80
+// If both are there, use the default one
+//
+#define  W83527_EXIST     BIT2
+#define  PC8374_EXIST     BIT1
+#define  PILOTIII_EXIST   BIT0
+#define  DEFAULT_SIO      PILOTIII_EXIST
+#define  DEFAULT_KDB      PC8374_EXIST
+
+#define IPMI_DEFAULT_SMM_IO_BASE           0xca2
+//
+// For Pilot III
+//
+
+#define PILOTIII_SWC_BASE_ADDRESS          0xA00
+#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
+#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
+#define PILOTIII_GPE1_BLK_BASE_ADDRESS     0x0A86
+#define PILOTIII_KCS3_DATA_BASE_ADDRESS    0x0CA4
+#define PILOTIII_KCS3_CMD_BASE_ADDRESS     0x0CA5
+#define PILOTIII_KCS4_DATA_BASE_ADDRESS    0x0CA2
+#define PILOTIII_KCS4_CMD_BASE_ADDRESS     0x0CA3
+#define PILOTIII_MAILBOX_BASE_ADDRESS      0x0600
+#define PILOTIII_MAILBOX_MASK              0xFFE0
+#define BMC_KCS_BASE_ADDRESS               0x0CA0
+#endif
+

+ 564 - 0
Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec

@@ -0,0 +1,564 @@
+## @file
+# Module describe the entire platform configuration.
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = OpenBoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = 7F1FFF90-0F5F-4980-88FE-A9E683CFBB32
+
+[Includes]
+Include
+Features/Tbt/Include
+CometlakeURvp/Include
+
+[Guids]
+
+gCometlakeOpenBoardPkgTokenSpaceGuid  =  {0xfe2ab368, 0x7cc1, 0x4de8, {0xb7, 0x19, 0xad, 0x56, 0xee, 0xb8, 0xcc, 0x84}}
+
+gTianoLogoGuid                        =  {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+gTbtInfoHobGuid                       =  {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}
+
+gPlatformModuleTokenSpaceGuid         =  {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+
+gMeInfoSetupGuid                      =  {0x78259433, 0x7b6d, 0x4db3, {0x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d}}
+gRealModeFileGuid                     =  {0xdf84ed23, 0x5d53, 0x423f, {0xaa, 0x81, 0x0f, 0x0e, 0x6f, 0x55, 0xc6, 0x9b}}
+gVirtualKeyboardDriverImageGuid       =  {0xe4735aac, 0x9c27, 0x493f, {0x86, 0xea, 0x9e, 0xff, 0x43, 0xd7, 0xad, 0xcd}}
+gPegConfigVariableGuid                =  {0xb414caf8, 0x8225, 0x4d6f, {0xb9, 0x18, 0xcd, 0xe5, 0xcb, 0x84, 0xcf, 0x0b}}
+gSaSetupVariableGuid                  =  {0x72c5e28c, 0x7783, 0x43a1, {0x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}}
+gMeSetupVariableGuid                  =  {0x5432122d, 0xd034, 0x49d2, {0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}}
+gCpuSetupVariableGuid                 =  {0xb08f97ff, 0xe6e8, 0x4193, {0xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa,  0xdb, 0x32}}
+gCpuSmmGuid                           =  {0x90d93e09, 0x4e91, 0x4b3d, {0x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe,  0x3c, 0x81}}
+gPchSetupVariableGuid                 =  {0x4570b7f1, 0xade8, 0x4943, {0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}}
+gSiSetupVariableGuid                  =  {0xAAF8E719, 0x48F8, 0x4099, {0xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}}
+gDebugConfigVariableGuid              =  {0xDE0A5E74, 0x4E3E, 0x3D96, {0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}}
+gDebugConfigHobGuid                   =  {0x2f6a6bb7, 0x9dc7, 0x4bf6, {0x94, 0x04, 0x22, 0x70, 0xc0, 0xe3, 0xbe, 0x2f}}
+gChassisIntrudeDetHobGuid             =  {0xdea43de2, 0x756b, 0x4b3b, {0x75, 0x1c, 0xad, 0xeb, 0x8d, 0xff, 0x56, 0xa3}}
+
+gGpioCheckConflictHobGuid             =  {0x5603f872, 0xefac, 0x40ae, {0xb9, 0x7e, 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}}
+
+gAttemptUsbFirstHotkeyInfoHobGuid     =  {0x38b8e214, 0x1468, 0x4bb7, {0x95, 0xb1, 0x74, 0x59, 0x1e, 0x4c, 0x6e, 0x1d}}
+gTianoLogoGuid                        =  {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+##
+## ChipsetInitBinary
+##
+gCnlPchLpChipsetInitTableDxGuid          =  {0xc9505bc0, 0xaa3d, 0x4056, {0x99, 0x95, 0x87, 0x0c, 0x8d, 0xe8, 0x59, 0x4e}}
+
+
+[Protocols]
+gTbtNvsAreaProtocolGuid               =  {0x4d6a54d1, 0xcd56, 0x47f3, {0x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}}
+gDxeTbtPolicyProtocolGuid             =  {0x196bf9e3, 0x20d7, 0x4b7b, {0x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}}
+
+[Ppis]
+gPeiTbtPolicyPpiGuid                  =  {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}
+gPeiTbtPolicyBoardInitDonePpiGuid     =  {0x970f9c60, 0x8547, 0x49d7, { 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}}
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+
+[PcdsFixedAtBuild]
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005
+
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x90000003
+gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|0x90000005
+gPlatformModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000006
+gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress|0xFED84000|UINT64|0x90000007
+gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize|0x1000|UINT32|0x90000008
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x90000009
+gPlatformModuleTokenSpaceGuid.PcdEdramMmioSize|0x4000|UINT32|0x9000000A
+gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000000B
+gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize|0x1000|UINT32|0x9000000C
+gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000D
+gPlatformModuleTokenSpaceGuid.PcdApicIoMmioSize|0x1000|UINT32|0x9000000E
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xCF000000|UINT64|0x9000000F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xD0000000|UINT64|0x90000010
+gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+gPlatformModuleTokenSpaceGuid.PcdPcieDockBridgeResourcePatchSmi|0x4D|UINT8|0x90000014
+gPlatformModuleTokenSpaceGuid.PcdCmosFastBootDefaultValue|0x01|UINT8|0x90000016
+gPlatformModuleTokenSpaceGuid.PcdCmosDebugPrintErrorLevelDefaultValue|0x80000046|UINT32|0x90000017
+gPlatformModuleTokenSpaceGuid.PcdOverClockingInterfaceSwSmi|0x72|UINT8|0x90000019
+gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|UINT16|0x9000001A
+gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E|UINT16|0x9000001B
+gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHeaderLength|0x48|UINT8|0x90000020
+gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x20000505
+gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT32|0x10001003
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000021
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x90000022
+
+[PcdsDynamic]
+# Board GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114
+
+# Board Expander GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047
+
+# TouchPanel & SDHC CD GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048
+
+# PCH-LP HSIO PTSS Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x0000004C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x0000004D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x00000050
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x00000051
+
+# PCH-H HSIO PTSS Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000058
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000059
+
+# HDA Verb Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060
+
+# SA Misc Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101
+
+# DRAM Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x0000006E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071
+
+# PEG RESET GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F
+
+# SPD Address Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C
+
+# CA Vref Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
+
+# USB 2.0 Port AFE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE
+
+# USB 2.0 Port Over Current Pin
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE
+
+# USB 3.0 Port Over Current Pin
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8
+
+# Misc
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC
+
+# TBT
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109
+
+# UCMC GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C
+
+# 0: Type-C
+# 1: Stacked-Jack
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013
+
+# gIntelPeiGraphicsVbtGuid =  {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}}
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|0x40000014
+#==============================================================
+#
+# The PCD which indicates the Memory Slot Population.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|BOOLEAN|0x00101027
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UINT64|0x00000010
+
+# Board GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|UINT32|0x001000115
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize|0|UINT16|0x001000116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0|UINT32|0x001000117
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize|0|UINT16|0x001000118
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT32|0x0010020C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x0010022E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x00100231
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x00100235
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|0x00100236
+
+# UCMC GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034
+
+# PEG RESET GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x00000074
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|0x00000075
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x00000105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|0x00000106
+
+# PCIE RTD3 GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x00000082
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00000083
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0x00000084
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0x00000085
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00000086
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN|0x00000087
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0000008A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000008B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0x0000008C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0x0000008D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x0000008E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN|0x0000008F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x00000132
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00000133
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0x00000134
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0x00000135
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00000136
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN|0x00000137
+
+# Root Port Clock Info
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+
+# GPIO Group Tier
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB
+
+# Board related PCH PmConfig
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEAN|0x000000F6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0x000000F7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0x000000F8
+
+# Misc
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x000000EF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000F0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x000000F1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x000000F2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x000000F9
+#gCometlakeOpenBoardPkgTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000000FC
+
+#PlatformInfoPcd
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101000
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101001
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x00101002
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123456789ABCDEF"|VOID*|0x00101007
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x00101008
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x00101009
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBiosVersion|L"0123456789012345678901234567890123456789"|VOID*|0x0010100E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789"|VOID*|0x0010100F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789"|VOID*|0x00101010
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101013
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A
+
+# PCH Misc Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0x00000061
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00000102
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x00000103
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110
+
+# Control PCD to dump default silicon policy
+gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOOLEAN|0x00010064
+
+# Pch SerialIo I2c Pads Termination
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x00000020
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x00000021
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x00000022
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x00000023
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x00000030
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x00000031
+#
+# The PCD which holds the pointer of Smbios Platform Info table
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010101B
+#
+# The PCD which used to enable / disable the code to use RVP Smbios Board Info
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEAN|0x0010101C
+#
+# The PCD which holds the pointer of RVP Smbios Board Info
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D
+#
+# CoEngineering Custom Defaults PCD
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT8|0x00100227
+#
+# The PCD which is defined to enable/disable the SMBus Alert function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E
+#
+# The PCD which is defined to enable/disable the SATA LED function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010101F
+#
+# The PCD which is defined to enable/disable the VR Alert function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020
+#
+# The PCD which is defined to enable/disable the PCH thermal hot threshold function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|0x00101021
+#
+# The PCD which is defined to enable/disable the memory thermal sensor GPIO C/D function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable|TRUE|BOOLEAN|0x00101022
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable|TRUE|BOOLEAN|0x00101023
+#
+# The PCD defines the I2C bus number to which PSS chip connected.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101025
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101026
+#
+# The PCD defines the USB port number to which BLE connected.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber                     |0x0|UINT8|0x00101028
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support                    |0x00|UINT8|0x00100113
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support                    |0x00|UINT8|0x00100114
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support                    |0x00|UINT8|0x00100115
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support                    |0x00|UINT8|0x00100116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support                    |0x00|UINT8|0x00100117
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support                    |0x00|UINT8|0x00100118
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport         |FALSE|BOOLEAN|0x00100119
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport       |FALSE|BOOLEAN|0x0010011A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport       |FALSE|BOOLEAN|0x0010011B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport     |FALSE|BOOLEAN|0x0010011C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport               |FALSE|BOOLEAN|0x0010011D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport                |FALSE|BOOLEAN|0x0010011F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin                 |0x00|UINT32|0x00100120
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport           |FALSE|BOOLEAN|0x00100121
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport           |FALSE|BOOLEAN|0x00100122
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature                  |FALSE|BOOLEAN|0x00100123
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent                       |0x0|UINT8|0x00100124
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00100212
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x00100213
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x00100209
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x0010020A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x0010020F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x00100210
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio                   |0x0|UINT32|0x00100126
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber              |0x0|UINT8|0x00100127
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio                   |0x0|UINT32|0x00100125
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|0x00100202
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00100217
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010003A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0010003B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010003D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0010003E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00100040
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x00100041
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00100043
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x00100044
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00100046
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x00100047
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00100049
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0010004A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed                     |0x0|UINT8|0x00100128
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed                     |0x0|UINT8|0x00100129
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed                     |0x0|UINT8|0x0010012A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed                     |0x0|UINT8|0x0010012B
+
+# Super IO Pcd
+gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF0000100
+gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0xF0000104
+gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0000105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport               |FALSE|BOOLEAN|0x00100112
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin                     |0x00|UINT32|0x00100111
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control                  |0x00|UINT8|0x00100103
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control                  |0x00|UINT8|0x00100104
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCmlURtd3TableEnable|FALSE|BOOLEAN|0x0010022C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0010004B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor                        |FALSE|BOOLEAN|0x00100105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO                           |FALSE|BOOLEAN|0x0010010A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM                          |FALSE|BOOLEAN|0x00100107
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO                          |FALSE|BOOLEAN|0x00100108
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON                        |FALSE|BOOLEAN|0x00100109
+
+[PcdsDynamicEx]
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable      |TRUE|BOOLEAN|0xF0000062
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport   |TRUE|BOOLEAN|0xF0000000
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable           |FALSE|BOOLEAN|0x000000115
+