TbtPolicyCommonDefinition.h 4.3 KB

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  1. /** @file
  2. TBT Policy Common definition.
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _TBT_POLICY_COMMON_H_
  7. #define _TBT_POLICY_COMMON_H_
  8. #include <Library/GpioLib.h>
  9. #include <IndustryStandard/Pci22.h>
  10. #define MAX_DTBT_CONTROLLER_NUMBER 2
  11. #define TYPE_PCIE 0x01
  12. #define TYPE_PEG 0x02
  13. #pragma pack(push, 1)
  14. //
  15. // dTBT Force Power GPIO Data Structure
  16. //
  17. typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
  18. GPIO_PAD GpioPad; ///< GPIO Pad Number
  19. BOOLEAN GpioLevel; ///< 0 = Active Low; 1 = Active High
  20. UINT8 Reserved[3]; ///< Reserved for DWORD alignment
  21. } DTBT_FORCE_POWER_GPIO_CONFIG;
  22. //
  23. // dTBT CIO Plug Event GPIO Data Structure
  24. //
  25. typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
  26. GPIO_PAD GpioPad; ///< GPIO Pad Number
  27. UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will change the XTBT method to the _Lxx or _Exx that we assign in this item.
  28. BOOLEAN AcpiGpeSignaturePorting; ///< 0 = No porting required(for 2-tier GPI GPE event architecture), 1 = Porting required(for 1-tier GPI GPE event architecture)
  29. UINT8 Reserved[3]; ///< Reserved for DWORD alignment
  30. } DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
  31. //
  32. // dTBT PCIE Reset GPIO Data Structure
  33. //
  34. typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
  35. GPIO_PAD GpioPad; ///< GPIO Pad Number
  36. BOOLEAN GpioLevel; ///< 0 = Active Low; 1 = Active High
  37. UINT8 Reserved[3]; ///< Reserved for DWORD alignment
  38. } DTBT_PCIE_RESET_GPIO_CONFIG;
  39. //
  40. // dTBT Controller Data Structure
  41. //
  42. typedef struct _DTBT_CONTROLLER_CONFIG {
  43. UINT8 DTbtControllerEn; ///< Enable/Disable DTbtController.
  44. UINT8 Type; ///< 01-Pcie RP, 02- PEG,Reserved. <Specific according to Board Design>
  45. UINT8 PcieRpNumber; ///< RP Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific according to Board Design>
  46. DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that can force dTBT Power On. <Specific according to Board Design>
  47. DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that can generate Hot-Plug event. <Specific according to Board Design>
  48. DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that is use to perform Reset when platform enters to Sx, it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO <Specific according to Board Design>
  49. GPIO_PAD PdResetGpioPad; ///< PD HRESET GPIO Pad Number
  50. GPIO_PAD PdSxEntryGpioPad; ///< PD SX Entry GPIO Pad Number
  51. GPIO_PAD PdSxAckGpioPad; ///< PD SX Ack GPIO Pad Number
  52. UINT8 Reserved[1]; ///< Reserved for DWORD alignment
  53. } DTBT_CONTROLLER_CONFIG;
  54. //
  55. // dTBT Controller Data Structure
  56. //
  57. typedef struct _DTBT_COMMON_CONFIG {
  58. UINT8 TbtBootOn; ///< Send BootOn Mailbox command when TbtBootOn is enabled.
  59. UINT8 TbtUsbOn; ///< Send UsbOn Mailbox command when TbtBootOn is enabled.
  60. UINT8 Gpio3ForcePwr; ///< Force GPIO to power on or not
  61. UINT16 Gpio3ForcePwrDly; ///< The delay time after do ForcePwr
  62. BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT controllers share the same GPIO pin <Specific according to Board Design>
  63. BOOLEAN PcieRstSupport; ///< 0 = Not Support, 1 = Supported. it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO
  64. UINT8 SecurityMode; ///< 0: SL0 No Security, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
  65. UINT8 ControlIommu; ///< Control Iommu behavior in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable exception list, 2: Enable Iommu, Enable exception list
  66. UINT8 Reserved[3]; ///< Reserved for DWORD alignment
  67. } DTBT_COMMON_CONFIG;
  68. #pragma pack(pop)
  69. #endif