TbtCommonLib.h 8.2 KB

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  1. /** @file
  2. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _TBT_COMMON_LIB_H_
  6. #define _TBT_COMMON_LIB_H_
  7. #include <Library/BaseLib.h>
  8. #include <Library/PciSegmentLib.h>
  9. #define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_RP 0 // @todo : Update when once finalized
  10. #define DEFAULT_PCI_BUS_NUMBER_ITBT_RP 0
  11. #define DEFAULT_PCI_DEVICE_NUMBER_ITBT_RP 0x07
  12. #define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0 0
  13. #define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0 0
  14. #define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0 0x0D
  15. #define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0 0x02
  16. #define DTBT_CONTROLLER 0x00
  17. #define DTBT_TYPE_PCH 0x01
  18. #define DTBT_TYPE_PEG 0x02
  19. #define ITBT_CONTROLLER 0x80
  20. #define TBT2PCIE_ITBT_R 0xEC
  21. #define PCIE2TBT_ITBT_R 0xF0
  22. #define TBT2PCIE_DTBT_R 0x548
  23. #define PCIE2TBT_DTBT_R 0x54C
  24. #define INVALID_RP_CONTROLLER_TYPE 0xFF
  25. //
  26. // Thunderbolt FW OS capability
  27. //
  28. #define NO_OS_NATIVE_SUPPORT 0
  29. #define OS_NATIVE_SUPPORT_ONLY 1
  30. #define OS_NATIVE_SUPPORT_RTD3 2
  31. #define ITBT_SAVE_STATE_OFFSET BIT4 // Bits 4-7 is for ITBT (HIA0/1/2/Reserved)
  32. #define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 is in use)
  33. /**
  34. Get Tbt2Pcie Register Offset
  35. @param[in] Type ITBT (0x80) or DTBT (0x00)
  36. @retval Register Register Variable
  37. **/
  38. #define GET_TBT2PCIE_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function, RegisterAddress) \
  39. if (Type == ITBT_CONTROLLER) { \
  40. RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_ITBT_R); \
  41. } else { \
  42. RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_DTBT_R); \
  43. }
  44. /**
  45. Get Pcie2Tbt Register Offset
  46. @param[in] Type ITBT (0x80) or DTBT (0x00)
  47. @retval Register Register Variable
  48. **/
  49. #define GET_PCIE2TBT_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function, RegisterAddress) \
  50. if (Type == ITBT_CONTROLLER) { \
  51. RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_ITBT_R); \
  52. } else { \
  53. RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_DTBT_R); \
  54. }
  55. #define PCIE2TBT_VLD_B BIT0
  56. #define TBT2PCIE_DON_R BIT0
  57. #define TBT_MAIL_BOX_DELAY (100*1000)
  58. #define TBT_5S_TIMEOUT 50
  59. #define TBT_1S_TIMEOUT 10
  60. #define TBT_3S_TIMEOUT 30
  61. #define PCIE2TBT_GO2SX (0x02 << 1)
  62. #define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1)
  63. #define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1)
  64. #define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
  65. #define PCIE2TBT_OS_UP (0x06 << 1)
  66. #define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1)
  67. #define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1)
  68. #define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1)
  69. #define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1)
  70. #define PCIE2TBT_BOOT_ON (0x18 << 1)
  71. #define PCIE2TBT_BOOT_OFF (0x19 << 1)
  72. #define PCIE2TBT_USB_ON (0x19 << 1)
  73. #define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1)
  74. #define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1)
  75. #define PCIE2TBT_POWER_CYCLE (0x1C << 1)
  76. #define PCIE2TBT_PREBOOTACL (0x1E << 1)
  77. #define CONNECT_TOPOLOGY_COMMAND (0x1F << 1)
  78. #define RESET_HR_BIT BIT0
  79. #define ENUMERATE_HR_BIT BIT1
  80. #ifndef AUTO
  81. #define AUTO 0x0
  82. #endif
  83. //
  84. //Thunder Bolt Device IDs
  85. //
  86. //
  87. // Alpine Ridge HR device IDs
  88. //
  89. #define AR_HR_2C 0x1576
  90. #define AR_HR_4C 0x1578
  91. #define AR_XHC 0x15B5
  92. #define AR_XHC_4C 0x15B6
  93. #define AR_HR_LP 0x15C0
  94. //
  95. // Alpine Ridge C0 HR device IDs
  96. //
  97. #define AR_HR_C0_2C 0x15DA
  98. #define AR_HR_C0_4C 0x15D3
  99. //
  100. // Titan Ridge HR device IDs
  101. //
  102. #define TR_HR_2C 0x15E7
  103. #define TR_HR_4C 0x15EA
  104. //
  105. //End of Thunderbolt(TM) Device IDs
  106. //
  107. typedef struct _DEV_ID {
  108. UINT8 Segment;
  109. UINT8 Bus;
  110. UINT8 Dev;
  111. UINT8 Fun;
  112. } DEV_ID;
  113. //@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
  114. //@todo should refactor this to only be present in that driver
  115. //@todo also definitions like this should never be in a .h file anyway
  116. //@todo this is a quick hack to get things compiling for now
  117. #ifdef __GNUC__
  118. #pragma GCC diagnostic warning "-Wunused-variable"
  119. #endif
  120. /**
  121. Based on the Security Mode Selection, BIOS drives FORCE_PWR.
  122. @param[in] GpioNumber
  123. @param[in] Value
  124. **/
  125. VOID
  126. ForceDtbtPower(
  127. IN UINT32 GpioNumber,
  128. IN BOOLEAN Value
  129. );
  130. /**
  131. Get Security Level.
  132. @param[in] Type ITBT (0x80) or DTBT (0x00)
  133. @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
  134. @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
  135. @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
  136. @param[in] Timeout Time out with 100 ms garnularity
  137. **/
  138. UINT8
  139. GetSecLevel (
  140. IN BOOLEAN Type,
  141. IN UINT8 Bus,
  142. IN UINT8 Device,
  143. IN UINT8 Function,
  144. IN UINT8 Command,
  145. IN UINT32 Timeout
  146. );
  147. /**
  148. Set Security Level.
  149. @param[in] Data Security State
  150. @param[in] Type ITBT (0x80) or DTBT (0x00)
  151. @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
  152. @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
  153. @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
  154. @param[in] Timeout Time out with 100 ms garnularity
  155. **/
  156. BOOLEAN
  157. SetSecLevel (
  158. IN UINT8 Data,
  159. IN BOOLEAN Type,
  160. IN UINT8 Bus,
  161. IN UINT8 Device,
  162. IN UINT8 Function,
  163. IN UINT8 Command,
  164. IN UINT32 Timeout
  165. );
  166. /**
  167. Execute TBT Mail Box Command
  168. @param[in] Command TBT Command
  169. @param[in] Type ITBT (0x80) or DTBT (0x00)
  170. @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
  171. @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
  172. @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
  173. @param[in] Timeout Time out with 100 ms garnularity
  174. @Retval true if command executes succesfully
  175. **/
  176. BOOLEAN
  177. TbtSetPcie2TbtCommand(
  178. IN UINT8 Command,
  179. IN BOOLEAN Type,
  180. IN UINT8 Bus,
  181. IN UINT8 Device,
  182. IN UINT8 Function,
  183. IN UINT32 Timeout
  184. );
  185. /**
  186. Check connected TBT controller is supported or not by DeviceID
  187. @param[in] DeviceID DeviceID of of TBT controller
  188. @retval TRUE Valid DeviceID
  189. @retval FALSE Invalid DeviceID
  190. **/
  191. BOOLEAN
  192. IsTbtHostRouter (
  193. IN UINT16 DeviceID
  194. );
  195. /**
  196. Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
  197. @param[in] RpNumber Root port physical number. (0-based)
  198. @param[out] RpDev Return corresponding root port device number.
  199. @param[out] RpFun Return corresponding root port function number.
  200. @retval EFI_SUCCESS Root port device and function is retrieved
  201. **/
  202. EFI_STATUS
  203. EFIAPI
  204. GetDTbtRpDevFun(
  205. IN BOOLEAN Type,
  206. IN UINTN RpNumber,
  207. OUT UINTN *RpDev,
  208. OUT UINTN *RpFunc
  209. );
  210. /**
  211. Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
  212. @param[in] CommandOffsetAddress Tbt2Pcie Register Address
  213. @param[in] TimeOut Time out with 100 ms garnularity
  214. @param[in] Tbt2PcieDone Wait condition (wait for Bit to Clear/Set)
  215. @param[out] *Tbt2PcieValue Function Register value
  216. **/
  217. BOOLEAN
  218. InternalWaitforCommandCompletion (
  219. IN UINT64 CommandOffsetAddress,
  220. IN UINT32 TimeOut,
  221. IN BOOLEAN Tbt2PcieDone,
  222. OUT UINT32 *Tbt2PcieValue
  223. );
  224. #endif