TbtNvsAreaDef.h 5.1 KB

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  1. /** @file
  2. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. //
  6. // Define TBT NVS Area operation region.
  7. //
  8. #ifndef _TBT_NVS_AREA_DEF_H_
  9. #define _TBT_NVS_AREA_DEF_H_
  10. #pragma pack (push,1)
  11. typedef struct {
  12. UINT8 ThunderboltSmiFunction; ///< Offset 0 Thunderbolt(TM) SMI Function Number
  13. UINT8 ThunderboltHotSmi; ///< Offset 1 SMI on Hot Plug for TBT devices
  14. UINT8 TbtWin10Support; ///< Offset 2 TbtWin10Support
  15. UINT8 TbtGpioFilter; ///< Offset 3 Gpio filter to detect USB Hotplug event
  16. UINT8 ThunderboltHotNotify; ///< Offset 4 Notify on Hot Plug for TBT devices
  17. UINT8 TbtSelector; ///< Offset 5 Thunderbolt(TM) Root port selector
  18. UINT8 WAKFinished; ///< Offset 6 WAK Finished
  19. UINT8 DiscreteTbtSupport; ///< Offset 7 Thunderbolt(TM) support
  20. UINT8 TbtAcpiRemovalSupport; ///< Offset 8 TbtAcpiRemovalSupport
  21. UINT32 TbtFrcPwrEn; ///< Offset 9 TbtFrcPwrEn
  22. UINT32 TbtFrcPwrGpioNo0; ///< Offset 13 TbtFrcPwrGpioNo
  23. UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17 TbtFrcPwrGpioLevel
  24. UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18 TbtCioPlugEventGpioNo
  25. UINT32 TbtPcieRstGpioNo0; ///< Offset 22 TbtPcieRstGpioNo
  26. UINT8 TbtPcieRstGpioLevel0; ///< Offset 26 TbtPcieRstGpioLevel
  27. UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27 Current Port that has plug event
  28. UINT8 RootportSelected0; ///< Offset 28 Root port Selected by the User
  29. UINT8 RootportSelected0Type; ///< Offset 29 Root port Type
  30. UINT8 RootportSelected1; ///< Offset 30 Root port Selected by the User
  31. UINT8 RootportSelected1Type; ///< Offset 31 Root port Type
  32. UINT8 RootportEnabled0; ///< Offset 32 Root port Enabled by the User
  33. UINT8 RootportEnabled1; ///< Offset 33 Root port Enabled by the User
  34. UINT32 TbtFrcPwrGpioNo1; ///< Offset 34 TbtFrcPwrGpioNo
  35. UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38 TbtFrcPwrGpioLevel
  36. UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39 TbtCioPlugEventGpioNo
  37. UINT32 TbtPcieRstGpioNo1; ///< Offset 43 TbtPcieRstGpioNo
  38. UINT8 TbtPcieRstGpioLevel1; ///< Offset 47 TbtPcieRstGpioLevel
  39. UINT8 TBtCommonGpioSupport; ///< Offset 48 Set if Single GPIO is used for Multi/Different Controller Hot plug support
  40. UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49 Root Port type for which SCI Triggered
  41. UINT8 TrOsup; ///< Offset 50 Titan Ridge Osup command
  42. UINT8 TbtAcDcSwitch; ///< Offset 51 TBT Dynamic AcDc L1
  43. UINT8 DTbtControllerEn0; ///< Offset 52 DTbtController0 is enabled or not. @deprecated since revision 2
  44. UINT8 DTbtControllerEn1; ///< Offset 53 DTbtController1 is enabled or not. @deprecated since revision 2
  45. UINT8 TbtAspm; ///< Offset 54 ASPM setting for all the PCIe device in TBT daisy chain.
  46. UINT8 TbtL1SubStates; ///< Offset 55 L1 SubState for for all the PCIe device in TBT daisy chain.
  47. UINT8 TbtSetClkReq; ///< Offset 56 CLK REQ for all the PCIe device in TBT daisy chain.
  48. UINT8 TbtLtr; ///< Offset 57 LTR for for all the PCIe device in TBT daisy chain.
  49. UINT8 TbtPtm; ///< Offset 58 PTM for for all the PCIe device in TBT daisy chain.
  50. UINT8 TbtWakeupSupport; ///< Offset 59 Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
  51. UINT16 Rtd3TbtOffDelay; ///< Offset 60 Rtd3TbtOffDelay TBT RTD3 Off Delay
  52. UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62 TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB at Sx entry point. HW logic is required.
  53. UINT8 Rtd3TbtSupport; ///< Offset 63 Enable Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
  54. UINT8 Rtd3TbtClkReq; ///< Offset 64 Enable TBT RTD3 CLKREQ mask.
  55. UINT16 Rtd3TbtClkReqDelay; ///< Offset 65 TBT RTD3 CLKREQ mask delay.
  56. //
  57. // Revision Field:
  58. //
  59. UINT8 TbtRevision; ///< Offset 67 Revison of TbtNvsArea
  60. } TBT_NVS_AREA;
  61. #pragma pack(pop)
  62. #endif