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WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110

Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Michael Kubacki před 4 roky
rodič
revize
4bbedf4fc9
31 změnil soubory, kde provedl 224 přidání a 1221 odebrání
  1. 2 2
      Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
  2. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
  3. 2 4
      Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
  4. 48 1006
      Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c
  5. 6 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
  6. 1 0
      Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
  7. 3 3
      Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
  8. 0 6
      Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
  9. 3 12
      Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
  10. 0 4
      Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
  11. 0 12
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
  12. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
  13. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
  14. 2 0
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
  15. 0 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
  16. 0 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
  17. 6 6
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
  18. 2 4
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
  19. 2 14
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.c
  20. 8 12
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c
  21. 9 12
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.c
  22. 5 3
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
  23. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
  24. 2 0
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
  25. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
  26. 7 5
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
  27. 1 1
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c
  28. 0 41
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
  29. 29 26
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
  30. 40 40
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
  31. 41 0
      Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h

+ 2 - 2
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c

@@ -173,7 +173,7 @@ EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformation2(
   // Retrieve BIST data from SecPlatform2
   //
   Status = SecPlatformInformation2Ppi->PlatformInformation2 (
-                                         PeiServices,
+                                         (CONST EFI_PEI_SERVICES  **) PeiServices,
                                          &InformationSize,
                                          SecPlatformInformation2
                                          );
@@ -240,7 +240,7 @@ EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformationInfoInFormat2(
   // Retrieve BIST data from SecPlatform
   //
   Status = SecPlatformInformationPpi->PlatformInformation (
-                                        PeiServices,
+                                        (CONST EFI_PEI_SERVICES  **) PeiServices,
                                         &InformationSize,
                                         SecPlatformInformation
                                         );

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h

@@ -9,7 +9,7 @@
 #ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_
 #define _PCIE_DEVICE_OVERRIDE_TABLE_H_
 
-#include <ConfigBlock/PcieRpconfig.h>
+#include <ConfigBlock/PcieRpConfig.h>
 #include <IndustryStandard/Pci22.h>
 
 #define PCI_CLASS_NETWORK             0x02

+ 2 - 4
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c

@@ -70,12 +70,11 @@ GpioExpGetRegister (
   IN UINT8 Register
   )
 {
-  EFI_STATUS Status;
   UINT8 WriBuf[1];
   UINT8 ReBuf[1] = {0};
 
   WriBuf[0] = Register;
-  Status = I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf, 1, ReBuf, WAIT_1_SECOND);
+  I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf, WAIT_1_SECOND);
 
   return ReBuf[0];
 }
@@ -99,13 +98,12 @@ GpioExpSetRegister (
   IN UINT8 Value
   )
 {
-  EFI_STATUS Status;
   UINT8 WriBuf[2];
 
   WriBuf[0] = Register;
   WriBuf[1] = Value;
-  Status = I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf, 0, NULL, WAIT_1_SECOND);
 
+  I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL, WAIT_1_SECOND);
 }
 /**
   Set the input register to a give value mentioned in the function.

Rozdílová data souboru nebyla zobrazena, protože soubor je příliš velký
+ 48 - 1006
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVerbTables.c


+ 6 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c

@@ -13,7 +13,12 @@
 #include <Library/HdaVerbTableLib.h>
 #include <Library/MemoryAllocationLib.h>
 #include <Library/PcdLib.h>
-#include "PchHdaVerbTables.h"
+
+extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc274;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc700;
+extern HDAUDIO_VERB_TABLE HdaVerbTableAlc701;
+extern HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700;
 
 /**
   Add verb table helper function.

+ 1 - 0
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf

@@ -36,6 +36,7 @@
 
 [Sources]
   PeiHdaVerbTableLib.c
+  PchHdaVerbTables.c
 
 ################################################################################
 #

+ 3 - 3
Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec

@@ -17,12 +17,12 @@
 DEC_SPECIFICATION = 0x00010017
 PACKAGE_NAME = OpenBoardPkg
 PACKAGE_VERSION = 0.1
-PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E
+PACKAGE_GUID = 8FE3E02F-BC79-41F2-9A0D-10140B292472
 
 [Includes]
 Include
-WhiskeylakeURvp\Include
-Features\Tbt\Include
+Features/Tbt/Include
+WhiskeylakeURvp/Include
 
 [Guids]
 

+ 0 - 6
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c

@@ -24,7 +24,6 @@
 #include <PlatformBoardConfig.h>
 #include <Library/CnviLib.h>
 #include <Register/PchRegsLpcCnl.h>
-#include <Ppi/PeiTbtPolicy.h>
 #include <PcieDeviceOverrideTable.h>
 
 VOID
@@ -275,7 +274,6 @@ UpdatePeiPchPolicy (
   EFI_STATUS                      Status;
   UINT8                           Index;
   DMI_HW_WIDTH_CONTROL            *DmiHaAWC;
-  UINT16                          LpcDid;
   PCH_GENERAL_CONFIG              *PchGeneralConfig;
   PCH_PCIE_CONFIG                 *PcieRpConfig;
   PCH_SATA_CONFIG                 *SataConfig;
@@ -295,7 +293,6 @@ UpdatePeiPchPolicy (
   USB_CONFIG                      *UsbConfig;
   PCH_ESPI_CONFIG                 *EspiConfig;
   PCH_CNVI_CONFIG                 *CnviConfig;
-  PEI_TBT_POLICY                  *PeiTbtPolicy;
   SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
 
   Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
@@ -345,9 +342,6 @@ UpdatePeiPchPolicy (
                 );
   ASSERT_EFI_ERROR (Status);
 
-  PeiTbtPolicy = NULL;
-  LpcDid = PchGetLpcDid ();
-
   DmiConfig->PwrOptEnable = TRUE;
   PmConfig->PchSlpS3MinAssert = 0;
   PmConfig->PchSlpS4MinAssert = 0;

+ 3 - 12
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c

@@ -1,9 +1,10 @@
 /** @file
-Do Platform Stage System Agent initialization.
+  Platform Stage System Agent initialization.
 
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
+
 **/
 
 #include "PeiSaPolicyUpdate.h"
@@ -26,7 +27,7 @@ Do Platform Stage System Agent initialization.
 /// Memory Reserved should be between 125% to 150% of the Current required memory
 /// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
 ///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
   { EfiACPIReclaimMemory,   FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) },  // ASL
   { EfiACPIMemoryNVS,       FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) },      // ACPI NVS (including S3 related)
   { EfiReservedMemoryType,  FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) },     // BIOS Reserved (including S3 related)
@@ -35,7 +36,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInfo
   { EfiMaxMemoryType, 0 }
 };
 
-
 /**
   UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
 
@@ -57,7 +57,6 @@ UpdatePeiSaPolicyPreMem (
   UINTN                           DataSize;
   EFI_MEMORY_TYPE_INFORMATION     MemoryData[EfiMaxMemoryType + 1];
   EFI_BOOT_MODE                   BootMode;
-  UINT8                           MorControl;
   UINT32                          TraceHubTotalMemSize;
   GRAPHICS_PEI_PREMEM_CONFIG      *GtPreMemConfig = NULL;
   MEMORY_CONFIGURATION            *MemConfig = NULL;
@@ -67,15 +66,9 @@ UpdatePeiSaPolicyPreMem (
   OVERCLOCKING_PREMEM_CONFIG      *OcPreMemConfig = NULL;
   VTD_CONFIG                      *Vtd = NULL;
   UINT32                          ProcessorTraceTotalMemSize;
-  UINT16                          AdjustedMmioSize;
-  CPU_FAMILY                      CpuFamilyId;
-  CPU_STEPPING                    CpuStepping;
 
   TraceHubTotalMemSize = 0;
   ProcessorTraceTotalMemSize = 0;
-  AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
-  CpuFamilyId = GetCpuFamily();
-  CpuStepping = GetCpuStepping();
 
   DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdatePeiSaPolicyPreMem\n"));
 
@@ -106,7 +99,6 @@ UpdatePeiSaPolicyPreMem (
   Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *)&Vtd);
   ASSERT_EFI_ERROR(Status);
 
-
   RcompData = MemConfigNoCrc->RcompData;
 
   //
@@ -124,7 +116,6 @@ UpdatePeiSaPolicyPreMem (
   ASSERT_EFI_ERROR(Status);
 
   MiscPeiPreMemConfig->S3DataPtr = NULL;
-  MorControl = 0;
   MiscPeiPreMemConfig->UserBd = 0; // It's a CRB mobile board by default (btCRBMB)
 
   PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform));

+ 0 - 4
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c

@@ -227,10 +227,6 @@ InitCommonPlatformPcd (
   )
 {
   PCD64_BLOB Data64;
-  TBT_INFO_HOB  *TbtInfoHob = NULL;
-
-  TbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
-
 
   //
   // Enable EC SMI# for SMI

+ 0 - 12
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h

@@ -1,12 +0,0 @@
-/** @file
-
-  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _WHISKEYLAKE_ERB_ID_H_
-#define _WHISKEYLAKE_ERB_ID_H_
-
-#define BoardIdWhiskeyLakeRvp          0x60
-#endif // _WHISKEYLAKE_RVP3_ID_H_
-

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c

@@ -16,7 +16,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c

@@ -15,7 +15,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI

+ 2 - 0
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h

@@ -9,6 +9,8 @@
 #ifndef _BOARD_FUNC_H_
 #define _BOARD_FUNC_H_
 
+#include <Uefi.h>
+
 EFI_STATUS
 PeiBoardSpecificInitPostMemNull (
   VOID

+ 0 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c

@@ -6,7 +6,6 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
 #include "BoardFunc.h"
 
 /**

+ 0 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c

@@ -6,7 +6,6 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
 #include <GopConfigLib.h>
 //
 // Null function for nothing GOP VBT update.

+ 6 - 6
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c

@@ -1,17 +1,17 @@
 /** @file
- Source code for the board PCH configuration Pcd init functions for Pre-Mmeory Init phase.
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
 
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
+#include "WhiskeylakeURvpInit.h"
 #include <GpioPinsCnlLp.h>
 #include <GpioPinsCnlH.h>
 #include <PlatformBoardConfig.h>        // for USB 20 AFE & Root Port Clk Info.
-#include "GpioTableWhlUDdr4PreMem.h"
 #include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
 
 /**
   Board Root Port Clock Info configuration init function for PEI pre-memory phase.
@@ -346,11 +346,11 @@ GpioTablePreMemInit (
   switch (BoardId) {
     case BoardIdWhiskeyLakeRvp:
       PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableWhlUDdr4PreMem);
-      PcdSet16S (PcdBoardGpioTablePreMemSize, sizeof (mGpioTableWhlUDdr4PreMem) / sizeof (GPIO_INIT_CONFIG));
+      PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableWhlUDdr4PreMemSize);
       PcdSet32S (PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableWhlUDdr4WwanOnEarlyPreMem);
-      PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, sizeof (mGpioTableWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG));
+      PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableWhlUDdr4WwanOnEarlyPreMemSize);
       PcdSet32S (PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableWhlUDdr4WwanOffEarlyPreMem);
-      PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, sizeof (mGpioTableWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG));
+      PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableWhlUDdr4WwanOffEarlyPreMemSize);
       break;
 
     default:

+ 2 - 4
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c

@@ -6,11 +6,11 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#include "BoardInitLib.h"
 #include "BoardSaConfigPreMem.h"
+#include "SaPolicyCommon.h"
+#include "WhiskeylakeURvpInit.h"
 #include <PlatformBoardConfig.h>
 #include <Library/CpuPlatformLib.h>
-#include "SaPolicyCommon.h"
 
 //
 // Display DDI settings for WHL ERB
@@ -74,10 +74,8 @@ MrcConfigInit (
   )
 {
   CPU_FAMILY    CpuFamilyId;
-  CPU_STEPPING  CpuStepping;
 
   CpuFamilyId = GetCpuFamily();
-  CpuStepping = GetCpuStepping();
 
   if (CpuFamilyId == EnumCpuCflDtHalo) {
     PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);

+ 2 - 14
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h → Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.c

@@ -1,14 +1,10 @@
 /** @file
   GPIO definition table
 
-
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#ifndef _GPIO_TABLE_DEFAULT_H_
-#define _GPIO_TABLE_DEFAULT_H_
-
 #include <GpioPinsCnlLp.h>
 #include <Library/GpioLib.h>
 #include <GpioConfig.h>
@@ -18,8 +14,7 @@
 //
 // CNL U DRR4 Board GPIO table configuration is used as default
 //
-
-GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] =
+GPIO_INIT_CONFIG mGpioTableDefault[] =
 {
 //                      Pmode,  GPI_IS,  GpioDir,  GPIOTxState,  RxEvCfg,  GPIRoutConfig,  PadRstCfg,  Term,
   //{GPIO_CNL_LP_GPP_A0,  { GpioPadModeNotUsed,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermNone }},
@@ -215,11 +210,4 @@ GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] =
   //(Default HW)  {GPIO_CNL_LP_GPD11,  { GpioPadModeNative1,  GpioHostOwnGpio,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioResetDefault,  GpioTermNone }},  //LANPHY_EN
   {GPIO_CNL_LP_PECI,  { GpioHardwareDefault,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermWpd20K }}, // 20K PD for PECI
 };
-
-GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemDefault[] =
-{
-  {END_OF_GPIO_TABLE,  {GpioPadModeGpio,    GpioHostOwnGpio, GpioDirNone,  GpioOutDefault, GpioIntDis, GpioDswReset,  GpioTermNone}},//Marking End of Table
-};
-
-#endif
-
+UINT16 mGpioTableDefaultSize = sizeof (mGpioTableDefault) / sizeof (GPIO_INIT_CONFIG);

+ 8 - 12
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h → Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c

@@ -1,19 +1,16 @@
 /** @file
-  GPIO definition table for WhiskeyLake U Ddr4 RVP
-
+  GPIO definition table for Whiskey Lake U DDR4 RVP
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
 
-#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_H_
-#define _CANNONLAKE_U_DDR4_GPIO_TABLE_H_
+**/
 
 #include <GpioPinsCnlLp.h>
 #include <Library/GpioLib.h>
 #include <GpioConfig.h>
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =
 {
 //                      Pmode,  GPI_IS,  GpioDir,  GPIOTxState,  RxEvCfg,  GPIRoutConfig,  PadRstCfg,  Term,
   //{GPIO_CNL_LP_GPP_A0,  { GpioPadModeNotUsed,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermNone }},
@@ -220,8 +217,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =
   //(Default HW)  {GPIO_CNL_LP_GPD11,  { GpioPadModeNative1,  GpioHostOwnGpio,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioResetDefault,  GpioTermNone }},  //LANPHY_EN
   {GPIO_CNL_LP_PECI,  { GpioHardwareDefault,  GpioHostOwnDefault,  GpioDirDefault,  GpioOutDefault,  GpioIntDefault,  GpioHostDeepReset,  GpioTermWpd20K }}, // 20K PD for PECI
 };
+UINT16 mGpioTableWhlUDdr4_0Size = sizeof (mGpioTableWhlUDdr4_0) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = {
+GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = {
   //                       Pmode,                GPI_IS,             GpioDir,        GPIOTxState,    RxEvCfg/GPIRoutConfig,          PadRstCfg,        Term,
   // WiGig start
   {GPIO_CNL_LP_GPP_A16,  { GpioPadModeGpio,      GpioHostOwnGpio,     GpioDirOut,    GpioOutHigh, GpioIntDefault,               GpioPlatformReset,  GpioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U
@@ -249,8 +247,9 @@ static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] = {
   {GPIO_CNL_LP_GPP_H17,  { GpioPadModeGpio,      GpioHostOwnGpio,    GpioDirNone, GpioOutDefault, GpioIntDis,                   GpioPlatformReset,  GpioTermNone   }}  //Unused so disabled / Not used on CNL U
   // Unused end
 };
+UINT16 mGpioTableCflUDdr4Size = sizeof (mGpioTableCflUDdr4) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = {
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = {
   //                       Pmode,                GPI_IS,             GpioDir,        GPIOTxState,    RxEvCfg/GPIRoutConfig,          PadRstCfg,        Term,
   // WiGig start
   {GPIO_CNL_LP_GPP_A16,  { GpioPadModeGpio, GpioHostOwnGpio,     GpioDirOut,    GpioOutHigh, GpioIntDefault,             GpioPlatformReset,  GpioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U
@@ -278,7 +277,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] = {
   {GPIO_CNL_LP_GPP_F3,   { GpioPadModeGpio, GpioHostOwnGpio,    GpioDirNone, GpioOutDefault, GpioIntDis,                 GpioPlatformReset,  GpioTermWpu20K }}  //Unused so disabled / WF_CLK_EN on CNL U
   // Unused end
 };
-
-
-#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_H_
-
+UINT16 mGpioTableWhlUDdr4Size = sizeof (mGpioTableWhlUDdr4) / sizeof (GPIO_INIT_CONFIG);

+ 9 - 12
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h → Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.c

@@ -1,27 +1,25 @@
 /** @file
-  GPIO definition table for WhiskeyLake U Ddr4 RVP Pre-Memory
+  GPIO definition table for Whiskey Lake U DDR4 RVP Pre-Memory
 
 
   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
-#define _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
-
 #include <GpioPinsCnlLp.h>
 #include <Library/GpioLib.h>
 #include <GpioConfig.h>
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =
 {
   {GPIO_CNL_LP_GPP_C15,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //SLOT1_RST_N
   {GPIO_CNL_LP_GPP_C14,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //SLOT1_PWREN_N
   {GPIO_CNL_LP_GPP_C12,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_RST_N
   {GPIO_CNL_LP_GPP_C13,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutHigh, GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_PWREN_N
 };
+UINT16 mGpioTableWhlUDdr4PreMemSize = sizeof (mGpioTableWhlUDdr4PreMem) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
 {
   // do not reset SLOT1 due to TR AIC card cannot be reset in S3/S4 resume.
   //{GPIO_CNL_LP_GPP_C15,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //SLOT1_RST_N
@@ -29,9 +27,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
   {GPIO_CNL_LP_GPP_C12,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutLow,  GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_RST_N
   {GPIO_CNL_LP_GPP_C13,  { GpioPadModeGpio,  GpioHostOwnAcpi,  GpioDirOut,  GpioOutHigh, GpioIntDis,  GpioPlatformReset,  GpioTermNone}},   //PCIE_NAND_PWREN_N
 };
+UINT16 mGpioTableWhlTbtRvpPreMemSize = sizeof (mGpioTableWhlTbtRvpPreMem) / sizeof (GPIO_INIT_CONFIG);
 
-
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
 {
   // Turn on WWAN power and de-assert reset pins by default
   {GPIO_CNL_LP_GPP_A11,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}},   //WWAN_WAKE_N
@@ -42,8 +40,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
   {GPIO_CNL_LP_GPP_H16,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
   {GPIO_CNL_LP_GPP_H17,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_DISABLE_N
 };
+UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize = sizeof (mGpioTableWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG);
 
-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
+GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
 {
   // Assert reset pins and then turn off WWAN power
   {GPIO_CNL_LP_GPP_A11,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}},   //WWAN_WAKE_N
@@ -54,6 +53,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
   {GPIO_CNL_LP_GPP_H16,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
   {GPIO_CNL_LP_GPP_H17,  { GpioPadModeGpio,  GpioHostOwnGpio,  GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioResumeReset,   GpioTermNone,   GpioOutputStateUnlock}}, //WWAN_DISABLE_N
 };
-
-#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
-
+UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize = sizeof (mGpioTableWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG);

+ 5 - 3
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf

@@ -19,11 +19,12 @@
 
 [LibraryClasses]
   BaseLib
-  DebugLib
   BaseMemoryLib
+  DebugLib
+  GpioExpanderLib
+  GpioLib
   HdaVerbTableLib
   MemoryAllocationLib
-  GpioExpanderLib
   PcdLib
 
 [Packages]
@@ -37,6 +38,8 @@
 [Sources]
   PeiWhiskeylakeURvpInitPostMemLib.c
   PeiBoardInitPostMemLib.c
+  GpioTableDefault.c
+  GpioTableWhiskeylakeUDdr4Rvp.c
 
 [Pcd]
   gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
@@ -50,4 +53,3 @@
   gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
 
   gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
-

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c

@@ -14,7 +14,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI

+ 2 - 0
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf

@@ -44,6 +44,8 @@
   PeiMultiBoardInitPostMemLib.c
   BoardFunc.c
   BoardFuncInit.c
+  GpioTableDefault.c
+  GpioTableWhiskeylakeUDdr4Rvp.c
 
 [FixedPcd]
 

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c

@@ -14,7 +14,7 @@
 #include <Library/PcdLib.h>
 #include <Library/DebugLib.h>
 
-#include <WhiskeylakeURvpId.h>
+#include <PlatformBoardId.h>
 
 EFI_STATUS
 EFIAPI

+ 7 - 5
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf

@@ -20,17 +20,18 @@
 
 [LibraryClasses]
   BaseLib
-  DebugLib
   BaseMemoryLib
+  DebugLib
+  GpioLib
   MemoryAllocationLib
-  PcdLib
   MultiBoardInitSupportLib
-  StallPpiLib
+  OcWdtLib
+  PcdLib
   PchResetLib
   PeiPlatformHookLib
-  PlatformHookLib
   PeiPolicyInitLib
-  OcWdtLib
+  PlatformHookLib
+  StallPpiLib
 
 [Packages]
   MinPlatformPkg/MinPlatformPkg.dec
@@ -47,6 +48,7 @@
   BoardSaInitPreMemLib.c
   BoardPchInitPreMemLib.c
   BoardFuncInitPreMem.c
+  GpioTableWhlUDdr4PreMem.c
 
 [Ppis]
   gEfiPeiReadOnlyVariable2PpiGuid

+ 1 - 1
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c

@@ -27,7 +27,7 @@
 #include <SioRegs.h>
 #include <Library/PchPcrLib.h>
 
-#include "PeiWhiskeylakeURvpInitLib.h"
+#include "WhiskeylakeURvpInit.h"
 
 #include <ConfigBlock.h>
 #include <ConfigBlock/MemoryConfig.h>

+ 0 - 41
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h

@@ -1,41 +0,0 @@
-/** @file
-
-  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_
-#define _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_
-
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/PcdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DebugLib.h>
-#include <Library/GpioLib.h>
-#include <Ppi/SiPolicy.h>
-#include <PchHsioPtssTables.h>
-#include <IoExpander.h>
-
-#include <WhiskeylakeURvpId.h>
-
-extern const UINT8 mDqByteMapSklRvp3[2][6][2];
-extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];
-extern const UINT8 mSkylakeRvp3Spd110[];
-extern const UINT16 mSkylakeRvp3Spd110Size;
-extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[];
-extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size;
-extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[];
-extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size;
-
-extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[];
-extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize;
-
-extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];
-extern UINT16 mGpioTableIoExpanderSize;
-extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel;
-extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[];
-extern UINT16 mGpioTableLpDdr3Rvp3Size;
-
-#endif // _PEI_Whiskeylake_RVP3_BOARD_INIT_LIB_H_
-

+ 29 - 26
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c

@@ -25,14 +25,12 @@
 #include <SioRegs.h>
 #include <Library/PchPcrLib.h>
 #include <IoExpander.h>
-#include "PeiWhiskeylakeURvpInitLib.h"
-#include "GpioTableDefault.h"
-#include "GpioTableWhlUDdr4.h"
 #include <AttemptUsbFirst.h>
 #include <PeiPlatformHookLib.h>
 #include <Library/PeiPolicyInitLib.h>
 #include <Library/PchInfoLib.h>
 #include <FirwmareConfigurations.h>
+#include "WhiskeylakeURvpInit.h"
 
 EFI_STATUS
 BoardFunctionInit(
@@ -49,7 +47,7 @@ GPIO init function for PEI post memory phase.
 EFI_STATUS
 BoardGpioInit(
   IN UINT16 BoardId
-)
+  )
 {
   //
   // GPIO Table Init.
@@ -57,16 +55,16 @@ BoardGpioInit(
   switch (BoardId) {
 
     case BoardIdWhiskeyLakeRvp:
-      PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableWhlUDdr4_0);
-      PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableWhlUDdr4_0) / sizeof(GPIO_INIT_CONFIG));
-      PcdSet32S(PcdBoardGpioTable2, (UINTN)mGpioTableWhlUDdr4);
-      PcdSet16S(PcdBoardGpioTable2Size, sizeof(mGpioTableWhlUDdr4) / sizeof(GPIO_INIT_CONFIG));
+      PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableWhlUDdr4_0);
+      PcdSet16S (PcdBoardGpioTableSize, mGpioTableWhlUDdr4_0Size);
+      PcdSet32S (PcdBoardGpioTable2, (UINTN) mGpioTableWhlUDdr4);
+      PcdSet16S (PcdBoardGpioTable2Size, mGpioTableWhlUDdr4Size);
       break;
 
     default:
-      DEBUG((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\n"));
-      PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableDefault);
-      PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableDefault) / sizeof(GPIO_INIT_CONFIG));
+      DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\n"));
+      PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault);
+      PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize);
       break;
   }
 
@@ -148,31 +146,36 @@ BoardSecurityInit (
 }
 
 /**
-WhiskeyLake board configuration init function for PEI post memory phase.
-
-@param[in]  Content  pointer to the buffer contain init information for board init.
+  Board configuration initialization in the post-memory boot phase.
 
-@retval EFI_SUCCESS             The function completed successfully.
-@retval EFI_INVALID_PARAMETER   The parameter is NULL.
 **/
-EFI_STATUS
-BoardConfigInit(
+VOID
+BoardConfigInit (
   VOID
-)
+  )
 {
   EFI_STATUS  Status;
   UINT16      BoardId;
 
   BoardId = BoardIdWhiskeyLakeRvp;
 
-  Status = BoardGpioInit(BoardId);
-  Status = TouchPanelGpioInit(BoardId);
-  Status = HdaVerbTableInit(BoardId);
-  Status = BoardMiscInit(BoardId);
-  Status = BoardFunctionInit(BoardId);
-  Status = BoardSecurityInit(BoardId);
+  Status = BoardGpioInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
 
-  return EFI_SUCCESS;
+  Status = TouchPanelGpioInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = HdaVerbTableInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardMiscInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardFunctionInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardSecurityInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
 }
 
 //@todo Review this functionality and if it is required for WHL SDS

+ 40 - 40
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c

@@ -27,7 +27,7 @@
 #include <SioRegs.h>
 #include <Library/PchPcrLib.h>
 
-#include "PeiWhiskeylakeURvpInitLib.h"
+#include "WhiskeylakeURvpInit.h"
 #include <ConfigBlock.h>
 #include <ConfigBlock/MemoryConfig.h>
 #include <Library/PeiServicesLib.h>
@@ -274,36 +274,51 @@ EarlyPlatformPchInit(
 }
 
 /**
-Board init function for PEI pre-memory phase.
+  Board configuration initialization in the pre-memory boot phase.
 
-@param  Content  pointer to the buffer contain init information for board init.
-
-@retval EFI_SUCCESS             The function completed successfully.
-@retval EFI_INVALID_PARAMETER   The parameter is NULL.
 **/
-EFI_STATUS
-BoardConfigInitPreMem(
+VOID
+BoardConfigInitPreMem (
   VOID
-)
+  )
 {
   EFI_STATUS Status;
   UINT16 BoardId;
 
   BoardId = BoardIdWhiskeyLakeRvp;
 
-  Status = MrcConfigInit(BoardId);
-  Status = SaGpioConfigInit(BoardId);
-  Status = SaMiscConfigInit(BoardId);
-  Status = RootPortClkInfoInit(BoardId);
-  Status = UsbConfigInit(BoardId);
-  Status = GpioGroupTierInit(BoardId);
-  Status = GpioTablePreMemInit(BoardId);
-  Status = PchPmConfigInit(BoardId);
-  Status = BoardMiscInitPreMem(BoardId);
-  Status = SaDisplayConfigInit(BoardId);
-  Status = BoardFunctionInitPreMem(BoardId);
+  Status = MrcConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
 
-  return EFI_SUCCESS;
+  Status = SaGpioConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaMiscConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = RootPortClkInfoInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = UsbConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GpioGroupTierInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GpioTablePreMemInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PchPmConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardMiscInitPreMem (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaDisplayConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardFunctionInitPreMem (BoardId);
+  ASSERT_EFI_ERROR (Status);
 }
 
 /**
@@ -328,7 +343,6 @@ PlatformInitPreMemCallBack(
   EFI_STATUS                        Status;
   UINT16                            ABase;
   UINT8                             FwConfig;
-  UINT8                             SynchDelay;
 
   //
   // Init Board Config Pcd.
@@ -337,7 +351,6 @@ PlatformInitPreMemCallBack(
 
   DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
   FwConfig = FwConfigProduction;
-  SynchDelay = 0;
   PcdSetBoolS(PcdPcieWwanEnable, FALSE);
   PcdSetBoolS(PcdWwanResetWorkaround, FALSE);
 
@@ -586,18 +599,16 @@ WhiskeylakeURvpBoardDebugInit (
   VOID
   )
 {
-  UINT64                            LpcBaseAddress;
-
   ///
   /// LPC I/O Configuration
   ///
-  PchLpcIoDecodeRangesSet(
+  PchLpcIoDecodeRangesSet (
     (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
     (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
     (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
-  );
+    );
 
-  PchLpcIoEnableDecodingSet(
+  PchLpcIoEnableDecodingSet (
     B_LPC_CFG_IOE_ME2 |
     B_LPC_CFG_IOE_SE |
     B_LPC_CFG_IOE_ME1 |
@@ -608,18 +619,7 @@ WhiskeylakeURvpBoardDebugInit (
     B_LPC_CFG_IOE_PPE |
     B_LPC_CFG_IOE_CBE |
     B_LPC_CFG_IOE_CAE
-  );
-
-  ///
-  /// Enable LPC IO decode for EC access
-  ///
-  LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS(
-    DEFAULT_PCI_SEGMENT_NUMBER_PCH,
-    DEFAULT_PCI_BUS_NUMBER_PCH,
-    PCI_DEVICE_NUMBER_PCH_LPC,
-    PCI_FUNCTION_NUMBER_PCH_LPC,
-    0
-  );
+    );
 
   return EFI_SUCCESS;
 }

+ 41 - 0
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h

@@ -0,0 +1,41 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _WHISKEY_LAKE_U_RVP_INIT_H_
+#define _WHISKEY_LAKE_U_RVP_INIT_H_
+
+#include <Uefi.h>
+#include <IoExpander.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchHsioPtssTables.h>
+
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[];
+extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[];
+extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size;
+
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[];
+extern UINT16 mGpioTableWhlUDdr4PreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[];
+extern UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[];
+extern UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize;
+
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[];
+extern UINT16 mGpioTableWhlUDdr4_0Size;
+extern GPIO_INIT_CONFIG mGpioTableDefault[];
+extern UINT16 mGpioTableDefaultSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4[];
+extern UINT16 mGpioTableWhlUDdr4Size;
+
+#endif // _WHISKEY_LAKE_U_RVP_INIT_H_
+

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