BoardInitLib.c 15 KB

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  1. /** @file
  2. Source code for the board configuration init function in DXE init phase.
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "BoardInitLib.h"
  7. #include <Library/HobLib.h>
  8. #include <MemInfoHob.h>
  9. #include <Library/PchSerialIoLib.h>
  10. #include <PlatformBoardConfig.h>
  11. #include <GpioPinsCnlLp.h>
  12. #include <GpioPinsCnlH.h>
  13. #include <Library/PchInfoLib.h>
  14. #include <Library/PchEspiLib.h>
  15. #include <Library/CpuPlatformLib.h>
  16. #include <TbtBoardInfo.h>
  17. #include <Library/CpuPlatformLib.h>
  18. #include <GopConfigLib.h>
  19. //
  20. // Null function for nothing GOP VBT update.
  21. //
  22. VOID
  23. GopVbtSpecificUpdateNull(
  24. IN CHILD_STRUCT **ChildStructPtr
  25. );
  26. //
  27. // for CFL U DDR4
  28. //
  29. VOID
  30. CflUDdr4GopVbtSpecificUpdate(
  31. IN CHILD_STRUCT **ChildStructPtr
  32. );
  33. /**
  34. Updates DIMM slots status for Desktop,server and workstation boards
  35. **/
  36. VOID
  37. UpdateDimmPopulationConfig(
  38. VOID
  39. )
  40. {
  41. MEMORY_INFO_DATA_HOB *MemInfo;
  42. UINT8 Slot0;
  43. UINT8 Slot1;
  44. UINT8 Slot2;
  45. UINT8 Slot3;
  46. CONTROLLER_INFO *ControllerInfo;
  47. EFI_HOB_GUID_TYPE *GuidHob;
  48. GuidHob = NULL;
  49. MemInfo = NULL;
  50. GuidHob = GetFirstGuidHob (&gSiMemoryInfoDataGuid);
  51. ASSERT (GuidHob != NULL);
  52. if (GuidHob != NULL) {
  53. MemInfo = (MEMORY_INFO_DATA_HOB *) GET_GUID_HOB_DATA (GuidHob);
  54. }
  55. if (MemInfo != NULL) {
  56. if (PcdGet8 (PcdPlatformFlavor) == FlavorDesktop ||
  57. PcdGet8 (PcdPlatformFlavor) == FlavorUpServer ||
  58. PcdGet8 (PcdPlatformFlavor) == FlavorWorkstation) {
  59. ControllerInfo = &MemInfo->Controller[0];
  60. Slot0 = ControllerInfo->ChannelInfo[0].DimmInfo[0].Status;
  61. Slot1 = ControllerInfo->ChannelInfo[0].DimmInfo[1].Status;
  62. Slot2 = ControllerInfo->ChannelInfo[1].DimmInfo[0].Status;
  63. Slot3 = ControllerInfo->ChannelInfo[1].DimmInfo[1].Status;
  64. //
  65. // Channel 0 Channel 1
  66. // Slot0 Slot1 Slot0 Slot1 - Population AIO board
  67. // 0 0 0 0 - Invalid - Invalid
  68. // 0 0 0 1 - Valid - Invalid
  69. // 0 0 1 0 - Invalid - Valid
  70. // 0 0 1 1 - Valid - Valid
  71. // 0 1 0 0 - Valid - Invalid
  72. // 0 1 0 1 - Valid - Invalid
  73. // 0 1 1 0 - Invalid - Invalid
  74. // 0 1 1 1 - Valid - Invalid
  75. // 1 0 0 0 - Invalid - Valid
  76. // 1 0 0 1 - Invalid - Invalid
  77. // 1 0 1 0 - Invalid - Valid
  78. // 1 0 1 1 - Invalid - Valid
  79. // 1 1 0 0 - Valid - Valid
  80. // 1 1 0 1 - Valid - Invalid
  81. // 1 1 1 0 - Invalid - Valid
  82. // 1 1 1 1 - Valid - Valid
  83. //
  84. if ((Slot0 && (Slot1 == 0)) || (Slot2 && (Slot3 == 0))) {
  85. PcdSetBoolS (PcdDimmPopulationError, TRUE);
  86. }
  87. }
  88. }
  89. }
  90. /**
  91. Init Misc Platform Board Config Block.
  92. @param[in] BoardId An unsigned integer represent the board id.
  93. @retval EFI_SUCCESS The function completed successfully.
  94. **/
  95. EFI_STATUS
  96. BoardMiscInit (
  97. IN UINT16 BoardId
  98. )
  99. {
  100. // PcdSet64S (PcdFuncBoardHookPlatformSetupOverride, (UINT64) (UINTN) BoardHookPlatformSetup);
  101. switch (BoardId) {
  102. case BoardIdWhiskeyLakeRvp:
  103. PcdSetBoolS (PcdPssReadSN, TRUE);
  104. PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
  105. PcdSet8S (PcdPssI2cBusNumber, 0x04);
  106. break;
  107. default:
  108. PcdSetBoolS (PcdPssReadSN, FALSE);
  109. PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
  110. PcdSet8S (PcdPssI2cBusNumber, 0x04);
  111. break;
  112. }
  113. return EFI_SUCCESS;
  114. }
  115. /**
  116. Init Platform Board Config Block for ACPI platform.
  117. @param[in] BoardId An unsigned integer represent the board id.
  118. @retval EFI_SUCCESS The function completed successfully.
  119. **/
  120. EFI_STATUS
  121. InitAcpiPlatformPcd (
  122. IN UINT16 BoardId
  123. )
  124. {
  125. TBT_INFO_HOB *TbtInfoHob = NULL;
  126. TbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
  127. //
  128. // Update OEM table ID
  129. //
  130. switch (BoardId) {
  131. case BoardIdWhiskeyLakeRvp:
  132. if ((TbtInfoHob != NULL) && (TbtInfoHob->DTbtControllerConfig[0].DTbtControllerEn == 1)) {
  133. PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_', 'w', 'h', 'l', 't', '4'));
  134. } else {
  135. PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_', 'w', 'h', 'l', 'd', '4'));
  136. }
  137. break;
  138. default:
  139. PcdSet64S (PcdXhciAcpiTableSignature, 0);
  140. break;
  141. }
  142. //
  143. // Modify Preferred_PM_Profile field based on Board SKU's. Default is set to Mobile
  144. //
  145. PcdSet8S (PcdPreferredPmProfile, EFI_ACPI_2_0_PM_PROFILE_MOBILE);
  146. //
  147. // Assign FingerPrint, Gnss, TouchPanel, Audio related GPIO.
  148. //
  149. switch(BoardId) {
  150. case BoardIdWhiskeyLakeRvp:
  151. PcdSet32S (PcdFingerPrintSleepGpio, GPIO_CNL_LP_GPP_B17);
  152. PcdSet32S (PcdFingerPrintIrqGpio, GPIO_CNL_LP_GPP_B16);
  153. //
  154. // Configure WWAN Reset pin
  155. //
  156. PcdSet32S (PcdGnssResetGpio, GPIO_CNL_LP_GPP_F1);
  157. PcdSet32S (PcdTouchpanelIrqGpio, GPIO_CNL_LP_GPP_D10);
  158. PcdSet32S (PcdTouchpadIrqGpio, GPIO_CNL_LP_GPP_B3);
  159. PcdSet32S (PcdHdaI2sCodecIrqGpio, GPIO_CNL_LP_GPP_C8);
  160. break;
  161. default:
  162. break;
  163. }
  164. //
  165. // Configure GPIOs for discrete USB BT module
  166. //
  167. switch(BoardId) {
  168. case BoardIdWhiskeyLakeRvp:
  169. PcdSet32S (PcdBtIrqGpio, GPIO_CNL_LP_GPP_B2);
  170. PcdSet32S (PcdBtRfKillGpio, GPIO_CNL_LP_GPP_B4);
  171. break;
  172. default:
  173. break;
  174. }
  175. //
  176. // Board Specific Init
  177. //
  178. switch (BoardId) {
  179. case BoardIdWhiskeyLakeRvp:
  180. PcdSetBoolS(PcdWhlErbRtd3TableEnable, TRUE);
  181. PcdSet8S (PcdHdaI2sCodecI2cBusNumber, 0); // I2S Audio Codec conntected to I2C0
  182. PcdSet8S (PcdBleUsbPortNumber, 9);
  183. break;
  184. default:
  185. break;
  186. }
  187. return EFI_SUCCESS;
  188. }
  189. /**
  190. Init Common Platform Board Config Block.
  191. @param[in] BoardId An unsigned integer represent the board id.
  192. @retval EFI_SUCCESS The function completed successfully.
  193. **/
  194. EFI_STATUS
  195. InitCommonPlatformPcd (
  196. IN UINT16 BoardId
  197. )
  198. {
  199. PCD64_BLOB Data64;
  200. //
  201. // Enable EC SMI# for SMI
  202. //
  203. switch (BoardId) {
  204. case BoardIdWhiskeyLakeRvp:
  205. PcdSet32S (PcdEcSmiGpio, GPIO_CNL_LP_GPP_E3);
  206. PcdSet32S (PcdEcLowPowerExitGpio, GPIO_CNL_LP_GPP_B23);
  207. break;
  208. };
  209. //
  210. // HID I2C Interrupt GPIO.
  211. //
  212. switch (BoardId) {
  213. default:
  214. // on all supported boards interrupt input is on same GPIO pad. How convenient.
  215. PcdSet32S (PcdHidI2cIntPad, GPIO_CNL_LP_GPP_D10);
  216. break;
  217. }
  218. //
  219. // PS2 KB Specific Init for Sds Serial platform.
  220. //
  221. if (BoardId == BoardIdWhiskeyLakeRvp) {
  222. PcdSetBoolS (PcdDetectPs2KbOnCmdAck, TRUE);
  223. } else {
  224. PcdSetBoolS (PcdDetectPs2KbOnCmdAck, FALSE);
  225. }
  226. switch (BoardId) {
  227. default:
  228. PcdSetBoolS (PcdSpdAddressOverride, FALSE);
  229. break;
  230. }
  231. //
  232. // DDISelection
  233. //
  234. switch (BoardId) {
  235. case BoardIdWhiskeyLakeRvp:
  236. PcdSet8S (PcdDDISelection, 1);
  237. break;
  238. default:
  239. PcdSet8S (PcdDDISelection, 0);
  240. break;
  241. }
  242. //
  243. // GFX Detect
  244. //
  245. switch (BoardId) {
  246. default:
  247. // Not all the boards support GFX_CRB_DET. This is not an error.
  248. Data64.BoardGpioConfig.Type = BoardGpioTypeNotSupported;
  249. break;
  250. }
  251. PcdSet64S (PcdGfxCrbDetectGpio, Data64.Blob);
  252. //
  253. // USB Type-C
  254. //
  255. switch (BoardId) {
  256. case BoardIdWhiskeyLakeRvp:
  257. PcdSetBoolS(PcdUsbTypeCSupport, TRUE);
  258. // Discete Ports
  259. PcdSet8S(PcdTypeCPortsSupported, 2);
  260. // TBT Port 1 mapping and properties [TBT AIC]
  261. PcdSet8S(PcdUsbTypeCPort1, 1);
  262. PcdSet8S(PcdUsbTypeCPort1Pch, 5);
  263. // TBT Port 2 mapping and properties [TBT AIC]
  264. PcdSet8S(PcdUsbTypeCPort2, 2);
  265. PcdSet8S(PcdUsbTypeCPort2Pch, 7);
  266. break;
  267. default:
  268. PcdSetBoolS (PcdUsbTypeCSupport, FALSE);
  269. break;
  270. }
  271. //
  272. // Battery Present
  273. //
  274. switch (BoardId) {
  275. default:
  276. PcdSet8S (PcdBatteryPresent, BOARD_REAL_BATTERY_SUPPORTED | BOARD_VIRTUAL_BATTERY_SUPPORTED);
  277. break;
  278. }
  279. //
  280. // TS-on-DIMM temperature
  281. //
  282. switch (BoardId) {
  283. case BoardIdWhiskeyLakeRvp:
  284. PcdSetBoolS (PcdTsOnDimmTemperature, TRUE);
  285. break;
  286. default:
  287. PcdSetBoolS (PcdTsOnDimmTemperature, FALSE);
  288. break;
  289. }
  290. //
  291. // Real Battery 1 Control & Real Battery 2 Control
  292. //
  293. PcdSet8S (PcdRealBattery1Control, 1);
  294. PcdSet8S (PcdRealBattery2Control, 2);
  295. //
  296. // Mipi Camera Sensor
  297. //
  298. PcdSetBoolS (PcdMipiCamSensor, FALSE);
  299. //
  300. // Mipi Camera Sensor Link Used
  301. //
  302. switch (BoardId) {
  303. case BoardIdWhiskeyLakeRvp:
  304. PcdSet8S (PcdMipiCam0LinkUsed, 3);
  305. PcdSet8S (PcdMipiCam1LinkUsed, 6);
  306. PcdSet8S (PcdMipiCam2LinkUsed, 9);
  307. PcdSet8S (PcdMipiCam3LinkUsed, 7);
  308. break;
  309. default:
  310. break;
  311. }
  312. //
  313. // H8S2113 SIO
  314. //
  315. switch(BoardId) {
  316. default:
  317. PcdSetBoolS (PcdH8S2113SIO, FALSE);
  318. break;
  319. }
  320. //
  321. // NCT6776F COM, SIO & HWMON
  322. //
  323. PcdSetBoolS (PcdNCT6776FCOM, FALSE);
  324. PcdSetBoolS (PcdNCT6776FSIO, FALSE);
  325. PcdSetBoolS (PcdNCT6776FHWMON, FALSE);
  326. //
  327. // SMC Runtime Sci Pin
  328. //
  329. switch (BoardId) {
  330. case BoardIdWhiskeyLakeRvp:
  331. PcdSet32S (PcdSmcRuntimeSciPin, (UINT32) GPIO_CNL_LP_GPP_E16);
  332. break;
  333. default:
  334. PcdSet32S (PcdSmcRuntimeSciPin, 0x00);
  335. break;
  336. }
  337. //
  338. // Convertable Dock Support
  339. //
  340. switch (BoardId) {
  341. default:
  342. PcdSetBoolS (PcdConvertableDockSupport, FALSE);
  343. break;
  344. }
  345. //
  346. // Ec Hotkey F3, F4, F5, F6, F7 and F8 Support
  347. //
  348. switch (BoardId) {
  349. case BoardIdWhiskeyLakeRvp:
  350. PcdSet8S (PcdEcHotKeyF3Support, 1);
  351. PcdSet8S (PcdEcHotKeyF4Support, 1);
  352. PcdSet8S (PcdEcHotKeyF5Support, 1);
  353. PcdSet8S (PcdEcHotKeyF6Support, 1);
  354. PcdSet8S (PcdEcHotKeyF7Support, 1);
  355. PcdSet8S (PcdEcHotKeyF8Support, 1);
  356. break;
  357. default:
  358. PcdSet8S (PcdEcHotKeyF3Support, 0);
  359. PcdSet8S (PcdEcHotKeyF4Support, 0);
  360. PcdSet8S (PcdEcHotKeyF5Support, 0);
  361. PcdSet8S (PcdEcHotKeyF6Support, 0);
  362. PcdSet8S (PcdEcHotKeyF7Support, 0);
  363. PcdSet8S (PcdEcHotKeyF8Support, 0);
  364. break;
  365. }
  366. //
  367. // Virtual Button Volume Up & Done Support
  368. // Virtual Button Home Button Support
  369. // Virtual Button Rotation Lock Support
  370. //
  371. switch (BoardId) {
  372. case BoardIdWhiskeyLakeRvp:
  373. PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, TRUE);
  374. PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, TRUE);
  375. PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE);
  376. PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE);
  377. break;
  378. default:
  379. PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, FALSE);
  380. PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, FALSE);
  381. PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE);
  382. PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE);
  383. break;
  384. }
  385. //
  386. // Slate Mode Switch Support
  387. //
  388. switch (BoardId) {
  389. case BoardIdWhiskeyLakeRvp:
  390. PcdSetBoolS (PcdSlateModeSwitchSupport, TRUE);
  391. break;
  392. default:
  393. PcdSetBoolS (PcdSlateModeSwitchSupport, FALSE);
  394. break;
  395. }
  396. //
  397. // Ac Dc Auto Switch Support
  398. //
  399. switch (BoardId) {
  400. default:
  401. PcdSetBoolS (PcdAcDcAutoSwitchSupport, TRUE);
  402. break;
  403. }
  404. //
  405. // Pm Power Button Gpio Pin
  406. //
  407. switch (BoardId) {
  408. case BoardIdWhiskeyLakeRvp:
  409. PcdSet32S (PcdPmPowerButtonGpioPin, (UINT32) GPIO_CNL_LP_GPD3);
  410. break;
  411. default:
  412. PcdSet32S (PcdPmPowerButtonGpioPin, 0x00);
  413. break;
  414. }
  415. //
  416. // Acpi Enable All Button Support
  417. //
  418. switch (BoardId) {
  419. case BoardIdWhiskeyLakeRvp:
  420. PcdSetBoolS (PcdAcpiEnableAllButtonSupport, TRUE);
  421. break;
  422. default:
  423. PcdSetBoolS (PcdAcpiEnableAllButtonSupport, FALSE);
  424. break;
  425. }
  426. //
  427. // Acpi Hid Driver Button Support
  428. //
  429. switch (BoardId) {
  430. case BoardIdWhiskeyLakeRvp:
  431. PcdSetBoolS (PcdAcpiHidDriverButtonSupport, TRUE);
  432. break;
  433. default:
  434. PcdSetBoolS (PcdAcpiHidDriverButtonSupport, FALSE);
  435. break;
  436. }
  437. //
  438. // USB Type C EC less
  439. //
  440. switch (BoardId) {
  441. default:
  442. PcdSetBoolS (PcdUsbTypeCEcLess, FALSE);
  443. break;
  444. }
  445. return EFI_SUCCESS;
  446. }
  447. /**
  448. Check if given rootport has device connected and enable wake capability
  449. @param[in] RpNum An unsigned integer represent the root port number.
  450. @retval TRUE if endpoint was connected
  451. @retval FALSE if no endpoint was detected
  452. **/
  453. BOOLEAN
  454. IsPcieEndPointPresent (
  455. IN UINT8 RpNum
  456. )
  457. {
  458. EFI_STATUS Status;
  459. UINTN RpDev;
  460. UINTN RpFun;
  461. UINT64 RpBaseAddress;
  462. Status = GetPchPcieRpDevFun (RpNum, &RpDev, &RpFun);
  463. if (!EFI_ERROR (Status)) {
  464. //
  465. // check if device is present
  466. //
  467. RpBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
  468. DEFAULT_PCI_SEGMENT_NUMBER_PCH,
  469. DEFAULT_PCI_BUS_NUMBER_PCH,
  470. RpDev,
  471. RpFun,
  472. 0
  473. );
  474. if ((PciSegmentRead16 (RpBaseAddress) != 0xFFFF) &&
  475. (PciSegmentRead16 (RpBaseAddress + R_PCH_PCIE_CFG_SLSTS) & B_PCIE_SLSTS_PDS)) {
  476. return TRUE;
  477. }
  478. }
  479. return FALSE;
  480. }
  481. /**
  482. Enable Tier2 GPIO Sci wake capability.
  483. @param[in] BoardId An unsigned integrer represent the board id.
  484. @retval EFI_SUCCESS The function completed successfully.
  485. **/
  486. EFI_STATUS
  487. Tier2GpioWakeSupport (
  488. IN UINT16 BoardId
  489. )
  490. {
  491. BOOLEAN Tier2GpioWakeEnable;
  492. Tier2GpioWakeEnable = FALSE;
  493. switch (BoardId) {
  494. case BoardIdWhiskeyLakeRvp:
  495. //
  496. // Root port #14: M.2 WLAN
  497. //
  498. if (IsPcieEndPointPresent (13)) {
  499. Tier2GpioWakeEnable = TRUE;
  500. }
  501. break;
  502. default:
  503. break;
  504. }
  505. PcdSetBoolS (PcdGpioTier2WakeEnable, Tier2GpioWakeEnable);
  506. return EFI_SUCCESS;
  507. }
  508. /**
  509. Board configuration init function for DXE phase.
  510. @param Content pointer to the buffer contain init information for board init.
  511. @retval EFI_SUCCESS The function completed successfully.
  512. **/
  513. EFI_STATUS
  514. EFIAPI
  515. BoardConfigInit (
  516. VOID
  517. )
  518. {
  519. EFI_STATUS Status;
  520. UINT16 BoardId;
  521. BoardId = BoardIdWhiskeyLakeRvp;
  522. Status = InitAcpiPlatformPcd (BoardId);
  523. ASSERT_EFI_ERROR(Status);
  524. Status = InitCommonPlatformPcd (BoardId);
  525. ASSERT_EFI_ERROR(Status);
  526. Status = BoardMiscInit (BoardId);
  527. ASSERT_EFI_ERROR(Status);
  528. Status = Tier2GpioWakeSupport (BoardId);
  529. ASSERT_EFI_ERROR(Status);
  530. return EFI_SUCCESS;
  531. }