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@@ -1,27 +1,25 @@
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/** @file
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- GPIO definition table for WhiskeyLake U Ddr4 RVP Pre-Memory
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+ GPIO definition table for Whiskey Lake U DDR4 RVP Pre-Memory
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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-#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
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-#define _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
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-
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#include <GpioPinsCnlLp.h>
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#include <Library/GpioLib.h>
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#include <GpioConfig.h>
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-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =
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+GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =
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{
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{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N
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{GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N
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{GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N
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{GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N
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};
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+UINT16 mGpioTableWhlUDdr4PreMemSize = sizeof (mGpioTableWhlUDdr4PreMem) / sizeof (GPIO_INIT_CONFIG);
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-static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
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+GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
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{
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// do not reset SLOT1 due to TR AIC card cannot be reset in S3/S4 resume.
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//{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N
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@@ -29,9 +27,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =
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{GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N
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{GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N
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};
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+UINT16 mGpioTableWhlTbtRvpPreMemSize = sizeof (mGpioTableWhlTbtRvpPreMem) / sizeof (GPIO_INIT_CONFIG);
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-
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-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
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+GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
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{
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// Turn on WWAN power and de-assert reset pins by default
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{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}}, //WWAN_WAKE_N
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@@ -42,8 +40,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =
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{GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
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{GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_DISABLE_N
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};
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+UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize = sizeof (mGpioTableWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG);
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-static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
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+GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
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{
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// Assert reset pins and then turn off WWAN power
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{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}}, //WWAN_WAKE_N
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@@ -54,6 +53,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =
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{GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
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{GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_DISABLE_N
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};
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-
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-#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_
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-
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+UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize = sizeof (mGpioTableWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG);
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