BoardSaInitPreMemLib.c 8.9 KB

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  1. /** @file
  2. Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "BoardSaConfigPreMem.h"
  7. #include "SaPolicyCommon.h"
  8. #include "WhiskeylakeURvpInit.h"
  9. #include <PlatformBoardConfig.h>
  10. #include <Library/CpuPlatformLib.h>
  11. //
  12. // Display DDI settings for WHL ERB
  13. //
  14. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = {
  15. DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
  16. DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  17. DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  18. DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  19. DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  20. DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  21. DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  22. DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  23. DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  24. };
  25. /**
  26. MRC configuration init function for PEI pre-memory phase.
  27. @param[in] BoardId An unsigned integer represent the board id.
  28. @retval EFI_SUCCESS The function completed successfully.
  29. **/
  30. EFI_STATUS
  31. SaMiscConfigInit (
  32. IN UINT16 BoardId
  33. )
  34. {
  35. //
  36. // UserBd
  37. //
  38. switch (BoardId) {
  39. case BoardIdWhiskeyLakeRvp:
  40. //
  41. // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
  42. // This is required to skip Memory voltage programming based on GPIO's in MRC
  43. //
  44. PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platform
  45. break;
  46. default:
  47. // MiscPeiPreMemConfig.UserBd = 0 by default.
  48. break;
  49. }
  50. PcdSet16S (PcdSaDdrFreqLimit, 0);
  51. return EFI_SUCCESS;
  52. }
  53. /**
  54. Board Memory Init related configuration init function for PEI pre-memory phase.
  55. @param[in] BoardId An unsigned integrer represent the board id.
  56. @retval EFI_SUCCESS The function completed successfully.
  57. **/
  58. EFI_STATUS
  59. MrcConfigInit (
  60. IN UINT16 BoardId
  61. )
  62. {
  63. CPU_FAMILY CpuFamilyId;
  64. CpuFamilyId = GetCpuFamily();
  65. if (CpuFamilyId == EnumCpuCflDtHalo) {
  66. PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
  67. } else {
  68. PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
  69. }
  70. //
  71. // Example policy for DIMM slots implementation boards:
  72. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  73. // by reading from DIMM SPD.
  74. // 2. No need to apply hardcoded SpdData buffers here for such board.
  75. //
  76. // Whiskey Lake U RVP has removable DIMM slots.
  77. // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0.
  78. // Example:
  79. // PcdMrcSpdData = 0
  80. // PcdMrcSpdDataSize = 0
  81. // PcdMrcSpdAddressTable0 = 0xA0
  82. // PcdMrcSpdAddressTable1 = 0xA2
  83. // PcdMrcSpdAddressTable2 = 0xA4
  84. // PcdMrcSpdAddressTable3 = 0xA6
  85. //
  86. // If a board has soldered down memory. It should use the following settings.
  87. // Example:
  88. // PcdMrcSpdAddressTable0 = 0
  89. // PcdMrcSpdAddressTable1 = 0
  90. // PcdMrcSpdAddressTable2 = 0
  91. // PcdMrcSpdAddressTable3 = 0
  92. // PcdMrcSpdData = static data buffer
  93. // PcdMrcSpdDataSize = sizeof (static data buffer)
  94. //
  95. //
  96. // SPD Address Table
  97. //
  98. PcdSet32S (PcdMrcSpdData, 0);
  99. PcdSet16S (PcdMrcSpdDataSize, 0);
  100. PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
  101. PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
  102. PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
  103. PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);
  104. //
  105. // DRAM SPD Data & related configuration
  106. //
  107. // Setting the PCD's to default value (WHL RVP3). It will be overriden to board specific settings below.
  108. PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapWhlUDdr4Rvp);
  109. PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapWhlUDdr4Rvp));
  110. PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramWhlUDdr4Rvp);
  111. PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramWhlUDdr4Rvp));
  112. switch (BoardId) {
  113. case BoardIdWhiskeyLakeRvp:
  114. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorCflUDdr4Interposer);
  115. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetWhlUDdr4Interposer);
  116. PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE);
  117. PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);
  118. break;
  119. default:
  120. break;
  121. }
  122. //
  123. // CA Vref routing: board-dependent
  124. // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
  125. // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
  126. // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
  127. //
  128. switch (BoardId) {
  129. case BoardIdWhiskeyLakeRvp:
  130. PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
  131. break;
  132. default:
  133. PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
  134. break;
  135. }
  136. return EFI_SUCCESS;
  137. }
  138. /**
  139. Board SA related GPIO configuration init function for PEI pre-memory phase.
  140. @param[in] BoardId An unsigned integer represent the board id.
  141. @retval EFI_SUCCESS The function completed successfully.
  142. **/
  143. EFI_STATUS
  144. SaGpioConfigInit (
  145. IN UINT16 BoardId
  146. )
  147. {
  148. //
  149. // Update board's GPIO for PEG slot reset
  150. //
  151. PcdSetBoolS (PcdPegGpioResetControl, TRUE);
  152. PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
  153. PcdSet32S (PcdPeg0ResetGpioPad, 0);
  154. PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
  155. PcdSet32S (PcdPeg3ResetGpioPad, 0);
  156. PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
  157. //
  158. // PCIE RTD3 GPIO
  159. //
  160. switch (BoardId) {
  161. case BoardIdWhiskeyLakeRvp:
  162. PcdSet8S(PcdRootPortIndex, 4);
  163. PcdSet8S (PcdPcie0GpioSupport, PchGpio);
  164. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  165. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  166. PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
  167. PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
  168. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  169. PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
  170. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  171. PcdSet8S (PcdPcie1GpioSupport, NotSupported);
  172. PcdSet32S (PcdPcie1WakeGpioNo, 0);
  173. PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
  174. PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
  175. PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
  176. PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
  177. PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
  178. PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
  179. PcdSet8S (PcdPcie2GpioSupport, NotSupported);
  180. PcdSet32S (PcdPcie2WakeGpioNo, 0);
  181. PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
  182. PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
  183. PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
  184. PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
  185. PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
  186. PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
  187. break;
  188. default:
  189. PcdSet8S(PcdRootPortIndex, 0xFF);
  190. PcdSet8S (PcdPcie0GpioSupport, NotSupported);
  191. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  192. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  193. PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
  194. PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
  195. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  196. PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
  197. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  198. PcdSet8S (PcdPcie1GpioSupport, NotSupported);
  199. PcdSet32S (PcdPcie1WakeGpioNo, 0);
  200. PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
  201. PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
  202. PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
  203. PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
  204. PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
  205. PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
  206. PcdSet8S (PcdPcie2GpioSupport, NotSupported);
  207. PcdSet32S (PcdPcie2WakeGpioNo, 0);
  208. PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
  209. PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
  210. PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
  211. PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
  212. PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
  213. PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
  214. break;
  215. }
  216. return EFI_SUCCESS;
  217. }
  218. /**
  219. SA Display DDI configuration init function for PEI pre-memory phase.
  220. @param[in] BoardId An unsigned integer represent the board id.
  221. @retval EFI_SUCCESS The function completed successfully.
  222. **/
  223. EFI_STATUS
  224. SaDisplayConfigInit (
  225. IN UINT16 BoardId
  226. )
  227. {
  228. //
  229. // Update Display DDI Config
  230. //
  231. switch (BoardId) {
  232. case BoardIdWhiskeyLakeRvp:
  233. PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConfig);
  234. PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdiConfig));
  235. break;
  236. default:
  237. break;
  238. }
  239. return EFI_SUCCESS;
  240. }