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@@ -1,54 +1,23 @@
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-/* ****************************************************************
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- * CADENCE Copyright (c) 2001-2018 *
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- * Cadence Design Systems, Inc. *
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- * All rights reserved. *
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- ******************************************************************
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- * The values calculated from this script are meant to be *
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- * representative programmings. The values may not reflect the *
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- * actual required programming for production use. Please *
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- * closely review all programmed values for technical accuracy *
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- * before use in production parts. *
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- ******************************************************************
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- *
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- * Module: regconfig.h
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- * Documentation: Register programming header file
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- *
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- ******************************************************************
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- ******************************************************************
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- * WARNING: This file was automatically generated. Manual
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- * editing may result in undetermined behavior.
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- ******************************************************************
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- ******************************************************************/
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-// REL: sifive.shanghai.n1-VIC_DDR__20180206
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-
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-
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-//`timescale 10ps/10ps
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-
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-// ********************************************************************
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-// Option: IP : IP Mode = PHY
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-// Option: BL : Burst Length = 16
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-// Option: CL : CAS Latency = 24
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-// Option: MHZ : Simulation MHz = 1333
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-// Option: AP : Auto Precharge Mode (0/1) = 0
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-// Option: DLLBP : DLL Bypass Mode (0/1) = 0
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-// Option: HALF : Half-Memory Support (0/1) = 0
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-// Option: RDIMM : Registered Dimm Support (0/1) = 0
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-// Option: AL : Additive Latency = 0
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-// Option: PREAM : Preamble Support (0/1/2/3) = 0
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-// Option: BOF : Burst On the Fly (0/1) = 0
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-// Option: WLS : Write Latency Set (0/1) = 0
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-// Option: TCK : Simulation period in ns =
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-// Option: WRDBIEN : Write DBI Enable (0/1) = 0
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-// Option: RDDBIEN : Read DBI Enable (0/1) = 0
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-// Option: RDPSTMBLE : RD Postamble En (0/1) = 0
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-// Option: WRPSTMBLE : WR Postamble En (0/1) = 0
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-// Option: CRC : CRC En (0/1) = 0
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-// Option: SOMA : Memory-SOMA file(s) = /proj/iprel/sifive.shanghai.n1-VIC_DDR/sifive.shanghai.n1-VIC_DDR__20180201/mcip/mem/sifive.shanghai.n1-VIC_DDR/memory/jedec_lpddr4_16gb_3200/memory.xml.sim
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-// Option: PL : CA Parity Latency = -1
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-// ********************************************************************
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-// Memory: jedec_lpddr4_16gb_3200
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-// ********************************************************************
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+/**
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+ ******************************************************************************
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+ * @file regconfig.h.sim_PHY.h
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+ * @author StarFive Technology
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+ * @version V1.0
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+ * @date 07/20/2020
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+ * @brief
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+ ******************************************************************************
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+ * @copy
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+ *
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+ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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+ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
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+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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+ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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+ *
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+ * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
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+ */
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#define DENALI_PHY_00_DATA 0b00000000000000000000010011110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0
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