syscon_sysmain_ctrl_macro.h 76 KB

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  1. /**
  2. ******************************************************************************
  3. * @file syscon_sysmain_ctrl_macro.h
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 07/24/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #ifndef _SYSCON_SYSMAIN_CTRL_MACRO_H_
  21. #define _SYSCON_SYSMAIN_CTRL_MACRO_H_
  22. //#define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x0
  23. #define syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x0
  24. #define syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4
  25. #define syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8
  26. #define syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC
  27. #define syscon_sysmain_ctrl_register4_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10
  28. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x14
  29. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x18
  30. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x1C
  31. #define syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x20
  32. #define syscon_sysmain_ctrl_SCFG_u74_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x24
  33. #define syscon_sysmain_ctrl_register10_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x28
  34. #define syscon_sysmain_ctrl_register11_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x2C
  35. #define syscon_sysmain_ctrl_register12_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x30
  36. #define syscon_sysmain_ctrl_register13_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x34
  37. #define syscon_sysmain_ctrl_register14_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x38
  38. #define syscon_sysmain_ctrl_register15_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x3C
  39. #define syscon_sysmain_ctrl_register16_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x40
  40. #define syscon_sysmain_ctrl_register17_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x44
  41. #define syscon_sysmain_ctrl_register18_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x48
  42. #define syscon_sysmain_ctrl_register19_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x4C
  43. #define syscon_sysmain_ctrl_register20_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x50
  44. #define syscon_sysmain_ctrl_register21_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x54
  45. #define syscon_sysmain_ctrl_register22_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x58
  46. #define syscon_sysmain_ctrl_register23_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x5C
  47. #define syscon_sysmain_ctrl_qspi_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x60
  48. #define syscon_sysmain_ctrl_intmem_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x64
  49. #define syscon_sysmain_ctrl_register26_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x68
  50. #define syscon_sysmain_ctrl_register27_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x6C
  51. #define syscon_sysmain_ctrl_register28_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x70
  52. #define syscon_sysmain_ctrl_register29_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x74
  53. #define syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x78
  54. #define syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x7C
  55. #define syscon_sysmain_ctrl_register32_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x80
  56. #define syscon_sysmain_ctrl_register33_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x84
  57. #define syscon_sysmain_ctrl_register34_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x88
  58. #define syscon_sysmain_ctrl_register35_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x8C
  59. #define syscon_sysmain_ctrl_register36_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x90
  60. #define syscon_sysmain_ctrl_register37_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x94
  61. #define syscon_sysmain_ctrl_register38_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x98
  62. #define syscon_sysmain_ctrl_register39_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x9C
  63. #define syscon_sysmain_ctrl_register40_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA0
  64. #define syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA4
  65. #define syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xA8
  66. #define syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xAC
  67. #define syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xB0
  68. #define syscon_sysmain_ctrl_register47_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xBC
  69. #define syscon_sysmain_ctrl_register48_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC0
  70. #define syscon_sysmain_ctrl_register52_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC4
  71. #define syscon_sysmain_ctrl_register49_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xC8
  72. #define syscon_sysmain_ctrl_register50_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xCC
  73. #define syscon_sysmain_ctrl_register51_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xD0
  74. #define syscon_sysmain_ctrl_register66_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xD8
  75. #define syscon_sysmain_ctrl_register53_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xDC
  76. #define syscon_sysmain_ctrl_register54_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE0
  77. #define syscon_sysmain_ctrl_register55_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE4
  78. #define syscon_sysmain_ctrl_register56_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xE8
  79. #define syscon_sysmain_ctrl_register57_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xEC
  80. #define syscon_sysmain_ctrl_register58_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF0
  81. #define syscon_sysmain_ctrl_register59_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF4
  82. #define syscon_sysmain_ctrl_register60_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xF8
  83. #define syscon_sysmain_ctrl_register61_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0xFC
  84. #define syscon_sysmain_ctrl_register62_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x100
  85. #define syscon_sysmain_ctrl_register63_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x104
  86. #define syscon_sysmain_ctrl_register64_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x108
  87. #define syscon_sysmain_ctrl_register65_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x10C
  88. #define syscon_sysmain_ctrl_register68_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x110
  89. #define syscon_sysmain_ctrl_register67_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x114
  90. #define syscon_sysmain_ctrl_register69_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x118
  91. #define syscon_sysmain_ctrl_register70_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x11C
  92. #define syscon_sysmain_ctrl_register71_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x120
  93. #define syscon_sysmain_ctrl_register72_REG_ADDR SYSCON_SYSMAIN_CTRL_BASE_ADDR + 0x124
  94. #define _SET_SYSCON_REG_SCFG_pll0_reset(v) { \
  95. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  96. _ezchip_macro_read_value_ &= ~(0x1); \
  97. _ezchip_macro_read_value_ |= (v&0x1); \
  98. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  99. }
  100. #define _GET_SYSCON_REG_SCFG_pll0_reset(_ezchip_macro_read_value_) { \
  101. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  102. _ezchip_macro_read_value_ &= 0x1;\
  103. }
  104. #define _SET_SYSCON_REG_SCFG_pll0_pwrdn(v) { \
  105. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  106. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  107. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  108. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  109. }
  110. #define _GET_SYSCON_REG_SCFG_pll0_pwrdn(_ezchip_macro_read_value_) { \
  111. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 1; \
  112. _ezchip_macro_read_value_ &= 0x1;\
  113. }
  114. #define _SET_SYSCON_REG_SCFG_pll0_intfb(v) { \
  115. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  116. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  117. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  118. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  119. }
  120. #define _GET_SYSCON_REG_SCFG_pll0_intfb(_ezchip_macro_read_value_) { \
  121. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 2; \
  122. _ezchip_macro_read_value_ &= 0x1;\
  123. }
  124. #define _SET_SYSCON_REG_SCFG_pll0_bypass(v) { \
  125. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  126. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  127. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  128. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  129. }
  130. #define _GET_SYSCON_REG_SCFG_pll0_bypass(_ezchip_macro_read_value_) { \
  131. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 3; \
  132. _ezchip_macro_read_value_ &= 0x1;\
  133. }
  134. #define _SET_SYSCON_REG_SCFG_pll0_clk_refdiv(v) { \
  135. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  136. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  137. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  138. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  139. }
  140. #define _GET_SYSCON_REG_SCFG_pll0_clk_refdiv(_ezchip_macro_read_value_) { \
  141. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 4; \
  142. _ezchip_macro_read_value_ &= 0xf;\
  143. }
  144. #define _SET_SYSCON_REG_SCFG_pll0_clk_fbkdiv(v) { \
  145. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  146. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  147. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  148. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  149. }
  150. #define _GET_SYSCON_REG_SCFG_pll0_clk_fbkdiv(_ezchip_macro_read_value_) { \
  151. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 8; \
  152. _ezchip_macro_read_value_ &= 0x3f;\
  153. }
  154. #define _SET_SYSCON_REG_SCFG_pll0_bw_adj(v) { \
  155. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  156. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  157. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  158. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  159. }
  160. #define _GET_SYSCON_REG_SCFG_pll0_bw_adj(_ezchip_macro_read_value_) { \
  161. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 16; \
  162. _ezchip_macro_read_value_ &= 0x3f;\
  163. }
  164. #define _SET_SYSCON_REG_SCFG_pll0_clk_outdiv(v) { \
  165. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR); \
  166. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  167. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  168. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR,_ezchip_macro_read_value_); \
  169. }
  170. #define _GET_SYSCON_REG_SCFG_pll0_clk_outdiv(_ezchip_macro_read_value_) { \
  171. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll0_REG_ADDR) >> 24; \
  172. _ezchip_macro_read_value_ &= 0xf;\
  173. }
  174. #define _SET_SYSCON_REG_SCFG_pll1_reset(v) { \
  175. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  176. _ezchip_macro_read_value_ &= ~(0x1); \
  177. _ezchip_macro_read_value_ |= (v&0x1); \
  178. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  179. }
  180. #define _GET_SYSCON_REG_SCFG_pll1_reset(_ezchip_macro_read_value_) { \
  181. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  182. _ezchip_macro_read_value_ &= 0x1;\
  183. }
  184. #define _SET_SYSCON_REG_SCFG_pll1_pwrdn(v) { \
  185. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  186. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  187. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  188. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  189. }
  190. #define _GET_SYSCON_REG_SCFG_pll1_pwrdn(_ezchip_macro_read_value_) { \
  191. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 1; \
  192. _ezchip_macro_read_value_ &= 0x1;\
  193. }
  194. #define _SET_SYSCON_REG_SCFG_pll1_intfb(v) { \
  195. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  196. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  197. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  198. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  199. }
  200. #define _GET_SYSCON_REG_SCFG_pll1_intfb(_ezchip_macro_read_value_) { \
  201. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 2; \
  202. _ezchip_macro_read_value_ &= 0x1;\
  203. }
  204. #define _SET_SYSCON_REG_SCFG_pll1_bypass(v) { \
  205. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  206. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  207. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  208. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  209. }
  210. #define _GET_SYSCON_REG_SCFG_pll1_bypass(_ezchip_macro_read_value_) { \
  211. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 3; \
  212. _ezchip_macro_read_value_ &= 0x1;\
  213. }
  214. #define _SET_SYSCON_REG_SCFG_pll1_clk_refdiv(v) { \
  215. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  216. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  217. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  218. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  219. }
  220. #define _GET_SYSCON_REG_SCFG_pll1_clk_refdiv(_ezchip_macro_read_value_) { \
  221. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 4; \
  222. _ezchip_macro_read_value_ &= 0xf;\
  223. }
  224. #define _SET_SYSCON_REG_SCFG_pll1_clk_fbkdiv(v) { \
  225. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  226. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  227. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  228. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  229. }
  230. #define _GET_SYSCON_REG_SCFG_pll1_clk_fbkdiv(_ezchip_macro_read_value_) { \
  231. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 8; \
  232. _ezchip_macro_read_value_ &= 0x3f;\
  233. }
  234. #define _SET_SYSCON_REG_SCFG_pll1_bw_adj(v) { \
  235. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  236. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  237. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  238. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  239. }
  240. #define _GET_SYSCON_REG_SCFG_pll1_bw_adj(_ezchip_macro_read_value_) { \
  241. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 16; \
  242. _ezchip_macro_read_value_ &= 0x3f;\
  243. }
  244. #define _SET_SYSCON_REG_SCFG_pll1_clk_outdiv(v) { \
  245. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR); \
  246. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  247. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  248. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,_ezchip_macro_read_value_); \
  249. }
  250. #define _GET_SYSCON_REG_SCFG_pll1_clk_outdiv(_ezchip_macro_read_value_) { \
  251. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR) >> 24; \
  252. _ezchip_macro_read_value_ &= 0xf;\
  253. }
  254. #define _SET_SYSCON_REG_SCFG_pll2_reset(v) { \
  255. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  256. _ezchip_macro_read_value_ &= ~(0x1); \
  257. _ezchip_macro_read_value_ |= (v&0x1); \
  258. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  259. }
  260. #define _GET_SYSCON_REG_SCFG_pll2_reset(_ezchip_macro_read_value_) { \
  261. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  262. _ezchip_macro_read_value_ &= 0x1;\
  263. }
  264. #define _SET_SYSCON_REG_SCFG_pll2_pwrdn(v) { \
  265. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  266. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  267. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  268. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  269. }
  270. #define _GET_SYSCON_REG_SCFG_pll2_pwrdn(_ezchip_macro_read_value_) { \
  271. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 1; \
  272. _ezchip_macro_read_value_ &= 0x1;\
  273. }
  274. #define _SET_SYSCON_REG_SCFG_pll2_intfb(v) { \
  275. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  276. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  277. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  278. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  279. }
  280. #define _GET_SYSCON_REG_SCFG_pll2_intfb(_ezchip_macro_read_value_) { \
  281. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 2; \
  282. _ezchip_macro_read_value_ &= 0x1;\
  283. }
  284. #define _SET_SYSCON_REG_SCFG_pll2_bypass(v) { \
  285. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  286. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  287. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  288. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  289. }
  290. #define _GET_SYSCON_REG_SCFG_pll2_bypass(_ezchip_macro_read_value_) { \
  291. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 3; \
  292. _ezchip_macro_read_value_ &= 0x1;\
  293. }
  294. #define _SET_SYSCON_REG_SCFG_pll2_clk_refdiv(v) { \
  295. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  296. _ezchip_macro_read_value_ &= ~(0xF<<4); \
  297. _ezchip_macro_read_value_ |= (v&0xF)<<4; \
  298. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  299. }
  300. #define _GET_SYSCON_REG_SCFG_pll2_clk_refdiv(_ezchip_macro_read_value_) { \
  301. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 4; \
  302. _ezchip_macro_read_value_ &= 0xf;\
  303. }
  304. #define _SET_SYSCON_REG_SCFG_pll2_clk_fbkdiv(v) { \
  305. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  306. _ezchip_macro_read_value_ &= ~(0x3F<<8); \
  307. _ezchip_macro_read_value_ |= (v&0x3F)<<8; \
  308. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  309. }
  310. #define _GET_SYSCON_REG_SCFG_pll2_clk_fbkdiv(_ezchip_macro_read_value_) { \
  311. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 8; \
  312. _ezchip_macro_read_value_ &= 0x3f;\
  313. }
  314. #define _SET_SYSCON_REG_SCFG_pll2_bw_adj(v) { \
  315. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  316. _ezchip_macro_read_value_ &= ~(0x3F<<16); \
  317. _ezchip_macro_read_value_ |= (v&0x3F)<<16; \
  318. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  319. }
  320. #define _GET_SYSCON_REG_SCFG_pll2_bw_adj(_ezchip_macro_read_value_) { \
  321. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 16; \
  322. _ezchip_macro_read_value_ &= 0x3f;\
  323. }
  324. #define _SET_SYSCON_REG_SCFG_pll2_clk_outdiv(v) { \
  325. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR); \
  326. _ezchip_macro_read_value_ &= ~(0xF<<24); \
  327. _ezchip_macro_read_value_ |= (v&0xF)<<24; \
  328. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR,_ezchip_macro_read_value_); \
  329. }
  330. #define _GET_SYSCON_REG_SCFG_pll2_clk_outdiv(_ezchip_macro_read_value_) { \
  331. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_pll2_REG_ADDR) >> 24; \
  332. _ezchip_macro_read_value_ &= 0xf;\
  333. }
  334. #define _SET_SYSCON_REG_SCFG_plls_stat_pll0_test(v) { \
  335. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  336. _ezchip_macro_read_value_ &= ~(0x1); \
  337. _ezchip_macro_read_value_ |= (v&0x1); \
  338. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  339. }
  340. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_test(_ezchip_macro_read_value_) { \
  341. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  342. _ezchip_macro_read_value_ &= 0x1;\
  343. }
  344. #define _SET_SYSCON_REG_SCFG_plls_stat_pll1_test(v) { \
  345. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  346. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  347. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  348. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  349. }
  350. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_test(_ezchip_macro_read_value_) { \
  351. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 1; \
  352. _ezchip_macro_read_value_ &= 0x1;\
  353. }
  354. #define _SET_SYSCON_REG_SCFG_plls_stat_pll2_test(v) { \
  355. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR); \
  356. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  357. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  358. MA_OUTW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR,_ezchip_macro_read_value_); \
  359. }
  360. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_test(_ezchip_macro_read_value_) { \
  361. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 2; \
  362. _ezchip_macro_read_value_ &= 0x1;\
  363. }
  364. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_lock(_ezchip_macro_read_value_) { \
  365. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 4; \
  366. _ezchip_macro_read_value_ &= 0x1;\
  367. }
  368. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_ref_slip(_ezchip_macro_read_value_) { \
  369. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 5; \
  370. _ezchip_macro_read_value_ &= 0x1;\
  371. }
  372. #define _GET_SYSCON_REG_SCFG_plls_stat_pll0_fdbk_slip(_ezchip_macro_read_value_) { \
  373. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 6; \
  374. _ezchip_macro_read_value_ &= 0x1;\
  375. }
  376. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_lock(_ezchip_macro_read_value_) { \
  377. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 8; \
  378. _ezchip_macro_read_value_ &= 0x1;\
  379. }
  380. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_ref_slip(_ezchip_macro_read_value_) { \
  381. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 9; \
  382. _ezchip_macro_read_value_ &= 0x1;\
  383. }
  384. #define _GET_SYSCON_REG_SCFG_plls_stat_pll1_fdbk_slip(_ezchip_macro_read_value_) { \
  385. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 10; \
  386. _ezchip_macro_read_value_ &= 0x1;\
  387. }
  388. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_lock(_ezchip_macro_read_value_) { \
  389. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 12; \
  390. _ezchip_macro_read_value_ &= 0x1;\
  391. }
  392. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_ref_slip(_ezchip_macro_read_value_) { \
  393. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 13; \
  394. _ezchip_macro_read_value_ &= 0x1;\
  395. }
  396. #define _GET_SYSCON_REG_SCFG_plls_stat_pll2_fdbk_slip(_ezchip_macro_read_value_) { \
  397. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_plls_stat_REG_ADDR) >> 14; \
  398. _ezchip_macro_read_value_ &= 0x1;\
  399. }
  400. #define _GET_SYSCON_REG_register4_SCFG_u74_halt_from_tile0(_ezchip_macro_read_value_) { \
  401. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR); \
  402. _ezchip_macro_read_value_ &= 0x1;\
  403. }
  404. #define _GET_SYSCON_REG_register4_SCFG_u74_halt_from_tile1(_ezchip_macro_read_value_) { \
  405. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 1; \
  406. _ezchip_macro_read_value_ &= 0x1;\
  407. }
  408. #define _GET_SYSCON_REG_register4_SCFG_u74_debug_ndreset(_ezchip_macro_read_value_) { \
  409. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 2; \
  410. _ezchip_macro_read_value_ &= 0x1;\
  411. }
  412. #define _GET_SYSCON_REG_register4_SCFG_u74_debug_dmactive(_ezchip_macro_read_value_) { \
  413. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register4_REG_ADDR) >> 3; \
  414. _ezchip_macro_read_value_ &= 0x1;\
  415. }
  416. #define _SET_SYSCON_REG_SCFG_u74_boot_vect0_low_b32(v) { \
  417. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR); \
  418. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  419. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  420. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR,_ezchip_macro_read_value_); \
  421. }
  422. #define _GET_SYSCON_REG_SCFG_u74_boot_vect0_low_b32(_ezchip_macro_read_value_) { \
  423. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_low_REG_ADDR); \
  424. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  425. }
  426. #define _SET_SYSCON_REG_SCFG_u74_boot_vect0_hi_b6(v) { \
  427. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR); \
  428. _ezchip_macro_read_value_ &= ~(0x3F); \
  429. _ezchip_macro_read_value_ |= (v&0x3F); \
  430. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR,_ezchip_macro_read_value_); \
  431. }
  432. #define _GET_SYSCON_REG_SCFG_u74_boot_vect0_hi_b6(_ezchip_macro_read_value_) { \
  433. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect0_hi_REG_ADDR); \
  434. _ezchip_macro_read_value_ &= 0x3f;\
  435. }
  436. #define _SET_SYSCON_REG_SCFG_u74_boot_vect1_low_b32(v) { \
  437. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR); \
  438. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  439. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  440. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR,_ezchip_macro_read_value_); \
  441. }
  442. #define _GET_SYSCON_REG_SCFG_u74_boot_vect1_low_b32(_ezchip_macro_read_value_) { \
  443. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_low_REG_ADDR); \
  444. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  445. }
  446. #define _SET_SYSCON_REG_SCFG_u74_boot_vect1_hi_b6(v) { \
  447. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR); \
  448. _ezchip_macro_read_value_ &= ~(0x3F); \
  449. _ezchip_macro_read_value_ |= (v&0x3F); \
  450. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR,_ezchip_macro_read_value_); \
  451. }
  452. #define _GET_SYSCON_REG_SCFG_u74_boot_vect1_hi_b6(_ezchip_macro_read_value_) { \
  453. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_boot_vect1_hi_REG_ADDR); \
  454. _ezchip_macro_read_value_ &= 0x3f;\
  455. }
  456. #define _SET_SYSCON_REG_SCFG_u74_PRID(v) { \
  457. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR); \
  458. _ezchip_macro_read_value_ &= ~(0x7FF); \
  459. _ezchip_macro_read_value_ |= (v&0x7FF); \
  460. MA_OUTW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR,_ezchip_macro_read_value_); \
  461. }
  462. #define _GET_SYSCON_REG_SCFG_u74_PRID(_ezchip_macro_read_value_) { \
  463. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_u74_REG_ADDR); \
  464. _ezchip_macro_read_value_ &= 0x7ff;\
  465. }
  466. #define _GET_SYSCON_REG_register10_e24_halt(_ezchip_macro_read_value_) { \
  467. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR); \
  468. _ezchip_macro_read_value_ &= 0x1;\
  469. }
  470. #define _GET_SYSCON_REG_register10_e24_dbg_reset(_ezchip_macro_read_value_) { \
  471. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR) >> 1; \
  472. _ezchip_macro_read_value_ &= 0x1;\
  473. }
  474. #define _GET_SYSCON_REG_register10_e24_dbg_active(_ezchip_macro_read_value_) { \
  475. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register10_REG_ADDR) >> 2; \
  476. _ezchip_macro_read_value_ &= 0x1;\
  477. }
  478. #define _SET_SYSCON_REG_register11_SCFG_nbdla_pwrbus_ram_a_pd(v) { \
  479. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register11_REG_ADDR); \
  480. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  481. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  482. MA_OUTW(syscon_sysmain_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
  483. }
  484. #define _GET_SYSCON_REG_register11_SCFG_nbdla_pwrbus_ram_a_pd(_ezchip_macro_read_value_) { \
  485. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register11_REG_ADDR); \
  486. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  487. }
  488. #define _SET_SYSCON_REG_register12_SCFG_nbdla_pwrbus_ram_c_pd(v) { \
  489. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register12_REG_ADDR); \
  490. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  491. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  492. MA_OUTW(syscon_sysmain_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
  493. }
  494. #define _GET_SYSCON_REG_register12_SCFG_nbdla_pwrbus_ram_c_pd(_ezchip_macro_read_value_) { \
  495. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register12_REG_ADDR); \
  496. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  497. }
  498. #define _SET_SYSCON_REG_register13_SCFG_nbdla_pwrbus_ram_o_pd(v) { \
  499. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register13_REG_ADDR); \
  500. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  501. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  502. MA_OUTW(syscon_sysmain_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
  503. }
  504. #define _GET_SYSCON_REG_register13_SCFG_nbdla_pwrbus_ram_o_pd(_ezchip_macro_read_value_) { \
  505. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register13_REG_ADDR); \
  506. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  507. }
  508. #define _SET_SYSCON_REG_register14_SCFG_nbdla_pwrbus_ram_p_pd(v) { \
  509. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register14_REG_ADDR); \
  510. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  511. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  512. MA_OUTW(syscon_sysmain_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
  513. }
  514. #define _GET_SYSCON_REG_register14_SCFG_nbdla_pwrbus_ram_p_pd(_ezchip_macro_read_value_) { \
  515. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register14_REG_ADDR); \
  516. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  517. }
  518. #define _SET_SYSCON_REG_register15_SCFG_nbdla_pwrbus_ram_x_pd(v) { \
  519. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register15_REG_ADDR); \
  520. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  521. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  522. MA_OUTW(syscon_sysmain_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
  523. }
  524. #define _GET_SYSCON_REG_register15_SCFG_nbdla_pwrbus_ram_x_pd(_ezchip_macro_read_value_) { \
  525. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register15_REG_ADDR); \
  526. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  527. }
  528. #define _SET_SYSCON_REG_register16_SCFG_nbdla_globclk_ovr_on(v) { \
  529. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  530. _ezchip_macro_read_value_ &= ~(0x1); \
  531. _ezchip_macro_read_value_ |= (v&0x1); \
  532. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  533. }
  534. #define _GET_SYSCON_REG_register16_SCFG_nbdla_globclk_ovr_on(_ezchip_macro_read_value_) { \
  535. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  536. _ezchip_macro_read_value_ &= 0x1;\
  537. }
  538. #define _SET_SYSCON_REG_register16_SCFG_nbdla_disable_clock_gating(v) { \
  539. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  540. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  541. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  542. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  543. }
  544. #define _GET_SYSCON_REG_register16_SCFG_nbdla_disable_clock_gating(_ezchip_macro_read_value_) { \
  545. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 1; \
  546. _ezchip_macro_read_value_ &= 0x1;\
  547. }
  548. #define _SET_SYSCON_REG_register16_SCFG_nbdla_direct_reset(v) { \
  549. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  550. _ezchip_macro_read_value_ &= ~(0x1<<2); \
  551. _ezchip_macro_read_value_ |= (v&0x1)<<2; \
  552. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  553. }
  554. #define _GET_SYSCON_REG_register16_SCFG_nbdla_direct_reset(_ezchip_macro_read_value_) { \
  555. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 2; \
  556. _ezchip_macro_read_value_ &= 0x1;\
  557. }
  558. #define _SET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(v) { \
  559. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR); \
  560. _ezchip_macro_read_value_ &= ~(0x1<<3); \
  561. _ezchip_macro_read_value_ |= (v&0x1)<<3; \
  562. MA_OUTW(syscon_sysmain_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
  563. }
  564. #define _GET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(_ezchip_macro_read_value_) { \
  565. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register16_REG_ADDR) >> 3; \
  566. _ezchip_macro_read_value_ &= 0x1;\
  567. }
  568. #define _GET_SYSCON_REG_register17_SCFG_jpegc_cur_inst_a(_ezchip_macro_read_value_) { \
  569. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register17_REG_ADDR); \
  570. _ezchip_macro_read_value_ &= 0x3;\
  571. }
  572. #define _GET_SYSCON_REG_register18_SCFG_wave511_vpu_idle(_ezchip_macro_read_value_) { \
  573. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register18_REG_ADDR); \
  574. _ezchip_macro_read_value_ &= 0x1;\
  575. }
  576. #define _GET_SYSCON_REG_register19_SCFG_wave521_vpu_idle(_ezchip_macro_read_value_) { \
  577. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register19_REG_ADDR); \
  578. _ezchip_macro_read_value_ &= 0x1;\
  579. }
  580. #define _SET_SYSCON_REG_register20_u0_syscon_162_SCFG_gc300_csys_req(v) { \
  581. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register20_REG_ADDR); \
  582. _ezchip_macro_read_value_ &= ~(0x1); \
  583. _ezchip_macro_read_value_ |= (v&0x1); \
  584. MA_OUTW(syscon_sysmain_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
  585. }
  586. #define _GET_SYSCON_REG_register20_u0_syscon_162_SCFG_gc300_csys_req(_ezchip_macro_read_value_) { \
  587. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register20_REG_ADDR); \
  588. _ezchip_macro_read_value_ &= 0x1;\
  589. }
  590. #define _GET_SYSCON_REG_register21_u0_syscon_162_SCFG_gc300_cactive(_ezchip_macro_read_value_) { \
  591. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register21_REG_ADDR); \
  592. _ezchip_macro_read_value_ &= 0x1;\
  593. }
  594. #define _GET_SYSCON_REG_register21_u0_syscon_162_SCFG_gc300_csys_ack(_ezchip_macro_read_value_) { \
  595. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register21_REG_ADDR) >> 1; \
  596. _ezchip_macro_read_value_ &= 0x1;\
  597. }
  598. #define _GET_SYSCON_REG_register22_u0_syscon_162_SCFG_gc300_debug_out(_ezchip_macro_read_value_) { \
  599. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register22_REG_ADDR); \
  600. _ezchip_macro_read_value_ &= 0xff;\
  601. }
  602. #define _SET_SYSCON_REG_register23_SCFG_cmsensor_rst0(v) { \
  603. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  604. _ezchip_macro_read_value_ &= ~(0x1); \
  605. _ezchip_macro_read_value_ |= (v&0x1); \
  606. MA_OUTW(syscon_sysmain_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  607. }
  608. #define _GET_SYSCON_REG_register23_SCFG_cmsensor_rst0(_ezchip_macro_read_value_) { \
  609. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  610. _ezchip_macro_read_value_ &= 0x1;\
  611. }
  612. #define _SET_SYSCON_REG_register23_SCFG_cmsensor_rst1(v) { \
  613. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR); \
  614. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  615. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  616. MA_OUTW(syscon_sysmain_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
  617. }
  618. #define _GET_SYSCON_REG_register23_SCFG_cmsensor_rst1(_ezchip_macro_read_value_) { \
  619. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register23_REG_ADDR) >> 1; \
  620. _ezchip_macro_read_value_ &= 0x1;\
  621. }
  622. #define _SET_SYSCON_REG_qspi_SCFG_sram_config(v) { \
  623. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_qspi_REG_ADDR); \
  624. _ezchip_macro_read_value_ &= ~(0xFF); \
  625. _ezchip_macro_read_value_ |= (v&0xFF); \
  626. MA_OUTW(syscon_sysmain_ctrl_qspi_REG_ADDR,_ezchip_macro_read_value_); \
  627. }
  628. #define _GET_SYSCON_REG_qspi_SCFG_sram_config(_ezchip_macro_read_value_) { \
  629. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_qspi_REG_ADDR); \
  630. _ezchip_macro_read_value_ &= 0xff;\
  631. }
  632. #define _SET_SYSCON_REG_intmem_SCFG_sram_config(v) { \
  633. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  634. _ezchip_macro_read_value_ &= ~(0xFF); \
  635. _ezchip_macro_read_value_ |= (v&0xFF); \
  636. MA_OUTW(syscon_sysmain_ctrl_intmem_REG_ADDR,_ezchip_macro_read_value_); \
  637. }
  638. #define _GET_SYSCON_REG_intmem_SCFG_sram_config(_ezchip_macro_read_value_) { \
  639. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  640. _ezchip_macro_read_value_ &= 0xff;\
  641. }
  642. #define _SET_SYSCON_REG_intmem_SCFG_sram_config_rom(v) { \
  643. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR); \
  644. _ezchip_macro_read_value_ &= ~(0xFF<<8); \
  645. _ezchip_macro_read_value_ |= (v&0xFF)<<8; \
  646. MA_OUTW(syscon_sysmain_ctrl_intmem_REG_ADDR,_ezchip_macro_read_value_); \
  647. }
  648. #define _GET_SYSCON_REG_intmem_SCFG_sram_config_rom(_ezchip_macro_read_value_) { \
  649. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_intmem_REG_ADDR) >> 8; \
  650. _ezchip_macro_read_value_ &= 0xff;\
  651. }
  652. #define _SET_SYSCON_REG_register26_SCFG_dma1p2p_sel(v) { \
  653. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register26_REG_ADDR); \
  654. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  655. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  656. MA_OUTW(syscon_sysmain_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
  657. }
  658. #define _GET_SYSCON_REG_register26_SCFG_dma1p2p_sel(_ezchip_macro_read_value_) { \
  659. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register26_REG_ADDR); \
  660. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  661. }
  662. #define _SET_SYSCON_REG_register27_SCFG_dmaezMst_sel(v) { \
  663. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register27_REG_ADDR); \
  664. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  665. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  666. MA_OUTW(syscon_sysmain_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
  667. }
  668. #define _GET_SYSCON_REG_register27_SCFG_dmaezMst_sel(_ezchip_macro_read_value_) { \
  669. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register27_REG_ADDR); \
  670. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  671. }
  672. #define _SET_SYSCON_REG_register28_SCFG_gmac_phy_intf_sel(v) { \
  673. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  674. _ezchip_macro_read_value_ &= ~(0x7); \
  675. _ezchip_macro_read_value_ |= (v&0x7); \
  676. MA_OUTW(syscon_sysmain_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  677. }
  678. #define _GET_SYSCON_REG_register28_SCFG_gmac_phy_intf_sel(_ezchip_macro_read_value_) { \
  679. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  680. _ezchip_macro_read_value_ &= 0x7;\
  681. }
  682. #define _SET_SYSCON_REG_register28_gmac_SCFG_sram_cfg(v) { \
  683. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR); \
  684. _ezchip_macro_read_value_ &= ~(0xFF<<4); \
  685. _ezchip_macro_read_value_ |= (v&0xFF)<<4; \
  686. MA_OUTW(syscon_sysmain_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
  687. }
  688. #define _GET_SYSCON_REG_register28_gmac_SCFG_sram_cfg(_ezchip_macro_read_value_) { \
  689. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register28_REG_ADDR) >> 4; \
  690. _ezchip_macro_read_value_ &= 0xff;\
  691. }
  692. #define _GET_SYSCON_REG_register29_gmac_speed(_ezchip_macro_read_value_) { \
  693. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR); \
  694. _ezchip_macro_read_value_ &= 0x3;\
  695. }
  696. #define _GET_SYSCON_REG_register29_gmac_ptp_pps(_ezchip_macro_read_value_) { \
  697. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR) >> 2; \
  698. _ezchip_macro_read_value_ &= 0x1;\
  699. }
  700. #define _GET_SYSCON_REG_register29_gmac_tx_ckg_ctrl(_ezchip_macro_read_value_) { \
  701. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register29_REG_ADDR) >> 3; \
  702. _ezchip_macro_read_value_ &= 0x1;\
  703. }
  704. #define _GET_SYSCON_REG_SCFG_gmac_timestamp0_ptp(_ezchip_macro_read_value_) { \
  705. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_gmac_timestamp0_REG_ADDR); \
  706. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  707. }
  708. #define _GET_SYSCON_REG_SCFG_gmac_timestamp1_ptp(_ezchip_macro_read_value_) { \
  709. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_gmac_timestamp1_REG_ADDR); \
  710. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  711. }
  712. #define _SET_SYSCON_REG_register32_SCFG_gmac_phy_rstn(v) { \
  713. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register32_REG_ADDR); \
  714. _ezchip_macro_read_value_ &= ~(0x1); \
  715. _ezchip_macro_read_value_ |= (v&0x1); \
  716. MA_OUTW(syscon_sysmain_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
  717. }
  718. #define _GET_SYSCON_REG_register32_SCFG_gmac_phy_rstn(_ezchip_macro_read_value_) { \
  719. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register32_REG_ADDR); \
  720. _ezchip_macro_read_value_ &= 0x1;\
  721. }
  722. #define _SET_SYSCON_REG_register33_SCFG_sdio0_hbig_endian(v) { \
  723. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  724. _ezchip_macro_read_value_ &= ~(0x1); \
  725. _ezchip_macro_read_value_ |= (v&0x1); \
  726. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  727. }
  728. #define _GET_SYSCON_REG_register33_SCFG_sdio0_hbig_endian(_ezchip_macro_read_value_) { \
  729. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  730. _ezchip_macro_read_value_ &= 0x1;\
  731. }
  732. #define _SET_SYSCON_REG_register33_SCFG_sdio0_m_hbig_endian(v) { \
  733. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  734. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  735. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  736. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  737. }
  738. #define _GET_SYSCON_REG_register33_SCFG_sdio0_m_hbig_endian(_ezchip_macro_read_value_) { \
  739. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR) >> 1; \
  740. _ezchip_macro_read_value_ &= 0x1;\
  741. }
  742. #define _SET_SYSCON_REG_register33_sdio0_SCFG_sram_config(v) { \
  743. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR); \
  744. _ezchip_macro_read_value_ &= ~(0xFF<<2); \
  745. _ezchip_macro_read_value_ |= (v&0xFF)<<2; \
  746. MA_OUTW(syscon_sysmain_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
  747. }
  748. #define _GET_SYSCON_REG_register33_sdio0_SCFG_sram_config(_ezchip_macro_read_value_) { \
  749. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register33_REG_ADDR) >> 2; \
  750. _ezchip_macro_read_value_ &= 0xff;\
  751. }
  752. #define _SET_SYSCON_REG_register34_SCFG_sdio1_hbig_endian(v) { \
  753. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  754. _ezchip_macro_read_value_ &= ~(0x1); \
  755. _ezchip_macro_read_value_ |= (v&0x1); \
  756. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  757. }
  758. #define _GET_SYSCON_REG_register34_SCFG_sdio1_hbig_endian(_ezchip_macro_read_value_) { \
  759. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  760. _ezchip_macro_read_value_ &= 0x1;\
  761. }
  762. #define _SET_SYSCON_REG_register34_SCFG_sdio1_m_hbig_endian(v) { \
  763. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  764. _ezchip_macro_read_value_ &= ~(0x1<<1); \
  765. _ezchip_macro_read_value_ |= (v&0x1)<<1; \
  766. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  767. }
  768. #define _GET_SYSCON_REG_register34_SCFG_sdio1_m_hbig_endian(_ezchip_macro_read_value_) { \
  769. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR) >> 1; \
  770. _ezchip_macro_read_value_ &= 0x1;\
  771. }
  772. #define _SET_SYSCON_REG_register34_sdio1_SCFG_sram_config(v) { \
  773. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR); \
  774. _ezchip_macro_read_value_ &= ~(0xFF<<2); \
  775. _ezchip_macro_read_value_ |= (v&0xFF)<<2; \
  776. MA_OUTW(syscon_sysmain_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
  777. }
  778. #define _GET_SYSCON_REG_register34_sdio1_SCFG_sram_config(_ezchip_macro_read_value_) { \
  779. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register34_REG_ADDR) >> 2; \
  780. _ezchip_macro_read_value_ &= 0xff;\
  781. }
  782. #define _SET_SYSCON_REG_register35_SCFG_spi2ahb_mode(v) { \
  783. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register35_REG_ADDR); \
  784. _ezchip_macro_read_value_ &= ~(0x3); \
  785. _ezchip_macro_read_value_ |= (v&0x3); \
  786. MA_OUTW(syscon_sysmain_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
  787. }
  788. #define _GET_SYSCON_REG_register35_SCFG_spi2ahb_mode(_ezchip_macro_read_value_) { \
  789. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register35_REG_ADDR); \
  790. _ezchip_macro_read_value_ &= 0x3;\
  791. }
  792. #define _GET_SYSCON_REG_register36_spi2ahb_sleep(_ezchip_macro_read_value_) { \
  793. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register36_REG_ADDR); \
  794. _ezchip_macro_read_value_ &= 0x1;\
  795. }
  796. #define _SET_SYSCON_REG_register37_ezmst_SCFG_sram_config(v) { \
  797. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register37_REG_ADDR); \
  798. _ezchip_macro_read_value_ &= ~(0xFF); \
  799. _ezchip_macro_read_value_ |= (v&0xFF); \
  800. MA_OUTW(syscon_sysmain_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
  801. }
  802. #define _GET_SYSCON_REG_register37_ezmst_SCFG_sram_config(_ezchip_macro_read_value_) { \
  803. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register37_REG_ADDR); \
  804. _ezchip_macro_read_value_ &= 0xff;\
  805. }
  806. #define _SET_SYSCON_REG_register38_sec_SCFG_sram_cfg(v) { \
  807. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register38_REG_ADDR); \
  808. _ezchip_macro_read_value_ &= ~(0xFF); \
  809. _ezchip_macro_read_value_ |= (v&0xFF); \
  810. MA_OUTW(syscon_sysmain_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
  811. }
  812. #define _GET_SYSCON_REG_register38_sec_SCFG_sram_cfg(_ezchip_macro_read_value_) { \
  813. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register38_REG_ADDR); \
  814. _ezchip_macro_read_value_ &= 0xff;\
  815. }
  816. #define _SET_SYSCON_REG_register39_uart0_SCFG_sram_config(v) { \
  817. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  818. _ezchip_macro_read_value_ &= ~(0xFF); \
  819. _ezchip_macro_read_value_ |= (v&0xFF); \
  820. MA_OUTW(syscon_sysmain_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  821. }
  822. #define _GET_SYSCON_REG_register39_uart0_SCFG_sram_config(_ezchip_macro_read_value_) { \
  823. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  824. _ezchip_macro_read_value_ &= 0xff;\
  825. }
  826. #define _SET_SYSCON_REG_register39_uart1_SCFG_sram_config(v) { \
  827. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR); \
  828. _ezchip_macro_read_value_ &= ~(0xFF<<8); \
  829. _ezchip_macro_read_value_ |= (v&0xFF)<<8; \
  830. MA_OUTW(syscon_sysmain_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
  831. }
  832. #define _GET_SYSCON_REG_register39_uart1_SCFG_sram_config(_ezchip_macro_read_value_) { \
  833. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register39_REG_ADDR) >> 8; \
  834. _ezchip_macro_read_value_ &= 0xff;\
  835. }
  836. #define _GET_SYSCON_REG_register40_trng_secure_mode(_ezchip_macro_read_value_) { \
  837. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register40_REG_ADDR); \
  838. _ezchip_macro_read_value_ &= 0x1;\
  839. }
  840. #define _GET_SYSCON_REG_register40_trng_nonce_mode(_ezchip_macro_read_value_) { \
  841. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register40_REG_ADDR) >> 1; \
  842. _ezchip_macro_read_value_ &= 0x1;\
  843. }
  844. #define _SET_SYSCON_REG_SCFG_intC1_7to0_int_src1(v) { \
  845. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR); \
  846. _ezchip_macro_read_value_ &= ~(0xFF); \
  847. _ezchip_macro_read_value_ |= (v&0xFF); \
  848. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR,_ezchip_macro_read_value_); \
  849. }
  850. #define _GET_SYSCON_REG_SCFG_intC1_7to0_int_src1(_ezchip_macro_read_value_) { \
  851. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC1_7to0_REG_ADDR); \
  852. _ezchip_macro_read_value_ &= 0xff;\
  853. }
  854. #define _SET_SYSCON_REG_SCFG_intC0_src15to8_int_src1(v) { \
  855. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR); \
  856. _ezchip_macro_read_value_ &= ~(0xFF); \
  857. _ezchip_macro_read_value_ |= (v&0xFF); \
  858. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR,_ezchip_macro_read_value_); \
  859. }
  860. #define _GET_SYSCON_REG_SCFG_intC0_src15to8_int_src1(_ezchip_macro_read_value_) { \
  861. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src15to8_REG_ADDR); \
  862. _ezchip_macro_read_value_ &= 0xff;\
  863. }
  864. #define _SET_SYSCON_REG_SCFG_intC0_src23to16_int_src1(v) { \
  865. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR); \
  866. _ezchip_macro_read_value_ &= ~(0xFF); \
  867. _ezchip_macro_read_value_ |= (v&0xFF); \
  868. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR,_ezchip_macro_read_value_); \
  869. }
  870. #define _GET_SYSCON_REG_SCFG_intC0_src23to16_int_src1(_ezchip_macro_read_value_) { \
  871. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src23to16_REG_ADDR); \
  872. _ezchip_macro_read_value_ &= 0xff;\
  873. }
  874. #define _SET_SYSCON_REG_SCFG_intC0_src31to24_int_src1(v) { \
  875. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR); \
  876. _ezchip_macro_read_value_ &= ~(0xFF); \
  877. _ezchip_macro_read_value_ |= (v&0xFF); \
  878. MA_OUTW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR,_ezchip_macro_read_value_); \
  879. }
  880. #define _GET_SYSCON_REG_SCFG_intC0_src31to24_int_src1(_ezchip_macro_read_value_) { \
  881. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_SCFG_intC0_src31to24_REG_ADDR); \
  882. _ezchip_macro_read_value_ &= 0xff;\
  883. }
  884. #define _SET_SYSCON_REG_register47_e24_reset_vector(v) { \
  885. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register47_REG_ADDR); \
  886. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  887. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  888. MA_OUTW(syscon_sysmain_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
  889. }
  890. #define _GET_SYSCON_REG_register47_e24_reset_vector(_ezchip_macro_read_value_) { \
  891. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register47_REG_ADDR); \
  892. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  893. }
  894. #define _SET_SYSCON_REG_register48_SCFG_qspi_sclk_dlychain_sel(v) { \
  895. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register48_REG_ADDR); \
  896. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  897. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  898. MA_OUTW(syscon_sysmain_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
  899. }
  900. #define _GET_SYSCON_REG_register48_SCFG_qspi_sclk_dlychain_sel(_ezchip_macro_read_value_) { \
  901. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register48_REG_ADDR); \
  902. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  903. }
  904. #define _SET_SYSCON_REG_register52_SCFG_gmac_rxclk_dlychain_sel(v) { \
  905. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register52_REG_ADDR); \
  906. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  907. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  908. MA_OUTW(syscon_sysmain_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
  909. }
  910. #define _GET_SYSCON_REG_register52_SCFG_gmac_rxclk_dlychain_sel(_ezchip_macro_read_value_) { \
  911. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register52_REG_ADDR); \
  912. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  913. }
  914. #define _SET_SYSCON_REG_register49_SCFG_gmac_gtxclk_dlychain_sel(v) { \
  915. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register49_REG_ADDR); \
  916. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  917. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  918. MA_OUTW(syscon_sysmain_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
  919. }
  920. #define _GET_SYSCON_REG_register49_SCFG_gmac_gtxclk_dlychain_sel(_ezchip_macro_read_value_) { \
  921. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register49_REG_ADDR); \
  922. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  923. }
  924. #define _SET_SYSCON_REG_register50_SCFG_sdio0_cclk_dlychain_sel(v) { \
  925. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register50_REG_ADDR); \
  926. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  927. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  928. MA_OUTW(syscon_sysmain_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
  929. }
  930. #define _GET_SYSCON_REG_register50_SCFG_sdio0_cclk_dlychain_sel(_ezchip_macro_read_value_) { \
  931. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register50_REG_ADDR); \
  932. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  933. }
  934. #define _SET_SYSCON_REG_register51_SCFG_sdio1_cclk_dlychain_sel(v) { \
  935. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register51_REG_ADDR); \
  936. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  937. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  938. MA_OUTW(syscon_sysmain_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
  939. }
  940. #define _GET_SYSCON_REG_register51_SCFG_sdio1_cclk_dlychain_sel(_ezchip_macro_read_value_) { \
  941. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register51_REG_ADDR); \
  942. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  943. }
  944. #define _SET_SYSCON_REG_register66_SCFG_axi_cache_sel(v) { \
  945. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  946. _ezchip_macro_read_value_ &= ~(0xFF); \
  947. _ezchip_macro_read_value_ |= (v&0xFF); \
  948. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  949. }
  950. #define _GET_SYSCON_REG_register66_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  951. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  952. _ezchip_macro_read_value_ &= 0xff;\
  953. }
  954. #define _SET_SYSCON_REG_register66_SCFG_default_arcache(v) { \
  955. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  956. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  957. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  958. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  959. }
  960. #define _GET_SYSCON_REG_register66_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  961. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR) >> 8; \
  962. _ezchip_macro_read_value_ &= 0xf;\
  963. }
  964. #define _SET_SYSCON_REG_register66_SCFG_default_awcache(v) { \
  965. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR); \
  966. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  967. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  968. MA_OUTW(syscon_sysmain_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
  969. }
  970. #define _GET_SYSCON_REG_register66_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  971. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register66_REG_ADDR) >> 12; \
  972. _ezchip_macro_read_value_ &= 0xf;\
  973. }
  974. #define _SET_SYSCON_REG_register53_SCFG_axi_cache_sel(v) { \
  975. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  976. _ezchip_macro_read_value_ &= ~(0xFF); \
  977. _ezchip_macro_read_value_ |= (v&0xFF); \
  978. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  979. }
  980. #define _GET_SYSCON_REG_register53_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  981. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  982. _ezchip_macro_read_value_ &= 0xff;\
  983. }
  984. #define _SET_SYSCON_REG_register53_SCFG_default_arcache(v) { \
  985. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  986. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  987. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  988. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  989. }
  990. #define _GET_SYSCON_REG_register53_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  991. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR) >> 8; \
  992. _ezchip_macro_read_value_ &= 0xf;\
  993. }
  994. #define _SET_SYSCON_REG_register53_SCFG_default_awcache(v) { \
  995. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR); \
  996. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  997. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  998. MA_OUTW(syscon_sysmain_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
  999. }
  1000. #define _GET_SYSCON_REG_register53_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1001. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register53_REG_ADDR) >> 12; \
  1002. _ezchip_macro_read_value_ &= 0xf;\
  1003. }
  1004. #define _SET_SYSCON_REG_register54_SCFG_axi_cache_sel(v) { \
  1005. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1006. _ezchip_macro_read_value_ &= ~(0xFF); \
  1007. _ezchip_macro_read_value_ |= (v&0xFF); \
  1008. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1009. }
  1010. #define _GET_SYSCON_REG_register54_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1011. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1012. _ezchip_macro_read_value_ &= 0xff;\
  1013. }
  1014. #define _SET_SYSCON_REG_register54_SCFG_default_arcache(v) { \
  1015. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1016. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1017. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1018. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1019. }
  1020. #define _GET_SYSCON_REG_register54_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1021. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR) >> 8; \
  1022. _ezchip_macro_read_value_ &= 0xf;\
  1023. }
  1024. #define _SET_SYSCON_REG_register54_SCFG_default_awcache(v) { \
  1025. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR); \
  1026. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1027. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1028. MA_OUTW(syscon_sysmain_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
  1029. }
  1030. #define _GET_SYSCON_REG_register54_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1031. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register54_REG_ADDR) >> 12; \
  1032. _ezchip_macro_read_value_ &= 0xf;\
  1033. }
  1034. #define _SET_SYSCON_REG_register55_SCFG_axi_cache_sel(v) { \
  1035. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1036. _ezchip_macro_read_value_ &= ~(0xFF); \
  1037. _ezchip_macro_read_value_ |= (v&0xFF); \
  1038. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1039. }
  1040. #define _GET_SYSCON_REG_register55_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1041. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1042. _ezchip_macro_read_value_ &= 0xff;\
  1043. }
  1044. #define _SET_SYSCON_REG_register55_SCFG_default_arcache(v) { \
  1045. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1046. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1047. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1048. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1049. }
  1050. #define _GET_SYSCON_REG_register55_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1051. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR) >> 8; \
  1052. _ezchip_macro_read_value_ &= 0xf;\
  1053. }
  1054. #define _SET_SYSCON_REG_register55_SCFG_default_awcache(v) { \
  1055. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR); \
  1056. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1057. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1058. MA_OUTW(syscon_sysmain_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
  1059. }
  1060. #define _GET_SYSCON_REG_register55_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1061. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register55_REG_ADDR) >> 12; \
  1062. _ezchip_macro_read_value_ &= 0xf;\
  1063. }
  1064. #define _SET_SYSCON_REG_register56_SCFG_axi_cache_sel(v) { \
  1065. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1066. _ezchip_macro_read_value_ &= ~(0xFF); \
  1067. _ezchip_macro_read_value_ |= (v&0xFF); \
  1068. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1069. }
  1070. #define _GET_SYSCON_REG_register56_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1071. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1072. _ezchip_macro_read_value_ &= 0xff;\
  1073. }
  1074. #define _SET_SYSCON_REG_register56_SCFG_default_arcache(v) { \
  1075. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1076. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1077. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1078. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1079. }
  1080. #define _GET_SYSCON_REG_register56_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1081. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR) >> 8; \
  1082. _ezchip_macro_read_value_ &= 0xf;\
  1083. }
  1084. #define _SET_SYSCON_REG_register56_SCFG_default_awcache(v) { \
  1085. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR); \
  1086. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1087. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1088. MA_OUTW(syscon_sysmain_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
  1089. }
  1090. #define _GET_SYSCON_REG_register56_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1091. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register56_REG_ADDR) >> 12; \
  1092. _ezchip_macro_read_value_ &= 0xf;\
  1093. }
  1094. #define _SET_SYSCON_REG_register57_SCFG_axi_cache_sel(v) { \
  1095. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1096. _ezchip_macro_read_value_ &= ~(0xFF); \
  1097. _ezchip_macro_read_value_ |= (v&0xFF); \
  1098. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1099. }
  1100. #define _GET_SYSCON_REG_register57_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1101. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1102. _ezchip_macro_read_value_ &= 0xff;\
  1103. }
  1104. #define _SET_SYSCON_REG_register57_SCFG_default_arcache(v) { \
  1105. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1106. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1107. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1108. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1109. }
  1110. #define _GET_SYSCON_REG_register57_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1111. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR) >> 8; \
  1112. _ezchip_macro_read_value_ &= 0xf;\
  1113. }
  1114. #define _SET_SYSCON_REG_register57_SCFG_default_awcache(v) { \
  1115. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR); \
  1116. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1117. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1118. MA_OUTW(syscon_sysmain_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
  1119. }
  1120. #define _GET_SYSCON_REG_register57_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1121. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register57_REG_ADDR) >> 12; \
  1122. _ezchip_macro_read_value_ &= 0xf;\
  1123. }
  1124. #define _SET_SYSCON_REG_register58_SCFG_axi_cache_sel(v) { \
  1125. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1126. _ezchip_macro_read_value_ &= ~(0xFF); \
  1127. _ezchip_macro_read_value_ |= (v&0xFF); \
  1128. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1129. }
  1130. #define _GET_SYSCON_REG_register58_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1131. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1132. _ezchip_macro_read_value_ &= 0xff;\
  1133. }
  1134. #define _SET_SYSCON_REG_register58_SCFG_default_arcache(v) { \
  1135. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1136. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1137. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1138. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1139. }
  1140. #define _GET_SYSCON_REG_register58_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1141. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR) >> 8; \
  1142. _ezchip_macro_read_value_ &= 0xf;\
  1143. }
  1144. #define _SET_SYSCON_REG_register58_SCFG_default_awcache(v) { \
  1145. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR); \
  1146. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1147. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1148. MA_OUTW(syscon_sysmain_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
  1149. }
  1150. #define _GET_SYSCON_REG_register58_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1151. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register58_REG_ADDR) >> 12; \
  1152. _ezchip_macro_read_value_ &= 0xf;\
  1153. }
  1154. #define _SET_SYSCON_REG_register59_SCFG_axi_cache_sel(v) { \
  1155. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1156. _ezchip_macro_read_value_ &= ~(0xFF); \
  1157. _ezchip_macro_read_value_ |= (v&0xFF); \
  1158. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1159. }
  1160. #define _GET_SYSCON_REG_register59_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1161. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1162. _ezchip_macro_read_value_ &= 0xff;\
  1163. }
  1164. #define _SET_SYSCON_REG_register59_SCFG_default_arcache(v) { \
  1165. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1166. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1167. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1168. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1169. }
  1170. #define _GET_SYSCON_REG_register59_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1171. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR) >> 8; \
  1172. _ezchip_macro_read_value_ &= 0xf;\
  1173. }
  1174. #define _SET_SYSCON_REG_register59_SCFG_default_awcache(v) { \
  1175. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR); \
  1176. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1177. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1178. MA_OUTW(syscon_sysmain_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
  1179. }
  1180. #define _GET_SYSCON_REG_register59_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1181. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register59_REG_ADDR) >> 12; \
  1182. _ezchip_macro_read_value_ &= 0xf;\
  1183. }
  1184. #define _SET_SYSCON_REG_register60_SCFG_axi_cache_sel(v) { \
  1185. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1186. _ezchip_macro_read_value_ &= ~(0xFF); \
  1187. _ezchip_macro_read_value_ |= (v&0xFF); \
  1188. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1189. }
  1190. #define _GET_SYSCON_REG_register60_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1191. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1192. _ezchip_macro_read_value_ &= 0xff;\
  1193. }
  1194. #define _SET_SYSCON_REG_register60_SCFG_default_arcache(v) { \
  1195. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1196. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1197. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1198. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1199. }
  1200. #define _GET_SYSCON_REG_register60_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1201. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR) >> 8; \
  1202. _ezchip_macro_read_value_ &= 0xf;\
  1203. }
  1204. #define _SET_SYSCON_REG_register60_SCFG_default_awcache(v) { \
  1205. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR); \
  1206. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1207. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1208. MA_OUTW(syscon_sysmain_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
  1209. }
  1210. #define _GET_SYSCON_REG_register60_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1211. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register60_REG_ADDR) >> 12; \
  1212. _ezchip_macro_read_value_ &= 0xf;\
  1213. }
  1214. #define _SET_SYSCON_REG_register61_SCFG_axi_cache_sel(v) { \
  1215. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1216. _ezchip_macro_read_value_ &= ~(0xFF); \
  1217. _ezchip_macro_read_value_ |= (v&0xFF); \
  1218. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1219. }
  1220. #define _GET_SYSCON_REG_register61_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1221. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1222. _ezchip_macro_read_value_ &= 0xff;\
  1223. }
  1224. #define _SET_SYSCON_REG_register61_SCFG_default_arcache(v) { \
  1225. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1226. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1227. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1228. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1229. }
  1230. #define _GET_SYSCON_REG_register61_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1231. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR) >> 8; \
  1232. _ezchip_macro_read_value_ &= 0xf;\
  1233. }
  1234. #define _SET_SYSCON_REG_register61_SCFG_default_awcache(v) { \
  1235. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR); \
  1236. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1237. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1238. MA_OUTW(syscon_sysmain_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
  1239. }
  1240. #define _GET_SYSCON_REG_register61_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1241. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register61_REG_ADDR) >> 12; \
  1242. _ezchip_macro_read_value_ &= 0xf;\
  1243. }
  1244. #define _SET_SYSCON_REG_register62_SCFG_axi_cache_sel(v) { \
  1245. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1246. _ezchip_macro_read_value_ &= ~(0xFF); \
  1247. _ezchip_macro_read_value_ |= (v&0xFF); \
  1248. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1249. }
  1250. #define _GET_SYSCON_REG_register62_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1251. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1252. _ezchip_macro_read_value_ &= 0xff;\
  1253. }
  1254. #define _SET_SYSCON_REG_register62_SCFG_default_arcache(v) { \
  1255. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1256. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1257. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1258. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1259. }
  1260. #define _GET_SYSCON_REG_register62_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1261. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR) >> 8; \
  1262. _ezchip_macro_read_value_ &= 0xf;\
  1263. }
  1264. #define _SET_SYSCON_REG_register62_SCFG_default_awcache(v) { \
  1265. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR); \
  1266. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1267. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1268. MA_OUTW(syscon_sysmain_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
  1269. }
  1270. #define _GET_SYSCON_REG_register62_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1271. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register62_REG_ADDR) >> 12; \
  1272. _ezchip_macro_read_value_ &= 0xf;\
  1273. }
  1274. #define _SET_SYSCON_REG_register63_SCFG_axi_cache_sel(v) { \
  1275. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1276. _ezchip_macro_read_value_ &= ~(0xFF); \
  1277. _ezchip_macro_read_value_ |= (v&0xFF); \
  1278. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1279. }
  1280. #define _GET_SYSCON_REG_register63_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1281. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1282. _ezchip_macro_read_value_ &= 0xff;\
  1283. }
  1284. #define _SET_SYSCON_REG_register63_SCFG_default_arcache(v) { \
  1285. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1286. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1287. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1288. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1289. }
  1290. #define _GET_SYSCON_REG_register63_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1291. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR) >> 8; \
  1292. _ezchip_macro_read_value_ &= 0xf;\
  1293. }
  1294. #define _SET_SYSCON_REG_register63_SCFG_default_awcache(v) { \
  1295. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR); \
  1296. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1297. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1298. MA_OUTW(syscon_sysmain_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
  1299. }
  1300. #define _GET_SYSCON_REG_register63_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1301. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register63_REG_ADDR) >> 12; \
  1302. _ezchip_macro_read_value_ &= 0xf;\
  1303. }
  1304. #define _SET_SYSCON_REG_register64_SCFG_axi_cache_sel(v) { \
  1305. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1306. _ezchip_macro_read_value_ &= ~(0xFF); \
  1307. _ezchip_macro_read_value_ |= (v&0xFF); \
  1308. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1309. }
  1310. #define _GET_SYSCON_REG_register64_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1311. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1312. _ezchip_macro_read_value_ &= 0xff;\
  1313. }
  1314. #define _SET_SYSCON_REG_register64_SCFG_default_arcache(v) { \
  1315. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1316. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1317. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1318. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1319. }
  1320. #define _GET_SYSCON_REG_register64_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1321. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR) >> 8; \
  1322. _ezchip_macro_read_value_ &= 0xf;\
  1323. }
  1324. #define _SET_SYSCON_REG_register64_SCFG_default_awcache(v) { \
  1325. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR); \
  1326. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1327. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1328. MA_OUTW(syscon_sysmain_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
  1329. }
  1330. #define _GET_SYSCON_REG_register64_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1331. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register64_REG_ADDR) >> 12; \
  1332. _ezchip_macro_read_value_ &= 0xf;\
  1333. }
  1334. #define _SET_SYSCON_REG_register65_SCFG_axi_cache_sel(v) { \
  1335. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1336. _ezchip_macro_read_value_ &= ~(0xFF); \
  1337. _ezchip_macro_read_value_ |= (v&0xFF); \
  1338. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1339. }
  1340. #define _GET_SYSCON_REG_register65_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1341. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1342. _ezchip_macro_read_value_ &= 0xff;\
  1343. }
  1344. #define _SET_SYSCON_REG_register65_SCFG_default_arcache(v) { \
  1345. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1346. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1347. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1348. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1349. }
  1350. #define _GET_SYSCON_REG_register65_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1351. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR) >> 8; \
  1352. _ezchip_macro_read_value_ &= 0xf;\
  1353. }
  1354. #define _SET_SYSCON_REG_register65_SCFG_default_awcache(v) { \
  1355. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR); \
  1356. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1357. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1358. MA_OUTW(syscon_sysmain_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
  1359. }
  1360. #define _GET_SYSCON_REG_register65_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1361. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register65_REG_ADDR) >> 12; \
  1362. _ezchip_macro_read_value_ &= 0xf;\
  1363. }
  1364. #define _SET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(v) { \
  1365. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register68_REG_ADDR); \
  1366. _ezchip_macro_read_value_ &= ~(0x1); \
  1367. _ezchip_macro_read_value_ |= (v&0x1); \
  1368. MA_OUTW(syscon_sysmain_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
  1369. }
  1370. #define _GET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(_ezchip_macro_read_value_) { \
  1371. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register68_REG_ADDR); \
  1372. _ezchip_macro_read_value_ &= 0x1;\
  1373. }
  1374. #define _SET_SYSCON_REG_register67_SCFG_axi_cache_sel(v) { \
  1375. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1376. _ezchip_macro_read_value_ &= ~(0xFF); \
  1377. _ezchip_macro_read_value_ |= (v&0xFF); \
  1378. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1379. }
  1380. #define _GET_SYSCON_REG_register67_SCFG_axi_cache_sel(_ezchip_macro_read_value_) { \
  1381. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1382. _ezchip_macro_read_value_ &= 0xff;\
  1383. }
  1384. #define _SET_SYSCON_REG_register67_SCFG_default_arcache(v) { \
  1385. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1386. _ezchip_macro_read_value_ &= ~(0xF<<8); \
  1387. _ezchip_macro_read_value_ |= (v&0xF)<<8; \
  1388. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1389. }
  1390. #define _GET_SYSCON_REG_register67_SCFG_default_arcache(_ezchip_macro_read_value_) { \
  1391. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR) >> 8; \
  1392. _ezchip_macro_read_value_ &= 0xf;\
  1393. }
  1394. #define _SET_SYSCON_REG_register67_SCFG_default_awcache(v) { \
  1395. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR); \
  1396. _ezchip_macro_read_value_ &= ~(0xF<<12); \
  1397. _ezchip_macro_read_value_ |= (v&0xF)<<12; \
  1398. MA_OUTW(syscon_sysmain_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
  1399. }
  1400. #define _GET_SYSCON_REG_register67_SCFG_default_awcache(_ezchip_macro_read_value_) { \
  1401. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register67_REG_ADDR) >> 12; \
  1402. _ezchip_macro_read_value_ &= 0xf;\
  1403. }
  1404. #define _SET_SYSCON_REG_register69_core1_en(v) { \
  1405. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register69_REG_ADDR); \
  1406. _ezchip_macro_read_value_ &= ~(0x1); \
  1407. _ezchip_macro_read_value_ |= (v&0x1); \
  1408. MA_OUTW(syscon_sysmain_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
  1409. }
  1410. #define _GET_SYSCON_REG_register69_core1_en(_ezchip_macro_read_value_) { \
  1411. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register69_REG_ADDR); \
  1412. _ezchip_macro_read_value_ &= 0x1;\
  1413. }
  1414. #define _SET_SYSCON_REG_register70_SCFG_boot_mode(v) { \
  1415. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR); \
  1416. _ezchip_macro_read_value_ &= ~(0x1); \
  1417. _ezchip_macro_read_value_ |= (v&0x1); \
  1418. MA_OUTW(syscon_sysmain_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
  1419. }
  1420. #define _GET_SYSCON_REG_register70_SCFG_boot_mode(_ezchip_macro_read_value_) { \
  1421. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR); \
  1422. _ezchip_macro_read_value_ &= 0x1;\
  1423. }
  1424. #define _GET_SYSCON_REG_register70_SCFG_u74_IOPAD_bootmode(_ezchip_macro_read_value_) { \
  1425. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register70_REG_ADDR) >> 1; \
  1426. _ezchip_macro_read_value_ &= 0x1;\
  1427. }
  1428. #define _SET_SYSCON_REG_register71_SCFG_u74_reset_vector(v) { \
  1429. uint32_t _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register71_REG_ADDR); \
  1430. _ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
  1431. _ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
  1432. MA_OUTW(syscon_sysmain_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
  1433. }
  1434. #define _GET_SYSCON_REG_register71_SCFG_u74_reset_vector(_ezchip_macro_read_value_) { \
  1435. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register71_REG_ADDR); \
  1436. _ezchip_macro_read_value_ &= 0xFFFFFFFF;\
  1437. }
  1438. #define _GET_SYSCON_REG_register72_u74_boot_device_sel(_ezchip_macro_read_value_) { \
  1439. _ezchip_macro_read_value_=MA_INW(syscon_sysmain_ctrl_register72_REG_ADDR); \
  1440. _ezchip_macro_read_value_ &= 0x7;\
  1441. }
  1442. #endif //_SYSCON_SYSMAIN_CTRL_MACRO_H_