clkgen_ctrl_macro.h 173 KB

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  1. /**
  2. ******************************************************************************
  3. * @file clkgen_ctrl_macro.h
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 07/20/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #ifndef _CLKGEN_MACRO_H_
  21. #define _CLKGEN_MACRO_H_
  22. //#define CLKGEN_BASE_ADDR 0x0
  23. #define clk_cpundbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x0
  24. #define clk_dla_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4
  25. #define clk_dsp_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8
  26. #define clk_gmacusb_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC
  27. #define clk_perh0_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10
  28. #define clk_perh1_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14
  29. #define clk_vin_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18
  30. #define clk_vout_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C
  31. #define clk_audio_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20
  32. #define clk_cdechifi4_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24
  33. #define clk_cdec_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28
  34. #define clk_voutbus_root_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C
  35. #define clk_cpunbus_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x30
  36. #define clk_dsp_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x34
  37. #define clk_perh0_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x38
  38. #define clk_perh1_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x3C
  39. #define clk_pll0_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x40
  40. #define clk_pll1_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x44
  41. #define clk_pll2_testout_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x48
  42. #define clk_pll2_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x4C
  43. #define clk_cpu_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x50
  44. #define clk_cpu_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x54
  45. #define clk_ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x58
  46. #define clk_apb1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x5C
  47. #define clk_apb2_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x60
  48. #define clk_dom3ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x64
  49. #define clk_dom7ahb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x68
  50. #define clk_u74_core0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x6C
  51. #define clk_u74_core1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x70
  52. #define clk_u74_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x74
  53. #define clk_u74rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x78
  54. #define clk_sgdma2p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x7C
  55. #define clk_dma2pnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x80
  56. #define clk_sgdma2p_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x84
  57. #define clk_dla_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x88
  58. #define clk_dla_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x8C
  59. #define clk_dlanoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x90
  60. #define clk_dla_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x94
  61. #define clk_vp6_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x98
  62. #define clk_vp6bus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x9C
  63. #define clk_vp6_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA0
  64. #define clk_vcdecbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA4
  65. #define clk_vdec_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xA8
  66. #define clk_vdec_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xAC
  67. #define clk_vdecbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB0
  68. #define clk_vdec_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB4
  69. #define clk_vdec_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xB8
  70. #define clk_vdec_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xBC
  71. #define clk_jpeg_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC0
  72. #define clk_jpeg_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC4
  73. #define clk_jpeg_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xC8
  74. #define clk_gc300_2x_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xCC
  75. #define clk_gc300_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD0
  76. #define clk_jpcgc300_axibus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD4
  77. #define clk_gc300_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xD8
  78. #define clk_jpcgc300_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xDC
  79. #define clk_venc_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE0
  80. #define clk_venc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE4
  81. #define clk_vencbrg_mainclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xE8
  82. #define clk_venc_bclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xEC
  83. #define clk_venc_cclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF0
  84. #define clk_venc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF4
  85. #define clk_ddrpll_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xF8
  86. #define clk_ddrpll_div4_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0xFC
  87. #define clk_ddrpll_div8_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x100
  88. #define clk_ddrosc_div2_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x104
  89. #define clk_ddrc0_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x108
  90. #define clk_ddrc1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x10C
  91. #define clk_ddrphy_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x110
  92. #define clk_noc_rob_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x114
  93. #define clk_noc_cog_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x118
  94. #define clk_nne_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x11C
  95. #define clk_nnebus_src1_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x120
  96. #define clk_nne_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x124
  97. #define clk_nne_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x128
  98. #define clk_nnenoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x12C
  99. #define clk_dlaslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x130
  100. #define clk_dspx2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x134
  101. #define clk_hifi4_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x138
  102. #define clk_hifi4_corefree_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x13C
  103. #define clk_hifi4_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x140
  104. #define clk_hifi4_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x144
  105. #define clk_hifi4_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x148
  106. #define clk_hifi4noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x14C
  107. #define clk_sgdma1p_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x150
  108. #define clk_sgdma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x154
  109. #define clk_dma1p_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x158
  110. #define clk_x2c_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x15C
  111. #define clk_usb_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x160
  112. #define clk_usb_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x164
  113. #define clk_usbnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x168
  114. #define clk_usbphy_rootdiv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x16C
  115. #define clk_usbphy_125m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x170
  116. #define clk_usbphy_plldiv25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x174
  117. #define clk_usbphy_25m_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x178
  118. #define clk_audio_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x17C
  119. #define clk_audio_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x180
  120. #define clk_audio_12288_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x184
  121. #define clk_vin_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x188
  122. #define clk_isp0_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x18C
  123. #define clk_isp0_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x190
  124. #define clk_isp0noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x194
  125. #define clk_ispslv_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x198
  126. #define clk_isp1_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x19C
  127. #define clk_isp1_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A0
  128. #define clk_isp1noc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A4
  129. #define clk_vin_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1A8
  130. #define clk_vin_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1AC
  131. #define clk_vinnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B0
  132. #define clk_vout_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B4
  133. #define clk_dispbus_src_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1B8
  134. #define clk_disp_bus_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1BC
  135. #define clk_disp_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C0
  136. #define clk_dispnoc_axi_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C4
  137. #define clk_sdio0_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1C8
  138. #define clk_sdio0_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1CC
  139. #define clk_sdio0_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D0
  140. #define clk_sdio1_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D4
  141. #define clk_sdio1_cclkint_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1D8
  142. #define clk_sdio1_cclkint_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1DC
  143. #define clk_gmac_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E0
  144. #define clk_gmac_root_div_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E4
  145. #define clk_gmac_ptp_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1E8
  146. #define clk_gmac_gtxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1EC
  147. #define clk_gmac_rmii_txclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F0
  148. #define clk_gmac_rmii_rxclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F4
  149. #define clk_gmac_tx_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1F8
  150. #define clk_gmac_tx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x1FC
  151. #define clk_gmac_rx_pre_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x200
  152. #define clk_gmac_rx_inv_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x204
  153. #define clk_gmac_rmii_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x208
  154. #define clk_gmac_tophyref_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x20C
  155. #define clk_spi2ahb_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x210
  156. #define clk_spi2ahb_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x214
  157. #define clk_ezmaster_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x218
  158. #define clk_e24_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x21C
  159. #define clk_e24rtc_toggle_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x220
  160. #define clk_qspi_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x224
  161. #define clk_qspi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x228
  162. #define clk_qspi_refclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x22C
  163. #define clk_sec_ahb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x230
  164. #define clk_aes_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x234
  165. #define clk_sha_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x238
  166. #define clk_pka_clk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x23C
  167. #define clk_trng_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x240
  168. #define clk_otp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x244
  169. #define clk_uart0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x248
  170. #define clk_uart0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x24C
  171. #define clk_uart1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x250
  172. #define clk_uart1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x254
  173. #define clk_spi0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x258
  174. #define clk_spi0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x25C
  175. #define clk_spi1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x260
  176. #define clk_spi1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x264
  177. #define clk_i2c0_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x268
  178. #define clk_i2c0_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x26C
  179. #define clk_i2c1_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x270
  180. #define clk_i2c1_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x274
  181. #define clk_gpio_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x278
  182. #define clk_uart2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x27C
  183. #define clk_uart2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x280
  184. #define clk_uart3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x284
  185. #define clk_uart3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x288
  186. #define clk_spi2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x28C
  187. #define clk_spi2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x290
  188. #define clk_spi3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x294
  189. #define clk_spi3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x298
  190. #define clk_i2c2_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x29C
  191. #define clk_i2c2_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A0
  192. #define clk_i2c3_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A4
  193. #define clk_i2c3_core_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2A8
  194. #define clk_wdtimer_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2AC
  195. #define clk_wdt_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B0
  196. #define clk_timer0_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B4
  197. #define clk_timer1_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2B8
  198. #define clk_timer2_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2BC
  199. #define clk_timer3_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C0
  200. #define clk_timer4_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C4
  201. #define clk_timer5_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2C8
  202. #define clk_timer6_coreclk_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2CC
  203. #define clk_vp6intc_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D0
  204. #define clk_pwm_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D4
  205. #define clk_msi_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2D8
  206. #define clk_temp_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2DC
  207. #define clk_temp_sense_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E0
  208. #define clk_syserr_apb_ctrl_REG_ADDR CLKGEN_BASE_ADDR + 0x2E4
  209. #define _ENABLE_CLOCK_clk_cpundbus_root_ {}
  210. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_osc_sys_ { \
  211. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  212. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  213. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  214. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  215. }
  216. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll0_out_ { \
  217. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  218. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  219. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  220. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  221. }
  222. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll1_out_ { \
  223. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  224. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  225. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  226. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  227. }
  228. #define _SWITCH_CLOCK_clk_cpundbus_root_SOURCE_clk_pll2_out_ { \
  229. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR); \
  230. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  231. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  232. MA_OUTW(clk_cpundbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  233. }
  234. #define _GET_CLOCK_SOURCE_STATUS_clk_cpundbus_root_(_ezchip_macro_read_value_) { \
  235. _ezchip_macro_read_value_=MA_INW(clk_cpundbus_root_ctrl_REG_ADDR) >> 24; \
  236. _ezchip_macro_read_value_ &= 0x3;\
  237. }
  238. #define _ENABLE_CLOCK_clk_dla_root_ {}
  239. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_osc_sys_ { \
  240. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  241. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  242. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  243. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  244. }
  245. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_ { \
  246. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  247. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  248. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  249. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  250. }
  251. #define _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll2_out_ { \
  252. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR); \
  253. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  254. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  255. MA_OUTW(clk_dla_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  256. }
  257. #define _GET_CLOCK_SOURCE_STATUS_clk_dla_root_(_ezchip_macro_read_value_) { \
  258. _ezchip_macro_read_value_=MA_INW(clk_dla_root_ctrl_REG_ADDR) >> 24; \
  259. _ezchip_macro_read_value_ &= 0x3;\
  260. }
  261. #define _ENABLE_CLOCK_clk_dsp_root_ {}
  262. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_osc_sys_ { \
  263. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  264. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  265. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  266. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  267. }
  268. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll0_out_ { \
  269. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  270. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  271. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  272. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  273. }
  274. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll1_out_ { \
  275. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  276. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  277. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  278. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  279. }
  280. #define _SWITCH_CLOCK_clk_dsp_root_SOURCE_clk_pll2_out_ { \
  281. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR); \
  282. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  283. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  284. MA_OUTW(clk_dsp_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  285. }
  286. #define _GET_CLOCK_SOURCE_STATUS_clk_dsp_root_(_ezchip_macro_read_value_) { \
  287. _ezchip_macro_read_value_=MA_INW(clk_dsp_root_ctrl_REG_ADDR) >> 24; \
  288. _ezchip_macro_read_value_ &= 0x3;\
  289. }
  290. #define _ENABLE_CLOCK_clk_gmacusb_root_ {}
  291. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_osc_sys_ { \
  292. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  293. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  294. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  295. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  296. }
  297. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll0_out_ { \
  298. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  299. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  300. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  301. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  302. }
  303. #define _SWITCH_CLOCK_clk_gmacusb_root_SOURCE_clk_pll2_out_ { \
  304. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR); \
  305. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  306. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  307. MA_OUTW(clk_gmacusb_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  308. }
  309. #define _GET_CLOCK_SOURCE_STATUS_clk_gmacusb_root_(_ezchip_macro_read_value_) { \
  310. _ezchip_macro_read_value_=MA_INW(clk_gmacusb_root_ctrl_REG_ADDR) >> 24; \
  311. _ezchip_macro_read_value_ &= 0x3;\
  312. }
  313. #define _ENABLE_CLOCK_clk_perh0_root_ {}
  314. #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_osc_sys_ { \
  315. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
  316. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  317. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  318. MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  319. }
  320. #define _SWITCH_CLOCK_clk_perh0_root_SOURCE_clk_pll0_out_ { \
  321. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR); \
  322. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  323. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  324. MA_OUTW(clk_perh0_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  325. }
  326. #define _GET_CLOCK_SOURCE_STATUS_clk_perh0_root_(_ezchip_macro_read_value_) { \
  327. _ezchip_macro_read_value_=MA_INW(clk_perh0_root_ctrl_REG_ADDR) >> 24; \
  328. _ezchip_macro_read_value_ &= 0x1;\
  329. }
  330. #define _ENABLE_CLOCK_clk_perh1_root_ {}
  331. #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_osc_sys_ { \
  332. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
  333. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  334. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  335. MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  336. }
  337. #define _SWITCH_CLOCK_clk_perh1_root_SOURCE_clk_pll2_out_ { \
  338. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR); \
  339. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  340. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  341. MA_OUTW(clk_perh1_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  342. }
  343. #define _GET_CLOCK_SOURCE_STATUS_clk_perh1_root_(_ezchip_macro_read_value_) { \
  344. _ezchip_macro_read_value_=MA_INW(clk_perh1_root_ctrl_REG_ADDR) >> 24; \
  345. _ezchip_macro_read_value_ &= 0x1;\
  346. }
  347. #define _ENABLE_CLOCK_clk_vin_root_ {}
  348. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_osc_sys_ { \
  349. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  350. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  351. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  352. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  353. }
  354. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll1_out_ { \
  355. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  356. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  357. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  358. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  359. }
  360. #define _SWITCH_CLOCK_clk_vin_root_SOURCE_clk_pll2_out_ { \
  361. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR); \
  362. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  363. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  364. MA_OUTW(clk_vin_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  365. }
  366. #define _GET_CLOCK_SOURCE_STATUS_clk_vin_root_(_ezchip_macro_read_value_) { \
  367. _ezchip_macro_read_value_=MA_INW(clk_vin_root_ctrl_REG_ADDR) >> 24; \
  368. _ezchip_macro_read_value_ &= 0x3;\
  369. }
  370. #define _ENABLE_CLOCK_clk_vout_root_ {}
  371. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_osc_aud_ { \
  372. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  373. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  374. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  375. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  376. }
  377. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll0_out_ { \
  378. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  379. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  380. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  381. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  382. }
  383. #define _SWITCH_CLOCK_clk_vout_root_SOURCE_clk_pll2_out_ { \
  384. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR); \
  385. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  386. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  387. MA_OUTW(clk_vout_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  388. }
  389. #define _GET_CLOCK_SOURCE_STATUS_clk_vout_root_(_ezchip_macro_read_value_) { \
  390. _ezchip_macro_read_value_=MA_INW(clk_vout_root_ctrl_REG_ADDR) >> 24; \
  391. _ezchip_macro_read_value_ &= 0x3;\
  392. }
  393. #define _ENABLE_CLOCK_clk_audio_root_ { \
  394. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  395. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  396. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  397. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  398. }
  399. #define _DISABLE_CLOCK_clk_audio_root_ { \
  400. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  401. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  402. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  403. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  404. }
  405. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
  406. _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR) >> 31; \
  407. _ezchip_macro_read_value_ &= 0x1;\
  408. }
  409. #define _DIVIDE_CLOCK_clk_audio_root_(div) { \
  410. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  411. _ezchip_macro_read_value_ &= ~(0xF); \
  412. _ezchip_macro_read_value_ |= (div&0xF); \
  413. MA_OUTW(clk_audio_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  414. }
  415. #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_root_(_ezchip_macro_read_value_) { \
  416. _ezchip_macro_read_value_=MA_INW(clk_audio_root_ctrl_REG_ADDR); \
  417. _ezchip_macro_read_value_ &= 0xf;\
  418. }
  419. #define _ENABLE_CLOCK_clk_cdechifi4_root_ {}
  420. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_osc_sys_ { \
  421. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  422. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  423. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  424. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  425. }
  426. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll1_out_ { \
  427. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  428. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  429. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  430. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  431. }
  432. #define _SWITCH_CLOCK_clk_cdechifi4_root_SOURCE_clk_pll2_out_ { \
  433. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR); \
  434. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  435. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  436. MA_OUTW(clk_cdechifi4_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  437. }
  438. #define _GET_CLOCK_SOURCE_STATUS_clk_cdechifi4_root_(_ezchip_macro_read_value_) { \
  439. _ezchip_macro_read_value_=MA_INW(clk_cdechifi4_root_ctrl_REG_ADDR) >> 24; \
  440. _ezchip_macro_read_value_ &= 0x3;\
  441. }
  442. #define _ENABLE_CLOCK_clk_cdec_root_ {}
  443. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_osc_sys_ { \
  444. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  445. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  446. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  447. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  448. }
  449. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll0_out_ { \
  450. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  451. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  452. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  453. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  454. }
  455. #define _SWITCH_CLOCK_clk_cdec_root_SOURCE_clk_pll1_out_ { \
  456. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR); \
  457. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  458. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  459. MA_OUTW(clk_cdec_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  460. }
  461. #define _GET_CLOCK_SOURCE_STATUS_clk_cdec_root_(_ezchip_macro_read_value_) { \
  462. _ezchip_macro_read_value_=MA_INW(clk_cdec_root_ctrl_REG_ADDR) >> 24; \
  463. _ezchip_macro_read_value_ &= 0x3;\
  464. }
  465. #define _ENABLE_CLOCK_clk_voutbus_root_ {}
  466. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_osc_aud_ { \
  467. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  468. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  469. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  470. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  471. }
  472. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll0_out_ { \
  473. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  474. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  475. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  476. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  477. }
  478. #define _SWITCH_CLOCK_clk_voutbus_root_SOURCE_clk_pll2_out_ { \
  479. uint32_t _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR); \
  480. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  481. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  482. MA_OUTW(clk_voutbus_root_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  483. }
  484. #define _GET_CLOCK_SOURCE_STATUS_clk_voutbus_root_(_ezchip_macro_read_value_) { \
  485. _ezchip_macro_read_value_=MA_INW(clk_voutbus_root_ctrl_REG_ADDR) >> 24; \
  486. _ezchip_macro_read_value_ &= 0x3;\
  487. }
  488. #define _ENABLE_CLOCK_clk_cpunbus_root_div_ {}
  489. #define _DIVIDE_CLOCK_clk_cpunbus_root_div_(div) { \
  490. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
  491. _ezchip_macro_read_value_ &= ~(0x3); \
  492. _ezchip_macro_read_value_ |= (div&0x3); \
  493. MA_OUTW(clk_cpunbus_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  494. }
  495. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpunbus_root_div_(_ezchip_macro_read_value_) { \
  496. _ezchip_macro_read_value_=MA_INW(clk_cpunbus_root_div_ctrl_REG_ADDR); \
  497. _ezchip_macro_read_value_ &= 0x3;\
  498. }
  499. #define _ENABLE_CLOCK_clk_dsp_root_div_ {}
  500. #define _DIVIDE_CLOCK_clk_dsp_root_div_(div) { \
  501. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
  502. _ezchip_macro_read_value_ &= ~(0x7); \
  503. _ezchip_macro_read_value_ |= (div&0x7); \
  504. MA_OUTW(clk_dsp_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  505. }
  506. #define _GET_CLOCK_DIVIDE_STATUS_clk_dsp_root_div_(_ezchip_macro_read_value_) { \
  507. _ezchip_macro_read_value_=MA_INW(clk_dsp_root_div_ctrl_REG_ADDR); \
  508. _ezchip_macro_read_value_ &= 0x7;\
  509. }
  510. #define _ENABLE_CLOCK_clk_perh0_src_ {}
  511. #define _DIVIDE_CLOCK_clk_perh0_src_(div) { \
  512. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
  513. _ezchip_macro_read_value_ &= ~(0x7); \
  514. _ezchip_macro_read_value_ |= (div&0x7); \
  515. MA_OUTW(clk_perh0_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  516. }
  517. #define _GET_CLOCK_DIVIDE_STATUS_clk_perh0_src_(_ezchip_macro_read_value_) { \
  518. _ezchip_macro_read_value_=MA_INW(clk_perh0_src_ctrl_REG_ADDR); \
  519. _ezchip_macro_read_value_ &= 0x7;\
  520. }
  521. #define _ENABLE_CLOCK_clk_perh1_src_ {}
  522. #define _DIVIDE_CLOCK_clk_perh1_src_(div) { \
  523. uint32_t _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
  524. _ezchip_macro_read_value_ &= ~(0x7); \
  525. _ezchip_macro_read_value_ |= (div&0x7); \
  526. MA_OUTW(clk_perh1_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  527. }
  528. #define _GET_CLOCK_DIVIDE_STATUS_clk_perh1_src_(_ezchip_macro_read_value_) { \
  529. _ezchip_macro_read_value_=MA_INW(clk_perh1_src_ctrl_REG_ADDR); \
  530. _ezchip_macro_read_value_ &= 0x7;\
  531. }
  532. #define _ENABLE_CLOCK_clk_pll0_testout_ { \
  533. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  534. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  535. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  536. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  537. }
  538. #define _DISABLE_CLOCK_clk_pll0_testout_ { \
  539. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  540. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  541. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  542. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  543. }
  544. #define _GET_CLOCK_ENABLE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
  545. _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR) >> 31; \
  546. _ezchip_macro_read_value_ &= 0x1;\
  547. }
  548. #define _DIVIDE_CLOCK_clk_pll0_testout_(div) { \
  549. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  550. _ezchip_macro_read_value_ &= ~(0x1F); \
  551. _ezchip_macro_read_value_ |= (div&0x1F); \
  552. MA_OUTW(clk_pll0_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  553. }
  554. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll0_testout_(_ezchip_macro_read_value_) { \
  555. _ezchip_macro_read_value_=MA_INW(clk_pll0_testout_ctrl_REG_ADDR); \
  556. _ezchip_macro_read_value_ &= 0x1f;\
  557. }
  558. #define _ENABLE_CLOCK_clk_pll1_testout_ { \
  559. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  560. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  561. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  562. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  563. }
  564. #define _DISABLE_CLOCK_clk_pll1_testout_ { \
  565. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  566. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  567. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  568. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  569. }
  570. #define _GET_CLOCK_ENABLE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
  571. _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR) >> 31; \
  572. _ezchip_macro_read_value_ &= 0x1;\
  573. }
  574. #define _DIVIDE_CLOCK_clk_pll1_testout_(div) { \
  575. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  576. _ezchip_macro_read_value_ &= ~(0x1F); \
  577. _ezchip_macro_read_value_ |= (div&0x1F); \
  578. MA_OUTW(clk_pll1_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  579. }
  580. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll1_testout_(_ezchip_macro_read_value_) { \
  581. _ezchip_macro_read_value_=MA_INW(clk_pll1_testout_ctrl_REG_ADDR); \
  582. _ezchip_macro_read_value_ &= 0x1f;\
  583. }
  584. #define _ENABLE_CLOCK_clk_pll2_testout_ { \
  585. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  586. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  587. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  588. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  589. }
  590. #define _DISABLE_CLOCK_clk_pll2_testout_ { \
  591. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  592. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  593. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  594. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  595. }
  596. #define _GET_CLOCK_ENABLE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
  597. _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR) >> 31; \
  598. _ezchip_macro_read_value_ &= 0x1;\
  599. }
  600. #define _DIVIDE_CLOCK_clk_pll2_testout_(div) { \
  601. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  602. _ezchip_macro_read_value_ &= ~(0x1F); \
  603. _ezchip_macro_read_value_ |= (div&0x1F); \
  604. MA_OUTW(clk_pll2_testout_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  605. }
  606. #define _GET_CLOCK_DIVIDE_STATUS_clk_pll2_testout_(_ezchip_macro_read_value_) { \
  607. _ezchip_macro_read_value_=MA_INW(clk_pll2_testout_ctrl_REG_ADDR); \
  608. _ezchip_macro_read_value_ &= 0x1f;\
  609. }
  610. #define _ENABLE_CLOCK_clk_pll2_refclk_ {}
  611. #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_sys_ { \
  612. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
  613. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  614. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  615. MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  616. }
  617. #define _SWITCH_CLOCK_clk_pll2_refclk_SOURCE_clk_osc_aud_ { \
  618. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR); \
  619. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  620. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  621. MA_OUTW(clk_pll2_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  622. }
  623. #define _GET_CLOCK_SOURCE_STATUS_clk_pll2_refclk_(_ezchip_macro_read_value_) { \
  624. _ezchip_macro_read_value_=MA_INW(clk_pll2_refclk_ctrl_REG_ADDR) >> 24; \
  625. _ezchip_macro_read_value_ &= 0x1;\
  626. }
  627. #define _ENABLE_CLOCK_clk_cpu_core_ {}
  628. #define _DIVIDE_CLOCK_clk_cpu_core_(div) { \
  629. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
  630. _ezchip_macro_read_value_ &= ~(0xF); \
  631. _ezchip_macro_read_value_ |= (div&0xF); \
  632. MA_OUTW(clk_cpu_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  633. }
  634. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_core_(_ezchip_macro_read_value_) { \
  635. _ezchip_macro_read_value_=MA_INW(clk_cpu_core_ctrl_REG_ADDR); \
  636. _ezchip_macro_read_value_ &= 0xf;\
  637. }
  638. #define _ENABLE_CLOCK_clk_cpu_axi_ {}
  639. #define _DIVIDE_CLOCK_clk_cpu_axi_(div) { \
  640. uint32_t _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
  641. _ezchip_macro_read_value_ &= ~(0xF); \
  642. _ezchip_macro_read_value_ |= (div&0xF); \
  643. MA_OUTW(clk_cpu_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  644. }
  645. #define _GET_CLOCK_DIVIDE_STATUS_clk_cpu_axi_(_ezchip_macro_read_value_) { \
  646. _ezchip_macro_read_value_=MA_INW(clk_cpu_axi_ctrl_REG_ADDR); \
  647. _ezchip_macro_read_value_ &= 0xf;\
  648. }
  649. #define _ENABLE_CLOCK_clk_ahb_bus_ {}
  650. #define _DIVIDE_CLOCK_clk_ahb_bus_(div) { \
  651. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
  652. _ezchip_macro_read_value_ &= ~(0xF); \
  653. _ezchip_macro_read_value_ |= (div&0xF); \
  654. MA_OUTW(clk_ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  655. }
  656. #define _GET_CLOCK_DIVIDE_STATUS_clk_ahb_bus_(_ezchip_macro_read_value_) { \
  657. _ezchip_macro_read_value_=MA_INW(clk_ahb_bus_ctrl_REG_ADDR); \
  658. _ezchip_macro_read_value_ &= 0xf;\
  659. }
  660. #define _ENABLE_CLOCK_clk_apb1_bus_ {}
  661. #define _DIVIDE_CLOCK_clk_apb1_bus_(div) { \
  662. uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
  663. _ezchip_macro_read_value_ &= ~(0xF); \
  664. _ezchip_macro_read_value_ |= (div&0xF); \
  665. MA_OUTW(clk_apb1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  666. }
  667. #define _GET_CLOCK_DIVIDE_STATUS_clk_apb1_bus_(_ezchip_macro_read_value_) { \
  668. _ezchip_macro_read_value_=MA_INW(clk_apb1_bus_ctrl_REG_ADDR); \
  669. _ezchip_macro_read_value_ &= 0xf;\
  670. }
  671. #define _ENABLE_CLOCK_clk_apb2_bus_ {}
  672. #define _DIVIDE_CLOCK_clk_apb2_bus_(div) { \
  673. uint32_t _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
  674. _ezchip_macro_read_value_ &= ~(0xF); \
  675. _ezchip_macro_read_value_ |= (div&0xF); \
  676. MA_OUTW(clk_apb2_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  677. }
  678. #define _GET_CLOCK_DIVIDE_STATUS_clk_apb2_bus_(_ezchip_macro_read_value_) { \
  679. _ezchip_macro_read_value_=MA_INW(clk_apb2_bus_ctrl_REG_ADDR); \
  680. _ezchip_macro_read_value_ &= 0xf;\
  681. }
  682. #define _ENABLE_CLOCK_clk_dom3ahb_bus_ { \
  683. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
  684. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  685. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  686. MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  687. }
  688. #define _DISABLE_CLOCK_clk_dom3ahb_bus_ { \
  689. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR); \
  690. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  691. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  692. MA_OUTW(clk_dom3ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  693. }
  694. #define _GET_CLOCK_ENABLE_STATUS_clk_dom3ahb_bus_(_ezchip_macro_read_value_) { \
  695. _ezchip_macro_read_value_=MA_INW(clk_dom3ahb_bus_ctrl_REG_ADDR) >> 31; \
  696. _ezchip_macro_read_value_ &= 0x1;\
  697. }
  698. #define _ENABLE_CLOCK_clk_dom7ahb_bus_ { \
  699. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
  700. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  701. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  702. MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  703. }
  704. #define _DISABLE_CLOCK_clk_dom7ahb_bus_ { \
  705. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR); \
  706. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  707. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  708. MA_OUTW(clk_dom7ahb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  709. }
  710. #define _GET_CLOCK_ENABLE_STATUS_clk_dom7ahb_bus_(_ezchip_macro_read_value_) { \
  711. _ezchip_macro_read_value_=MA_INW(clk_dom7ahb_bus_ctrl_REG_ADDR) >> 31; \
  712. _ezchip_macro_read_value_ &= 0x1;\
  713. }
  714. #define _ENABLE_CLOCK_clk_u74_core0_ { \
  715. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
  716. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  717. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  718. MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  719. }
  720. #define _DISABLE_CLOCK_clk_u74_core0_ { \
  721. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR); \
  722. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  723. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  724. MA_OUTW(clk_u74_core0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  725. }
  726. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core0_(_ezchip_macro_read_value_) { \
  727. _ezchip_macro_read_value_=MA_INW(clk_u74_core0_ctrl_REG_ADDR) >> 31; \
  728. _ezchip_macro_read_value_ &= 0x1;\
  729. }
  730. #define _ENABLE_CLOCK_clk_u74_core1_ { \
  731. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  732. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  733. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  734. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  735. }
  736. #define _DISABLE_CLOCK_clk_u74_core1_ { \
  737. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  738. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  739. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  740. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  741. }
  742. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
  743. _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR) >> 31; \
  744. _ezchip_macro_read_value_ &= 0x1;\
  745. }
  746. #define _DIVIDE_CLOCK_clk_u74_core1_(div) { \
  747. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  748. _ezchip_macro_read_value_ &= ~(0xF); \
  749. _ezchip_macro_read_value_ |= (div&0xF); \
  750. MA_OUTW(clk_u74_core1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  751. }
  752. #define _GET_CLOCK_DIVIDE_STATUS_clk_u74_core1_(_ezchip_macro_read_value_) { \
  753. _ezchip_macro_read_value_=MA_INW(clk_u74_core1_ctrl_REG_ADDR); \
  754. _ezchip_macro_read_value_ &= 0xf;\
  755. }
  756. #define _ENABLE_CLOCK_clk_u74_axi_ { \
  757. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
  758. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  759. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  760. MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  761. }
  762. #define _DISABLE_CLOCK_clk_u74_axi_ { \
  763. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR); \
  764. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  765. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  766. MA_OUTW(clk_u74_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  767. }
  768. #define _GET_CLOCK_ENABLE_STATUS_clk_u74_axi_(_ezchip_macro_read_value_) { \
  769. _ezchip_macro_read_value_=MA_INW(clk_u74_axi_ctrl_REG_ADDR) >> 31; \
  770. _ezchip_macro_read_value_ &= 0x1;\
  771. }
  772. #define _ENABLE_CLOCK_clk_u74rtc_toggle_ { \
  773. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
  774. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  775. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  776. MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  777. }
  778. #define _DISABLE_CLOCK_clk_u74rtc_toggle_ { \
  779. uint32_t _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR); \
  780. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  781. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  782. MA_OUTW(clk_u74rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  783. }
  784. #define _GET_CLOCK_ENABLE_STATUS_clk_u74rtc_toggle_(_ezchip_macro_read_value_) { \
  785. _ezchip_macro_read_value_=MA_INW(clk_u74rtc_toggle_ctrl_REG_ADDR) >> 31; \
  786. _ezchip_macro_read_value_ &= 0x1;\
  787. }
  788. #define _ENABLE_CLOCK_clk_sgdma2p_axi_ { \
  789. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
  790. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  791. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  792. MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  793. }
  794. #define _DISABLE_CLOCK_clk_sgdma2p_axi_ { \
  795. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR); \
  796. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  797. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  798. MA_OUTW(clk_sgdma2p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  799. }
  800. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_axi_(_ezchip_macro_read_value_) { \
  801. _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_axi_ctrl_REG_ADDR) >> 31; \
  802. _ezchip_macro_read_value_ &= 0x1;\
  803. }
  804. #define _ENABLE_CLOCK_clk_dma2pnoc_axi_ { \
  805. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
  806. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  807. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  808. MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  809. }
  810. #define _DISABLE_CLOCK_clk_dma2pnoc_axi_ { \
  811. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR); \
  812. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  813. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  814. MA_OUTW(clk_dma2pnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  815. }
  816. #define _GET_CLOCK_ENABLE_STATUS_clk_dma2pnoc_axi_(_ezchip_macro_read_value_) { \
  817. _ezchip_macro_read_value_=MA_INW(clk_dma2pnoc_axi_ctrl_REG_ADDR) >> 31; \
  818. _ezchip_macro_read_value_ &= 0x1;\
  819. }
  820. #define _ENABLE_CLOCK_clk_sgdma2p_ahb_ { \
  821. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
  822. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  823. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  824. MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  825. }
  826. #define _DISABLE_CLOCK_clk_sgdma2p_ahb_ { \
  827. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR); \
  828. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  829. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  830. MA_OUTW(clk_sgdma2p_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  831. }
  832. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma2p_ahb_(_ezchip_macro_read_value_) { \
  833. _ezchip_macro_read_value_=MA_INW(clk_sgdma2p_ahb_ctrl_REG_ADDR) >> 31; \
  834. _ezchip_macro_read_value_ &= 0x1;\
  835. }
  836. #define _ENABLE_CLOCK_clk_dla_bus_ {}
  837. #define _DIVIDE_CLOCK_clk_dla_bus_(div) { \
  838. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
  839. _ezchip_macro_read_value_ &= ~(0x7); \
  840. _ezchip_macro_read_value_ |= (div&0x7); \
  841. MA_OUTW(clk_dla_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  842. }
  843. #define _GET_CLOCK_DIVIDE_STATUS_clk_dla_bus_(_ezchip_macro_read_value_) { \
  844. _ezchip_macro_read_value_=MA_INW(clk_dla_bus_ctrl_REG_ADDR); \
  845. _ezchip_macro_read_value_ &= 0x7;\
  846. }
  847. #define _ENABLE_CLOCK_clk_dla_axi_ { \
  848. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
  849. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  850. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  851. MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  852. }
  853. #define _DISABLE_CLOCK_clk_dla_axi_ { \
  854. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR); \
  855. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  856. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  857. MA_OUTW(clk_dla_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  858. }
  859. #define _GET_CLOCK_ENABLE_STATUS_clk_dla_axi_(_ezchip_macro_read_value_) { \
  860. _ezchip_macro_read_value_=MA_INW(clk_dla_axi_ctrl_REG_ADDR) >> 31; \
  861. _ezchip_macro_read_value_ &= 0x1;\
  862. }
  863. #define _ENABLE_CLOCK_clk_dlanoc_axi_ { \
  864. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
  865. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  866. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  867. MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  868. }
  869. #define _DISABLE_CLOCK_clk_dlanoc_axi_ { \
  870. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR); \
  871. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  872. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  873. MA_OUTW(clk_dlanoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  874. }
  875. #define _GET_CLOCK_ENABLE_STATUS_clk_dlanoc_axi_(_ezchip_macro_read_value_) { \
  876. _ezchip_macro_read_value_=MA_INW(clk_dlanoc_axi_ctrl_REG_ADDR) >> 31; \
  877. _ezchip_macro_read_value_ &= 0x1;\
  878. }
  879. #define _ENABLE_CLOCK_clk_dla_apb_ { \
  880. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
  881. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  882. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  883. MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  884. }
  885. #define _DISABLE_CLOCK_clk_dla_apb_ { \
  886. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR); \
  887. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  888. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  889. MA_OUTW(clk_dla_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  890. }
  891. #define _GET_CLOCK_ENABLE_STATUS_clk_dla_apb_(_ezchip_macro_read_value_) { \
  892. _ezchip_macro_read_value_=MA_INW(clk_dla_apb_ctrl_REG_ADDR) >> 31; \
  893. _ezchip_macro_read_value_ &= 0x1;\
  894. }
  895. #define _ENABLE_CLOCK_clk_vp6_core_ { \
  896. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  897. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  898. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  899. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  900. }
  901. #define _DISABLE_CLOCK_clk_vp6_core_ { \
  902. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  903. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  904. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  905. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  906. }
  907. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
  908. _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR) >> 31; \
  909. _ezchip_macro_read_value_ &= 0x1;\
  910. }
  911. #define _DIVIDE_CLOCK_clk_vp6_core_(div) { \
  912. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  913. _ezchip_macro_read_value_ &= ~(0x7); \
  914. _ezchip_macro_read_value_ |= (div&0x7); \
  915. MA_OUTW(clk_vp6_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  916. }
  917. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_core_(_ezchip_macro_read_value_) { \
  918. _ezchip_macro_read_value_=MA_INW(clk_vp6_core_ctrl_REG_ADDR); \
  919. _ezchip_macro_read_value_ &= 0x7;\
  920. }
  921. #define _ENABLE_CLOCK_clk_vp6bus_src_ {}
  922. #define _DIVIDE_CLOCK_clk_vp6bus_src_(div) { \
  923. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
  924. _ezchip_macro_read_value_ &= ~(0x7); \
  925. _ezchip_macro_read_value_ |= (div&0x7); \
  926. MA_OUTW(clk_vp6bus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  927. }
  928. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6bus_src_(_ezchip_macro_read_value_) { \
  929. _ezchip_macro_read_value_=MA_INW(clk_vp6bus_src_ctrl_REG_ADDR); \
  930. _ezchip_macro_read_value_ &= 0x7;\
  931. }
  932. #define _ENABLE_CLOCK_clk_vp6_axi_ { \
  933. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  934. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  935. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  936. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  937. }
  938. #define _DISABLE_CLOCK_clk_vp6_axi_ { \
  939. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  940. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  941. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  942. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  943. }
  944. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
  945. _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR) >> 31; \
  946. _ezchip_macro_read_value_ &= 0x1;\
  947. }
  948. #define _DIVIDE_CLOCK_clk_vp6_axi_(div) { \
  949. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  950. _ezchip_macro_read_value_ &= ~(0x7); \
  951. _ezchip_macro_read_value_ |= (div&0x7); \
  952. MA_OUTW(clk_vp6_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  953. }
  954. #define _GET_CLOCK_DIVIDE_STATUS_clk_vp6_axi_(_ezchip_macro_read_value_) { \
  955. _ezchip_macro_read_value_=MA_INW(clk_vp6_axi_ctrl_REG_ADDR); \
  956. _ezchip_macro_read_value_ &= 0x7;\
  957. }
  958. #define _ENABLE_CLOCK_clk_vcdecbus_src_ {}
  959. #define _DIVIDE_CLOCK_clk_vcdecbus_src_(div) { \
  960. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
  961. _ezchip_macro_read_value_ &= ~(0x7); \
  962. _ezchip_macro_read_value_ |= (div&0x7); \
  963. MA_OUTW(clk_vcdecbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  964. }
  965. #define _GET_CLOCK_DIVIDE_STATUS_clk_vcdecbus_src_(_ezchip_macro_read_value_) { \
  966. _ezchip_macro_read_value_=MA_INW(clk_vcdecbus_src_ctrl_REG_ADDR); \
  967. _ezchip_macro_read_value_ &= 0x7;\
  968. }
  969. #define _ENABLE_CLOCK_clk_vdec_bus_ {}
  970. #define _DIVIDE_CLOCK_clk_vdec_bus_(div) { \
  971. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
  972. _ezchip_macro_read_value_ &= ~(0xF); \
  973. _ezchip_macro_read_value_ |= (div&0xF); \
  974. MA_OUTW(clk_vdec_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  975. }
  976. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bus_(_ezchip_macro_read_value_) { \
  977. _ezchip_macro_read_value_=MA_INW(clk_vdec_bus_ctrl_REG_ADDR); \
  978. _ezchip_macro_read_value_ &= 0xf;\
  979. }
  980. #define _ENABLE_CLOCK_clk_vdec_axi_ { \
  981. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
  982. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  983. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  984. MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  985. }
  986. #define _DISABLE_CLOCK_clk_vdec_axi_ { \
  987. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR); \
  988. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  989. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  990. MA_OUTW(clk_vdec_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  991. }
  992. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_axi_(_ezchip_macro_read_value_) { \
  993. _ezchip_macro_read_value_=MA_INW(clk_vdec_axi_ctrl_REG_ADDR) >> 31; \
  994. _ezchip_macro_read_value_ &= 0x1;\
  995. }
  996. #define _ENABLE_CLOCK_clk_vdecbrg_mainclk_ { \
  997. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
  998. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  999. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1000. MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1001. }
  1002. #define _DISABLE_CLOCK_clk_vdecbrg_mainclk_ { \
  1003. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR); \
  1004. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1005. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1006. MA_OUTW(clk_vdecbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1007. }
  1008. #define _GET_CLOCK_ENABLE_STATUS_clk_vdecbrg_mainclk_(_ezchip_macro_read_value_) { \
  1009. _ezchip_macro_read_value_=MA_INW(clk_vdecbrg_mainclk_ctrl_REG_ADDR) >> 31; \
  1010. _ezchip_macro_read_value_ &= 0x1;\
  1011. }
  1012. #define _ENABLE_CLOCK_clk_vdec_bclk_ { \
  1013. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1014. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1015. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1016. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1017. }
  1018. #define _DISABLE_CLOCK_clk_vdec_bclk_ { \
  1019. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1020. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1021. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1022. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1023. }
  1024. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
  1025. _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR) >> 31; \
  1026. _ezchip_macro_read_value_ &= 0x1;\
  1027. }
  1028. #define _DIVIDE_CLOCK_clk_vdec_bclk_(div) { \
  1029. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1030. _ezchip_macro_read_value_ &= ~(0xF); \
  1031. _ezchip_macro_read_value_ |= (div&0xF); \
  1032. MA_OUTW(clk_vdec_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1033. }
  1034. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_bclk_(_ezchip_macro_read_value_) { \
  1035. _ezchip_macro_read_value_=MA_INW(clk_vdec_bclk_ctrl_REG_ADDR); \
  1036. _ezchip_macro_read_value_ &= 0xf;\
  1037. }
  1038. #define _ENABLE_CLOCK_clk_vdec_cclk_ { \
  1039. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1040. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1041. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1042. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1043. }
  1044. #define _DISABLE_CLOCK_clk_vdec_cclk_ { \
  1045. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1046. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1047. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1048. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1049. }
  1050. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
  1051. _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR) >> 31; \
  1052. _ezchip_macro_read_value_ &= 0x1;\
  1053. }
  1054. #define _DIVIDE_CLOCK_clk_vdec_cclk_(div) { \
  1055. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1056. _ezchip_macro_read_value_ &= ~(0xF); \
  1057. _ezchip_macro_read_value_ |= (div&0xF); \
  1058. MA_OUTW(clk_vdec_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1059. }
  1060. #define _GET_CLOCK_DIVIDE_STATUS_clk_vdec_cclk_(_ezchip_macro_read_value_) { \
  1061. _ezchip_macro_read_value_=MA_INW(clk_vdec_cclk_ctrl_REG_ADDR); \
  1062. _ezchip_macro_read_value_ &= 0xf;\
  1063. }
  1064. #define _ENABLE_CLOCK_clk_vdec_apb_ { \
  1065. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
  1066. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1067. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1068. MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1069. }
  1070. #define _DISABLE_CLOCK_clk_vdec_apb_ { \
  1071. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR); \
  1072. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1073. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1074. MA_OUTW(clk_vdec_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1075. }
  1076. #define _GET_CLOCK_ENABLE_STATUS_clk_vdec_apb_(_ezchip_macro_read_value_) { \
  1077. _ezchip_macro_read_value_=MA_INW(clk_vdec_apb_ctrl_REG_ADDR) >> 31; \
  1078. _ezchip_macro_read_value_ &= 0x1;\
  1079. }
  1080. #define _ENABLE_CLOCK_clk_jpeg_axi_ { \
  1081. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1082. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1083. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1084. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1085. }
  1086. #define _DISABLE_CLOCK_clk_jpeg_axi_ { \
  1087. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1088. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1089. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1090. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1091. }
  1092. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
  1093. _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR) >> 31; \
  1094. _ezchip_macro_read_value_ &= 0x1;\
  1095. }
  1096. #define _DIVIDE_CLOCK_clk_jpeg_axi_(div) { \
  1097. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1098. _ezchip_macro_read_value_ &= ~(0xF); \
  1099. _ezchip_macro_read_value_ |= (div&0xF); \
  1100. MA_OUTW(clk_jpeg_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1101. }
  1102. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_axi_(_ezchip_macro_read_value_) { \
  1103. _ezchip_macro_read_value_=MA_INW(clk_jpeg_axi_ctrl_REG_ADDR); \
  1104. _ezchip_macro_read_value_ &= 0xf;\
  1105. }
  1106. #define _ENABLE_CLOCK_clk_jpeg_cclk_ { \
  1107. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1108. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1109. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1110. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1111. }
  1112. #define _DISABLE_CLOCK_clk_jpeg_cclk_ { \
  1113. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1114. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1115. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1116. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1117. }
  1118. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
  1119. _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR) >> 31; \
  1120. _ezchip_macro_read_value_ &= 0x1;\
  1121. }
  1122. #define _DIVIDE_CLOCK_clk_jpeg_cclk_(div) { \
  1123. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1124. _ezchip_macro_read_value_ &= ~(0xF); \
  1125. _ezchip_macro_read_value_ |= (div&0xF); \
  1126. MA_OUTW(clk_jpeg_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1127. }
  1128. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpeg_cclk_(_ezchip_macro_read_value_) { \
  1129. _ezchip_macro_read_value_=MA_INW(clk_jpeg_cclk_ctrl_REG_ADDR); \
  1130. _ezchip_macro_read_value_ &= 0xf;\
  1131. }
  1132. #define _ENABLE_CLOCK_clk_jpeg_apb_ { \
  1133. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
  1134. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1135. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1136. MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1137. }
  1138. #define _DISABLE_CLOCK_clk_jpeg_apb_ { \
  1139. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR); \
  1140. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1141. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1142. MA_OUTW(clk_jpeg_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1143. }
  1144. #define _GET_CLOCK_ENABLE_STATUS_clk_jpeg_apb_(_ezchip_macro_read_value_) { \
  1145. _ezchip_macro_read_value_=MA_INW(clk_jpeg_apb_ctrl_REG_ADDR) >> 31; \
  1146. _ezchip_macro_read_value_ &= 0x1;\
  1147. }
  1148. #define _ENABLE_CLOCK_clk_gc300_2x_ { \
  1149. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1150. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1151. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1152. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1153. }
  1154. #define _DISABLE_CLOCK_clk_gc300_2x_ { \
  1155. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1156. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1157. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1158. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1159. }
  1160. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
  1161. _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR) >> 31; \
  1162. _ezchip_macro_read_value_ &= 0x1;\
  1163. }
  1164. #define _DIVIDE_CLOCK_clk_gc300_2x_(div) { \
  1165. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1166. _ezchip_macro_read_value_ &= ~(0xF); \
  1167. _ezchip_macro_read_value_ |= (div&0xF); \
  1168. MA_OUTW(clk_gc300_2x_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1169. }
  1170. #define _GET_CLOCK_DIVIDE_STATUS_clk_gc300_2x_(_ezchip_macro_read_value_) { \
  1171. _ezchip_macro_read_value_=MA_INW(clk_gc300_2x_ctrl_REG_ADDR); \
  1172. _ezchip_macro_read_value_ &= 0xf;\
  1173. }
  1174. #define _ENABLE_CLOCK_clk_gc300_ahb_ { \
  1175. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
  1176. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1177. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1178. MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1179. }
  1180. #define _DISABLE_CLOCK_clk_gc300_ahb_ { \
  1181. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR); \
  1182. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1183. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1184. MA_OUTW(clk_gc300_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1185. }
  1186. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_ahb_(_ezchip_macro_read_value_) { \
  1187. _ezchip_macro_read_value_=MA_INW(clk_gc300_ahb_ctrl_REG_ADDR) >> 31; \
  1188. _ezchip_macro_read_value_ &= 0x1;\
  1189. }
  1190. #define _ENABLE_CLOCK_clk_jpcgc300_axibus_ {}
  1191. #define _DIVIDE_CLOCK_clk_jpcgc300_axibus_(div) { \
  1192. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
  1193. _ezchip_macro_read_value_ &= ~(0xF); \
  1194. _ezchip_macro_read_value_ |= (div&0xF); \
  1195. MA_OUTW(clk_jpcgc300_axibus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1196. }
  1197. #define _GET_CLOCK_DIVIDE_STATUS_clk_jpcgc300_axibus_(_ezchip_macro_read_value_) { \
  1198. _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_axibus_ctrl_REG_ADDR); \
  1199. _ezchip_macro_read_value_ &= 0xf;\
  1200. }
  1201. #define _ENABLE_CLOCK_clk_gc300_axi_ { \
  1202. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
  1203. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1204. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1205. MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1206. }
  1207. #define _DISABLE_CLOCK_clk_gc300_axi_ { \
  1208. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR); \
  1209. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1210. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1211. MA_OUTW(clk_gc300_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1212. }
  1213. #define _GET_CLOCK_ENABLE_STATUS_clk_gc300_axi_(_ezchip_macro_read_value_) { \
  1214. _ezchip_macro_read_value_=MA_INW(clk_gc300_axi_ctrl_REG_ADDR) >> 31; \
  1215. _ezchip_macro_read_value_ &= 0x1;\
  1216. }
  1217. #define _ENABLE_CLOCK_clk_jpcgc300_mainclk_ { \
  1218. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
  1219. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1220. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1221. MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1222. }
  1223. #define _DISABLE_CLOCK_clk_jpcgc300_mainclk_ { \
  1224. uint32_t _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR); \
  1225. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1226. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1227. MA_OUTW(clk_jpcgc300_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1228. }
  1229. #define _GET_CLOCK_ENABLE_STATUS_clk_jpcgc300_mainclk_(_ezchip_macro_read_value_) { \
  1230. _ezchip_macro_read_value_=MA_INW(clk_jpcgc300_mainclk_ctrl_REG_ADDR) >> 31; \
  1231. _ezchip_macro_read_value_ &= 0x1;\
  1232. }
  1233. #define _ENABLE_CLOCK_clk_venc_bus_ {}
  1234. #define _DIVIDE_CLOCK_clk_venc_bus_(div) { \
  1235. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
  1236. _ezchip_macro_read_value_ &= ~(0xF); \
  1237. _ezchip_macro_read_value_ |= (div&0xF); \
  1238. MA_OUTW(clk_venc_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1239. }
  1240. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bus_(_ezchip_macro_read_value_) { \
  1241. _ezchip_macro_read_value_=MA_INW(clk_venc_bus_ctrl_REG_ADDR); \
  1242. _ezchip_macro_read_value_ &= 0xf;\
  1243. }
  1244. #define _ENABLE_CLOCK_clk_venc_axi_ { \
  1245. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
  1246. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1247. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1248. MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1249. }
  1250. #define _DISABLE_CLOCK_clk_venc_axi_ { \
  1251. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR); \
  1252. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1253. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1254. MA_OUTW(clk_venc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1255. }
  1256. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_axi_(_ezchip_macro_read_value_) { \
  1257. _ezchip_macro_read_value_=MA_INW(clk_venc_axi_ctrl_REG_ADDR) >> 31; \
  1258. _ezchip_macro_read_value_ &= 0x1;\
  1259. }
  1260. #define _ENABLE_CLOCK_clk_vencbrg_mainclk_ { \
  1261. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
  1262. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1263. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1264. MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1265. }
  1266. #define _DISABLE_CLOCK_clk_vencbrg_mainclk_ { \
  1267. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR); \
  1268. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1269. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1270. MA_OUTW(clk_vencbrg_mainclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1271. }
  1272. #define _GET_CLOCK_ENABLE_STATUS_clk_vencbrg_mainclk_(_ezchip_macro_read_value_) { \
  1273. _ezchip_macro_read_value_=MA_INW(clk_vencbrg_mainclk_ctrl_REG_ADDR) >> 31; \
  1274. _ezchip_macro_read_value_ &= 0x1;\
  1275. }
  1276. #define _ENABLE_CLOCK_clk_venc_bclk_ { \
  1277. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1278. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1279. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1280. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1281. }
  1282. #define _DISABLE_CLOCK_clk_venc_bclk_ { \
  1283. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1284. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1285. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1286. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1287. }
  1288. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
  1289. _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR) >> 31; \
  1290. _ezchip_macro_read_value_ &= 0x1;\
  1291. }
  1292. #define _DIVIDE_CLOCK_clk_venc_bclk_(div) { \
  1293. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1294. _ezchip_macro_read_value_ &= ~(0xF); \
  1295. _ezchip_macro_read_value_ |= (div&0xF); \
  1296. MA_OUTW(clk_venc_bclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1297. }
  1298. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_bclk_(_ezchip_macro_read_value_) { \
  1299. _ezchip_macro_read_value_=MA_INW(clk_venc_bclk_ctrl_REG_ADDR); \
  1300. _ezchip_macro_read_value_ &= 0xf;\
  1301. }
  1302. #define _ENABLE_CLOCK_clk_venc_cclk_ { \
  1303. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1304. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1305. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1306. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1307. }
  1308. #define _DISABLE_CLOCK_clk_venc_cclk_ { \
  1309. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1310. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1311. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1312. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1313. }
  1314. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
  1315. _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR) >> 31; \
  1316. _ezchip_macro_read_value_ &= 0x1;\
  1317. }
  1318. #define _DIVIDE_CLOCK_clk_venc_cclk_(div) { \
  1319. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1320. _ezchip_macro_read_value_ &= ~(0xF); \
  1321. _ezchip_macro_read_value_ |= (div&0xF); \
  1322. MA_OUTW(clk_venc_cclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1323. }
  1324. #define _GET_CLOCK_DIVIDE_STATUS_clk_venc_cclk_(_ezchip_macro_read_value_) { \
  1325. _ezchip_macro_read_value_=MA_INW(clk_venc_cclk_ctrl_REG_ADDR); \
  1326. _ezchip_macro_read_value_ &= 0xf;\
  1327. }
  1328. #define _ENABLE_CLOCK_clk_venc_apb_ { \
  1329. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
  1330. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1331. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1332. MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1333. }
  1334. #define _DISABLE_CLOCK_clk_venc_apb_ { \
  1335. uint32_t _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR); \
  1336. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1337. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1338. MA_OUTW(clk_venc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1339. }
  1340. #define _GET_CLOCK_ENABLE_STATUS_clk_venc_apb_(_ezchip_macro_read_value_) { \
  1341. _ezchip_macro_read_value_=MA_INW(clk_venc_apb_ctrl_REG_ADDR) >> 31; \
  1342. _ezchip_macro_read_value_ &= 0x1;\
  1343. }
  1344. #define _ENABLE_CLOCK_clk_ddrpll_div2_ { \
  1345. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1346. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1347. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1348. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1349. }
  1350. #define _DISABLE_CLOCK_clk_ddrpll_div2_ { \
  1351. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1352. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1353. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1354. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1355. }
  1356. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
  1357. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR) >> 31; \
  1358. _ezchip_macro_read_value_ &= 0x1;\
  1359. }
  1360. #define _DIVIDE_CLOCK_clk_ddrpll_div2_(div) { \
  1361. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1362. _ezchip_macro_read_value_ &= ~(0x3); \
  1363. _ezchip_macro_read_value_ |= (div&0x3); \
  1364. MA_OUTW(clk_ddrpll_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1365. }
  1366. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div2_(_ezchip_macro_read_value_) { \
  1367. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div2_ctrl_REG_ADDR); \
  1368. _ezchip_macro_read_value_ &= 0x3;\
  1369. }
  1370. #define _ENABLE_CLOCK_clk_ddrpll_div4_ { \
  1371. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1372. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1373. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1374. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1375. }
  1376. #define _DISABLE_CLOCK_clk_ddrpll_div4_ { \
  1377. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1378. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1379. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1380. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1381. }
  1382. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
  1383. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR) >> 31; \
  1384. _ezchip_macro_read_value_ &= 0x1;\
  1385. }
  1386. #define _DIVIDE_CLOCK_clk_ddrpll_div4_(div) { \
  1387. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1388. _ezchip_macro_read_value_ &= ~(0x3); \
  1389. _ezchip_macro_read_value_ |= (div&0x3); \
  1390. MA_OUTW(clk_ddrpll_div4_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1391. }
  1392. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div4_(_ezchip_macro_read_value_) { \
  1393. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div4_ctrl_REG_ADDR); \
  1394. _ezchip_macro_read_value_ &= 0x3;\
  1395. }
  1396. #define _ENABLE_CLOCK_clk_ddrpll_div8_ { \
  1397. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1398. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1399. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1400. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1401. }
  1402. #define _DISABLE_CLOCK_clk_ddrpll_div8_ { \
  1403. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1404. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1405. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1406. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1407. }
  1408. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
  1409. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR) >> 31; \
  1410. _ezchip_macro_read_value_ &= 0x1;\
  1411. }
  1412. #define _DIVIDE_CLOCK_clk_ddrpll_div8_(div) { \
  1413. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1414. _ezchip_macro_read_value_ &= ~(0x3); \
  1415. _ezchip_macro_read_value_ |= (div&0x3); \
  1416. MA_OUTW(clk_ddrpll_div8_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1417. }
  1418. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrpll_div8_(_ezchip_macro_read_value_) { \
  1419. _ezchip_macro_read_value_=MA_INW(clk_ddrpll_div8_ctrl_REG_ADDR); \
  1420. _ezchip_macro_read_value_ &= 0x3;\
  1421. }
  1422. #define _ENABLE_CLOCK_clk_ddrosc_div2_ { \
  1423. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1424. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1425. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1426. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1427. }
  1428. #define _DISABLE_CLOCK_clk_ddrosc_div2_ { \
  1429. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1430. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1431. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1432. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1433. }
  1434. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
  1435. _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR) >> 31; \
  1436. _ezchip_macro_read_value_ &= 0x1;\
  1437. }
  1438. #define _DIVIDE_CLOCK_clk_ddrosc_div2_(div) { \
  1439. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1440. _ezchip_macro_read_value_ &= ~(0x3); \
  1441. _ezchip_macro_read_value_ |= (div&0x3); \
  1442. MA_OUTW(clk_ddrosc_div2_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1443. }
  1444. #define _GET_CLOCK_DIVIDE_STATUS_clk_ddrosc_div2_(_ezchip_macro_read_value_) { \
  1445. _ezchip_macro_read_value_=MA_INW(clk_ddrosc_div2_ctrl_REG_ADDR); \
  1446. _ezchip_macro_read_value_ &= 0x3;\
  1447. }
  1448. #define _ENABLE_CLOCK_clk_ddrc0_ { \
  1449. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1450. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1451. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1452. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1453. }
  1454. #define _DISABLE_CLOCK_clk_ddrc0_ { \
  1455. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1456. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1457. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1458. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1459. }
  1460. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
  1461. _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 31; \
  1462. _ezchip_macro_read_value_ &= 0x1;\
  1463. }
  1464. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_ { \
  1465. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1466. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1467. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  1468. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1469. }
  1470. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_ { \
  1471. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1472. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1473. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  1474. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1475. }
  1476. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_ { \
  1477. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1478. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1479. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  1480. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1481. }
  1482. #define _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_ { \
  1483. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR); \
  1484. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1485. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  1486. MA_OUTW(clk_ddrc0_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1487. }
  1488. #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc0_(_ezchip_macro_read_value_) { \
  1489. _ezchip_macro_read_value_=MA_INW(clk_ddrc0_ctrl_REG_ADDR) >> 24; \
  1490. _ezchip_macro_read_value_ &= 0x3;\
  1491. }
  1492. #define _ENABLE_CLOCK_clk_ddrc1_ { \
  1493. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1494. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1495. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1496. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1497. }
  1498. #define _DISABLE_CLOCK_clk_ddrc1_ { \
  1499. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1500. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1501. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1502. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1503. }
  1504. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
  1505. _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 31; \
  1506. _ezchip_macro_read_value_ &= 0x1;\
  1507. }
  1508. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_ { \
  1509. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1510. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1511. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  1512. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1513. }
  1514. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_ { \
  1515. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1516. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1517. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  1518. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1519. }
  1520. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_ { \
  1521. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1522. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1523. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  1524. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1525. }
  1526. #define _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_ { \
  1527. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR); \
  1528. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  1529. _ezchip_macro_read_value_ |= (0x3&0x3)<<24; \
  1530. MA_OUTW(clk_ddrc1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1531. }
  1532. #define _GET_CLOCK_SOURCE_STATUS_clk_ddrc1_(_ezchip_macro_read_value_) { \
  1533. _ezchip_macro_read_value_=MA_INW(clk_ddrc1_ctrl_REG_ADDR) >> 24; \
  1534. _ezchip_macro_read_value_ &= 0x3;\
  1535. }
  1536. #define _ENABLE_CLOCK_clk_ddrphy_apb_ { \
  1537. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
  1538. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1539. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1540. MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1541. }
  1542. #define _DISABLE_CLOCK_clk_ddrphy_apb_ { \
  1543. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR); \
  1544. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1545. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1546. MA_OUTW(clk_ddrphy_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1547. }
  1548. #define _GET_CLOCK_ENABLE_STATUS_clk_ddrphy_apb_(_ezchip_macro_read_value_) { \
  1549. _ezchip_macro_read_value_=MA_INW(clk_ddrphy_apb_ctrl_REG_ADDR) >> 31; \
  1550. _ezchip_macro_read_value_ &= 0x1;\
  1551. }
  1552. #define _ENABLE_CLOCK_clk_noc_rob_ {}
  1553. #define _DIVIDE_CLOCK_clk_noc_rob_(div) { \
  1554. uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
  1555. _ezchip_macro_read_value_ &= ~(0xF); \
  1556. _ezchip_macro_read_value_ |= (div&0xF); \
  1557. MA_OUTW(clk_noc_rob_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1558. }
  1559. #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_rob_(_ezchip_macro_read_value_) { \
  1560. _ezchip_macro_read_value_=MA_INW(clk_noc_rob_ctrl_REG_ADDR); \
  1561. _ezchip_macro_read_value_ &= 0xf;\
  1562. }
  1563. #define _ENABLE_CLOCK_clk_noc_cog_ {}
  1564. #define _DIVIDE_CLOCK_clk_noc_cog_(div) { \
  1565. uint32_t _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
  1566. _ezchip_macro_read_value_ &= ~(0xF); \
  1567. _ezchip_macro_read_value_ |= (div&0xF); \
  1568. MA_OUTW(clk_noc_cog_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1569. }
  1570. #define _GET_CLOCK_DIVIDE_STATUS_clk_noc_cog_(_ezchip_macro_read_value_) { \
  1571. _ezchip_macro_read_value_=MA_INW(clk_noc_cog_ctrl_REG_ADDR); \
  1572. _ezchip_macro_read_value_ &= 0xf;\
  1573. }
  1574. #define _ENABLE_CLOCK_clk_nne_ahb_ { \
  1575. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
  1576. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1577. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1578. MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1579. }
  1580. #define _DISABLE_CLOCK_clk_nne_ahb_ { \
  1581. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR); \
  1582. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1583. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1584. MA_OUTW(clk_nne_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1585. }
  1586. #define _GET_CLOCK_ENABLE_STATUS_clk_nne_ahb_(_ezchip_macro_read_value_) { \
  1587. _ezchip_macro_read_value_=MA_INW(clk_nne_ahb_ctrl_REG_ADDR) >> 31; \
  1588. _ezchip_macro_read_value_ &= 0x1;\
  1589. }
  1590. #define _ENABLE_CLOCK_clk_nnebus_src1_ {}
  1591. #define _DIVIDE_CLOCK_clk_nnebus_src1_(div) { \
  1592. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
  1593. _ezchip_macro_read_value_ &= ~(0x7); \
  1594. _ezchip_macro_read_value_ |= (div&0x7); \
  1595. MA_OUTW(clk_nnebus_src1_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1596. }
  1597. #define _GET_CLOCK_DIVIDE_STATUS_clk_nnebus_src1_(_ezchip_macro_read_value_) { \
  1598. _ezchip_macro_read_value_=MA_INW(clk_nnebus_src1_ctrl_REG_ADDR); \
  1599. _ezchip_macro_read_value_ &= 0x7;\
  1600. }
  1601. #define _ENABLE_CLOCK_clk_nne_bus_ {}
  1602. #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_cpu_axi_ { \
  1603. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
  1604. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1605. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  1606. MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1607. }
  1608. #define _SWITCH_CLOCK_clk_nne_bus_SOURCE_clk_nnebus_src1_ { \
  1609. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR); \
  1610. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1611. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  1612. MA_OUTW(clk_nne_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1613. }
  1614. #define _GET_CLOCK_SOURCE_STATUS_clk_nne_bus_(_ezchip_macro_read_value_) { \
  1615. _ezchip_macro_read_value_=MA_INW(clk_nne_bus_ctrl_REG_ADDR) >> 24; \
  1616. _ezchip_macro_read_value_ &= 0x1;\
  1617. }
  1618. #define _ENABLE_CLOCK_clk_nne_axi_ { \
  1619. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
  1620. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1621. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1622. MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1623. }
  1624. #define _DISABLE_CLOCK_clk_nne_axi_ { \
  1625. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR); \
  1626. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1627. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1628. MA_OUTW(clk_nne_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1629. }
  1630. #define _GET_CLOCK_ENABLE_STATUS_clk_nne_axi_(_ezchip_macro_read_value_) { \
  1631. _ezchip_macro_read_value_=MA_INW(clk_nne_axi_ctrl_REG_ADDR) >> 31; \
  1632. _ezchip_macro_read_value_ &= 0x1;\
  1633. }
  1634. #define _ENABLE_CLOCK_clk_nnenoc_axi_ { \
  1635. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
  1636. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1637. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1638. MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1639. }
  1640. #define _DISABLE_CLOCK_clk_nnenoc_axi_ { \
  1641. uint32_t _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR); \
  1642. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1643. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1644. MA_OUTW(clk_nnenoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1645. }
  1646. #define _GET_CLOCK_ENABLE_STATUS_clk_nnenoc_axi_(_ezchip_macro_read_value_) { \
  1647. _ezchip_macro_read_value_=MA_INW(clk_nnenoc_axi_ctrl_REG_ADDR) >> 31; \
  1648. _ezchip_macro_read_value_ &= 0x1;\
  1649. }
  1650. #define _ENABLE_CLOCK_clk_dlaslv_axi_ { \
  1651. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
  1652. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1653. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1654. MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1655. }
  1656. #define _DISABLE_CLOCK_clk_dlaslv_axi_ { \
  1657. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR); \
  1658. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1659. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1660. MA_OUTW(clk_dlaslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1661. }
  1662. #define _GET_CLOCK_ENABLE_STATUS_clk_dlaslv_axi_(_ezchip_macro_read_value_) { \
  1663. _ezchip_macro_read_value_=MA_INW(clk_dlaslv_axi_ctrl_REG_ADDR) >> 31; \
  1664. _ezchip_macro_read_value_ &= 0x1;\
  1665. }
  1666. #define _ENABLE_CLOCK_clk_dspx2c_axi_ { \
  1667. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
  1668. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1669. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1670. MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1671. }
  1672. #define _DISABLE_CLOCK_clk_dspx2c_axi_ { \
  1673. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR); \
  1674. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1675. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1676. MA_OUTW(clk_dspx2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1677. }
  1678. #define _GET_CLOCK_ENABLE_STATUS_clk_dspx2c_axi_(_ezchip_macro_read_value_) { \
  1679. _ezchip_macro_read_value_=MA_INW(clk_dspx2c_axi_ctrl_REG_ADDR) >> 31; \
  1680. _ezchip_macro_read_value_ &= 0x1;\
  1681. }
  1682. #define _ENABLE_CLOCK_clk_hifi4_src_ {}
  1683. #define _DIVIDE_CLOCK_clk_hifi4_src_(div) { \
  1684. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
  1685. _ezchip_macro_read_value_ &= ~(0x7); \
  1686. _ezchip_macro_read_value_ |= (div&0x7); \
  1687. MA_OUTW(clk_hifi4_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1688. }
  1689. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_src_(_ezchip_macro_read_value_) { \
  1690. _ezchip_macro_read_value_=MA_INW(clk_hifi4_src_ctrl_REG_ADDR); \
  1691. _ezchip_macro_read_value_ &= 0x7;\
  1692. }
  1693. #define _ENABLE_CLOCK_clk_hifi4_corefree_ {}
  1694. #define _DIVIDE_CLOCK_clk_hifi4_corefree_(div) { \
  1695. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
  1696. _ezchip_macro_read_value_ &= ~(0xF); \
  1697. _ezchip_macro_read_value_ |= (div&0xF); \
  1698. MA_OUTW(clk_hifi4_corefree_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1699. }
  1700. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_corefree_(_ezchip_macro_read_value_) { \
  1701. _ezchip_macro_read_value_=MA_INW(clk_hifi4_corefree_ctrl_REG_ADDR); \
  1702. _ezchip_macro_read_value_ &= 0xf;\
  1703. }
  1704. #define _ENABLE_CLOCK_clk_hifi4_core_ { \
  1705. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
  1706. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1707. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1708. MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1709. }
  1710. #define _DISABLE_CLOCK_clk_hifi4_core_ { \
  1711. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR); \
  1712. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1713. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1714. MA_OUTW(clk_hifi4_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1715. }
  1716. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_core_(_ezchip_macro_read_value_) { \
  1717. _ezchip_macro_read_value_=MA_INW(clk_hifi4_core_ctrl_REG_ADDR) >> 31; \
  1718. _ezchip_macro_read_value_ &= 0x1;\
  1719. }
  1720. #define _ENABLE_CLOCK_clk_hifi4_bus_ {}
  1721. #define _DIVIDE_CLOCK_clk_hifi4_bus_(div) { \
  1722. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
  1723. _ezchip_macro_read_value_ &= ~(0xF); \
  1724. _ezchip_macro_read_value_ |= (div&0xF); \
  1725. MA_OUTW(clk_hifi4_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1726. }
  1727. #define _GET_CLOCK_DIVIDE_STATUS_clk_hifi4_bus_(_ezchip_macro_read_value_) { \
  1728. _ezchip_macro_read_value_=MA_INW(clk_hifi4_bus_ctrl_REG_ADDR); \
  1729. _ezchip_macro_read_value_ &= 0xf;\
  1730. }
  1731. #define _ENABLE_CLOCK_clk_hifi4_axi_ { \
  1732. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
  1733. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1734. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1735. MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1736. }
  1737. #define _DISABLE_CLOCK_clk_hifi4_axi_ { \
  1738. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR); \
  1739. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1740. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1741. MA_OUTW(clk_hifi4_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1742. }
  1743. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4_axi_(_ezchip_macro_read_value_) { \
  1744. _ezchip_macro_read_value_=MA_INW(clk_hifi4_axi_ctrl_REG_ADDR) >> 31; \
  1745. _ezchip_macro_read_value_ &= 0x1;\
  1746. }
  1747. #define _ENABLE_CLOCK_clk_hifi4noc_axi_ { \
  1748. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
  1749. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1750. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1751. MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1752. }
  1753. #define _DISABLE_CLOCK_clk_hifi4noc_axi_ { \
  1754. uint32_t _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR); \
  1755. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1756. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1757. MA_OUTW(clk_hifi4noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1758. }
  1759. #define _GET_CLOCK_ENABLE_STATUS_clk_hifi4noc_axi_(_ezchip_macro_read_value_) { \
  1760. _ezchip_macro_read_value_=MA_INW(clk_hifi4noc_axi_ctrl_REG_ADDR) >> 31; \
  1761. _ezchip_macro_read_value_ &= 0x1;\
  1762. }
  1763. #define _ENABLE_CLOCK_clk_sgdma1p_bus_ {}
  1764. #define _DIVIDE_CLOCK_clk_sgdma1p_bus_(div) { \
  1765. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
  1766. _ezchip_macro_read_value_ &= ~(0xF); \
  1767. _ezchip_macro_read_value_ |= (div&0xF); \
  1768. MA_OUTW(clk_sgdma1p_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1769. }
  1770. #define _GET_CLOCK_DIVIDE_STATUS_clk_sgdma1p_bus_(_ezchip_macro_read_value_) { \
  1771. _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_bus_ctrl_REG_ADDR); \
  1772. _ezchip_macro_read_value_ &= 0xf;\
  1773. }
  1774. #define _ENABLE_CLOCK_clk_sgdma1p_axi_ { \
  1775. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
  1776. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1777. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1778. MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1779. }
  1780. #define _DISABLE_CLOCK_clk_sgdma1p_axi_ { \
  1781. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR); \
  1782. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1783. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1784. MA_OUTW(clk_sgdma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1785. }
  1786. #define _GET_CLOCK_ENABLE_STATUS_clk_sgdma1p_axi_(_ezchip_macro_read_value_) { \
  1787. _ezchip_macro_read_value_=MA_INW(clk_sgdma1p_axi_ctrl_REG_ADDR) >> 31; \
  1788. _ezchip_macro_read_value_ &= 0x1;\
  1789. }
  1790. #define _ENABLE_CLOCK_clk_dma1p_axi_ { \
  1791. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
  1792. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1793. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1794. MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1795. }
  1796. #define _DISABLE_CLOCK_clk_dma1p_axi_ { \
  1797. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR); \
  1798. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1799. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1800. MA_OUTW(clk_dma1p_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1801. }
  1802. #define _GET_CLOCK_ENABLE_STATUS_clk_dma1p_axi_(_ezchip_macro_read_value_) { \
  1803. _ezchip_macro_read_value_=MA_INW(clk_dma1p_axi_ctrl_REG_ADDR) >> 31; \
  1804. _ezchip_macro_read_value_ &= 0x1;\
  1805. }
  1806. #define _ENABLE_CLOCK_clk_x2c_axi_ { \
  1807. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1808. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1809. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1810. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1811. }
  1812. #define _DISABLE_CLOCK_clk_x2c_axi_ { \
  1813. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1814. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1815. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1816. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1817. }
  1818. #define _GET_CLOCK_ENABLE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
  1819. _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR) >> 31; \
  1820. _ezchip_macro_read_value_ &= 0x1;\
  1821. }
  1822. #define _DIVIDE_CLOCK_clk_x2c_axi_(div) { \
  1823. uint32_t _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1824. _ezchip_macro_read_value_ &= ~(0xF); \
  1825. _ezchip_macro_read_value_ |= (div&0xF); \
  1826. MA_OUTW(clk_x2c_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1827. }
  1828. #define _GET_CLOCK_DIVIDE_STATUS_clk_x2c_axi_(_ezchip_macro_read_value_) { \
  1829. _ezchip_macro_read_value_=MA_INW(clk_x2c_axi_ctrl_REG_ADDR); \
  1830. _ezchip_macro_read_value_ &= 0xf;\
  1831. }
  1832. #define _ENABLE_CLOCK_clk_usb_bus_ {}
  1833. #define _DIVIDE_CLOCK_clk_usb_bus_(div) { \
  1834. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
  1835. _ezchip_macro_read_value_ &= ~(0xF); \
  1836. _ezchip_macro_read_value_ |= (div&0xF); \
  1837. MA_OUTW(clk_usb_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1838. }
  1839. #define _GET_CLOCK_DIVIDE_STATUS_clk_usb_bus_(_ezchip_macro_read_value_) { \
  1840. _ezchip_macro_read_value_=MA_INW(clk_usb_bus_ctrl_REG_ADDR); \
  1841. _ezchip_macro_read_value_ &= 0xf;\
  1842. }
  1843. #define _ENABLE_CLOCK_clk_usb_axi_ { \
  1844. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
  1845. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1846. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1847. MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1848. }
  1849. #define _DISABLE_CLOCK_clk_usb_axi_ { \
  1850. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR); \
  1851. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1852. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1853. MA_OUTW(clk_usb_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1854. }
  1855. #define _GET_CLOCK_ENABLE_STATUS_clk_usb_axi_(_ezchip_macro_read_value_) { \
  1856. _ezchip_macro_read_value_=MA_INW(clk_usb_axi_ctrl_REG_ADDR) >> 31; \
  1857. _ezchip_macro_read_value_ &= 0x1;\
  1858. }
  1859. #define _ENABLE_CLOCK_clk_usbnoc_axi_ { \
  1860. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
  1861. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1862. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1863. MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1864. }
  1865. #define _DISABLE_CLOCK_clk_usbnoc_axi_ { \
  1866. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR); \
  1867. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1868. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1869. MA_OUTW(clk_usbnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1870. }
  1871. #define _GET_CLOCK_ENABLE_STATUS_clk_usbnoc_axi_(_ezchip_macro_read_value_) { \
  1872. _ezchip_macro_read_value_=MA_INW(clk_usbnoc_axi_ctrl_REG_ADDR) >> 31; \
  1873. _ezchip_macro_read_value_ &= 0x1;\
  1874. }
  1875. #define _ENABLE_CLOCK_clk_usbphy_rootdiv_ {}
  1876. #define _DIVIDE_CLOCK_clk_usbphy_rootdiv_(div) { \
  1877. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
  1878. _ezchip_macro_read_value_ &= ~(0x7); \
  1879. _ezchip_macro_read_value_ |= (div&0x7); \
  1880. MA_OUTW(clk_usbphy_rootdiv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1881. }
  1882. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_rootdiv_(_ezchip_macro_read_value_) { \
  1883. _ezchip_macro_read_value_=MA_INW(clk_usbphy_rootdiv_ctrl_REG_ADDR); \
  1884. _ezchip_macro_read_value_ &= 0x7;\
  1885. }
  1886. #define _ENABLE_CLOCK_clk_usbphy_125m_ { \
  1887. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1888. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1889. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1890. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1891. }
  1892. #define _DISABLE_CLOCK_clk_usbphy_125m_ { \
  1893. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1894. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1895. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1896. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1897. }
  1898. #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
  1899. _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR) >> 31; \
  1900. _ezchip_macro_read_value_ &= 0x1;\
  1901. }
  1902. #define _DIVIDE_CLOCK_clk_usbphy_125m_(div) { \
  1903. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1904. _ezchip_macro_read_value_ &= ~(0xF); \
  1905. _ezchip_macro_read_value_ |= (div&0xF); \
  1906. MA_OUTW(clk_usbphy_125m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1907. }
  1908. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_125m_(_ezchip_macro_read_value_) { \
  1909. _ezchip_macro_read_value_=MA_INW(clk_usbphy_125m_ctrl_REG_ADDR); \
  1910. _ezchip_macro_read_value_ &= 0xf;\
  1911. }
  1912. #define _ENABLE_CLOCK_clk_usbphy_plldiv25m_ { \
  1913. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1914. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1915. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1916. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1917. }
  1918. #define _DISABLE_CLOCK_clk_usbphy_plldiv25m_ { \
  1919. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1920. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1921. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1922. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1923. }
  1924. #define _GET_CLOCK_ENABLE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
  1925. _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR) >> 31; \
  1926. _ezchip_macro_read_value_ &= 0x1;\
  1927. }
  1928. #define _DIVIDE_CLOCK_clk_usbphy_plldiv25m_(div) { \
  1929. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1930. _ezchip_macro_read_value_ &= ~(0x3F); \
  1931. _ezchip_macro_read_value_ |= (div&0x3F); \
  1932. MA_OUTW(clk_usbphy_plldiv25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1933. }
  1934. #define _GET_CLOCK_DIVIDE_STATUS_clk_usbphy_plldiv25m_(_ezchip_macro_read_value_) { \
  1935. _ezchip_macro_read_value_=MA_INW(clk_usbphy_plldiv25m_ctrl_REG_ADDR); \
  1936. _ezchip_macro_read_value_ &= 0x3f;\
  1937. }
  1938. #define _ENABLE_CLOCK_clk_usbphy_25m_ {}
  1939. #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_osc_sys_ { \
  1940. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
  1941. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1942. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  1943. MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1944. }
  1945. #define _SWITCH_CLOCK_clk_usbphy_25m_SOURCE_clk_usbphy_plldiv25m_ { \
  1946. uint32_t _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR); \
  1947. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  1948. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  1949. MA_OUTW(clk_usbphy_25m_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1950. }
  1951. #define _GET_CLOCK_SOURCE_STATUS_clk_usbphy_25m_(_ezchip_macro_read_value_) { \
  1952. _ezchip_macro_read_value_=MA_INW(clk_usbphy_25m_ctrl_REG_ADDR) >> 24; \
  1953. _ezchip_macro_read_value_ &= 0x1;\
  1954. }
  1955. #define _ENABLE_CLOCK_clk_audio_div_ {}
  1956. #define _DIVIDE_CLOCK_clk_audio_div_(div) { \
  1957. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
  1958. _ezchip_macro_read_value_ &= ~(0x3FFFF); \
  1959. _ezchip_macro_read_value_ |= (div&0x3FFFF); \
  1960. MA_OUTW(clk_audio_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1961. }
  1962. #define _GET_CLOCK_DIVIDE_STATUS_clk_audio_div_(_ezchip_macro_read_value_) { \
  1963. _ezchip_macro_read_value_=MA_INW(clk_audio_div_ctrl_REG_ADDR); \
  1964. _ezchip_macro_read_value_ &= 0x3ffff;\
  1965. }
  1966. #define _ENABLE_CLOCK_clk_audio_src_ { \
  1967. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
  1968. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1969. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1970. MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1971. }
  1972. #define _DISABLE_CLOCK_clk_audio_src_ { \
  1973. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR); \
  1974. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1975. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1976. MA_OUTW(clk_audio_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1977. }
  1978. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_src_(_ezchip_macro_read_value_) { \
  1979. _ezchip_macro_read_value_=MA_INW(clk_audio_src_ctrl_REG_ADDR) >> 31; \
  1980. _ezchip_macro_read_value_ &= 0x1;\
  1981. }
  1982. #define _ENABLE_CLOCK_clk_audio_12288_ { \
  1983. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
  1984. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1985. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  1986. MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1987. }
  1988. #define _DISABLE_CLOCK_clk_audio_12288_ { \
  1989. uint32_t _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR); \
  1990. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  1991. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  1992. MA_OUTW(clk_audio_12288_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  1993. }
  1994. #define _GET_CLOCK_ENABLE_STATUS_clk_audio_12288_(_ezchip_macro_read_value_) { \
  1995. _ezchip_macro_read_value_=MA_INW(clk_audio_12288_ctrl_REG_ADDR) >> 31; \
  1996. _ezchip_macro_read_value_ &= 0x1;\
  1997. }
  1998. #define _ENABLE_CLOCK_clk_vin_src_ { \
  1999. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2000. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2001. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2002. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2003. }
  2004. #define _DISABLE_CLOCK_clk_vin_src_ { \
  2005. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2006. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2007. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2008. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2009. }
  2010. #define _GET_CLOCK_ENABLE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
  2011. _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR) >> 31; \
  2012. _ezchip_macro_read_value_ &= 0x1;\
  2013. }
  2014. #define _DIVIDE_CLOCK_clk_vin_src_(div) { \
  2015. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2016. _ezchip_macro_read_value_ &= ~(0x7); \
  2017. _ezchip_macro_read_value_ |= (div&0x7); \
  2018. MA_OUTW(clk_vin_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2019. }
  2020. #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_src_(_ezchip_macro_read_value_) { \
  2021. _ezchip_macro_read_value_=MA_INW(clk_vin_src_ctrl_REG_ADDR); \
  2022. _ezchip_macro_read_value_ &= 0x7;\
  2023. }
  2024. #define _ENABLE_CLOCK_clk_isp0_bus_ {}
  2025. #define _DIVIDE_CLOCK_clk_isp0_bus_(div) { \
  2026. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
  2027. _ezchip_macro_read_value_ &= ~(0xF); \
  2028. _ezchip_macro_read_value_ |= (div&0xF); \
  2029. MA_OUTW(clk_isp0_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2030. }
  2031. #define _GET_CLOCK_DIVIDE_STATUS_clk_isp0_bus_(_ezchip_macro_read_value_) { \
  2032. _ezchip_macro_read_value_=MA_INW(clk_isp0_bus_ctrl_REG_ADDR); \
  2033. _ezchip_macro_read_value_ &= 0xf;\
  2034. }
  2035. #define _ENABLE_CLOCK_clk_isp0_axi_ { \
  2036. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
  2037. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2038. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2039. MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2040. }
  2041. #define _DISABLE_CLOCK_clk_isp0_axi_ { \
  2042. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR); \
  2043. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2044. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2045. MA_OUTW(clk_isp0_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2046. }
  2047. #define _GET_CLOCK_ENABLE_STATUS_clk_isp0_axi_(_ezchip_macro_read_value_) { \
  2048. _ezchip_macro_read_value_=MA_INW(clk_isp0_axi_ctrl_REG_ADDR) >> 31; \
  2049. _ezchip_macro_read_value_ &= 0x1;\
  2050. }
  2051. #define _ENABLE_CLOCK_clk_isp0noc_axi_ { \
  2052. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
  2053. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2054. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2055. MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2056. }
  2057. #define _DISABLE_CLOCK_clk_isp0noc_axi_ { \
  2058. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR); \
  2059. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2060. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2061. MA_OUTW(clk_isp0noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2062. }
  2063. #define _GET_CLOCK_ENABLE_STATUS_clk_isp0noc_axi_(_ezchip_macro_read_value_) { \
  2064. _ezchip_macro_read_value_=MA_INW(clk_isp0noc_axi_ctrl_REG_ADDR) >> 31; \
  2065. _ezchip_macro_read_value_ &= 0x1;\
  2066. }
  2067. #define _ENABLE_CLOCK_clk_ispslv_axi_ { \
  2068. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
  2069. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2070. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2071. MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2072. }
  2073. #define _DISABLE_CLOCK_clk_ispslv_axi_ { \
  2074. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR); \
  2075. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2076. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2077. MA_OUTW(clk_ispslv_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2078. }
  2079. #define _GET_CLOCK_ENABLE_STATUS_clk_ispslv_axi_(_ezchip_macro_read_value_) { \
  2080. _ezchip_macro_read_value_=MA_INW(clk_ispslv_axi_ctrl_REG_ADDR) >> 31; \
  2081. _ezchip_macro_read_value_ &= 0x1;\
  2082. }
  2083. #define _ENABLE_CLOCK_clk_isp1_bus_ {}
  2084. #define _DIVIDE_CLOCK_clk_isp1_bus_(div) { \
  2085. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
  2086. _ezchip_macro_read_value_ &= ~(0xF); \
  2087. _ezchip_macro_read_value_ |= (div&0xF); \
  2088. MA_OUTW(clk_isp1_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2089. }
  2090. #define _GET_CLOCK_DIVIDE_STATUS_clk_isp1_bus_(_ezchip_macro_read_value_) { \
  2091. _ezchip_macro_read_value_=MA_INW(clk_isp1_bus_ctrl_REG_ADDR); \
  2092. _ezchip_macro_read_value_ &= 0xf;\
  2093. }
  2094. #define _ENABLE_CLOCK_clk_isp1_axi_ { \
  2095. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
  2096. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2097. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2098. MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2099. }
  2100. #define _DISABLE_CLOCK_clk_isp1_axi_ { \
  2101. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR); \
  2102. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2103. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2104. MA_OUTW(clk_isp1_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2105. }
  2106. #define _GET_CLOCK_ENABLE_STATUS_clk_isp1_axi_(_ezchip_macro_read_value_) { \
  2107. _ezchip_macro_read_value_=MA_INW(clk_isp1_axi_ctrl_REG_ADDR) >> 31; \
  2108. _ezchip_macro_read_value_ &= 0x1;\
  2109. }
  2110. #define _ENABLE_CLOCK_clk_isp1noc_axi_ { \
  2111. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
  2112. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2113. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2114. MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2115. }
  2116. #define _DISABLE_CLOCK_clk_isp1noc_axi_ { \
  2117. uint32_t _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR); \
  2118. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2119. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2120. MA_OUTW(clk_isp1noc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2121. }
  2122. #define _GET_CLOCK_ENABLE_STATUS_clk_isp1noc_axi_(_ezchip_macro_read_value_) { \
  2123. _ezchip_macro_read_value_=MA_INW(clk_isp1noc_axi_ctrl_REG_ADDR) >> 31; \
  2124. _ezchip_macro_read_value_ &= 0x1;\
  2125. }
  2126. #define _ENABLE_CLOCK_clk_vin_bus_ {}
  2127. #define _DIVIDE_CLOCK_clk_vin_bus_(div) { \
  2128. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
  2129. _ezchip_macro_read_value_ &= ~(0xF); \
  2130. _ezchip_macro_read_value_ |= (div&0xF); \
  2131. MA_OUTW(clk_vin_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2132. }
  2133. #define _GET_CLOCK_DIVIDE_STATUS_clk_vin_bus_(_ezchip_macro_read_value_) { \
  2134. _ezchip_macro_read_value_=MA_INW(clk_vin_bus_ctrl_REG_ADDR); \
  2135. _ezchip_macro_read_value_ &= 0xf;\
  2136. }
  2137. #define _ENABLE_CLOCK_clk_vin_axi_ { \
  2138. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
  2139. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2140. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2141. MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2142. }
  2143. #define _DISABLE_CLOCK_clk_vin_axi_ { \
  2144. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR); \
  2145. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2146. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2147. MA_OUTW(clk_vin_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2148. }
  2149. #define _GET_CLOCK_ENABLE_STATUS_clk_vin_axi_(_ezchip_macro_read_value_) { \
  2150. _ezchip_macro_read_value_=MA_INW(clk_vin_axi_ctrl_REG_ADDR) >> 31; \
  2151. _ezchip_macro_read_value_ &= 0x1;\
  2152. }
  2153. #define _ENABLE_CLOCK_clk_vinnoc_axi_ { \
  2154. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
  2155. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2156. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2157. MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2158. }
  2159. #define _DISABLE_CLOCK_clk_vinnoc_axi_ { \
  2160. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR); \
  2161. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2162. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2163. MA_OUTW(clk_vinnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2164. }
  2165. #define _GET_CLOCK_ENABLE_STATUS_clk_vinnoc_axi_(_ezchip_macro_read_value_) { \
  2166. _ezchip_macro_read_value_=MA_INW(clk_vinnoc_axi_ctrl_REG_ADDR) >> 31; \
  2167. _ezchip_macro_read_value_ &= 0x1;\
  2168. }
  2169. #define _ENABLE_CLOCK_clk_vout_src_ { \
  2170. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2171. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2172. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2173. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2174. }
  2175. #define _DISABLE_CLOCK_clk_vout_src_ { \
  2176. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2177. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2178. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2179. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2180. }
  2181. #define _GET_CLOCK_ENABLE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
  2182. _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR) >> 31; \
  2183. _ezchip_macro_read_value_ &= 0x1;\
  2184. }
  2185. #define _DIVIDE_CLOCK_clk_vout_src_(div) { \
  2186. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2187. _ezchip_macro_read_value_ &= ~(0x7); \
  2188. _ezchip_macro_read_value_ |= (div&0x7); \
  2189. MA_OUTW(clk_vout_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2190. }
  2191. #define _GET_CLOCK_DIVIDE_STATUS_clk_vout_src_(_ezchip_macro_read_value_) { \
  2192. _ezchip_macro_read_value_=MA_INW(clk_vout_src_ctrl_REG_ADDR); \
  2193. _ezchip_macro_read_value_ &= 0x7;\
  2194. }
  2195. #define _ENABLE_CLOCK_clk_dispbus_src_ {}
  2196. #define _DIVIDE_CLOCK_clk_dispbus_src_(div) { \
  2197. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
  2198. _ezchip_macro_read_value_ &= ~(0x7); \
  2199. _ezchip_macro_read_value_ |= (div&0x7); \
  2200. MA_OUTW(clk_dispbus_src_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2201. }
  2202. #define _GET_CLOCK_DIVIDE_STATUS_clk_dispbus_src_(_ezchip_macro_read_value_) { \
  2203. _ezchip_macro_read_value_=MA_INW(clk_dispbus_src_ctrl_REG_ADDR); \
  2204. _ezchip_macro_read_value_ &= 0x7;\
  2205. }
  2206. #define _ENABLE_CLOCK_clk_disp_bus_ {}
  2207. #define _DIVIDE_CLOCK_clk_disp_bus_(div) { \
  2208. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
  2209. _ezchip_macro_read_value_ &= ~(0x7); \
  2210. _ezchip_macro_read_value_ |= (div&0x7); \
  2211. MA_OUTW(clk_disp_bus_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2212. }
  2213. #define _GET_CLOCK_DIVIDE_STATUS_clk_disp_bus_(_ezchip_macro_read_value_) { \
  2214. _ezchip_macro_read_value_=MA_INW(clk_disp_bus_ctrl_REG_ADDR); \
  2215. _ezchip_macro_read_value_ &= 0x7;\
  2216. }
  2217. #define _ENABLE_CLOCK_clk_disp_axi_ { \
  2218. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
  2219. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2220. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2221. MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2222. }
  2223. #define _DISABLE_CLOCK_clk_disp_axi_ { \
  2224. uint32_t _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR); \
  2225. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2226. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2227. MA_OUTW(clk_disp_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2228. }
  2229. #define _GET_CLOCK_ENABLE_STATUS_clk_disp_axi_(_ezchip_macro_read_value_) { \
  2230. _ezchip_macro_read_value_=MA_INW(clk_disp_axi_ctrl_REG_ADDR) >> 31; \
  2231. _ezchip_macro_read_value_ &= 0x1;\
  2232. }
  2233. #define _ENABLE_CLOCK_clk_dispnoc_axi_ { \
  2234. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
  2235. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2236. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2237. MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2238. }
  2239. #define _DISABLE_CLOCK_clk_dispnoc_axi_ { \
  2240. uint32_t _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR); \
  2241. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2242. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2243. MA_OUTW(clk_dispnoc_axi_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2244. }
  2245. #define _GET_CLOCK_ENABLE_STATUS_clk_dispnoc_axi_(_ezchip_macro_read_value_) { \
  2246. _ezchip_macro_read_value_=MA_INW(clk_dispnoc_axi_ctrl_REG_ADDR) >> 31; \
  2247. _ezchip_macro_read_value_ &= 0x1;\
  2248. }
  2249. #define _ENABLE_CLOCK_clk_sdio0_ahb_ { \
  2250. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
  2251. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2252. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2253. MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2254. }
  2255. #define _DISABLE_CLOCK_clk_sdio0_ahb_ { \
  2256. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR); \
  2257. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2258. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2259. MA_OUTW(clk_sdio0_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2260. }
  2261. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_ahb_(_ezchip_macro_read_value_) { \
  2262. _ezchip_macro_read_value_=MA_INW(clk_sdio0_ahb_ctrl_REG_ADDR) >> 31; \
  2263. _ezchip_macro_read_value_ &= 0x1;\
  2264. }
  2265. #define _ENABLE_CLOCK_clk_sdio0_cclkint_ { \
  2266. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2267. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2268. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2269. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2270. }
  2271. #define _DISABLE_CLOCK_clk_sdio0_cclkint_ { \
  2272. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2273. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2274. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2275. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2276. }
  2277. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
  2278. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR) >> 31; \
  2279. _ezchip_macro_read_value_ &= 0x1;\
  2280. }
  2281. #define _DIVIDE_CLOCK_clk_sdio0_cclkint_(div) { \
  2282. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2283. _ezchip_macro_read_value_ &= ~(0x1F); \
  2284. _ezchip_macro_read_value_ |= (div&0x1F); \
  2285. MA_OUTW(clk_sdio0_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2286. }
  2287. #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio0_cclkint_(_ezchip_macro_read_value_) { \
  2288. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_ctrl_REG_ADDR); \
  2289. _ezchip_macro_read_value_ &= 0x1f;\
  2290. }
  2291. #define _ENABLE_CLOCK_clk_sdio0_cclkint_inv_ {}
  2292. #define _SET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
  2293. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
  2294. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2295. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2296. MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2297. }
  2298. #define _UNSET_CLOCK_clk_sdio0_cclkint_inv_POLARITY_ { \
  2299. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR); \
  2300. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2301. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2302. MA_OUTW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2303. }
  2304. #define _GET_CLOCK_POLARITY_STATUS_clk_sdio0_cclkint_inv_(_ezchip_macro_read_value_) { \
  2305. _ezchip_macro_read_value_=MA_INW(clk_sdio0_cclkint_inv_ctrl_REG_ADDR) >> 30; \
  2306. _ezchip_macro_read_value_ &= 0x1;\
  2307. }
  2308. #define _ENABLE_CLOCK_clk_sdio1_ahb_ { \
  2309. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
  2310. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2311. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2312. MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2313. }
  2314. #define _DISABLE_CLOCK_clk_sdio1_ahb_ { \
  2315. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR); \
  2316. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2317. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2318. MA_OUTW(clk_sdio1_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2319. }
  2320. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_ahb_(_ezchip_macro_read_value_) { \
  2321. _ezchip_macro_read_value_=MA_INW(clk_sdio1_ahb_ctrl_REG_ADDR) >> 31; \
  2322. _ezchip_macro_read_value_ &= 0x1;\
  2323. }
  2324. #define _ENABLE_CLOCK_clk_sdio1_cclkint_ { \
  2325. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2326. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2327. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2328. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2329. }
  2330. #define _DISABLE_CLOCK_clk_sdio1_cclkint_ { \
  2331. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2332. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2333. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2334. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2335. }
  2336. #define _GET_CLOCK_ENABLE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
  2337. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR) >> 31; \
  2338. _ezchip_macro_read_value_ &= 0x1;\
  2339. }
  2340. #define _DIVIDE_CLOCK_clk_sdio1_cclkint_(div) { \
  2341. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2342. _ezchip_macro_read_value_ &= ~(0x1F); \
  2343. _ezchip_macro_read_value_ |= (div&0x1F); \
  2344. MA_OUTW(clk_sdio1_cclkint_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2345. }
  2346. #define _GET_CLOCK_DIVIDE_STATUS_clk_sdio1_cclkint_(_ezchip_macro_read_value_) { \
  2347. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_ctrl_REG_ADDR); \
  2348. _ezchip_macro_read_value_ &= 0x1f;\
  2349. }
  2350. #define _ENABLE_CLOCK_clk_sdio1_cclkint_inv_ {}
  2351. #define _SET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
  2352. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
  2353. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2354. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2355. MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2356. }
  2357. #define _UNSET_CLOCK_clk_sdio1_cclkint_inv_POLARITY_ { \
  2358. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR); \
  2359. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2360. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2361. MA_OUTW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2362. }
  2363. #define _GET_CLOCK_POLARITY_STATUS_clk_sdio1_cclkint_inv_(_ezchip_macro_read_value_) { \
  2364. _ezchip_macro_read_value_=MA_INW(clk_sdio1_cclkint_inv_ctrl_REG_ADDR) >> 30; \
  2365. _ezchip_macro_read_value_ &= 0x1;\
  2366. }
  2367. #define _ENABLE_CLOCK_clk_gmac_ahb_ { \
  2368. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
  2369. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2370. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2371. MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2372. }
  2373. #define _DISABLE_CLOCK_clk_gmac_ahb_ { \
  2374. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR); \
  2375. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2376. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2377. MA_OUTW(clk_gmac_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2378. }
  2379. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ahb_(_ezchip_macro_read_value_) { \
  2380. _ezchip_macro_read_value_=MA_INW(clk_gmac_ahb_ctrl_REG_ADDR) >> 31; \
  2381. _ezchip_macro_read_value_ &= 0x1;\
  2382. }
  2383. #define _ENABLE_CLOCK_clk_gmac_root_div_ {}
  2384. #define _DIVIDE_CLOCK_clk_gmac_root_div_(div) { \
  2385. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
  2386. _ezchip_macro_read_value_ &= ~(0xF); \
  2387. _ezchip_macro_read_value_ |= (div&0xF); \
  2388. MA_OUTW(clk_gmac_root_div_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2389. }
  2390. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_root_div_(_ezchip_macro_read_value_) { \
  2391. _ezchip_macro_read_value_=MA_INW(clk_gmac_root_div_ctrl_REG_ADDR); \
  2392. _ezchip_macro_read_value_ &= 0xf;\
  2393. }
  2394. #define _ENABLE_CLOCK_clk_gmac_ptp_refclk_ { \
  2395. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2396. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2397. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2398. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2399. }
  2400. #define _DISABLE_CLOCK_clk_gmac_ptp_refclk_ { \
  2401. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2402. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2403. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2404. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2405. }
  2406. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
  2407. _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR) >> 31; \
  2408. _ezchip_macro_read_value_ &= 0x1;\
  2409. }
  2410. #define _DIVIDE_CLOCK_clk_gmac_ptp_refclk_(div) { \
  2411. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2412. _ezchip_macro_read_value_ &= ~(0x1F); \
  2413. _ezchip_macro_read_value_ |= (div&0x1F); \
  2414. MA_OUTW(clk_gmac_ptp_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2415. }
  2416. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_ptp_refclk_(_ezchip_macro_read_value_) { \
  2417. _ezchip_macro_read_value_=MA_INW(clk_gmac_ptp_refclk_ctrl_REG_ADDR); \
  2418. _ezchip_macro_read_value_ &= 0x1f;\
  2419. }
  2420. #define _ENABLE_CLOCK_clk_gmac_gtxclk_ { \
  2421. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2422. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2423. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2424. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2425. }
  2426. #define _DISABLE_CLOCK_clk_gmac_gtxclk_ { \
  2427. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2428. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2429. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2430. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2431. }
  2432. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
  2433. _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR) >> 31; \
  2434. _ezchip_macro_read_value_ &= 0x1;\
  2435. }
  2436. #define _DIVIDE_CLOCK_clk_gmac_gtxclk_(div) { \
  2437. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2438. _ezchip_macro_read_value_ &= ~(0xFF); \
  2439. _ezchip_macro_read_value_ |= (div&0xFF); \
  2440. MA_OUTW(clk_gmac_gtxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2441. }
  2442. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_gtxclk_(_ezchip_macro_read_value_) { \
  2443. _ezchip_macro_read_value_=MA_INW(clk_gmac_gtxclk_ctrl_REG_ADDR); \
  2444. _ezchip_macro_read_value_ &= 0xff;\
  2445. }
  2446. #define _ENABLE_CLOCK_clk_gmac_rmii_txclk_ { \
  2447. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2448. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2449. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2450. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2451. }
  2452. #define _DISABLE_CLOCK_clk_gmac_rmii_txclk_ { \
  2453. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2454. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2455. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2456. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2457. }
  2458. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
  2459. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR) >> 31; \
  2460. _ezchip_macro_read_value_ &= 0x1;\
  2461. }
  2462. #define _DIVIDE_CLOCK_clk_gmac_rmii_txclk_(div) { \
  2463. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2464. _ezchip_macro_read_value_ &= ~(0xF); \
  2465. _ezchip_macro_read_value_ |= (div&0xF); \
  2466. MA_OUTW(clk_gmac_rmii_txclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2467. }
  2468. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_txclk_(_ezchip_macro_read_value_) { \
  2469. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_txclk_ctrl_REG_ADDR); \
  2470. _ezchip_macro_read_value_ &= 0xf;\
  2471. }
  2472. #define _ENABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
  2473. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2474. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2475. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2476. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2477. }
  2478. #define _DISABLE_CLOCK_clk_gmac_rmii_rxclk_ { \
  2479. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2480. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2481. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2482. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2483. }
  2484. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
  2485. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR) >> 31; \
  2486. _ezchip_macro_read_value_ &= 0x1;\
  2487. }
  2488. #define _DIVIDE_CLOCK_clk_gmac_rmii_rxclk_(div) { \
  2489. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2490. _ezchip_macro_read_value_ &= ~(0xF); \
  2491. _ezchip_macro_read_value_ |= (div&0xF); \
  2492. MA_OUTW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2493. }
  2494. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_rmii_rxclk_(_ezchip_macro_read_value_) { \
  2495. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_rxclk_ctrl_REG_ADDR); \
  2496. _ezchip_macro_read_value_ &= 0xf;\
  2497. }
  2498. #define _ENABLE_CLOCK_clk_gmac_tx_ {}
  2499. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_gtxclk_ { \
  2500. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2501. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2502. _ezchip_macro_read_value_ |= (0x0&0x3)<<24; \
  2503. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2504. }
  2505. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_mii_txclk_ { \
  2506. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2507. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2508. _ezchip_macro_read_value_ |= (0x1&0x3)<<24; \
  2509. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2510. }
  2511. #define _SWITCH_CLOCK_clk_gmac_tx_SOURCE_clk_gmac_rmii_txclk_ { \
  2512. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR); \
  2513. _ezchip_macro_read_value_ &= ~(0x3<<24); \
  2514. _ezchip_macro_read_value_ |= (0x2&0x3)<<24; \
  2515. MA_OUTW(clk_gmac_tx_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2516. }
  2517. #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_tx_(_ezchip_macro_read_value_) { \
  2518. _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_ctrl_REG_ADDR) >> 24; \
  2519. _ezchip_macro_read_value_ &= 0x3;\
  2520. }
  2521. #define _ENABLE_CLOCK_clk_gmac_tx_inv_ {}
  2522. #define _SET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
  2523. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
  2524. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2525. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2526. MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2527. }
  2528. #define _UNSET_CLOCK_clk_gmac_tx_inv_POLARITY_ { \
  2529. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR); \
  2530. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2531. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2532. MA_OUTW(clk_gmac_tx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2533. }
  2534. #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_tx_inv_(_ezchip_macro_read_value_) { \
  2535. _ezchip_macro_read_value_=MA_INW(clk_gmac_tx_inv_ctrl_REG_ADDR) >> 30; \
  2536. _ezchip_macro_read_value_ &= 0x1;\
  2537. }
  2538. #define _ENABLE_CLOCK_clk_gmac_rx_pre_ {}
  2539. #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_gr_mii_rxclk_ { \
  2540. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
  2541. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  2542. _ezchip_macro_read_value_ |= (0x0&0x1)<<24; \
  2543. MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2544. }
  2545. #define _SWITCH_CLOCK_clk_gmac_rx_pre_SOURCE_clk_gmac_rmii_rxclk_ { \
  2546. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR); \
  2547. _ezchip_macro_read_value_ &= ~(0x1<<24); \
  2548. _ezchip_macro_read_value_ |= (0x1&0x1)<<24; \
  2549. MA_OUTW(clk_gmac_rx_pre_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2550. }
  2551. #define _GET_CLOCK_SOURCE_STATUS_clk_gmac_rx_pre_(_ezchip_macro_read_value_) { \
  2552. _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_pre_ctrl_REG_ADDR) >> 24; \
  2553. _ezchip_macro_read_value_ &= 0x1;\
  2554. }
  2555. #define _ENABLE_CLOCK_clk_gmac_rx_inv_ {}
  2556. #define _SET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
  2557. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
  2558. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2559. _ezchip_macro_read_value_ |= (0x1&0x1)<<30; \
  2560. MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2561. }
  2562. #define _UNSET_CLOCK_clk_gmac_rx_inv_POLARITY_ { \
  2563. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR); \
  2564. _ezchip_macro_read_value_ &= ~(0x1<<30); \
  2565. _ezchip_macro_read_value_ |= (0x0&0x1)<<30; \
  2566. MA_OUTW(clk_gmac_rx_inv_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2567. }
  2568. #define _GET_CLOCK_POLARITY_STATUS_clk_gmac_rx_inv_(_ezchip_macro_read_value_) { \
  2569. _ezchip_macro_read_value_=MA_INW(clk_gmac_rx_inv_ctrl_REG_ADDR) >> 30; \
  2570. _ezchip_macro_read_value_ &= 0x1;\
  2571. }
  2572. #define _ENABLE_CLOCK_clk_gmac_rmii_ { \
  2573. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
  2574. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2575. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2576. MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2577. }
  2578. #define _DISABLE_CLOCK_clk_gmac_rmii_ { \
  2579. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR); \
  2580. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2581. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2582. MA_OUTW(clk_gmac_rmii_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2583. }
  2584. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_rmii_(_ezchip_macro_read_value_) { \
  2585. _ezchip_macro_read_value_=MA_INW(clk_gmac_rmii_ctrl_REG_ADDR) >> 31; \
  2586. _ezchip_macro_read_value_ &= 0x1;\
  2587. }
  2588. #define _ENABLE_CLOCK_clk_gmac_tophyref_ { \
  2589. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2590. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2591. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2592. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2593. }
  2594. #define _DISABLE_CLOCK_clk_gmac_tophyref_ { \
  2595. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2596. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2597. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2598. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2599. }
  2600. #define _GET_CLOCK_ENABLE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
  2601. _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR) >> 31; \
  2602. _ezchip_macro_read_value_ &= 0x1;\
  2603. }
  2604. #define _DIVIDE_CLOCK_clk_gmac_tophyref_(div) { \
  2605. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2606. _ezchip_macro_read_value_ &= ~(0x7F); \
  2607. _ezchip_macro_read_value_ |= (div&0x7F); \
  2608. MA_OUTW(clk_gmac_tophyref_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2609. }
  2610. #define _GET_CLOCK_DIVIDE_STATUS_clk_gmac_tophyref_(_ezchip_macro_read_value_) { \
  2611. _ezchip_macro_read_value_=MA_INW(clk_gmac_tophyref_ctrl_REG_ADDR); \
  2612. _ezchip_macro_read_value_ &= 0x7f;\
  2613. }
  2614. #define _ENABLE_CLOCK_clk_spi2ahb_ahb_ { \
  2615. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
  2616. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2617. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2618. MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2619. }
  2620. #define _DISABLE_CLOCK_clk_spi2ahb_ahb_ { \
  2621. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR); \
  2622. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2623. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2624. MA_OUTW(clk_spi2ahb_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2625. }
  2626. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_ahb_(_ezchip_macro_read_value_) { \
  2627. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_ahb_ctrl_REG_ADDR) >> 31; \
  2628. _ezchip_macro_read_value_ &= 0x1;\
  2629. }
  2630. #define _ENABLE_CLOCK_clk_spi2ahb_core_ { \
  2631. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2632. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2633. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2634. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2635. }
  2636. #define _DISABLE_CLOCK_clk_spi2ahb_core_ { \
  2637. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2638. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2639. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2640. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2641. }
  2642. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
  2643. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR) >> 31; \
  2644. _ezchip_macro_read_value_ &= 0x1;\
  2645. }
  2646. #define _DIVIDE_CLOCK_clk_spi2ahb_core_(div) { \
  2647. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2648. _ezchip_macro_read_value_ &= ~(0x1F); \
  2649. _ezchip_macro_read_value_ |= (div&0x1F); \
  2650. MA_OUTW(clk_spi2ahb_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2651. }
  2652. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2ahb_core_(_ezchip_macro_read_value_) { \
  2653. _ezchip_macro_read_value_=MA_INW(clk_spi2ahb_core_ctrl_REG_ADDR); \
  2654. _ezchip_macro_read_value_ &= 0x1f;\
  2655. }
  2656. #define _ENABLE_CLOCK_clk_ezmaster_ahb_ { \
  2657. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
  2658. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2659. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2660. MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2661. }
  2662. #define _DISABLE_CLOCK_clk_ezmaster_ahb_ { \
  2663. uint32_t _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR); \
  2664. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2665. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2666. MA_OUTW(clk_ezmaster_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2667. }
  2668. #define _GET_CLOCK_ENABLE_STATUS_clk_ezmaster_ahb_(_ezchip_macro_read_value_) { \
  2669. _ezchip_macro_read_value_=MA_INW(clk_ezmaster_ahb_ctrl_REG_ADDR) >> 31; \
  2670. _ezchip_macro_read_value_ &= 0x1;\
  2671. }
  2672. #define _ENABLE_CLOCK_clk_e24_ahb_ { \
  2673. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
  2674. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2675. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2676. MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2677. }
  2678. #define _DISABLE_CLOCK_clk_e24_ahb_ { \
  2679. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR); \
  2680. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2681. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2682. MA_OUTW(clk_e24_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2683. }
  2684. #define _GET_CLOCK_ENABLE_STATUS_clk_e24_ahb_(_ezchip_macro_read_value_) { \
  2685. _ezchip_macro_read_value_=MA_INW(clk_e24_ahb_ctrl_REG_ADDR) >> 31; \
  2686. _ezchip_macro_read_value_ &= 0x1;\
  2687. }
  2688. #define _ENABLE_CLOCK_clk_e24rtc_toggle_ { \
  2689. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
  2690. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2691. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2692. MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2693. }
  2694. #define _DISABLE_CLOCK_clk_e24rtc_toggle_ { \
  2695. uint32_t _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR); \
  2696. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2697. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2698. MA_OUTW(clk_e24rtc_toggle_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2699. }
  2700. #define _GET_CLOCK_ENABLE_STATUS_clk_e24rtc_toggle_(_ezchip_macro_read_value_) { \
  2701. _ezchip_macro_read_value_=MA_INW(clk_e24rtc_toggle_ctrl_REG_ADDR) >> 31; \
  2702. _ezchip_macro_read_value_ &= 0x1;\
  2703. }
  2704. #define _ENABLE_CLOCK_clk_qspi_ahb_ { \
  2705. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
  2706. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2707. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2708. MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2709. }
  2710. #define _DISABLE_CLOCK_clk_qspi_ahb_ { \
  2711. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR); \
  2712. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2713. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2714. MA_OUTW(clk_qspi_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2715. }
  2716. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_ahb_(_ezchip_macro_read_value_) { \
  2717. _ezchip_macro_read_value_=MA_INW(clk_qspi_ahb_ctrl_REG_ADDR) >> 31; \
  2718. _ezchip_macro_read_value_ &= 0x1;\
  2719. }
  2720. #define _ENABLE_CLOCK_clk_qspi_apb_ { \
  2721. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
  2722. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2723. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2724. MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2725. }
  2726. #define _DISABLE_CLOCK_clk_qspi_apb_ { \
  2727. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR); \
  2728. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2729. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2730. MA_OUTW(clk_qspi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2731. }
  2732. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_apb_(_ezchip_macro_read_value_) { \
  2733. _ezchip_macro_read_value_=MA_INW(clk_qspi_apb_ctrl_REG_ADDR) >> 31; \
  2734. _ezchip_macro_read_value_ &= 0x1;\
  2735. }
  2736. #define _ENABLE_CLOCK_clk_qspi_refclk_ { \
  2737. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2738. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2739. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2740. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2741. }
  2742. #define _DISABLE_CLOCK_clk_qspi_refclk_ { \
  2743. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2744. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2745. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2746. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2747. }
  2748. #define _GET_CLOCK_ENABLE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
  2749. _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR) >> 31; \
  2750. _ezchip_macro_read_value_ &= 0x1;\
  2751. }
  2752. #define _DIVIDE_CLOCK_clk_qspi_refclk_(div) { \
  2753. uint32_t _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2754. _ezchip_macro_read_value_ &= ~(0x1F); \
  2755. _ezchip_macro_read_value_ |= (div&0x1F); \
  2756. MA_OUTW(clk_qspi_refclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2757. }
  2758. #define _GET_CLOCK_DIVIDE_STATUS_clk_qspi_refclk_(_ezchip_macro_read_value_) { \
  2759. _ezchip_macro_read_value_=MA_INW(clk_qspi_refclk_ctrl_REG_ADDR); \
  2760. _ezchip_macro_read_value_ &= 0x1f;\
  2761. }
  2762. #define _ENABLE_CLOCK_clk_sec_ahb_ { \
  2763. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
  2764. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2765. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2766. MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2767. }
  2768. #define _DISABLE_CLOCK_clk_sec_ahb_ { \
  2769. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR); \
  2770. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2771. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2772. MA_OUTW(clk_sec_ahb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2773. }
  2774. #define _GET_CLOCK_ENABLE_STATUS_clk_sec_ahb_(_ezchip_macro_read_value_) { \
  2775. _ezchip_macro_read_value_=MA_INW(clk_sec_ahb_ctrl_REG_ADDR) >> 31; \
  2776. _ezchip_macro_read_value_ &= 0x1;\
  2777. }
  2778. #define _ENABLE_CLOCK_clk_aes_clk_ { \
  2779. uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
  2780. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2781. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2782. MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2783. }
  2784. #define _DISABLE_CLOCK_clk_aes_clk_ { \
  2785. uint32_t _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR); \
  2786. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2787. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2788. MA_OUTW(clk_aes_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2789. }
  2790. #define _GET_CLOCK_ENABLE_STATUS_clk_aes_clk_(_ezchip_macro_read_value_) { \
  2791. _ezchip_macro_read_value_=MA_INW(clk_aes_clk_ctrl_REG_ADDR) >> 31; \
  2792. _ezchip_macro_read_value_ &= 0x1;\
  2793. }
  2794. #define _ENABLE_CLOCK_clk_sha_clk_ { \
  2795. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
  2796. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2797. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2798. MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2799. }
  2800. #define _DISABLE_CLOCK_clk_sha_clk_ { \
  2801. uint32_t _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR); \
  2802. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2803. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2804. MA_OUTW(clk_sha_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2805. }
  2806. #define _GET_CLOCK_ENABLE_STATUS_clk_sha_clk_(_ezchip_macro_read_value_) { \
  2807. _ezchip_macro_read_value_=MA_INW(clk_sha_clk_ctrl_REG_ADDR) >> 31; \
  2808. _ezchip_macro_read_value_ &= 0x1;\
  2809. }
  2810. #define _ENABLE_CLOCK_clk_pka_clk_ { \
  2811. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
  2812. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2813. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2814. MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2815. }
  2816. #define _DISABLE_CLOCK_clk_pka_clk_ { \
  2817. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR); \
  2818. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2819. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2820. MA_OUTW(clk_pka_clk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2821. }
  2822. #define _GET_CLOCK_ENABLE_STATUS_clk_pka_clk_(_ezchip_macro_read_value_) { \
  2823. _ezchip_macro_read_value_=MA_INW(clk_pka_clk_ctrl_REG_ADDR) >> 31; \
  2824. _ezchip_macro_read_value_ &= 0x1;\
  2825. }
  2826. #define _ENABLE_CLOCK_clk_trng_apb_ { \
  2827. uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
  2828. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2829. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2830. MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2831. }
  2832. #define _DISABLE_CLOCK_clk_trng_apb_ { \
  2833. uint32_t _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR); \
  2834. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2835. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2836. MA_OUTW(clk_trng_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2837. }
  2838. #define _GET_CLOCK_ENABLE_STATUS_clk_trng_apb_(_ezchip_macro_read_value_) { \
  2839. _ezchip_macro_read_value_=MA_INW(clk_trng_apb_ctrl_REG_ADDR) >> 31; \
  2840. _ezchip_macro_read_value_ &= 0x1;\
  2841. }
  2842. #define _ENABLE_CLOCK_clk_otp_apb_ { \
  2843. uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
  2844. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2845. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2846. MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2847. }
  2848. #define _DISABLE_CLOCK_clk_otp_apb_ { \
  2849. uint32_t _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR); \
  2850. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2851. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2852. MA_OUTW(clk_otp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2853. }
  2854. #define _GET_CLOCK_ENABLE_STATUS_clk_otp_apb_(_ezchip_macro_read_value_) { \
  2855. _ezchip_macro_read_value_=MA_INW(clk_otp_apb_ctrl_REG_ADDR) >> 31; \
  2856. _ezchip_macro_read_value_ &= 0x1;\
  2857. }
  2858. #define _ENABLE_CLOCK_clk_uart0_apb_ { \
  2859. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
  2860. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2861. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2862. MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2863. }
  2864. #define _DISABLE_CLOCK_clk_uart0_apb_ { \
  2865. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR); \
  2866. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2867. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2868. MA_OUTW(clk_uart0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2869. }
  2870. #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_apb_(_ezchip_macro_read_value_) { \
  2871. _ezchip_macro_read_value_=MA_INW(clk_uart0_apb_ctrl_REG_ADDR) >> 31; \
  2872. _ezchip_macro_read_value_ &= 0x1;\
  2873. }
  2874. #define _ENABLE_CLOCK_clk_uart0_core_ { \
  2875. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2876. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2877. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2878. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2879. }
  2880. #define _DISABLE_CLOCK_clk_uart0_core_ { \
  2881. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2882. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2883. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2884. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2885. }
  2886. #define _GET_CLOCK_ENABLE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
  2887. _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR) >> 31; \
  2888. _ezchip_macro_read_value_ &= 0x1;\
  2889. }
  2890. #define _DIVIDE_CLOCK_clk_uart0_core_(div) { \
  2891. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2892. _ezchip_macro_read_value_ &= ~(0x3F); \
  2893. _ezchip_macro_read_value_ |= (div&0x3F); \
  2894. MA_OUTW(clk_uart0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2895. }
  2896. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart0_core_(_ezchip_macro_read_value_) { \
  2897. _ezchip_macro_read_value_=MA_INW(clk_uart0_core_ctrl_REG_ADDR); \
  2898. _ezchip_macro_read_value_ &= 0x3f;\
  2899. }
  2900. #define _ENABLE_CLOCK_clk_uart1_apb_ { \
  2901. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
  2902. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2903. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2904. MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2905. }
  2906. #define _DISABLE_CLOCK_clk_uart1_apb_ { \
  2907. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR); \
  2908. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2909. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2910. MA_OUTW(clk_uart1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2911. }
  2912. #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_apb_(_ezchip_macro_read_value_) { \
  2913. _ezchip_macro_read_value_=MA_INW(clk_uart1_apb_ctrl_REG_ADDR) >> 31; \
  2914. _ezchip_macro_read_value_ &= 0x1;\
  2915. }
  2916. #define _ENABLE_CLOCK_clk_uart1_core_ { \
  2917. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2918. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2919. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2920. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2921. }
  2922. #define _DISABLE_CLOCK_clk_uart1_core_ { \
  2923. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2924. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2925. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2926. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2927. }
  2928. #define _GET_CLOCK_ENABLE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
  2929. _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR) >> 31; \
  2930. _ezchip_macro_read_value_ &= 0x1;\
  2931. }
  2932. #define _DIVIDE_CLOCK_clk_uart1_core_(div) { \
  2933. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2934. _ezchip_macro_read_value_ &= ~(0x3F); \
  2935. _ezchip_macro_read_value_ |= (div&0x3F); \
  2936. MA_OUTW(clk_uart1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2937. }
  2938. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart1_core_(_ezchip_macro_read_value_) { \
  2939. _ezchip_macro_read_value_=MA_INW(clk_uart1_core_ctrl_REG_ADDR); \
  2940. _ezchip_macro_read_value_ &= 0x3f;\
  2941. }
  2942. #define _ENABLE_CLOCK_clk_spi0_apb_ { \
  2943. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
  2944. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2945. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2946. MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2947. }
  2948. #define _DISABLE_CLOCK_clk_spi0_apb_ { \
  2949. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR); \
  2950. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2951. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2952. MA_OUTW(clk_spi0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2953. }
  2954. #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_apb_(_ezchip_macro_read_value_) { \
  2955. _ezchip_macro_read_value_=MA_INW(clk_spi0_apb_ctrl_REG_ADDR) >> 31; \
  2956. _ezchip_macro_read_value_ &= 0x1;\
  2957. }
  2958. #define _ENABLE_CLOCK_clk_spi0_core_ { \
  2959. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2960. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2961. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2962. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2963. }
  2964. #define _DISABLE_CLOCK_clk_spi0_core_ { \
  2965. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2966. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2967. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2968. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2969. }
  2970. #define _GET_CLOCK_ENABLE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
  2971. _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR) >> 31; \
  2972. _ezchip_macro_read_value_ &= 0x1;\
  2973. }
  2974. #define _DIVIDE_CLOCK_clk_spi0_core_(div) { \
  2975. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2976. _ezchip_macro_read_value_ &= ~(0x3F); \
  2977. _ezchip_macro_read_value_ |= (div&0x3F); \
  2978. MA_OUTW(clk_spi0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2979. }
  2980. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi0_core_(_ezchip_macro_read_value_) { \
  2981. _ezchip_macro_read_value_=MA_INW(clk_spi0_core_ctrl_REG_ADDR); \
  2982. _ezchip_macro_read_value_ &= 0x3f;\
  2983. }
  2984. #define _ENABLE_CLOCK_clk_spi1_apb_ { \
  2985. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
  2986. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2987. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  2988. MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2989. }
  2990. #define _DISABLE_CLOCK_clk_spi1_apb_ { \
  2991. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR); \
  2992. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  2993. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  2994. MA_OUTW(clk_spi1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  2995. }
  2996. #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_apb_(_ezchip_macro_read_value_) { \
  2997. _ezchip_macro_read_value_=MA_INW(clk_spi1_apb_ctrl_REG_ADDR) >> 31; \
  2998. _ezchip_macro_read_value_ &= 0x1;\
  2999. }
  3000. #define _ENABLE_CLOCK_clk_spi1_core_ { \
  3001. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3002. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3003. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3004. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3005. }
  3006. #define _DISABLE_CLOCK_clk_spi1_core_ { \
  3007. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3008. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3009. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3010. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3011. }
  3012. #define _GET_CLOCK_ENABLE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
  3013. _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR) >> 31; \
  3014. _ezchip_macro_read_value_ &= 0x1;\
  3015. }
  3016. #define _DIVIDE_CLOCK_clk_spi1_core_(div) { \
  3017. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3018. _ezchip_macro_read_value_ &= ~(0x3F); \
  3019. _ezchip_macro_read_value_ |= (div&0x3F); \
  3020. MA_OUTW(clk_spi1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3021. }
  3022. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi1_core_(_ezchip_macro_read_value_) { \
  3023. _ezchip_macro_read_value_=MA_INW(clk_spi1_core_ctrl_REG_ADDR); \
  3024. _ezchip_macro_read_value_ &= 0x3f;\
  3025. }
  3026. #define _ENABLE_CLOCK_clk_i2c0_apb_ { \
  3027. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
  3028. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3029. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3030. MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3031. }
  3032. #define _DISABLE_CLOCK_clk_i2c0_apb_ { \
  3033. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR); \
  3034. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3035. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3036. MA_OUTW(clk_i2c0_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3037. }
  3038. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_apb_(_ezchip_macro_read_value_) { \
  3039. _ezchip_macro_read_value_=MA_INW(clk_i2c0_apb_ctrl_REG_ADDR) >> 31; \
  3040. _ezchip_macro_read_value_ &= 0x1;\
  3041. }
  3042. #define _ENABLE_CLOCK_clk_i2c0_core_ { \
  3043. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3044. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3045. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3046. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3047. }
  3048. #define _DISABLE_CLOCK_clk_i2c0_core_ { \
  3049. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3050. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3051. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3052. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3053. }
  3054. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
  3055. _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR) >> 31; \
  3056. _ezchip_macro_read_value_ &= 0x1;\
  3057. }
  3058. #define _DIVIDE_CLOCK_clk_i2c0_core_(div) { \
  3059. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3060. _ezchip_macro_read_value_ &= ~(0x3F); \
  3061. _ezchip_macro_read_value_ |= (div&0x3F); \
  3062. MA_OUTW(clk_i2c0_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3063. }
  3064. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c0_core_(_ezchip_macro_read_value_) { \
  3065. _ezchip_macro_read_value_=MA_INW(clk_i2c0_core_ctrl_REG_ADDR); \
  3066. _ezchip_macro_read_value_ &= 0x3f;\
  3067. }
  3068. #define _ENABLE_CLOCK_clk_i2c1_apb_ { \
  3069. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
  3070. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3071. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3072. MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3073. }
  3074. #define _DISABLE_CLOCK_clk_i2c1_apb_ { \
  3075. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR); \
  3076. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3077. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3078. MA_OUTW(clk_i2c1_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3079. }
  3080. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_apb_(_ezchip_macro_read_value_) { \
  3081. _ezchip_macro_read_value_=MA_INW(clk_i2c1_apb_ctrl_REG_ADDR) >> 31; \
  3082. _ezchip_macro_read_value_ &= 0x1;\
  3083. }
  3084. #define _ENABLE_CLOCK_clk_i2c1_core_ { \
  3085. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3086. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3087. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3088. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3089. }
  3090. #define _DISABLE_CLOCK_clk_i2c1_core_ { \
  3091. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3092. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3093. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3094. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3095. }
  3096. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
  3097. _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR) >> 31; \
  3098. _ezchip_macro_read_value_ &= 0x1;\
  3099. }
  3100. #define _DIVIDE_CLOCK_clk_i2c1_core_(div) { \
  3101. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3102. _ezchip_macro_read_value_ &= ~(0x3F); \
  3103. _ezchip_macro_read_value_ |= (div&0x3F); \
  3104. MA_OUTW(clk_i2c1_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3105. }
  3106. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c1_core_(_ezchip_macro_read_value_) { \
  3107. _ezchip_macro_read_value_=MA_INW(clk_i2c1_core_ctrl_REG_ADDR); \
  3108. _ezchip_macro_read_value_ &= 0x3f;\
  3109. }
  3110. #define _ENABLE_CLOCK_clk_gpio_apb_ { \
  3111. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
  3112. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3113. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3114. MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3115. }
  3116. #define _DISABLE_CLOCK_clk_gpio_apb_ { \
  3117. uint32_t _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR); \
  3118. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3119. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3120. MA_OUTW(clk_gpio_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3121. }
  3122. #define _GET_CLOCK_ENABLE_STATUS_clk_gpio_apb_(_ezchip_macro_read_value_) { \
  3123. _ezchip_macro_read_value_=MA_INW(clk_gpio_apb_ctrl_REG_ADDR) >> 31; \
  3124. _ezchip_macro_read_value_ &= 0x1;\
  3125. }
  3126. #define _ENABLE_CLOCK_clk_uart2_apb_ { \
  3127. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
  3128. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3129. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3130. MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3131. }
  3132. #define _DISABLE_CLOCK_clk_uart2_apb_ { \
  3133. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR); \
  3134. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3135. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3136. MA_OUTW(clk_uart2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3137. }
  3138. #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_apb_(_ezchip_macro_read_value_) { \
  3139. _ezchip_macro_read_value_=MA_INW(clk_uart2_apb_ctrl_REG_ADDR) >> 31; \
  3140. _ezchip_macro_read_value_ &= 0x1;\
  3141. }
  3142. #define _ENABLE_CLOCK_clk_uart2_core_ { \
  3143. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3144. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3145. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3146. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3147. }
  3148. #define _DISABLE_CLOCK_clk_uart2_core_ { \
  3149. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3150. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3151. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3152. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3153. }
  3154. #define _GET_CLOCK_ENABLE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
  3155. _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR) >> 31; \
  3156. _ezchip_macro_read_value_ &= 0x1;\
  3157. }
  3158. #define _DIVIDE_CLOCK_clk_uart2_core_(div) { \
  3159. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3160. _ezchip_macro_read_value_ &= ~(0x3F); \
  3161. _ezchip_macro_read_value_ |= (div&0x3F); \
  3162. MA_OUTW(clk_uart2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3163. }
  3164. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart2_core_(_ezchip_macro_read_value_) { \
  3165. _ezchip_macro_read_value_=MA_INW(clk_uart2_core_ctrl_REG_ADDR); \
  3166. _ezchip_macro_read_value_ &= 0x3f;\
  3167. }
  3168. #define _ENABLE_CLOCK_clk_uart3_apb_ { \
  3169. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
  3170. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3171. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3172. MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3173. }
  3174. #define _DISABLE_CLOCK_clk_uart3_apb_ { \
  3175. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR); \
  3176. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3177. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3178. MA_OUTW(clk_uart3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3179. }
  3180. #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_apb_(_ezchip_macro_read_value_) { \
  3181. _ezchip_macro_read_value_=MA_INW(clk_uart3_apb_ctrl_REG_ADDR) >> 31; \
  3182. _ezchip_macro_read_value_ &= 0x1;\
  3183. }
  3184. #define _ENABLE_CLOCK_clk_uart3_core_ { \
  3185. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3186. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3187. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3188. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3189. }
  3190. #define _DISABLE_CLOCK_clk_uart3_core_ { \
  3191. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3192. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3193. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3194. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3195. }
  3196. #define _GET_CLOCK_ENABLE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
  3197. _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR) >> 31; \
  3198. _ezchip_macro_read_value_ &= 0x1;\
  3199. }
  3200. #define _DIVIDE_CLOCK_clk_uart3_core_(div) { \
  3201. uint32_t _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3202. _ezchip_macro_read_value_ &= ~(0x3F); \
  3203. _ezchip_macro_read_value_ |= (div&0x3F); \
  3204. MA_OUTW(clk_uart3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3205. }
  3206. #define _GET_CLOCK_DIVIDE_STATUS_clk_uart3_core_(_ezchip_macro_read_value_) { \
  3207. _ezchip_macro_read_value_=MA_INW(clk_uart3_core_ctrl_REG_ADDR); \
  3208. _ezchip_macro_read_value_ &= 0x3f;\
  3209. }
  3210. #define _ENABLE_CLOCK_clk_spi2_apb_ { \
  3211. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
  3212. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3213. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3214. MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3215. }
  3216. #define _DISABLE_CLOCK_clk_spi2_apb_ { \
  3217. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR); \
  3218. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3219. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3220. MA_OUTW(clk_spi2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3221. }
  3222. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_apb_(_ezchip_macro_read_value_) { \
  3223. _ezchip_macro_read_value_=MA_INW(clk_spi2_apb_ctrl_REG_ADDR) >> 31; \
  3224. _ezchip_macro_read_value_ &= 0x1;\
  3225. }
  3226. #define _ENABLE_CLOCK_clk_spi2_core_ { \
  3227. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3228. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3229. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3230. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3231. }
  3232. #define _DISABLE_CLOCK_clk_spi2_core_ { \
  3233. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3234. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3235. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3236. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3237. }
  3238. #define _GET_CLOCK_ENABLE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
  3239. _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR) >> 31; \
  3240. _ezchip_macro_read_value_ &= 0x1;\
  3241. }
  3242. #define _DIVIDE_CLOCK_clk_spi2_core_(div) { \
  3243. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3244. _ezchip_macro_read_value_ &= ~(0x3F); \
  3245. _ezchip_macro_read_value_ |= (div&0x3F); \
  3246. MA_OUTW(clk_spi2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3247. }
  3248. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi2_core_(_ezchip_macro_read_value_) { \
  3249. _ezchip_macro_read_value_=MA_INW(clk_spi2_core_ctrl_REG_ADDR); \
  3250. _ezchip_macro_read_value_ &= 0x3f;\
  3251. }
  3252. #define _ENABLE_CLOCK_clk_spi3_apb_ { \
  3253. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
  3254. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3255. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3256. MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3257. }
  3258. #define _DISABLE_CLOCK_clk_spi3_apb_ { \
  3259. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR); \
  3260. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3261. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3262. MA_OUTW(clk_spi3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3263. }
  3264. #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_apb_(_ezchip_macro_read_value_) { \
  3265. _ezchip_macro_read_value_=MA_INW(clk_spi3_apb_ctrl_REG_ADDR) >> 31; \
  3266. _ezchip_macro_read_value_ &= 0x1;\
  3267. }
  3268. #define _ENABLE_CLOCK_clk_spi3_core_ { \
  3269. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3270. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3271. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3272. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3273. }
  3274. #define _DISABLE_CLOCK_clk_spi3_core_ { \
  3275. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3276. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3277. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3278. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3279. }
  3280. #define _GET_CLOCK_ENABLE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
  3281. _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR) >> 31; \
  3282. _ezchip_macro_read_value_ &= 0x1;\
  3283. }
  3284. #define _DIVIDE_CLOCK_clk_spi3_core_(div) { \
  3285. uint32_t _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3286. _ezchip_macro_read_value_ &= ~(0x3F); \
  3287. _ezchip_macro_read_value_ |= (div&0x3F); \
  3288. MA_OUTW(clk_spi3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3289. }
  3290. #define _GET_CLOCK_DIVIDE_STATUS_clk_spi3_core_(_ezchip_macro_read_value_) { \
  3291. _ezchip_macro_read_value_=MA_INW(clk_spi3_core_ctrl_REG_ADDR); \
  3292. _ezchip_macro_read_value_ &= 0x3f;\
  3293. }
  3294. #define _ENABLE_CLOCK_clk_i2c2_apb_ { \
  3295. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
  3296. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3297. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3298. MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3299. }
  3300. #define _DISABLE_CLOCK_clk_i2c2_apb_ { \
  3301. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR); \
  3302. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3303. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3304. MA_OUTW(clk_i2c2_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3305. }
  3306. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_apb_(_ezchip_macro_read_value_) { \
  3307. _ezchip_macro_read_value_=MA_INW(clk_i2c2_apb_ctrl_REG_ADDR) >> 31; \
  3308. _ezchip_macro_read_value_ &= 0x1;\
  3309. }
  3310. #define _ENABLE_CLOCK_clk_i2c2_core_ { \
  3311. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3312. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3313. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3314. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3315. }
  3316. #define _DISABLE_CLOCK_clk_i2c2_core_ { \
  3317. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3318. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3319. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3320. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3321. }
  3322. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
  3323. _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR) >> 31; \
  3324. _ezchip_macro_read_value_ &= 0x1;\
  3325. }
  3326. #define _DIVIDE_CLOCK_clk_i2c2_core_(div) { \
  3327. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3328. _ezchip_macro_read_value_ &= ~(0x3F); \
  3329. _ezchip_macro_read_value_ |= (div&0x3F); \
  3330. MA_OUTW(clk_i2c2_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3331. }
  3332. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c2_core_(_ezchip_macro_read_value_) { \
  3333. _ezchip_macro_read_value_=MA_INW(clk_i2c2_core_ctrl_REG_ADDR); \
  3334. _ezchip_macro_read_value_ &= 0x3f;\
  3335. }
  3336. #define _ENABLE_CLOCK_clk_i2c3_apb_ { \
  3337. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
  3338. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3339. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3340. MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3341. }
  3342. #define _DISABLE_CLOCK_clk_i2c3_apb_ { \
  3343. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR); \
  3344. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3345. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3346. MA_OUTW(clk_i2c3_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3347. }
  3348. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_apb_(_ezchip_macro_read_value_) { \
  3349. _ezchip_macro_read_value_=MA_INW(clk_i2c3_apb_ctrl_REG_ADDR) >> 31; \
  3350. _ezchip_macro_read_value_ &= 0x1;\
  3351. }
  3352. #define _ENABLE_CLOCK_clk_i2c3_core_ { \
  3353. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3354. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3355. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3356. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3357. }
  3358. #define _DISABLE_CLOCK_clk_i2c3_core_ { \
  3359. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3360. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3361. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3362. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3363. }
  3364. #define _GET_CLOCK_ENABLE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
  3365. _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR) >> 31; \
  3366. _ezchip_macro_read_value_ &= 0x1;\
  3367. }
  3368. #define _DIVIDE_CLOCK_clk_i2c3_core_(div) { \
  3369. uint32_t _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3370. _ezchip_macro_read_value_ &= ~(0x3F); \
  3371. _ezchip_macro_read_value_ |= (div&0x3F); \
  3372. MA_OUTW(clk_i2c3_core_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3373. }
  3374. #define _GET_CLOCK_DIVIDE_STATUS_clk_i2c3_core_(_ezchip_macro_read_value_) { \
  3375. _ezchip_macro_read_value_=MA_INW(clk_i2c3_core_ctrl_REG_ADDR); \
  3376. _ezchip_macro_read_value_ &= 0x3f;\
  3377. }
  3378. #define _ENABLE_CLOCK_clk_wdtimer_apb_ { \
  3379. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
  3380. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3381. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3382. MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3383. }
  3384. #define _DISABLE_CLOCK_clk_wdtimer_apb_ { \
  3385. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR); \
  3386. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3387. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3388. MA_OUTW(clk_wdtimer_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3389. }
  3390. #define _GET_CLOCK_ENABLE_STATUS_clk_wdtimer_apb_(_ezchip_macro_read_value_) { \
  3391. _ezchip_macro_read_value_=MA_INW(clk_wdtimer_apb_ctrl_REG_ADDR) >> 31; \
  3392. _ezchip_macro_read_value_ &= 0x1;\
  3393. }
  3394. #define _ENABLE_CLOCK_clk_wdt_coreclk_ { \
  3395. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3396. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3397. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3398. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3399. }
  3400. #define _DISABLE_CLOCK_clk_wdt_coreclk_ { \
  3401. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3402. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3403. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3404. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3405. }
  3406. #define _GET_CLOCK_ENABLE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
  3407. _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR) >> 31; \
  3408. _ezchip_macro_read_value_ &= 0x1;\
  3409. }
  3410. #define _DIVIDE_CLOCK_clk_wdt_coreclk_(div) { \
  3411. uint32_t _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3412. _ezchip_macro_read_value_ &= ~(0x3F); \
  3413. _ezchip_macro_read_value_ |= (div&0x3F); \
  3414. MA_OUTW(clk_wdt_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3415. }
  3416. #define _GET_CLOCK_DIVIDE_STATUS_clk_wdt_coreclk_(_ezchip_macro_read_value_) { \
  3417. _ezchip_macro_read_value_=MA_INW(clk_wdt_coreclk_ctrl_REG_ADDR); \
  3418. _ezchip_macro_read_value_ &= 0x3f;\
  3419. }
  3420. #define _ENABLE_CLOCK_clk_timer0_coreclk_ { \
  3421. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3422. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3423. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3424. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3425. }
  3426. #define _DISABLE_CLOCK_clk_timer0_coreclk_ { \
  3427. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3428. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3429. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3430. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3431. }
  3432. #define _GET_CLOCK_ENABLE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
  3433. _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR) >> 31; \
  3434. _ezchip_macro_read_value_ &= 0x1;\
  3435. }
  3436. #define _DIVIDE_CLOCK_clk_timer0_coreclk_(div) { \
  3437. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3438. _ezchip_macro_read_value_ &= ~(0x3F); \
  3439. _ezchip_macro_read_value_ |= (div&0x3F); \
  3440. MA_OUTW(clk_timer0_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3441. }
  3442. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer0_coreclk_(_ezchip_macro_read_value_) { \
  3443. _ezchip_macro_read_value_=MA_INW(clk_timer0_coreclk_ctrl_REG_ADDR); \
  3444. _ezchip_macro_read_value_ &= 0x3f;\
  3445. }
  3446. #define _ENABLE_CLOCK_clk_timer1_coreclk_ { \
  3447. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3448. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3449. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3450. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3451. }
  3452. #define _DISABLE_CLOCK_clk_timer1_coreclk_ { \
  3453. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3454. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3455. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3456. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3457. }
  3458. #define _GET_CLOCK_ENABLE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
  3459. _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR) >> 31; \
  3460. _ezchip_macro_read_value_ &= 0x1;\
  3461. }
  3462. #define _DIVIDE_CLOCK_clk_timer1_coreclk_(div) { \
  3463. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3464. _ezchip_macro_read_value_ &= ~(0x3F); \
  3465. _ezchip_macro_read_value_ |= (div&0x3F); \
  3466. MA_OUTW(clk_timer1_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3467. }
  3468. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer1_coreclk_(_ezchip_macro_read_value_) { \
  3469. _ezchip_macro_read_value_=MA_INW(clk_timer1_coreclk_ctrl_REG_ADDR); \
  3470. _ezchip_macro_read_value_ &= 0x3f;\
  3471. }
  3472. #define _ENABLE_CLOCK_clk_timer2_coreclk_ { \
  3473. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3474. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3475. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3476. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3477. }
  3478. #define _DISABLE_CLOCK_clk_timer2_coreclk_ { \
  3479. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3480. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3481. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3482. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3483. }
  3484. #define _GET_CLOCK_ENABLE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
  3485. _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR) >> 31; \
  3486. _ezchip_macro_read_value_ &= 0x1;\
  3487. }
  3488. #define _DIVIDE_CLOCK_clk_timer2_coreclk_(div) { \
  3489. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3490. _ezchip_macro_read_value_ &= ~(0x3F); \
  3491. _ezchip_macro_read_value_ |= (div&0x3F); \
  3492. MA_OUTW(clk_timer2_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3493. }
  3494. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer2_coreclk_(_ezchip_macro_read_value_) { \
  3495. _ezchip_macro_read_value_=MA_INW(clk_timer2_coreclk_ctrl_REG_ADDR); \
  3496. _ezchip_macro_read_value_ &= 0x3f;\
  3497. }
  3498. #define _ENABLE_CLOCK_clk_timer3_coreclk_ { \
  3499. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3500. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3501. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3502. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3503. }
  3504. #define _DISABLE_CLOCK_clk_timer3_coreclk_ { \
  3505. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3506. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3507. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3508. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3509. }
  3510. #define _GET_CLOCK_ENABLE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
  3511. _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR) >> 31; \
  3512. _ezchip_macro_read_value_ &= 0x1;\
  3513. }
  3514. #define _DIVIDE_CLOCK_clk_timer3_coreclk_(div) { \
  3515. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3516. _ezchip_macro_read_value_ &= ~(0x3F); \
  3517. _ezchip_macro_read_value_ |= (div&0x3F); \
  3518. MA_OUTW(clk_timer3_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3519. }
  3520. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer3_coreclk_(_ezchip_macro_read_value_) { \
  3521. _ezchip_macro_read_value_=MA_INW(clk_timer3_coreclk_ctrl_REG_ADDR); \
  3522. _ezchip_macro_read_value_ &= 0x3f;\
  3523. }
  3524. #define _ENABLE_CLOCK_clk_timer4_coreclk_ { \
  3525. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3526. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3527. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3528. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3529. }
  3530. #define _DISABLE_CLOCK_clk_timer4_coreclk_ { \
  3531. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3532. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3533. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3534. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3535. }
  3536. #define _GET_CLOCK_ENABLE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
  3537. _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR) >> 31; \
  3538. _ezchip_macro_read_value_ &= 0x1;\
  3539. }
  3540. #define _DIVIDE_CLOCK_clk_timer4_coreclk_(div) { \
  3541. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3542. _ezchip_macro_read_value_ &= ~(0x3F); \
  3543. _ezchip_macro_read_value_ |= (div&0x3F); \
  3544. MA_OUTW(clk_timer4_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3545. }
  3546. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer4_coreclk_(_ezchip_macro_read_value_) { \
  3547. _ezchip_macro_read_value_=MA_INW(clk_timer4_coreclk_ctrl_REG_ADDR); \
  3548. _ezchip_macro_read_value_ &= 0x3f;\
  3549. }
  3550. #define _ENABLE_CLOCK_clk_timer5_coreclk_ { \
  3551. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3552. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3553. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3554. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3555. }
  3556. #define _DISABLE_CLOCK_clk_timer5_coreclk_ { \
  3557. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3558. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3559. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3560. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3561. }
  3562. #define _GET_CLOCK_ENABLE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
  3563. _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR) >> 31; \
  3564. _ezchip_macro_read_value_ &= 0x1;\
  3565. }
  3566. #define _DIVIDE_CLOCK_clk_timer5_coreclk_(div) { \
  3567. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3568. _ezchip_macro_read_value_ &= ~(0x3F); \
  3569. _ezchip_macro_read_value_ |= (div&0x3F); \
  3570. MA_OUTW(clk_timer5_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3571. }
  3572. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer5_coreclk_(_ezchip_macro_read_value_) { \
  3573. _ezchip_macro_read_value_=MA_INW(clk_timer5_coreclk_ctrl_REG_ADDR); \
  3574. _ezchip_macro_read_value_ &= 0x3f;\
  3575. }
  3576. #define _ENABLE_CLOCK_clk_timer6_coreclk_ { \
  3577. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3578. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3579. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3580. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3581. }
  3582. #define _DISABLE_CLOCK_clk_timer6_coreclk_ { \
  3583. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3584. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3585. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3586. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3587. }
  3588. #define _GET_CLOCK_ENABLE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
  3589. _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR) >> 31; \
  3590. _ezchip_macro_read_value_ &= 0x1;\
  3591. }
  3592. #define _DIVIDE_CLOCK_clk_timer6_coreclk_(div) { \
  3593. uint32_t _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3594. _ezchip_macro_read_value_ &= ~(0x3F); \
  3595. _ezchip_macro_read_value_ |= (div&0x3F); \
  3596. MA_OUTW(clk_timer6_coreclk_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3597. }
  3598. #define _GET_CLOCK_DIVIDE_STATUS_clk_timer6_coreclk_(_ezchip_macro_read_value_) { \
  3599. _ezchip_macro_read_value_=MA_INW(clk_timer6_coreclk_ctrl_REG_ADDR); \
  3600. _ezchip_macro_read_value_ &= 0x3f;\
  3601. }
  3602. #define _ENABLE_CLOCK_clk_vp6intc_apb_ { \
  3603. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
  3604. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3605. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3606. MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3607. }
  3608. #define _DISABLE_CLOCK_clk_vp6intc_apb_ { \
  3609. uint32_t _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR); \
  3610. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3611. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3612. MA_OUTW(clk_vp6intc_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3613. }
  3614. #define _GET_CLOCK_ENABLE_STATUS_clk_vp6intc_apb_(_ezchip_macro_read_value_) { \
  3615. _ezchip_macro_read_value_=MA_INW(clk_vp6intc_apb_ctrl_REG_ADDR) >> 31; \
  3616. _ezchip_macro_read_value_ &= 0x1;\
  3617. }
  3618. #define _ENABLE_CLOCK_clk_pwm_apb_ { \
  3619. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
  3620. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3621. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3622. MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3623. }
  3624. #define _DISABLE_CLOCK_clk_pwm_apb_ { \
  3625. uint32_t _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR); \
  3626. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3627. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3628. MA_OUTW(clk_pwm_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3629. }
  3630. #define _GET_CLOCK_ENABLE_STATUS_clk_pwm_apb_(_ezchip_macro_read_value_) { \
  3631. _ezchip_macro_read_value_=MA_INW(clk_pwm_apb_ctrl_REG_ADDR) >> 31; \
  3632. _ezchip_macro_read_value_ &= 0x1;\
  3633. }
  3634. #define _ENABLE_CLOCK_clk_msi_apb_ { \
  3635. uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
  3636. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3637. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3638. MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3639. }
  3640. #define _DISABLE_CLOCK_clk_msi_apb_ { \
  3641. uint32_t _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR); \
  3642. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3643. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3644. MA_OUTW(clk_msi_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3645. }
  3646. #define _GET_CLOCK_ENABLE_STATUS_clk_msi_apb_(_ezchip_macro_read_value_) { \
  3647. _ezchip_macro_read_value_=MA_INW(clk_msi_apb_ctrl_REG_ADDR) >> 31; \
  3648. _ezchip_macro_read_value_ &= 0x1;\
  3649. }
  3650. #define _ENABLE_CLOCK_clk_temp_apb_ { \
  3651. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
  3652. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3653. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3654. MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3655. }
  3656. #define _DISABLE_CLOCK_clk_temp_apb_ { \
  3657. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR); \
  3658. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3659. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3660. MA_OUTW(clk_temp_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3661. }
  3662. #define _GET_CLOCK_ENABLE_STATUS_clk_temp_apb_(_ezchip_macro_read_value_) { \
  3663. _ezchip_macro_read_value_=MA_INW(clk_temp_apb_ctrl_REG_ADDR) >> 31; \
  3664. _ezchip_macro_read_value_ &= 0x1;\
  3665. }
  3666. #define _ENABLE_CLOCK_clk_temp_sense_ { \
  3667. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3668. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3669. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3670. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3671. }
  3672. #define _DISABLE_CLOCK_clk_temp_sense_ { \
  3673. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3674. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3675. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3676. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3677. }
  3678. #define _GET_CLOCK_ENABLE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
  3679. _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR) >> 31; \
  3680. _ezchip_macro_read_value_ &= 0x1;\
  3681. }
  3682. #define _DIVIDE_CLOCK_clk_temp_sense_(div) { \
  3683. uint32_t _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3684. _ezchip_macro_read_value_ &= ~(0x1F); \
  3685. _ezchip_macro_read_value_ |= (div&0x1F); \
  3686. MA_OUTW(clk_temp_sense_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3687. }
  3688. #define _GET_CLOCK_DIVIDE_STATUS_clk_temp_sense_(_ezchip_macro_read_value_) { \
  3689. _ezchip_macro_read_value_=MA_INW(clk_temp_sense_ctrl_REG_ADDR); \
  3690. _ezchip_macro_read_value_ &= 0x1f;\
  3691. }
  3692. #define _ENABLE_CLOCK_clk_syserr_apb_ { \
  3693. uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
  3694. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3695. _ezchip_macro_read_value_ |= (0x1&0x1)<<31; \
  3696. MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3697. }
  3698. #define _DISABLE_CLOCK_clk_syserr_apb_ { \
  3699. uint32_t _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR); \
  3700. _ezchip_macro_read_value_ &= ~(0x1<<31); \
  3701. _ezchip_macro_read_value_ |= (0x0&0x1)<<31; \
  3702. MA_OUTW(clk_syserr_apb_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  3703. }
  3704. #define _GET_CLOCK_ENABLE_STATUS_clk_syserr_apb_(_ezchip_macro_read_value_) { \
  3705. _ezchip_macro_read_value_=MA_INW(clk_syserr_apb_ctrl_REG_ADDR) >> 31; \
  3706. _ezchip_macro_read_value_ &= 0x1;\
  3707. }
  3708. #endif //_CLKGEN_MACRO_H_