vic_module_reset_clkgen.h 4.0 KB

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  1. /**
  2. ******************************************************************************
  3. * @file vic_module_reset_clkgen.h
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 07/24/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #ifndef _SFC_VIC_MODULE_RESET_CLKGEN_H
  21. #define _SFC_VIC_MODULE_RESET_CLKGEN_H
  22. #define vic_uart0_reset_clk_gpio_isp_enable { \
  23. _ENABLE_CLOCK_clk_uart0_apb_; \
  24. _ENABLE_CLOCK_clk_uart0_core_; \
  25. _DIVIDE_CLOCK_clk_uart0_core_(8); \
  26. _CLEAR_RESET_rstgen_rstn_uart0_core_; \
  27. _CLEAR_RESET_rstgen_rstn_uart0_apb_; \
  28. SET_GPIO_uart0_pad_sin(13); \
  29. SET_GPIO_13_doen_HIGH; \
  30. SET_GPIO_12_dout_uart0_pad_sout; \
  31. SET_GPIO_12_doen_LOW; \
  32. }
  33. #define vic_uart0_reset_clk_gpio_misc_enable { \
  34. _ENABLE_CLOCK_clk_uart0_apb_; \
  35. _ENABLE_CLOCK_clk_uart0_core_; \
  36. _CLEAR_RESET_rstgen_rstn_uart0_core_; \
  37. _CLEAR_RESET_rstgen_rstn_uart0_apb_; \
  38. SET_GPIO_uart0_pad_sin(5); \
  39. SET_GPIO_5_doen_HIGH; \
  40. SET_GPIO_6_dout_uart0_pad_sout; \
  41. SET_GPIO_6_doen_LOW; \
  42. }
  43. #define vic_uart1_reset_clk_gpio_isp_enable { \
  44. _ENABLE_CLOCK_clk_uart1_apb_; \
  45. _ENABLE_CLOCK_clk_uart1_core_; \
  46. _CLEAR_RESET_rstgen_rstn_uart1_core_; \
  47. _CLEAR_RESET_rstgen_rstn_uart1_apb_; \
  48. SET_GPIO_12_dout_uart1_pad_sout; \
  49. SET_GPIO_uart1_pad_sin(13); \
  50. SET_GPIO_13_doen_HIGH; \
  51. SET_GPIO_12_doen_LOW; \
  52. }
  53. #define vic_uart1_reset_clk_gpio_misc_enable { \
  54. _ENABLE_CLOCK_clk_uart1_apb_; \
  55. _ENABLE_CLOCK_clk_uart1_core_; \
  56. _CLEAR_RESET_rstgen_rstn_uart1_core_; \
  57. _CLEAR_RESET_rstgen_rstn_uart1_apb_; \
  58. SET_GPIO_6_dout_uart1_pad_sout; \
  59. SET_GPIO_uart1_pad_sin(5); \
  60. SET_GPIO_5_doen_HIGH; \
  61. SET_GPIO_6_doen_LOW; \
  62. }
  63. #define vic_uart2_reset_clk_gpio_isp_enable { \
  64. _ENABLE_CLOCK_clk_uart2_apb_; \
  65. _ENABLE_CLOCK_clk_uart2_core_; \
  66. _CLEAR_RESET_rstgen_rstn_uart2_core_; \
  67. _CLEAR_RESET_rstgen_rstn_uart2_apb_; \
  68. SET_GPIO_uart2_pad_sin(13); \
  69. SET_GPIO_13_doen_HIGH; \
  70. SET_GPIO_12_dout_uart2_pad_sout; \
  71. SET_GPIO_12_doen_LOW; \
  72. }
  73. #define vic_uart2_reset_clk_disable { \
  74. _DISABLE_CLOCK_clk_uart2_apb_; \
  75. _ASSERT_RESET_rstgen_rstn_uart2_apb_; \
  76. _ASSERT_RESET_rstgen_rstn_uart2_core_; \
  77. }
  78. #define vic_uart2_reset_clk_gpio_misc_enable { \
  79. vic_uart2_reset_clk_disable; \
  80. _ENABLE_CLOCK_clk_uart2_apb_; \
  81. _ENABLE_CLOCK_clk_uart2_core_; \
  82. _CLEAR_RESET_rstgen_rstn_uart2_core_; \
  83. _CLEAR_RESET_rstgen_rstn_uart2_apb_; \
  84. SET_GPIO_uart2_pad_sin(13); \
  85. SET_GPIO_13_doen_HIGH; \
  86. SET_GPIO_14_dout_uart2_pad_sout; \
  87. SET_GPIO_14_doen_LOW; \
  88. }
  89. #define vic_uart3_reset_clk_gpio_isp_enable { \
  90. _ENABLE_CLOCK_clk_uart3_apb_; \
  91. _ENABLE_CLOCK_clk_uart3_core_; \
  92. _CLEAR_RESET_rstgen_rstn_uart3_core_; \
  93. _CLEAR_RESET_rstgen_rstn_uart3_apb_; \
  94. SET_GPIO_uart3_pad_sin(13); \
  95. SET_GPIO_13_doen_HIGH; \
  96. SET_GPIO_12_dout_uart3_pad_sout; \
  97. SET_GPIO_12_doen_LOW; \
  98. }
  99. #define vic_uart3_reset_clk_gpio_misc_enable { \
  100. _ENABLE_CLOCK_clk_uart3_apb_; \
  101. _ENABLE_CLOCK_clk_uart3_core_; \
  102. _CLEAR_RESET_rstgen_rstn_uart3_core_; \
  103. _CLEAR_RESET_rstgen_rstn_uart3_apb_; \
  104. SET_GPIO_uart2_pad_sin(13); \
  105. SET_GPIO_13_doen_HIGH; \
  106. SET_GPIO_14_dout_uart2_pad_sout; \
  107. SET_GPIO_14_doen_LOW; \
  108. }
  109. #endif /* _SFC_VIC_MODULE_RESET_CLKGEN_H */