socz80 port for the de0 (not nano) board

Godzil 19e0d870d4 Build for DE0, only SDRAM not working for now. пре 9 година
vhdl 19e0d870d4 Build for DE0, only SDRAM not working for now. пре 9 година
.gitignore 19e0d870d4 Build for DE0, only SDRAM not working for now. пре 9 година
Makefile 19e0d870d4 Build for DE0, only SDRAM not working for now. пре 9 година
README.md 1203b4ca68 Update README.md пре 9 година
de0.tcl 19e0d870d4 Build for DE0, only SDRAM not working for now. пре 9 година
de0_nano.tcl e35013a1af Initial de0 nano support пре 9 година

README.md

socz80-de0

This is a port of Will Sowerbutts’ socz80 retro microcomputer (http://sowerbutts.com/socz80) for the Tersasic DE0 board based on the DE0 nano port from https://github.com/slp/socz80-de0_nano.

Building

Make sure you have the Altera Quartus II software (I’ve used version 13.0 from Web Edition) binaries on your $PATH. Then run «make» for building the SOF file, and «make load» for loading it on your board.

Software

This project only contains the VHDL files for building the core and its depencies. You can find some software for this microcomputer and instructions about what you can do with it inside the tarball of the original project (http://sowerbutts.com/socz80/socz80-2014-04-30.tar.gz).

TODO

  • Make it work on the DE0. Z80 + SRAM, ROM and UART are working, but SDRAM need more tweak. I also need to publish the changes.
  • Add support for the integrated SD Card
  • Video Out and PS2 for a keyboard could be also a nice entry.
  • Currently the 4 hex digit are used to show the CPU PC, but I will also create an IO device to show on them the value you want
  • Also add all the SW switch and Button 1 and 2 to GPI and the LED to GPO minus the one used to display the CPU status. and Button 0 is used for Reset.
  • The original design was developed for a Papilo Pro board, which feautres a reasonable amount of non volatile memory onboard. The DE0 have a flash device, it may be nice to allow to map it to memory. Not sure if allow write to it is a good idea.
  • Also the two GPIO header could be added to the IO mapping.