Browse Source

Initial de0 nano support

Sergio L. Pascual 9 years ago
parent
commit
e35013a1af
5 changed files with 251 additions and 255 deletions
  1. 21 0
      Makefile
  2. 202 0
      de0_nano.tcl
  3. 9 122
      vhdl/DRAM.vhd
  4. 5 23
      vhdl/SDRAM_Controller.vhd
  5. 14 110
      vhdl/top_level.vhd

+ 21 - 0
Makefile

@@ -0,0 +1,21 @@
+DESIGN_NAME = de0_nano
+QUARTUS_OPTIONS =
+
+
+all: sta
+
+project: $(TCL_FILE)
+        quartus_sh $(QUARTUS_OPTIONS) -t $(DESIGN_NAME).tcl
+
+map: project
+        quartus_map $(QUARTUS_OPTIONS) $(DESIGN_NAME)
+
+fit: map
+        quartus_fit $(QUARTUS_OPTIONS) $(DESIGN_NAME)
+
+asm: fit
+        quartus_asm $(QUARTUS_OPTIONS) $(DESIGN_NAME)
+
+sta: asm
+        quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
+

+ 202 - 0
de0_nano.tcl

@@ -0,0 +1,202 @@
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+# Quartus II: Generate Tcl File for Project
+# File: de0_nano.tcl
+# Generated on: Sat Sep  6 02:27:17 2014
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+	if {[string compare $quartus(project) "de0_nano"]} {
+		puts "Project de0_nano is not open"
+		set make_assignments 0
+	}
+} else {
+	# Only open if not already open
+	if {[project_exists de0_nano]} {
+		project_open -revision de0_nano de0_nano
+	} else {
+		project_new -revision de0_nano de0_nano
+	}
+	set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+	set_global_assignment -name FAMILY "Cyclone IV E"
+	set_global_assignment -name DEVICE EP4CE22F17C6
+	set_global_assignment -name TOP_LEVEL_ENTITY top_level
+	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+	set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:30:55  AUGUST 28, 2014"
+	set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+	set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+	set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+	set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+	set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+	set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+	set_global_assignment -name VHDL_FILE vhdl/DRAM.vhd
+	set_global_assignment -name VHDL_FILE vhdl/SDRAM_Controller.vhd
+	set_global_assignment -name VHDL_FILE vhdl/gpio.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80.vhd
+	set_global_assignment -name VHDL_FILE vhdl/top_level.vhd
+	set_global_assignment -name VHDL_FILE vhdl/Z80cpu.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_Pack.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_ALU.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_MCode.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_Reg.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80se.vhd
+	set_global_assignment -name VHDL_FILE vhdl/MMU.vhd
+	set_global_assignment -name VHDL_FILE vhdl/MonZ80.vhd
+	set_global_assignment -name VHDL_FILE vhdl/SSRAM.vhd
+	set_global_assignment -name VHDL_FILE vhdl/uart_interface.vhd
+	set_global_assignment -name VHDL_FILE vhdl/fifo.vhd
+	set_global_assignment -name VHDL_FILE vhdl/uart.vhd
+	set_global_assignment -name VHDL_FILE vhdl/timer.vhd
+	set_global_assignment -name VHDL_FILE vhdl/pll.vhd
+	set_global_assignment -name VHDL_FILE vhdl/clkscale.vhd
+	set_location_assignment PIN_J15 -to rst_n_pad_i
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i
+	set_location_assignment PIN_R8 -to sys_clk_pad_i
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i
+	set_location_assignment PIN_F13 -to serial_rx
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to serial_rx
+	set_location_assignment PIN_T15 -to serial_tx
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to serial_tx
+	set_location_assignment PIN_A15 -to leds[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[0]
+	set_location_assignment PIN_A13 -to leds[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[1]
+	set_location_assignment PIN_B13 -to leds[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[2]
+	set_location_assignment PIN_A11 -to leds[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[3]
+	set_location_assignment PIN_D1 -to leds[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds[4]
+	set_location_assignment PIN_P2 -to SDRAM_ADDR[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
+	set_location_assignment PIN_N5 -to SDRAM_ADDR[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
+	set_location_assignment PIN_N6 -to SDRAM_ADDR[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
+	set_location_assignment PIN_M8 -to SDRAM_ADDR[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
+	set_location_assignment PIN_P8 -to SDRAM_ADDR[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
+	set_location_assignment PIN_T7 -to SDRAM_ADDR[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
+	set_location_assignment PIN_N8 -to SDRAM_ADDR[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
+	set_location_assignment PIN_T6 -to SDRAM_ADDR[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
+	set_location_assignment PIN_R1 -to SDRAM_ADDR[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
+	set_location_assignment PIN_P1 -to SDRAM_ADDR[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
+	set_location_assignment PIN_N2 -to SDRAM_ADDR[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
+	set_location_assignment PIN_N1 -to SDRAM_ADDR[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
+	set_location_assignment PIN_L4 -to SDRAM_ADDR[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
+	set_location_assignment PIN_G2 -to SDRAM_DQ[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
+	set_location_assignment PIN_G1 -to SDRAM_DQ[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
+	set_location_assignment PIN_L8 -to SDRAM_DQ[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
+	set_location_assignment PIN_K5 -to SDRAM_DQ[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
+	set_location_assignment PIN_K2 -to SDRAM_DQ[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
+	set_location_assignment PIN_J2 -to SDRAM_DQ[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
+	set_location_assignment PIN_J1 -to SDRAM_DQ[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
+	set_location_assignment PIN_R7 -to SDRAM_DQ[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
+	set_location_assignment PIN_T4 -to SDRAM_DQ[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
+	set_location_assignment PIN_T2 -to SDRAM_DQ[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
+	set_location_assignment PIN_T3 -to SDRAM_DQ[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
+	set_location_assignment PIN_R3 -to SDRAM_DQ[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
+	set_location_assignment PIN_R5 -to SDRAM_DQ[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
+	set_location_assignment PIN_P3 -to SDRAM_DQ[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
+	set_location_assignment PIN_N3 -to SDRAM_DQ[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
+	set_location_assignment PIN_K1 -to SDRAM_DQ[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
+	set_location_assignment PIN_R6 -to SDRAM_DQM[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
+	set_location_assignment PIN_T5 -to SDRAM_DQM[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
+	set_location_assignment PIN_M7 -to SDRAM_BA[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
+	set_location_assignment PIN_M6 -to SDRAM_BA[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
+	set_location_assignment PIN_L1 -to SDRAM_nCAS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
+	set_location_assignment PIN_L7 -to SDRAM_CKE
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
+	set_location_assignment PIN_P6 -to SDRAM_CS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS
+	set_location_assignment PIN_L2 -to SDRAM_nRAS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
+	set_location_assignment PIN_C2 -to SDRAM_nWE
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
+	set_location_assignment PIN_R4 -to SDRAM_CLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_command"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_address"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_dqm"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_cke"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_bank"
+	set_instance_assignment -name FAST_INPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_data"
+	set_instance_assignment -name FAST_INPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|captured_data"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CKE
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CLK
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+	set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# Commit assignments
+	export_assignments
+
+	# Close project
+	if {$need_to_close_project} {
+		project_close
+	}
+}

+ 9 - 122
vhdl/DRAM.vhd

@@ -112,29 +112,19 @@ architecture behaviour of DRAM is
     signal current_state : controller_state;
     signal next_state    : controller_state;
 
-    -- here's the cache memory signals
-    signal cache_line_memory_write_enable : std_logic;
-    signal cache_line_memory_data_in      : std_logic_vector(35 downto 0); -- 35 downto 32: validity bits; 31 downto 0: four data bytes
-    signal cache_line_memory_data_out     : std_logic_vector(35 downto 0);
-    signal cache_tag_memory_write_enable  : std_logic;
-    signal cache_tag_memory_data_in       : std_logic_vector(8 downto 0);
-    signal cache_tag_memory_data_out      : std_logic_vector(8 downto 0);
-
     -- break up the incoming physical address
     alias address_byte       : std_logic_vector(1 downto 0)  is mem_address(1 downto 0);
     alias address_line       : std_logic_vector(11 downto 0) is mem_address(13 downto 2);
     alias address_tag        : std_logic_vector(8 downto 0)  is mem_address(22 downto 14);
     alias address_word       : std_logic_vector(20 downto 0) is mem_address(22 downto 2);
-                                                             -- mem_address(23) is unused in this design
-    alias cache_inhibit      : std_logic                     is mem_address(24);
+                                                             -- mem_address(23) and mem_address(24) are unused in this design
 
 begin
 
     -- this should be based on the generic, really
-    cmd_address <= mem_address(22 downto 2); -- address_tag & address_line
+    cmd_address <= '0' & '0' & mem_address(22 downto 2); -- address_tag & address_line
     cmd_data_in <= data_in & data_in & data_in & data_in; -- write the same data four times
     cmd_wr <= req_write;
-    cache_tag_memory_data_in <= address_tag;
     coldboot <= not seen_ready;
 
     compute_next_state: process(req_read, req_write, current_state, cache_hit, cmd_ready, cs, sdram_data_out_ready, word_changed)
@@ -152,14 +142,9 @@ begin
                             next_state <= st_idle;
                             -- come back next cycle!
                         else
-                            if cache_hit = '1' then
-                                mem_wait <= '0';
-                                next_state <= st_read_done;
-                            else
-                                cmd_enable <= '1';
-                                mem_wait <= '1';
-                                next_state <= st_read;
-                            end if;
+                            cmd_enable <= '1';
+                            mem_wait <= '1';
+                            next_state <= st_read;
                         end if;
                     elsif req_write = '1' then
                         if word_changed = '1' then
@@ -191,14 +176,14 @@ begin
                     -- this kind of implies that they gave up on us?
                     next_state <= st_idle;
                 end if;
-                mem_wait <= (not sdram_data_out_ready) and (not cache_hit);
+                mem_wait <= (not sdram_data_out_ready);
             when st_read_done =>
                 if cs = '1' and req_read = '1' then
                     next_state <= st_read_done;
                 else
                     next_state <= st_idle;
                 end if;
-                mem_wait <= (not sdram_data_out_ready) and (not cache_hit);
+                mem_wait <= (not sdram_data_out_ready);
             when st_write =>
                 if cs = '1' and req_write = '1' then
                     next_state <= st_write;
@@ -218,37 +203,6 @@ begin
         end if;
     end process;
 
-    cache_address_check: process(cache_tag_memory_data_out, cache_line_memory_data_out, address_tag)
-    begin
-        if cache_tag_memory_data_out = address_tag then
-            address_hit <= '1';
-            current_byte_valid <= cache_line_memory_data_out(35 downto 32);
-        else
-            address_hit <= '0';
-            current_byte_valid <= "0000";
-        end if;
-    end process;
-
-    cache_byte_valid_check: process(address_byte, current_byte_valid)
-    begin
-        case address_byte is
-            when "00"   => byte_valid_hit <= current_byte_valid(0);
-            when "01"   => byte_valid_hit <= current_byte_valid(1);
-            when "10"   => byte_valid_hit <= current_byte_valid(2);
-            when "11"   => byte_valid_hit <= current_byte_valid(3);
-            when others => byte_valid_hit <= '0';
-        end case;
-    end process;
-
-    cache_hit_check: process(byte_valid_hit, address_hit, cache_inhibit)
-    begin
-        if address_hit = '1' and byte_valid_hit = '1' and cache_inhibit = '0' then
-            cache_hit <= '1';
-        else
-            cache_hit <= '0';
-        end if;
-    end process;
-
     byte_enable_decode: process(address_byte)
     begin
         case address_byte is
@@ -260,14 +214,14 @@ begin
         end case;
     end process;
 
-    data_out_demux: process(address_byte, sdram_data_out_ready, sdram_data_out, cache_line_memory_data_out, current_word)
+    data_out_demux: process(address_byte, sdram_data_out_ready, sdram_data_out, current_word)
     begin
         -- when the SDRAM is presenting data, feed it direct to the CPU.
         -- otherwise feed data from our cache memory.
         if sdram_data_out_ready = '1' then
             current_word <= sdram_data_out;
         else
-            current_word <= cache_line_memory_data_out(31 downto 0);
+            current_word <= (others => '0');
         end if;
 
         case address_byte is
@@ -279,51 +233,6 @@ begin
         end case;
     end process;
 
-    cache_write: process(current_state, data_in, next_state, write_back, cache_line_memory_data_out, sdram_data_out, sdram_data_out_ready, address_byte, current_byte_valid)
-    begin
-        if (next_state = st_read) or (write_back = '1') then
-            cache_tag_memory_write_enable <= '1';
-        else
-            cache_tag_memory_write_enable <= '0';
-        end if;
-
-        cache_line_memory_write_enable <= '0';
-        cache_line_memory_data_in <= cache_line_memory_data_out;
-
-        if next_state = st_read then
-            cache_line_memory_data_in <= (others => '0'); -- set word and all valid flags to 1
-            cache_line_memory_write_enable <= '1';
-        end if;
-
-        -- has our read completed?
-        if current_state = st_read then
-            if sdram_data_out_ready = '1' then
-                cache_line_memory_data_in <= "1111" & sdram_data_out;
-                cache_line_memory_write_enable <= '1';
-            end if;
-        elsif write_back = '1' then 
-            case address_byte is
-                when "00"   =>
-                    cache_line_memory_data_in <= current_byte_valid(3 downto 1) & "1" & 
-                                                 cache_line_memory_data_out(31 downto  8) & data_in;
-                when "01"   =>
-                    cache_line_memory_data_in <= 
-                                                current_byte_valid(3 downto 2) & "1" & current_byte_valid(0) &
-                                                cache_line_memory_data_out(31 downto 16) & data_in & cache_line_memory_data_out(7 downto 0);
-                when "10"   =>
-                    cache_line_memory_data_in <= 
-                                                current_byte_valid(3) & "1" & current_byte_valid(1 downto 0) &
-                                                cache_line_memory_data_out(31 downto 24) & data_in & cache_line_memory_data_out(15 downto 0);
-                when "11"   =>
-                    cache_line_memory_data_in <= 
-                                                "1" & current_byte_valid(2 downto 0) &
-                                                data_in & cache_line_memory_data_out(23 downto 0);
-                when others => -- shut up, compiler!
-            end case;
-            cache_line_memory_write_enable <= '1';
-        end if;
-    end process;
-
     sdram_registers: process(clk)
     begin
         if rising_edge(clk) then
@@ -370,26 +279,4 @@ begin
                 SDRAM_DATA      => SDRAM_DQ
             );
 
-    -- block RAM used to store cache line data and byte validity (packs nicely into 36 bits)
-    cacheline_memory_sram: entity work.RAM4K36
-    port map (
-        clk      => clk,
-        reset    => reset,
-        write    => cache_line_memory_write_enable,
-        address  => address_line,
-        data_in  => cache_line_memory_data_in,
-        data_out => cache_line_memory_data_out
-        
-    );
-
-    -- block RAM used to store cache line tag memory (packs nicely into 9 bits)
-    cachetag_memory_sram: entity work.RAM4K9
-    port map (
-        clk      => clk,
-        reset    => reset,
-        write    => cache_tag_memory_write_enable,
-        address  => address_line,
-        data_in  => cache_tag_memory_data_in,
-        data_out => cache_tag_memory_data_out
-    );
 end;

+ 5 - 23
vhdl/SDRAM_Controller.vhd

@@ -26,8 +26,9 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 library UNISIM;
-use UNISIM.VComponents.all;
 use IEEE.NUMERIC_STD.ALL;
+library altera_mf;
+use altera_mf.altera_mf_components.all;
 
 
 entity SDRAM_Controller is
@@ -190,14 +191,6 @@ begin
    --addr_bank             <= cmd_address( 9 downto  8);      -- 1:0  <=  9:8
    --addr_col(8 downto 0)  <= cmd_address( 7 downto  0) & '0'; -- 8:0  <=  7:0 & '0'
 
-   -----------------------------------------------------------
-   -- Forward the SDRAM clock to the SDRAM chip - 180 degress 
-   -- out of phase with the control signals (ensuring setup and holdup 
-  -----------------------------------------------------------
- sdram_clk_forward : ODDR2
-   generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")
-   port map (Q => sdram_clk, C0 => clk, C1 => not clk, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1');
-
    -----------------------------------------------
    --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    --!! Ensure that all outputs are registered. !!
@@ -218,9 +211,9 @@ begin
    ---------------------------------------------------------------
 iob_dq_g: for i in 0 to 15 generate
    begin
-iob_dq_iob: IOBUF
-   generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "FAST")
-   port map ( O  => sdram_din(i), IO => sdram_data(i), I  => iob_data(i), T  => iob_dq_hiz);
+iob_dq_iob: altiobuf_bidir
+   generic map (number_of_channels => 1)
+   port map ( dataout(0)  => sdram_din(i), dataio(0) => sdram_data(i), datain(0) => iob_data(i), oe(0)  => iob_dq_hiz);
 end generate;
                                      
 capture_proc: process(clk) 
@@ -447,17 +440,6 @@ main_proc: process(clk)
             when s_write_2 =>
                state           <= s_write_3;
                iob_data        <= iob_data_next;
-               -- can we do a back-to-back write?
-               if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
-                  if save_wr = '1' then
-                     -- back-to-back write?
-                     state           <= s_write_1;
-                     ready_for_new   <= '1';
-                     got_transaction <= '0';
-                  end if;
-                  -- Although it looks right in simulation you can't go write-to-read 
-                  -- here due to bus contention, as iob_dq_hiz takes a few ns.
-               end if;
          
             when s_write_3 =>  -- must wait tRDL, hence the extra idle state
                -- back to back transaction?

+ 14 - 110
vhdl/top_level.vhd

@@ -20,6 +20,8 @@ use UNISIM.VComponents.all;
 
 entity top_level is
     Port ( sysclk_32m          : in    std_logic;
+           sys_clk_pad_i       : in    std_logic;
+           rst_n_pad_i         : in    std_logic;
            leds                : out   std_logic_vector(4 downto 0);
            reset_button        : in    std_logic;
            console_select      : in    std_logic;
@@ -61,12 +63,12 @@ entity top_level is
 end top_level;
 
 architecture Behavioral of top_level is
-    constant clk_freq_mhz        : natural := 128; -- this is the frequency which the PLL outputs, in MHz.
+    constant clk_freq_mhz        : natural := 100; -- this is the frequency which the PLL outputs, in MHz.
 
     -- SDRAM configuration
-    constant sdram_address_width : natural := 22;
-    constant sdram_column_bits   : natural := 8;
-    constant cycles_per_refresh  : natural := (64000*clk_freq_mhz)/4096-1;
+    constant sdram_address_width : natural := 24;
+    constant sdram_column_bits   : natural := 9;
+    constant cycles_per_refresh  : natural := (64000*clk_freq_mhz)/8192-1;
 
     -- For simulation, we don't need a long init stage. but for real DRAM we need approx 101us.
     -- The constant below has a different value when interpreted by the synthesis and simulator 
@@ -353,7 +355,7 @@ begin
                coldboot => coldboot,
 
                -- interface to hardware SDRAM chip
-               SDRAM_CLK       => SDRAM_CLK,
+               SDRAM_CLK       => open,
                SDRAM_CKE       => SDRAM_CKE,
                SDRAM_CS        => SDRAM_CS,
                SDRAM_nRAS      => SDRAM_nRAS,
@@ -407,25 +409,6 @@ begin
                req_write => req_write
            );
 
-   -- UART connected to MAX3232 on optional IO board
-   uart1: entity work.uart_interface
-   generic map ( flow_control => 1, clk_frequency => (clk_freq_mhz * 1000000) )
-   port map(
-               clk => clk,
-               reset => system_reset,
-               serial_in => uart1_rx,
-               serial_out => uart1_tx,
-               serial_rts => uart1_rts,
-               serial_cts => uart1_cts,
-               cpu_address => virtual_address(2 downto 0),
-               cpu_data_in => cpu_data_out,
-               cpu_data_out => uart1_data_out,
-               enable => uart1_cs,
-               interrupt => uart1_interrupt,
-               req_read => req_read,
-               req_write => req_write
-           );
-
    -- Timer device (internally scales the clock to 1MHz)
    timer: entity work.timer
    generic map ( clk_frequency => (clk_freq_mhz * 1000000) )
@@ -441,42 +424,6 @@ begin
                interrupt => timer_interrupt
            );
 
-   -- SPI master device connected to Papilio Pro 8MB flash ROM
-   spimaster0: entity work.spimaster
-   port map(
-               clk => clk,
-               reset => system_reset,
-               cpu_address => virtual_address(2 downto 0),
-               cpu_wait => spimaster0_wait,
-               data_in => cpu_data_out,
-               data_out => spimaster0_data_out,
-               enable => spimaster0_cs,
-               req_read => req_read,
-               req_write => req_write,
-               slave_cs => flash_spi_cs,
-               slave_clk => flash_spi_clk,
-               slave_mosi => flash_spi_mosi,
-               slave_miso => flash_spi_miso
-           );
-
-   -- SPI master device connected to SD card socket on the IO board
-   spimaster1: entity work.spimaster
-   port map(
-               clk => clk,
-               reset => system_reset,
-               cpu_address => virtual_address(2 downto 0),
-               cpu_wait => spimaster1_wait,
-               data_in => cpu_data_out,
-               data_out => spimaster1_data_out,
-               enable => spimaster1_cs,
-               req_read => req_read,
-               req_write => req_write,
-               slave_cs => sdcard_spi_cs,
-               slave_clk => sdcard_spi_clk,
-               slave_mosi => sdcard_spi_mosi,
-               slave_miso => sdcard_spi_miso
-           );
-
    -- GPIO to FPGA pins and/or internal signals
    gpio: entity work.gpio
    port map(
@@ -508,56 +455,13 @@ begin
                clk_enable => cpu_clk_enable
            );
 
-   -- PLL scales 32MHz Papilio Pro oscillator frequency to 128MHz
-   -- clock for our logic.
-   clock_pll: PLL_BASE 
-   generic map (
-               BANDWIDTH      => "OPTIMIZED",        -- "HIGH", "LOW" or "OPTIMIZED" 
-               CLKFBOUT_MULT  => 16,                 -- Multiply value for all CLKOUT clock outputs (1-64)
-               CLKFBOUT_PHASE => 0.0,                -- Phase offset in degrees of the clock feedback output (0.0-360.0).
-               CLKIN_PERIOD   => 31.25,              -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-                                                     -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-               CLKOUT0_DIVIDE => 4,                  -- 32MHz * 16 / 4 = 128MHz. Adjust clk_freq_mhz constant (above) if you change this.
-               CLKOUT1_DIVIDE => 1,
-               CLKOUT2_DIVIDE => 1,       
-               CLKOUT3_DIVIDE => 1,
-               CLKOUT4_DIVIDE => 1,       
-               CLKOUT5_DIVIDE => 1,
-                                               -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
-               CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5,
-               CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5,
-               CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,
-                                               -- CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-               CLKOUT0_PHASE => 0.0,      CLKOUT1_PHASE => 0.0, -- Capture clock
-               CLKOUT2_PHASE => 0.0,      CLKOUT3_PHASE => 0.0,
-               CLKOUT4_PHASE => 0.0,      CLKOUT5_PHASE => 0.0,
-
-               CLK_FEEDBACK => "CLKFBOUT",           -- Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
-               COMPENSATION => "SYSTEM_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL" 
-               DIVCLK_DIVIDE => 1,                   -- Division value for all output clocks (1-52)
-               REF_JITTER => 0.1,                    -- Reference Clock Jitter in UI (0.000-0.999).
-               RESET_ON_LOSS_OF_LOCK => FALSE        -- Must be set to FALSE
-           ) 
-   port map(
-               CLKIN    => sysclk_32m,   -- 1-bit input: Clock input
-               CLKFBOUT => clk_feedback, -- 1-bit output: PLL_BASE feedback output
-               CLKFBIN  => clk_feedback, -- 1-bit input: Feedback clock input
-                                         -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
-               CLKOUT0 => clk_unbuffered, -- 64MHz clock output
-               CLKOUT1 => open,
-               CLKOUT2 => open,      
-               CLKOUT3 => open,
-               CLKOUT4 => open,      
-               CLKOUT5 => open,
-               LOCKED  => open,  -- 1-bit output: PLL_BASE lock status output
-               RST     => '0'    -- 1-bit input: Reset input
+   pll: entity work.pll
+   port map (
+               areset => open,
+               inclk0 => sys_clk_pad_i,
+               c0 => sdram_clk, -- 100 Mhz - 180 deg
+               c1 => clk, -- 100 Mhz
+               locked => open
            );
 
-   -- Buffering of clocks
-   BUFG_clk: BUFG 
-   port map(
-               O => clk,     
-               I => clk_unbuffered
-            );
-
 end Behavioral;