top_level.vhd 18 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| Top level module: connects modules to each other and the outside world |--
  10. --+-------------------------------------------------------------------------+--
  11. --
  12. -- See README.txt for more details
  13. --
  14. library IEEE;
  15. use IEEE.STD_LOGIC_1164.ALL;
  16. use IEEE.NUMERIC_STD.ALL;
  17. library UNISIM;
  18. use UNISIM.VComponents.all;
  19. entity top_level is
  20. Port ( sysclk_32m : in std_logic;
  21. sys_clk_pad_i : in std_logic;
  22. rst_n_pad_i : in std_logic;
  23. leds : out std_logic_vector(4 downto 0);
  24. reset_button : in std_logic;
  25. console_select : in std_logic;
  26. -- UART0 (to FTDI USB chip, no flow control)
  27. serial_rx : in std_logic;
  28. serial_tx : out std_logic;
  29. -- UART0 (to MAX3232 level shifter chip, hardware flow control)
  30. uart1_rx : in std_logic;
  31. uart1_cts : in std_logic;
  32. uart1_tx : out std_logic;
  33. uart1_rts : out std_logic;
  34. -- SPI flash chip
  35. flash_spi_cs : out std_logic;
  36. flash_spi_clk : out std_logic;
  37. flash_spi_mosi : out std_logic;
  38. flash_spi_miso : in std_logic;
  39. -- SD card socket
  40. sdcard_spi_cs : out std_logic;
  41. sdcard_spi_clk : out std_logic;
  42. sdcard_spi_mosi : out std_logic;
  43. sdcard_spi_miso : in std_logic;
  44. -- SDRAM chip
  45. SDRAM_CLK : out std_logic;
  46. SDRAM_CKE : out std_logic;
  47. SDRAM_CS : out std_logic;
  48. SDRAM_nRAS : out std_logic;
  49. SDRAM_nCAS : out std_logic;
  50. SDRAM_nWE : out std_logic;
  51. SDRAM_DQM : out std_logic_vector( 1 downto 0);
  52. SDRAM_ADDR : out std_logic_vector (12 downto 0);
  53. SDRAM_BA : out std_logic_vector( 1 downto 0);
  54. SDRAM_DQ : inout std_logic_vector (15 downto 0)
  55. );
  56. end top_level;
  57. architecture Behavioral of top_level is
  58. constant clk_freq_mhz : natural := 100; -- this is the frequency which the PLL outputs, in MHz.
  59. -- SDRAM configuration
  60. constant sdram_address_width : natural := 24;
  61. constant sdram_column_bits : natural := 9;
  62. constant cycles_per_refresh : natural := (64000*clk_freq_mhz)/8192-1;
  63. -- For simulation, we don't need a long init stage. but for real DRAM we need approx 101us.
  64. -- The constant below has a different value when interpreted by the synthesis and simulator
  65. -- tools in order to achieve the desired timing in each.
  66. constant sdram_startup_cycles: natural := 101 * clk_freq_mhz
  67. -- pragma translate_off
  68. - 10000 -- reduce the value the simulator uses
  69. -- pragma translate_on
  70. ;
  71. -- signals for clocking
  72. signal clk_feedback : std_logic; -- PLL clock feedback
  73. signal clk_unbuffered : std_logic; -- unbuffered system clock
  74. signal clk : std_logic; -- buffered system clock (all logic should be clocked by this)
  75. -- console latch
  76. signal console_select_clk1 : std_logic;
  77. signal console_select_sync : std_logic;
  78. signal swap_uart01 : std_logic := '0';
  79. -- system reset signals
  80. signal power_on_reset : std_logic_vector(1 downto 0) := (others => '1');
  81. signal system_reset : std_logic;
  82. signal reset_button_clk1 : std_logic;
  83. signal reset_button_sync : std_logic; -- reset button signal, synchronised to our clock
  84. signal reset_request_uart : std_logic; -- reset request signal from FTDI UART (when you send "!~!~!~" to the UART, this line is asserted)
  85. -- CPU control
  86. signal coldboot : std_logic;
  87. signal cpu_clk_enable : std_logic;
  88. signal cpu_m1_cycle : std_logic;
  89. signal cpu_req_mem : std_logic;
  90. signal cpu_req_io : std_logic;
  91. signal req_mem : std_logic;
  92. signal req_io : std_logic;
  93. signal req_read : std_logic;
  94. signal req_write : std_logic;
  95. signal virtual_address : std_logic_vector(15 downto 0);
  96. signal physical_address : std_logic_vector(25 downto 0);
  97. signal mem_wait : std_logic;
  98. signal cpu_wait : std_logic;
  99. signal dram_wait : std_logic;
  100. signal mmu_wait : std_logic;
  101. signal spimaster0_wait : std_logic;
  102. signal spimaster1_wait : std_logic;
  103. -- chip selects
  104. signal mmu_cs : std_logic;
  105. signal rom_cs : std_logic;
  106. signal sram_cs : std_logic;
  107. signal dram_cs : std_logic;
  108. signal uartA_cs : std_logic;
  109. signal uartB_cs : std_logic;
  110. signal uart0_cs : std_logic;
  111. signal uart1_cs : std_logic;
  112. signal timer_cs : std_logic;
  113. signal spimaster0_cs : std_logic;
  114. signal spimaster1_cs : std_logic;
  115. signal clkscale_cs : std_logic;
  116. signal gpio_cs : std_logic;
  117. -- data bus
  118. signal cpu_data_in : std_logic_vector(7 downto 0);
  119. signal cpu_data_out : std_logic_vector(7 downto 0);
  120. signal rom_data_out : std_logic_vector(7 downto 0);
  121. signal sram_data_out : std_logic_vector(7 downto 0);
  122. signal dram_data_out : std_logic_vector(7 downto 0);
  123. signal uart0_data_out : std_logic_vector(7 downto 0);
  124. signal uart1_data_out : std_logic_vector(7 downto 0);
  125. signal timer_data_out : std_logic_vector(7 downto 0);
  126. signal spimaster0_data_out : std_logic_vector(7 downto 0);
  127. signal spimaster1_data_out : std_logic_vector(7 downto 0);
  128. signal mmu_data_out : std_logic_vector(7 downto 0);
  129. signal clkscale_out : std_logic_vector(7 downto 0);
  130. signal gpio_data_out : std_logic_vector(7 downto 0);
  131. -- GPIO
  132. signal gpio_input : std_logic_vector(7 downto 0);
  133. signal gpio_output : std_logic_vector(7 downto 0);
  134. -- Interrupts
  135. signal cpu_interrupt_in : std_logic;
  136. signal timer_interrupt : std_logic;
  137. signal uart0_interrupt : std_logic;
  138. signal uart1_interrupt : std_logic;
  139. begin
  140. -- Hold CPU reset high for 8 clock cycles on startup,
  141. -- and when the user presses their reset button.
  142. process(clk)
  143. begin
  144. if rising_edge(clk) then
  145. -- Xilinx advises using two flip-flops are used to bring external
  146. -- signals which feed control logic into our clock domain.
  147. reset_button_clk1 <= reset_button;
  148. reset_button_sync <= reset_button_clk1;
  149. console_select_clk1 <= console_select;
  150. console_select_sync <= console_select_clk1;
  151. -- reset the system when requested
  152. if (power_on_reset(0) = '1' or reset_button_sync = '1' or reset_request_uart = '1') then
  153. system_reset <= '1';
  154. else
  155. system_reset <= '0';
  156. end if;
  157. -- shift 0s into the power_on_reset shift register from the MSB
  158. power_on_reset <= '0' & power_on_reset(power_on_reset'length-1 downto 1);
  159. -- During reset, latch the console select jumper. This is used to
  160. -- optionally swap over the UART roles and move the system console to
  161. -- the second serial port on the IO board.
  162. if system_reset = '1' then
  163. swap_uart01 <= console_select_sync;
  164. else
  165. swap_uart01 <= swap_uart01;
  166. end if;
  167. end if;
  168. end process;
  169. -- GPIO input signal routing
  170. gpio_input <= coldboot & swap_uart01 & "000000";
  171. -- GPIO output signal routing
  172. leds(0) <= gpio_output(0);
  173. leds(1) <= gpio_output(1);
  174. leds(2) <= gpio_output(2);
  175. leds(3) <= gpio_output(3);
  176. -- User LED (LED1) on Papilio Pro indicates when the CPU is being asked to wait (eg by the SDRAM cache)
  177. leds(4) <= cpu_wait;
  178. -- Interrupt signal for the CPU
  179. cpu_interrupt_in <= (timer_interrupt or uart0_interrupt or uart1_interrupt);
  180. -- Z80 CPU core
  181. cpu: entity work.Z80cpu
  182. port map (
  183. reset => system_reset,
  184. clk => clk,
  185. clk_enable => cpu_clk_enable,
  186. m1_cycle => cpu_m1_cycle,
  187. interrupt => cpu_interrupt_in,
  188. nmi => '0',
  189. req_mem => cpu_req_mem,
  190. req_io => cpu_req_io,
  191. req_read => req_read,
  192. req_write => req_write,
  193. mem_wait => cpu_wait,
  194. address => virtual_address,
  195. data_in => cpu_data_in,
  196. data_out => cpu_data_out
  197. );
  198. -- Memory management unit
  199. mmu: entity work.MMU
  200. port map (
  201. reset => system_reset,
  202. clk => clk,
  203. address_in => virtual_address,
  204. address_out => physical_address,
  205. cpu_data_in => cpu_data_out,
  206. cpu_data_out => mmu_data_out,
  207. req_mem_in => cpu_req_mem,
  208. req_io_in => cpu_req_io,
  209. req_mem_out => req_mem,
  210. req_io_out => req_io,
  211. req_read => req_read,
  212. req_write => req_write,
  213. io_cs => mmu_cs,
  214. cpu_wait => mmu_wait,
  215. access_violated => open -- for now!!
  216. );
  217. -- This process determines which IO or memory device the CPU is addressing
  218. -- and asserts the appropriate chip select signals.
  219. cs_process: process(req_mem, req_io, physical_address, virtual_address, uartA_cs, uartB_cs, swap_uart01)
  220. begin
  221. -- memory chip selects: default to unselected
  222. rom_cs <= '0';
  223. sram_cs <= '0';
  224. dram_cs <= '0';
  225. -- io chip selects: default to unselected
  226. uartA_cs <= '0';
  227. uartB_cs <= '0';
  228. mmu_cs <= '0';
  229. timer_cs <= '0';
  230. spimaster0_cs <= '0';
  231. spimaster1_cs <= '0';
  232. clkscale_cs <= '0';
  233. gpio_cs <= '0';
  234. -- memory address decoding
  235. -- address space is organised as:
  236. -- 0x0 000 000 - 0x0 FFF FFF 16MB DRAM (cached) (mapped to 8MB DRAM twice)
  237. -- 0x1 000 000 - 0x1 FFF FFF 16MB DRAM (uncached) (mapped to 8MB DRAM twice)
  238. -- 0x2 000 000 - 0x2 000 FFF 4KB monitor ROM (FPGA block RAM)
  239. -- 0x2 001 000 - 0x2 001 FFF 4KB SRAM (FPGA block RAM)
  240. -- 0x2 002 000 - 0x3 FFF FFF unused space for future expansion
  241. if physical_address(25) = '0' then
  242. -- bottom 32MB: DRAM handles this
  243. dram_cs <= req_mem;
  244. else
  245. -- top 32MB: other memory devices
  246. case physical_address(24 downto 12) is
  247. when "0000000000000" => rom_cs <= req_mem;
  248. when "0000000000001" => sram_cs <= req_mem;
  249. when others => -- undecoded memory space
  250. end case;
  251. end if;
  252. -- IO address decoding
  253. case virtual_address(7 downto 3) is
  254. when "00000" => uartA_cs <= req_io; -- 00 ... 07
  255. when "00010" => timer_cs <= req_io; -- 10 ... 17
  256. when "00011" => spimaster0_cs <= req_io; -- 18 ... 1F
  257. when "00100" => gpio_cs <= req_io; -- 20 ... 27
  258. when "00101" => uartB_cs <= req_io; -- 28 ... 2F
  259. when "00110" => spimaster1_cs <= req_io; -- 30 ... 37
  260. -- unused ports
  261. when "11110" => clkscale_cs <= req_io; -- F0 ... F7
  262. when "11111" => mmu_cs <= req_io; -- F8 ... FF
  263. when others =>
  264. end case;
  265. -- send the UART chip select to the appropriate UART depending
  266. -- on whether they have been swapped over or not.
  267. if swap_uart01 = '0' then
  268. uart0_cs <= uartB_cs;
  269. uart1_cs <= uartA_cs;
  270. else
  271. uart0_cs <= uartA_cs;
  272. uart1_cs <= uartB_cs;
  273. end if;
  274. end process;
  275. -- the selected memory device can request the CPU to wait
  276. mem_wait <=
  277. dram_wait when dram_cs='1' else
  278. spimaster0_wait when spimaster0_cs='1' else
  279. spimaster1_wait when spimaster1_cs='1' else
  280. '0';
  281. -- the MMU can, at any time, request the CPU wait (this is used when
  282. -- translating IO to memory requests, to implement a wait state for
  283. -- the "17th page")
  284. cpu_wait <= (mem_wait or mmu_wait);
  285. -- input mux for CPU data bus
  286. cpu_data_in <=
  287. rom_data_out when rom_cs='1' else
  288. dram_data_out when dram_cs='1' else
  289. sram_data_out when sram_cs='1' else
  290. uart0_data_out when uart0_cs='1' else
  291. uart1_data_out when uart1_cs='1' else
  292. timer_data_out when timer_cs='1' else
  293. mmu_data_out when mmu_cs='1' else
  294. spimaster0_data_out when spimaster0_cs='1' else
  295. spimaster1_data_out when spimaster1_cs='1' else
  296. clkscale_out when clkscale_cs='1' else
  297. gpio_data_out when gpio_cs='1' else
  298. rom_data_out; -- default case
  299. dram: entity work.DRAM
  300. generic map(
  301. sdram_address_width => sdram_address_width,
  302. sdram_column_bits => sdram_column_bits,
  303. sdram_startup_cycles=> sdram_startup_cycles,
  304. cycles_per_refresh => cycles_per_refresh
  305. )
  306. port map(
  307. clk => clk,
  308. reset => '0', -- important to note that we DO NOT reset the SDRAM controller on reset (it would stop refreshing, which would be bad)
  309. -- interface to synthetic CPU
  310. cs => dram_cs,
  311. req_read => req_read,
  312. req_write => req_write,
  313. mem_address => physical_address(24 downto 0),
  314. mem_wait => dram_wait,
  315. data_in => cpu_data_out,
  316. data_out => dram_data_out,
  317. coldboot => coldboot,
  318. -- interface to hardware SDRAM chip
  319. SDRAM_CLK => open,
  320. SDRAM_CKE => SDRAM_CKE,
  321. SDRAM_CS => SDRAM_CS,
  322. SDRAM_nRAS => SDRAM_nRAS,
  323. SDRAM_nCAS => SDRAM_nCAS,
  324. SDRAM_nWE => SDRAM_nWE,
  325. SDRAM_DQM => SDRAM_DQM,
  326. SDRAM_BA => SDRAM_BA,
  327. SDRAM_ADDR => SDRAM_ADDR,
  328. SDRAM_DQ => SDRAM_DQ
  329. );
  330. -- 4KB system ROM implemented in block RAM
  331. rom: entity work.MonZ80
  332. port map(
  333. clk => clk,
  334. A => physical_address(11 downto 0),
  335. D => rom_data_out
  336. );
  337. -- 4KB SRAM memory implemented in block RAM
  338. sram: entity work.SSRAM
  339. generic map(
  340. AddrWidth => 12
  341. )
  342. port map(
  343. clk => clk,
  344. ce => sram_cs,
  345. we => req_write,
  346. A => physical_address(11 downto 0),
  347. DIn => cpu_data_out,
  348. DOut => sram_data_out
  349. );
  350. -- UART connected to FTDI USB UART
  351. uart0: entity work.uart_interface
  352. generic map ( watch_for_reset => 1, clk_frequency => (clk_freq_mhz * 1000000) )
  353. port map(
  354. clk => clk,
  355. reset => system_reset,
  356. reset_out => reset_request_uart, -- result of watching for reset sequence on the input
  357. serial_in => serial_rx,
  358. serial_out => serial_tx,
  359. serial_rts => open,
  360. serial_cts => '0',
  361. cpu_address => virtual_address(2 downto 0),
  362. cpu_data_in => cpu_data_out,
  363. cpu_data_out => uart0_data_out,
  364. enable => uart0_cs,
  365. interrupt => uart0_interrupt,
  366. req_read => req_read,
  367. req_write => req_write
  368. );
  369. -- Timer device (internally scales the clock to 1MHz)
  370. timer: entity work.timer
  371. generic map ( clk_frequency => (clk_freq_mhz * 1000000) )
  372. port map(
  373. clk => clk,
  374. reset => system_reset,
  375. cpu_address => virtual_address(2 downto 0),
  376. data_in => cpu_data_out,
  377. data_out => timer_data_out,
  378. enable => timer_cs,
  379. req_read => req_read,
  380. req_write => req_write,
  381. interrupt => timer_interrupt
  382. );
  383. -- GPIO to FPGA pins and/or internal signals
  384. gpio: entity work.gpio
  385. port map(
  386. clk => clk,
  387. reset => system_reset,
  388. cpu_address => virtual_address(2 downto 0),
  389. data_in => cpu_data_out,
  390. data_out => gpio_data_out,
  391. enable => gpio_cs,
  392. read_notwrite => req_read,
  393. input_pins => gpio_input,
  394. output_pins => gpio_output
  395. );
  396. -- An attempt to allow the CPU clock to be scaled back to run
  397. -- at slower speeds without affecting the clock signal sent to
  398. -- IO devices. Basically this was an attempt to make CP/M games
  399. -- playable :) Very limited success. Might be simpler to remove
  400. -- this entirely.
  401. clkscale: entity work.clkscale
  402. port map (
  403. clk => clk,
  404. reset => system_reset,
  405. cpu_address => virtual_address(2 downto 0),
  406. data_in => cpu_data_out,
  407. data_out => clkscale_out,
  408. enable => clkscale_cs,
  409. read_notwrite => req_read,
  410. clk_enable => cpu_clk_enable
  411. );
  412. pll: entity work.pll
  413. port map (
  414. areset => open,
  415. inclk0 => sys_clk_pad_i,
  416. c0 => sdram_clk, -- 100 Mhz - 180 deg
  417. c1 => clk, -- 100 Mhz
  418. locked => open
  419. );
  420. end Behavioral;