Browse Source

Build for DE0, only SDRAM not working for now.

Godzil 9 years ago
parent
commit
19e0d870d4
9 changed files with 973 additions and 83 deletions
  1. 6 0
      .gitignore
  2. 6 2
      Makefile
  3. 625 0
      de0.tcl
  4. 44 0
      vhdl/DE0_SEG7.vhd
  5. 1 1
      vhdl/DRAM.vhd
  6. 8 8
      vhdl/SDRAM_Controller.vhd
  7. 1 1
      vhdl/pll.vhd
  8. 145 0
      vhdl/spimaster.vhd
  9. 137 71
      vhdl/top_level.vhd

+ 6 - 0
.gitignore

@@ -0,0 +1,6 @@
+*.bak
+output_files/
+db/
+greybox_tmp/
+incremental_db/
+simulation/

+ 6 - 2
Makefile

@@ -1,4 +1,4 @@
-DESIGN_NAME = de0_nano
+DESIGN_NAME = de0
 QUARTUS_OPTIONS =
 
 
@@ -20,4 +20,8 @@ sta: asm
 	quartus_sta $(QUARTUS_OPTIONS) $(DESIGN_NAME)
 
 load: asm
-	quartus_pgm --mode=jtag -o p\;$(DESIGN_NAME).sof
+	quartus_pgm --mode=jtag -o p\;output_files/$(DESIGN_NAME).sof
+
+loadonly:
+	quartus_sh $(QUARTUS_OPTIONS)
+	quartus_pgm --mode=jtag -o p\;output_files/$(DESIGN_NAME).sof

+ 625 - 0
de0.tcl

@@ -0,0 +1,625 @@
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors.  Please refer to the
+# applicable agreement for further details.
+
+# Quartus II: Generate Tcl File for Project
+# File: de0_nano.tcl
+# Generated on: Sat Sep  6 02:27:17 2014
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+	if {[string compare $quartus(project) "de0"]} {
+		puts "Project de0 is not open"
+		set make_assignments 0
+	}
+} else {
+	# Only open if not already open
+	if {[project_exists de0]} {
+		project_open -revision de0 de0
+	} else {
+		project_new -revision de0 de0
+	}
+	set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+	# Define the FPGA Type and other parameters
+	set_global_assignment -name FAMILY "Cyclone III"
+	set_global_assignment -name DEVICE EP3C16F484C6
+	set_global_assignment -name TOP_LEVEL_ENTITY top_level
+	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
+	set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:15:50  DECEMBER 10, 2014"
+	set_global_assignment -name LAST_QUARTUS_VERSION 13.0
+	set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+	set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+	set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+	set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+	set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+	set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+	set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+	set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+	# VHDL Files
+	set_global_assignment -name VHDL_FILE vhdl/DE0_SEG7.vhd
+	set_global_assignment -name VHDL_FILE vhdl/uart_interface.vhd
+	set_global_assignment -name VHDL_FILE vhdl/uart.vhd
+	set_global_assignment -name VHDL_FILE vhdl/top_level.vhd
+	set_global_assignment -name VHDL_FILE vhdl/timer.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80se.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_Reg.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_Pack.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_MCode.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80_ALU.vhd
+	set_global_assignment -name VHDL_FILE vhdl/T80.vhd
+	set_global_assignment -name VHDL_FILE vhdl/SSRAM.vhd
+	set_global_assignment -name VHDL_FILE vhdl/SDRAM_Controller.vhd
+	set_global_assignment -name VHDL_FILE vhdl/pll.vhd
+	set_global_assignment -name VHDL_FILE vhdl/MonZ80.vhd
+	set_global_assignment -name VHDL_FILE vhdl/MMU.vhd
+	set_global_assignment -name VHDL_FILE vhdl/gpio.vhd
+	set_global_assignment -name VHDL_FILE vhdl/fifo.vhd
+	set_global_assignment -name VHDL_FILE vhdl/DRAM.vhd
+	set_global_assignment -name VHDL_FILE vhdl/spimaster.vhd
+	set_global_assignment -name VHDL_FILE vhdl/clkscale.vhd
+	set_global_assignment -name VHDL_FILE vhdl/Z80cpu.vhd
+	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# Assign Port to IOs
+	set_location_assignment PIN_B1 -to LEDG[9]
+	set_location_assignment PIN_B2 -to LEDG[8]
+	set_location_assignment PIN_C2 -to LEDG[7]
+	set_location_assignment PIN_C1 -to LEDG[6]
+	set_location_assignment PIN_E1 -to LEDG[5]
+	set_location_assignment PIN_F2 -to LEDG[4]
+	set_location_assignment PIN_H1 -to LEDG[3]
+	set_location_assignment PIN_J3 -to LEDG[2]
+	set_location_assignment PIN_J2 -to LEDG[1]
+	set_location_assignment PIN_J1 -to LEDG[0]
+	set_location_assignment PIN_D2 -to SW[9]
+	set_location_assignment PIN_E4 -to SW[8]
+	set_location_assignment PIN_E3 -to SW[7]
+	set_location_assignment PIN_H7 -to SW[6]
+	set_location_assignment PIN_J7 -to SW[5]
+	set_location_assignment PIN_G5 -to SW[4]
+	set_location_assignment PIN_G4 -to SW[3]
+	set_location_assignment PIN_H6 -to SW[2]
+	set_location_assignment PIN_H5 -to SW[1]
+	set_location_assignment PIN_J6 -to SW[0]
+	set_location_assignment PIN_F1 -to BUTTON[2]
+	set_location_assignment PIN_G3 -to BUTTON[1]
+	set_location_assignment PIN_H2 -to BUTTON[0]
+	set_location_assignment PIN_R2 -to FL_ADDR[21]
+	set_location_assignment PIN_P3 -to FL_ADDR[20]
+	set_location_assignment PIN_P1 -to FL_ADDR[19]
+	set_location_assignment PIN_M6 -to FL_ADDR[18]
+	set_location_assignment PIN_M5 -to FL_ADDR[17]
+	set_location_assignment PIN_AA2 -to FL_ADDR[16]
+	set_location_assignment PIN_L6 -to FL_ADDR[15]
+	set_location_assignment PIN_L7 -to FL_ADDR[14]
+	set_location_assignment PIN_M1 -to FL_ADDR[13]
+	set_location_assignment PIN_M2 -to FL_ADDR[12]
+	set_location_assignment PIN_M3 -to FL_ADDR[11]
+	set_location_assignment PIN_N1 -to FL_ADDR[10]
+	set_location_assignment PIN_N2 -to FL_ADDR[9]
+	set_location_assignment PIN_P2 -to FL_ADDR[8]
+	set_location_assignment PIN_M4 -to FL_ADDR[7]
+	set_location_assignment PIN_M8 -to FL_ADDR[6]
+	set_location_assignment PIN_N6 -to FL_ADDR[5]
+	set_location_assignment PIN_N5 -to FL_ADDR[4]
+	set_location_assignment PIN_N7 -to FL_ADDR[3]
+	set_location_assignment PIN_P6 -to FL_ADDR[2]
+	set_location_assignment PIN_P5 -to FL_ADDR[1]
+	set_location_assignment PIN_P7 -to FL_ADDR[0]
+	set_location_assignment PIN_AA1 -to FL_BYTE_N
+	set_location_assignment PIN_N8 -to FL_CE_N
+	set_location_assignment PIN_R7 -to FL_DQ[0]
+	set_location_assignment PIN_P8 -to FL_DQ[1]
+	set_location_assignment PIN_R8 -to FL_DQ[2]
+	set_location_assignment PIN_U1 -to FL_DQ[3]
+	set_location_assignment PIN_V2 -to FL_DQ[4]
+	set_location_assignment PIN_V3 -to FL_DQ[5]
+	set_location_assignment PIN_W1 -to FL_DQ[6]
+	set_location_assignment PIN_Y1 -to FL_DQ[7]
+	set_location_assignment PIN_T5 -to FL_DQ[8]
+	set_location_assignment PIN_T7 -to FL_DQ[9]
+	set_location_assignment PIN_T4 -to FL_DQ[10]
+	set_location_assignment PIN_U2 -to FL_DQ[11]
+	set_location_assignment PIN_V1 -to FL_DQ[12]
+	set_location_assignment PIN_V4 -to FL_DQ[13]
+	set_location_assignment PIN_W2 -to FL_DQ[14]
+	set_location_assignment PIN_R6 -to FL_OE_N
+	set_location_assignment PIN_R1 -to FL_RST_N
+	set_location_assignment PIN_M7 -to FL_RY
+	set_location_assignment PIN_P4 -to FL_WE_N
+	set_location_assignment PIN_T3 -to FL_WP_N
+	set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+	set_location_assignment PIN_U7 -to GPIO0_D[31]
+	set_location_assignment PIN_V5 -to GPIO0_D[30]
+	set_location_assignment PIN_W6 -to GPIO0_D[29]
+	set_location_assignment PIN_W7 -to GPIO0_D[28]
+	set_location_assignment PIN_V8 -to GPIO0_D[27]
+	set_location_assignment PIN_T8 -to GPIO0_D[26]
+	set_location_assignment PIN_W10 -to GPIO0_D[25]
+	set_location_assignment PIN_Y10 -to GPIO0_D[24]
+	set_location_assignment PIN_V11 -to GPIO0_D[23]
+	set_location_assignment PIN_R10 -to GPIO0_D[22]
+	set_location_assignment PIN_V12 -to GPIO0_D[21]
+	set_location_assignment PIN_U13 -to GPIO0_D[20]
+	set_location_assignment PIN_W13 -to GPIO0_D[19]
+	set_location_assignment PIN_Y13 -to GPIO0_D[18]
+	set_location_assignment PIN_U14 -to GPIO0_D[17]
+	set_location_assignment PIN_V14 -to GPIO0_D[16]
+	set_location_assignment PIN_AA4 -to GPIO0_D[15]
+	set_location_assignment PIN_AB4 -to GPIO0_D[14]
+	set_location_assignment PIN_AA5 -to GPIO0_D[13]
+	set_location_assignment PIN_AB5 -to GPIO0_D[12]
+	set_location_assignment PIN_AA8 -to GPIO0_D[11]
+	set_location_assignment PIN_AB8 -to GPIO0_D[10]
+	set_location_assignment PIN_AA10 -to GPIO0_D[9]
+	set_location_assignment PIN_AB10 -to GPIO0_D[8]
+	set_location_assignment PIN_AA13 -to GPIO0_D[7]
+	set_location_assignment PIN_AB13 -to GPIO0_D[6]
+	set_location_assignment PIN_AB14 -to GPIO0_D[5]
+	set_location_assignment PIN_AA14 -to GPIO0_D[4]
+	set_location_assignment PIN_AB15 -to GPIO0_D[3]
+	set_location_assignment PIN_AA15 -to GPIO0_D[2]
+	set_location_assignment PIN_AA16 -to GPIO0_D[1]
+	set_location_assignment PIN_AB16 -to GPIO0_D[0]
+	set_location_assignment PIN_AB12 -to GPIO0_CLKIN[0]
+	set_location_assignment PIN_AA12 -to GPIO0_CLKIN[1]
+	set_location_assignment PIN_AB3 -to GPIO0_CLKOUT[0]
+	set_location_assignment PIN_AA3 -to GPIO0_CLKOUT[1]
+	set_location_assignment PIN_AA11 -to GPIO1_CLKIN[1]
+	set_location_assignment PIN_AB11 -to GPIO1_CLKIN[0]
+	set_location_assignment PIN_T16 -to GPIO1_CLKOUT[1]
+	set_location_assignment PIN_R16 -to GPIO1_CLKOUT[0]
+	set_location_assignment PIN_V7 -to GPIO1_D[31]
+	set_location_assignment PIN_V6 -to GPIO1_D[30]
+	set_location_assignment PIN_U8 -to GPIO1_D[29]
+	set_location_assignment PIN_Y7 -to GPIO1_D[28]
+	set_location_assignment PIN_T9 -to GPIO1_D[27]
+	set_location_assignment PIN_U9 -to GPIO1_D[26]
+	set_location_assignment PIN_T10 -to GPIO1_D[25]
+	set_location_assignment PIN_U10 -to GPIO1_D[24]
+	set_location_assignment PIN_R12 -to GPIO1_D[23]
+	set_location_assignment PIN_R11 -to GPIO1_D[22]
+	set_location_assignment PIN_T12 -to GPIO1_D[21]
+	set_location_assignment PIN_U12 -to GPIO1_D[20]
+	set_location_assignment PIN_R14 -to GPIO1_D[19]
+	set_location_assignment PIN_T14 -to GPIO1_D[18]
+	set_location_assignment PIN_AB7 -to GPIO1_D[17]
+	set_location_assignment PIN_AA7 -to GPIO1_D[16]
+	set_location_assignment PIN_AA9 -to GPIO1_D[15]
+	set_location_assignment PIN_AB9 -to GPIO1_D[14]
+	set_location_assignment PIN_V15 -to GPIO1_D[13]
+	set_location_assignment PIN_W15 -to GPIO1_D[12]
+	set_location_assignment PIN_T15 -to GPIO1_D[11]
+	set_location_assignment PIN_U15 -to GPIO1_D[10]
+	set_location_assignment PIN_W17 -to GPIO1_D[9]
+	set_location_assignment PIN_Y17 -to GPIO1_D[8]
+	set_location_assignment PIN_AB17 -to GPIO1_D[7]
+	set_location_assignment PIN_AA17 -to GPIO1_D[6]
+	set_location_assignment PIN_AA18 -to GPIO1_D[5]
+	set_location_assignment PIN_AB18 -to GPIO1_D[4]
+	set_location_assignment PIN_AB19 -to GPIO1_D[3]
+	set_location_assignment PIN_AA19 -to GPIO1_D[2]
+	set_location_assignment PIN_AB20 -to GPIO1_D[1]
+	set_location_assignment PIN_AA20 -to GPIO1_D[0]
+	set_location_assignment PIN_P22 -to PS2_KBCLK
+	set_location_assignment PIN_P21 -to PS2_KBDAT
+	set_location_assignment PIN_R21 -to PS2_MSCLK
+	set_location_assignment PIN_R22 -to PS2_MSDAT
+	set_location_assignment PIN_U22 -to UART_RXD
+	set_location_assignment PIN_U21 -to UART_TXD
+	set_location_assignment PIN_V22 -to UART_RTS
+	set_location_assignment PIN_V21 -to UART_CTS
+	set_location_assignment PIN_Y21 -to SD_CLK
+	set_location_assignment PIN_Y22 -to SD_CMD
+	set_location_assignment PIN_AA22 -to SD_DAT0
+	set_location_assignment PIN_W21 -to SD_DAT3
+	set_location_assignment PIN_W20 -to SD_WP_N
+	set_location_assignment PIN_C20 -to LCD_DATA[7]
+	set_location_assignment PIN_D20 -to LCD_DATA[6]
+	set_location_assignment PIN_B21 -to LCD_DATA[5]
+	set_location_assignment PIN_B22 -to LCD_DATA[4]
+	set_location_assignment PIN_C21 -to LCD_DATA[3]
+	set_location_assignment PIN_C22 -to LCD_DATA[2]
+	set_location_assignment PIN_D21 -to LCD_DATA[1]
+	set_location_assignment PIN_D22 -to LCD_DATA[0]
+	set_location_assignment PIN_E22 -to LCD_RW
+	set_location_assignment PIN_F22 -to LCD_RS
+	set_location_assignment PIN_E21 -to LCD_EN
+	set_location_assignment PIN_F21 -to LCD_BLON
+	set_location_assignment PIN_J21 -to VGA_G[3]
+	set_location_assignment PIN_K17 -to VGA_G[2]
+	set_location_assignment PIN_J17 -to VGA_G[1]
+	set_location_assignment PIN_H22 -to VGA_G[0]
+	set_location_assignment PIN_L21 -to VGA_HS
+	set_location_assignment PIN_L22 -to VGA_VS
+	set_location_assignment PIN_H21 -to VGA_R[3]
+	set_location_assignment PIN_H20 -to VGA_R[2]
+	set_location_assignment PIN_H17 -to VGA_R[1]
+	set_location_assignment PIN_H19 -to VGA_R[0]
+	set_location_assignment PIN_K18 -to VGA_B[3]
+	set_location_assignment PIN_J22 -to VGA_B[2]
+	set_location_assignment PIN_K21 -to VGA_B[1]
+	set_location_assignment PIN_K22 -to VGA_B[0]
+	set_location_assignment PIN_G21 -to CLOCK_50
+	set_location_assignment PIN_E11 -to HEX0_D[0]
+	set_location_assignment PIN_F11 -to HEX0_D[1]
+	set_location_assignment PIN_H12 -to HEX0_D[2]
+	set_location_assignment PIN_H13 -to HEX0_D[3]
+	set_location_assignment PIN_G12 -to HEX0_D[4]
+	set_location_assignment PIN_F12 -to HEX0_D[5]
+	set_location_assignment PIN_F13 -to HEX0_D[6]
+	set_location_assignment PIN_D13 -to HEX0_DP
+	set_location_assignment PIN_A15 -to HEX1_D[6]
+	set_location_assignment PIN_E14 -to HEX1_D[5]
+	set_location_assignment PIN_B14 -to HEX1_D[4]
+	set_location_assignment PIN_A14 -to HEX1_D[3]
+	set_location_assignment PIN_C13 -to HEX1_D[2]
+	set_location_assignment PIN_B13 -to HEX1_D[1]
+	set_location_assignment PIN_A13 -to HEX1_D[0]
+	set_location_assignment PIN_B15 -to HEX1_DP
+	set_location_assignment PIN_F14 -to HEX2_D[6]
+	set_location_assignment PIN_B17 -to HEX2_D[5]
+	set_location_assignment PIN_A17 -to HEX2_D[4]
+	set_location_assignment PIN_E15 -to HEX2_D[3]
+	set_location_assignment PIN_B16 -to HEX2_D[2]
+	set_location_assignment PIN_A16 -to HEX2_D[1]
+	set_location_assignment PIN_D15 -to HEX2_D[0]
+	set_location_assignment PIN_A18 -to HEX2_DP
+	set_location_assignment PIN_G15 -to HEX3_D[6]
+	set_location_assignment PIN_D19 -to HEX3_D[5]
+	set_location_assignment PIN_C19 -to HEX3_D[4]
+	set_location_assignment PIN_B19 -to HEX3_D[3]
+	set_location_assignment PIN_A19 -to HEX3_D[2]
+	set_location_assignment PIN_F15 -to HEX3_D[1]
+	set_location_assignment PIN_B18 -to HEX3_D[0]
+	set_location_assignment PIN_G16 -to HEX3_DP
+	set_location_assignment PIN_G8 -to DRAM_CAS_N
+	set_location_assignment PIN_G7 -to DRAM_CS_N
+	set_location_assignment PIN_E5 -to DRAM_CLK
+	set_location_assignment PIN_E6 -to DRAM_CKE
+	set_location_assignment PIN_B5 -to DRAM_BA_0
+	set_location_assignment PIN_A4 -to DRAM_BA_1
+	set_location_assignment PIN_F10 -to DRAM_DQ[15]
+	set_location_assignment PIN_E10 -to DRAM_DQ[14]
+	set_location_assignment PIN_A10 -to DRAM_DQ[13]
+	set_location_assignment PIN_B10 -to DRAM_DQ[12]
+	set_location_assignment PIN_C10 -to DRAM_DQ[11]
+	set_location_assignment PIN_A9 -to DRAM_DQ[10]
+	set_location_assignment PIN_B9 -to DRAM_DQ[9]
+	set_location_assignment PIN_A8 -to DRAM_DQ[8]
+	set_location_assignment PIN_F8 -to DRAM_DQ[7]
+	set_location_assignment PIN_H9 -to DRAM_DQ[6]
+	set_location_assignment PIN_G9 -to DRAM_DQ[5]
+	set_location_assignment PIN_F9 -to DRAM_DQ[4]
+	set_location_assignment PIN_E9 -to DRAM_DQ[3]
+	set_location_assignment PIN_H10 -to DRAM_DQ[2]
+	set_location_assignment PIN_G10 -to DRAM_DQ[1]
+	set_location_assignment PIN_D10 -to DRAM_DQ[0]
+	set_location_assignment PIN_E7 -to DRAM_LDQM
+	set_location_assignment PIN_B8 -to DRAM_UDQM
+	set_location_assignment PIN_F7 -to DRAM_RAS_N
+	set_location_assignment PIN_D6 -to DRAM_WE_N
+	set_location_assignment PIN_B12 -to CLOCK_50_2
+	set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+	set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+	set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+	set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+	set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+	set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+	set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+	set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+	set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+	set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+	set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+	set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+	set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+	# Set IO types
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[28]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[29]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[30]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[31]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[16]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[17]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[18]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[19]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[20]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[21]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[22]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[23]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[24]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[25]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[26]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[27]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[28]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[29]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[30]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[31]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[16]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[17]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[18]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[19]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[20]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[21]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[22]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[23]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[24]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[25]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[26]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[27]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+
+	# Set some specific information to some internal signals and IOs
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_command"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_address"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_dqm"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_cke"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_bank"
+	set_instance_assignment -name FAST_INPUT_REGISTER  ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|iob_data"
+	set_instance_assignment -name FAST_INPUT_REGISTER  ON -to "DRAM:dram|SDRAM_Controller:sdram_ctrl|captured_data"
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_ADDR
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CKE
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CLK
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+	set_instance_assignment -name FAST_INPUT_REGISTER  ON -to SDRAM_DQ
+
+	# Commit assignments
+	export_assignments
+
+	# Close project
+	if {$need_to_close_project} {
+		project_close
+	}
+}

+ 44 - 0
vhdl/DE0_SEG7.vhd

@@ -0,0 +1,44 @@
+--+-----------------------------------------------------------------------+-------------------------------------+--
+--|________  ___________________________  ____________________ ________   | (c) 2014-2015 Manoel Trapier        |--
+--|\______ \ \_   _____/\   _  \______  \/   _____/\_   _____//  _____/   | godzil@986-studio.com               |--
+--| |    |  \ |    __)_ /  /_\  \  /    /\_____  \  |    __)_/   \  ___   |                                     |--
+--| |    `   \|        \\  \_/   \/    / /        \ |        \    \_\  \  | A 7 Segment for DE0, just for fun   |--
+--|/_______  /_______  / \_____  /____/ /_______  //_______  /\______  /  |                                     |--
+--|        \/        \/        \/               \/         \/        \/   |          http://www.986-studio.com/ |--
+--+-----------------------------------------------------------------------+-------------------------------------+--
+--| DE0 7 Segment                                                                                               |--
+--+-------------------------------------------------------------------------------------------------------------+--
+--
+-- See README.txt for more details
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity DE0_SEG7 is
+    port(
+        in_value: in  std_logic_vector(3 downto 0);
+        segment:  out std_logic_vector(6 downto 0)
+    );
+end DE0_SEG7;
+
+architecture Behavioral of DE0_SEG7 is
+begin
+    segment <= "1000000" when in_value = X"0" else -- ---t----
+               "1111001" when in_value = X"1" else -- |      |
+               "0100100" when in_value = X"2" else -- lt      rt
+               "0110000" when in_value = X"3" else -- |      |
+               "0011001" when in_value = X"4" else -- ---m----
+               "0010010" when in_value = X"5" else -- |      |
+               "0000010" when in_value = X"6" else -- lb      rb
+               "1111000" when in_value = X"7" else -- |      |
+               "0000000" when in_value = X"8" else -- ---b----
+               "0011000" when in_value = X"9" else
+               "0001000" when in_value = X"A" else
+               "0000011" when in_value = X"B" else
+               "1000110" when in_value = X"C" else
+               "0100001" when in_value = X"D" else
+               "0000110" when in_value = X"E" else
+               "0001110";
+end architecture;

+ 1 - 1
vhdl/DRAM.vhd

@@ -122,7 +122,7 @@ architecture behaviour of DRAM is
 begin
 
     -- this should be based on the generic, really
-    cmd_address <= '0' & '0' & mem_address(22 downto 2); -- address_tag & address_line
+    cmd_address <= mem_address((sdram_address_width) downto 2); -- address_tag & address_line
     cmd_data_in <= data_in & data_in & data_in & data_in; -- write the same data four times
     cmd_wr <= req_write;
     coldboot <= not seen_ready;

+ 8 - 8
vhdl/SDRAM_Controller.vhd

@@ -102,19 +102,19 @@ architecture Behavioral of SDRAM_Controller is
    signal iob_cke         : std_logic := '0';
    signal iob_bank        : std_logic_vector( 1 downto 0) := (others => '0');
    
-   attribute IOB: string;
-   attribute IOB of iob_command: signal is "true";
-   attribute IOB of iob_address: signal is "true";
-   attribute IOB of iob_dqm    : signal is "true";
-   attribute IOB of iob_cke    : signal is "true";
-   attribute IOB of iob_bank   : signal is "true";
-   attribute IOB of iob_data   : signal is "true";
+   --attribute IOB: string;
+   --attribute IOB of iob_command: signal is "true";
+   --attribute IOB of iob_address: signal is "true";
+   --attribute IOB of iob_dqm    : signal is "true";
+   --attribute IOB of iob_cke    : signal is "true";
+   --attribute IOB of iob_bank   : signal is "true";
+   --attribute IOB of iob_data   : signal is "true";
    
    signal iob_data_next      : std_logic_vector(15 downto 0) := (others => '0');
    signal captured_data      : std_logic_vector(15 downto 0) := (others => '0');
    signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
    signal sdram_din          : std_logic_vector(15 downto 0);
-   attribute IOB of captured_data : signal is "true";
+   --attribute IOB of captured_data : signal is "true";
    
    type fsm_state is (s_startup,
                       s_idle_in_6, s_idle_in_5, s_idle_in_4,   s_idle_in_3, s_idle_in_2, s_idle_in_1,

+ 1 - 1
vhdl/pll.vhd

@@ -170,7 +170,7 @@ BEGIN
 		clk2_phase_shift => "0",
 		compensate_clock => "CLK1",
 		inclk0_input_frequency => 20000,
-		intended_device_family => "Cyclone IV E",
+		intended_device_family => "Cyclone III",
 		lpm_hint => "CBX_MODULE_PREFIX=pll",
 		lpm_type => "altpll",
 		operation_mode => "NORMAL",

+ 145 - 0
vhdl/spimaster.vhd

@@ -0,0 +1,145 @@
+--+-----------------------------------+-------------------------------------+--
+--|                      ___   ___    | (c) 2013-2014 William R Sowerbutts  |--
+--|   ___  ___   ___ ___( _ ) / _ \   | will@sowerbutts.com                 |--
+--|  / __|/ _ \ / __|_  / _ \| | | |  |                                     |--
+--|  \__ \ (_) | (__ / / (_) | |_| |  | A Z80 FPGA computer, just for fun   |--
+--|  |___/\___/ \___/___\___/ \___/   |                                     |--
+--|                                   |              http://sowerbutts.com/ |--
+--+-----------------------------------+-------------------------------------+--
+--| A rudimentary SPI master peripheral                                     |--
+--+-------------------------------------------------------------------------+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity spimaster is
+    port ( clk              : in  std_logic;
+           reset            : in  std_logic;
+           cpu_address      : in  std_logic_vector(2 downto 0);
+           cpu_wait         : out std_logic;
+           data_in          : in  std_logic_vector(7 downto 0);
+           data_out         : out std_logic_vector(7 downto 0);
+           enable           : in  std_logic;
+           req_read         : in  std_logic;
+           req_write        : in  std_logic;
+           slave_cs         : out std_logic;
+           slave_clk        : out std_logic;
+           slave_mosi       : out std_logic;
+           slave_miso       : in  std_logic
+    );
+end spimaster;
+
+-- registers:
+-- base+0   -- chip select control; bit 0 is slave_cs
+-- base+1   -- status register; bit 0 indicates "transmitter busy"
+-- base+2   -- transmitter: write a byte here, starts SPI bus transaction
+-- base+3   -- receiver: last byte received (updated on each transation)
+-- base+4   -- clock divider: clk counts from 0 to whatever is in this register before proceeding
+--
+-- Note that if an SPI transfer is underway already the CPU will be
+-- forced to wait until it completes before any register can be
+-- read or written. This is very convenient as it means you can
+-- just read or write bytes without checking the status register.
+
+architecture Behavioral of spimaster is
+
+    -- start up in idle state
+    signal slave_cs_register  : std_logic := '1';
+    signal slave_clk_register : std_logic := '1'; 
+    signal slave_mosi_register: std_logic := '0';
+    signal data_out_sr        : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
+    signal data_in_sr         : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
+    signal busy_sr            : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
+    signal clk_divide_target  : unsigned(7 downto 0) := (others => '0');
+    signal clk_divide_value   : unsigned(7 downto 0) := (others => '0');
+    signal cpu_was_idle       : std_logic := '1';
+
+    -- cpu visible registers
+    signal chip_select_out    : std_logic_vector(7 downto 0);
+    signal status_data_out    : std_logic_vector(7 downto 0);
+
+begin
+
+    chip_select_out <= "0000000" & slave_cs_register;
+    status_data_out <= "0000000" & busy_sr(7);
+    cpu_wait <= busy_sr(7);
+
+    with cpu_address select
+        data_out <=
+            chip_select_out                     when "000",
+            status_data_out                     when "001",
+            data_out_sr                         when "010",
+            data_in_sr                          when "011",
+            std_logic_vector(clk_divide_target) when "100",
+            status_data_out                     when others;
+
+    slave_cs   <= slave_cs_register;
+    slave_clk  <= slave_clk_register;
+    slave_mosi <= slave_mosi_register;
+
+    spimaster_proc: process(clk)
+    begin
+        if rising_edge(clk) then
+            if reset = '1' then
+                slave_cs_register <= '1';
+                slave_clk_register <= '1';
+                slave_mosi_register <= '0';
+                data_out_sr <= (others => '0');
+                data_in_sr <= (others => '0');
+                busy_sr <= (others => '0');
+                clk_divide_target <= (others => '0');
+                clk_divide_value <= (others => '0');
+                cpu_was_idle <= '1';
+            else
+                -- divide down input clk to get 2 * spi clk
+                clk_divide_value <= clk_divide_value + 1;
+                if clk_divide_value = clk_divide_target then
+                    clk_divide_value <= to_unsigned(0, 8);
+                end if;
+
+                if busy_sr(7) = '1' then
+                    if clk_divide_value = clk_divide_target then
+                        -- we're in the midst of a transaction! whoo!
+                        if slave_clk_register = '1' then
+                            -- clk is high; next cycle will be falling edge of clk
+                            slave_clk_register <= '0';
+                            slave_mosi_register <= data_out_sr(7);
+                            -- shift data out
+                            data_out_sr <= data_out_sr(6 downto 0) & '0';
+                        else
+                            -- clk is low; next cycle will be rising edge of clk
+                            slave_clk_register <= '1';
+                            -- shift busy
+                            busy_sr <= busy_sr(6 downto 0) & '0';
+                            -- latch data in
+                            data_in_sr <= data_in_sr(6 downto 0) & slave_miso;
+                        end if;
+                    end if;
+                end if;
+
+
+                if enable = '1' and req_write = '1' then
+                    if busy_sr(7) = '0' and cpu_was_idle = '1' then
+                        cpu_was_idle <= '0';
+                        case cpu_address is
+                            when "000" => 
+                                slave_cs_register <= data_in(0);
+                            when "010" => 
+                            -- only allow writes when transmitter is idle
+                                data_out_sr <= data_in; 
+                                busy_sr <= (others => '1');
+                            when "100" =>
+                                clk_divide_target <= unsigned(data_in);
+                            when others => -- no change
+                        end case;
+                    else
+                        cpu_was_idle <= cpu_was_idle;
+                    end if;
+                else
+                    cpu_was_idle <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+end Behavioral;

+ 137 - 71
vhdl/top_level.vhd

@@ -17,59 +17,62 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
 entity top_level is
-    Port ( sysclk_32m          : in    std_logic;
-           sys_clk_pad_i       : in    std_logic;
-           rst_n_pad_i         : in    std_logic;
-           leds                : out   std_logic_vector(4 downto 0);
-           reset_button        : in    std_logic;
-           console_select      : in    std_logic;
-
-           -- UART0 (to FTDI USB chip, no flow control)
-           serial_rx           : in    std_logic;
-           serial_tx           : out   std_logic;
-
-           -- UART0 (to MAX3232 level shifter chip, hardware flow control)
-           uart1_rx            : in    std_logic;
-           uart1_cts           : in    std_logic;
-           uart1_tx            : out   std_logic;
-           uart1_rts           : out   std_logic;
-
-           -- SPI flash chip
-           flash_spi_cs        : out   std_logic;
-           flash_spi_clk       : out   std_logic;
-           flash_spi_mosi      : out   std_logic;
-           flash_spi_miso      : in    std_logic;
-
-           -- SD card socket
-           sdcard_spi_cs       : out   std_logic;
-           sdcard_spi_clk      : out   std_logic;
-           sdcard_spi_mosi     : out   std_logic;
-           sdcard_spi_miso     : in    std_logic;
-
-           -- SDRAM chip
-           SDRAM_CLK           : out   std_logic;
-           SDRAM_CKE           : out   std_logic;
-           SDRAM_CS            : out   std_logic;
-           SDRAM_nRAS          : out   std_logic;
-           SDRAM_nCAS          : out   std_logic;
-           SDRAM_nWE           : out   std_logic;
-           SDRAM_DQM           : out   std_logic_vector( 1 downto 0);
-           SDRAM_ADDR          : out   std_logic_vector (12 downto 0);
-           SDRAM_BA            : out   std_logic_vector( 1 downto 0);
-           SDRAM_DQ            : inout std_logic_vector (15 downto 0)
-       );
+    Port (
+        CLOCK_50          : in    std_logic;
+        LEDG              : out   std_logic_vector(9 downto 0);
+        BUTTON            : in    std_logic_vector(2 downto 0);
+        SW                : in    std_logic_vector(9 downto 0);
+
+        -- UART0 (to MAX3232 level shifter chip, hardware flow control)
+        UART_RXD           : in    std_logic;
+        UART_TXD           : out   std_logic;
+
+        -- GPIOs
+        GPIO1_D            : inout    std_logic_vector(31 downto 0);
+        GPIO0_D            : inout    std_logic_vector(31 downto 0);
+
+        -- 7-SEG Display
+        HEX0_D:  out   std_logic_vector(6 downto 0);
+        --HEX0_DP: out   std_logic;
+        HEX1_D:  out   std_logic_vector(6 downto 0);
+        --HEX1_DP: out   std_logic;
+        HEX2_D:  out   std_logic_vector(6 downto 0);
+        --HEX2_DP: out   std_logic;
+        HEX3_D:  out   std_logic_vector(6 downto 0);
+        --sHEX3_DP: out   std_logic
+
+        -- SD card socket
+        SD_CLK  : out std_logic;
+        SD_CMD  : in std_logic;
+        SD_DAT0 : out std_logic;
+        SD_DAT3 : out std_logic;
+        SD_WP_N : in std_logic;
+
+        -- SDRAM chip
+        DRAM_CLK            : out   std_logic;
+        DRAM_CKE            : out   std_logic;
+        DRAM_CS_N           : out   std_logic;
+        DRAM_RAS_N          : out   std_logic;
+        DRAM_CAS_N          : out   std_logic;
+        DRAM_WE_N           : out   std_logic;
+        DRAM_DQM            : out   std_logic_vector( 1 downto 0);
+        DRAM_ADDR           : out   std_logic_vector (12 downto 0);
+        DRAM_BA             : out   std_logic_vector( 1 downto 0);
+        DRAM_DQ             : inout std_logic_vector (15 downto 0)
+    );
 end top_level;
 
 architecture Behavioral of top_level is
     constant clk_freq_mhz        : natural := 50; -- this is the frequency which the PLL outputs, in MHz.
 
     -- SDRAM configuration
-    constant sdram_address_width : natural := 24;
-    constant sdram_column_bits   : natural := 9;
-    constant cycles_per_refresh  : natural := (64000*clk_freq_mhz)/8192-1;
+    constant sdram_line_count    : natural := 4096;
+    constant sdram_address_width : natural := 22;
+    constant sdram_column_bits   : natural := 8;
+    constant cycles_per_refresh  : natural := (64000*clk_freq_mhz)/sdram_line_count-1;
 
     -- For simulation, we don't need a long init stage. but for real DRAM we need approx 101us.
-    -- The constant below has a different value when interpreted by the synthesis and simulator 
+    -- The constant below has a different value when interpreted by the synthesis and simulator
     -- tools in order to achieve the desired timing in each.
     constant sdram_startup_cycles: natural := 101 * clk_freq_mhz
     -- pragma translate_off
@@ -146,6 +149,10 @@ architecture Behavioral of top_level is
     -- GPIO
     signal gpio_input           : std_logic_vector(7 downto 0);
     signal gpio_output          : std_logic_vector(7 downto 0);
+    signal gpio_bank0_input     : std_logic_vector(31 downto 0);
+    signal gpio_bank0_output    : std_logic_vector(31 downto 0);
+    signal gpio_bank1_input     : std_logic_vector(31 downto 0);
+    signal gpio_bank1_output    : std_logic_vector(31 downto 0);
 
     -- Interrupts
     signal cpu_interrupt_in     : std_logic;
@@ -161,13 +168,13 @@ begin
         if rising_edge(clk) then
             -- Xilinx advises using two flip-flops are used to bring external
             -- signals which feed control logic into our clock domain.
-            reset_button_clk1 <= reset_button;
+            reset_button_clk1 <= not BUTTON(0);
             reset_button_sync <= reset_button_clk1;
-            console_select_clk1 <= console_select;
+            console_select_clk1 <= SW(9);
             console_select_sync <= console_select_clk1;
 
             -- reset the system when requested
-            if (power_on_reset(0) = '1') then
+            if (power_on_reset(0) = '1' or reset_button_sync = '1' or reset_request_uart = '1') then
                 system_reset <= '1';
             else
                 system_reset <= '0';
@@ -188,20 +195,40 @@ begin
     end process;
 
     -- GPIO input signal routing
-    gpio_input <= coldboot & swap_uart01 & "000000";
+    gpio_input(0) <= SW(0);
+    gpio_input(1) <= SW(1);
+    gpio_input(2) <= SW(2);
+    gpio_input(3) <= SW(3);
+    gpio_input(4) <= SW(4);
+    gpio_input(5) <= SW(5);
+    gpio_input(6) <= swap_uart01;
+    gpio_input(7) <= coldboot;
 
     -- GPIO output signal routing
-    leds(0) <= gpio_output(0);
-    leds(1) <= gpio_output(1);
-    leds(2) <= gpio_output(2);
-    leds(3) <= gpio_output(3);
+    LEDG(0) <= gpio_output(0);
+    LEDG(1) <= gpio_output(1);
+    LEDG(2) <= gpio_output(2);
+    LEDG(3) <= gpio_output(3);
+    LEDG(4) <= gpio_output(4);
+    LEDG(5) <= gpio_output(5);
+    LEDG(6) <= gpio_output(6);
+    LEDG(7) <= gpio_output(7);
 
     -- User LED (LED1) on Papilio Pro indicates when the CPU is being asked to wait (eg by the SDRAM cache)
-    leds(4) <= cpu_wait;
+    LEDG(9) <= cpu_wait;
+
+    --
+    LEDG(8) <= clk or not(BUTTON(2));
 
     -- Interrupt signal for the CPU
     cpu_interrupt_in <= (timer_interrupt or uart0_interrupt or uart1_interrupt);
 
+    -- 7 Seg
+    seg0: entity work.DE0_SEG7 port map(virtual_address(3 downto 0), HEX0_D);
+    seg1: entity work.DE0_SEG7 port map(virtual_address(7 downto 4), HEX1_D);
+    seg2: entity work.DE0_SEG7 port map(virtual_address(11 downto 8), HEX2_D);
+    seg3: entity work.DE0_SEG7 port map(virtual_address(15 downto 12), HEX3_D);
+
     -- Z80 CPU core
     cpu: entity work.Z80cpu
     port map (
@@ -311,8 +338,8 @@ begin
        spimaster1_wait when spimaster1_cs='1' else
        '0';
 
-    -- the MMU can, at any time, request the CPU wait (this is used when 
-    -- translating IO to memory requests, to implement a wait state for 
+    -- the MMU can, at any time, request the CPU wait (this is used when
+    -- translating IO to memory requests, to implement a wait state for
     -- the "17th page")
     cpu_wait <= (mem_wait or mmu_wait);
 
@@ -353,16 +380,16 @@ begin
                coldboot => coldboot,
 
                -- interface to hardware SDRAM chip
-               SDRAM_CLK       => open,
-               SDRAM_CKE       => SDRAM_CKE,
-               SDRAM_CS        => SDRAM_CS,
-               SDRAM_nRAS      => SDRAM_nRAS,
-               SDRAM_nCAS      => SDRAM_nCAS,
-               SDRAM_nWE       => SDRAM_nWE,
-               SDRAM_DQM       => SDRAM_DQM,
-               SDRAM_BA        => SDRAM_BA,
-               SDRAM_ADDR      => SDRAM_ADDR,
-               SDRAM_DQ        => SDRAM_DQ
+              SDRAM_CLK        => open,
+              SDRAM_CKE        => DRAM_CKE,
+              SDRAM_CS         => DRAM_CS_N,
+              SDRAM_nCAS       => DRAM_CAS_N,
+              SDRAM_nRAS       => DRAM_RAS_N,
+              SDRAM_nWE        => DRAM_WE_N,
+              SDRAM_DQM        => DRAM_DQM,
+              SDRAM_BA         => DRAM_BA,
+              SDRAM_ADDR       => DRAM_ADDR,
+              SDRAM_DQ         => DRAM_DQ
            );
 
    -- 4KB system ROM implemented in block RAM
@@ -394,8 +421,8 @@ begin
                clk => clk,
                reset => system_reset,
                reset_out => reset_request_uart, -- result of watching for reset sequence on the input
-               serial_in => serial_rx,
-               serial_out => serial_tx,
+               serial_in => UART_RXD,
+               serial_out => UART_TXD,
                serial_rts => open,
                serial_cts => '0',
                cpu_address => virtual_address(2 downto 0),
@@ -407,6 +434,26 @@ begin
                req_write => req_write
            );
 
+   -- UART connected to two GPIOs (1(30), 1(31))
+   uart1: entity work.uart_interface
+   generic map ( watch_for_reset => 1, clk_frequency => (clk_freq_mhz * 1000000) )
+   port map(
+               clk => clk,
+               reset => system_reset,
+               reset_out => open,
+               serial_in => GPIO1_D(30),
+               serial_out => GPIO1_D(31),
+               serial_rts => open,
+               serial_cts => '0',
+               cpu_address => virtual_address(2 downto 0),
+               cpu_data_in => cpu_data_out,
+               cpu_data_out => uart1_data_out,
+               enable => uart1_cs,
+               interrupt => uart1_interrupt,
+               req_read => req_read,
+               req_write => req_write
+           );
+
    -- Timer device (internally scales the clock to 1MHz)
    timer: entity work.timer
    generic map ( clk_frequency => (clk_freq_mhz * 1000000) )
@@ -436,9 +483,28 @@ begin
                output_pins => gpio_output
            );
 
+  -- SPI master device connected to SD card socket on the IO board
+  spimaster1: entity work.spimaster
+  port map(
+              clk => clk,
+              reset => system_reset,
+              cpu_address => virtual_address(2 downto 0),
+              cpu_wait => spimaster1_wait,
+              data_in => cpu_data_out,
+              data_out => spimaster1_data_out,
+              enable => spimaster1_cs,
+              req_read => req_read,
+              req_write => req_write,
+              slave_cs => SD_DAT3,
+              slave_clk => SD_CLK,
+              slave_mosi => SD_DAT0,
+              slave_miso => SD_CMD
+          );
+
+
    -- An attempt to allow the CPU clock to be scaled back to run
    -- at slower speeds without affecting the clock signal sent to
-   -- IO devices. Basically this was an attempt to make CP/M games 
+   -- IO devices. Basically this was an attempt to make CP/M games
    -- playable :) Very limited success. Might be simpler to remove
    -- this entirely.
    clkscale: entity work.clkscale
@@ -456,8 +522,8 @@ begin
    pll: entity work.pll
    port map (
                areset => open,
-               inclk0 => sys_clk_pad_i,
-               c0 => sdram_clk, -- 100 Mhz - 180 deg
+               inclk0 => CLOCK_50,
+               c0 => DRAM_CLK, -- 100 Mhz - 180 deg
                c1 => clk, -- 100 Mhz
                locked => open
            );