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@@ -87,6 +87,9 @@ always @(posedge CLK2) begin
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end
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wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
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+wire [7:0] CX4_SNES_DATA_IN;
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+wire [7:0] CX4_SNES_DATA_OUT;
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+
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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@@ -114,9 +117,6 @@ wire [7:0] MSU_SNES_DATA_OUT;
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wire [5:0] msu_status_reset_bits;
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wire [5:0] msu_status_set_bits;
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-wire [7:0] CX4_SNES_DATA_IN;
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-wire [7:0] CX4_SNES_DATA_OUT;
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-
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wire [23:0] MAPPED_SNES_ADDR;
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wire ROM_ADDR0;
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@@ -369,25 +369,28 @@ parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000;
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parameter ST_MCU_WR_END = 21'b000010000000000000000;
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parameter ST_CX4_RD_ADDR = 21'b000100000000000000000;
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parameter ST_CX4_RD_WAIT = 21'b001000000000000000000;
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-parameter ST_CX4_RD_WAIT2 = 21'b010000000000000000000;
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-parameter ST_CX4_RD_END = 21'b100000000000000000000;
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+parameter ST_CX4_RD_END = 21'b010000000000000000000;
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-parameter ROM_RD_WAIT = 4'h4;
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+parameter ROM_RD_WAIT = 4'h0;
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parameter ROM_RD_WAIT_MCU = 4'h6;
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+parameter ROM_WR_WAIT = 4'h4;
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parameter ROM_WR_WAIT1 = 4'h2;
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-parameter ROM_WR_WAIT2 = 4'h3;
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-parameter ROM_WR_WAIT_MCU = 4'h6;
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+parameter ROM_WR_WAIT2 = 4'h1;
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+parameter ROM_WR_WAIT_MCU = 4'h5;
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parameter ROM_RD_WAIT_CX4 = 4'h6;
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+parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
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+
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reg [20:0] STATE;
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initial STATE = ST_IDLE;
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-assign MSU_SNES_DATA_IN = SNES_DATA;
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-assign CX4_SNES_DATA_IN = SNES_DATA;
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-
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reg [7:0] SNES_DINr;
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+reg [7:0] SNES_DOUTr;
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reg [7:0] ROM_DOUTr;
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+assign MSU_SNES_DATA_IN = SNES_DATA;
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+assign CX4_SNES_DATA_IN = SNES_DATA;
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+
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reg [7:0] r213fr;
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reg r213f_forceread;
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reg [2:0] r213f_delay;
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@@ -419,25 +422,61 @@ always @(posedge CLK2) begin
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end
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wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
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-wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active;
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-assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
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-assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
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+reg RQ_MCU_RDYr;
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+initial RQ_MCU_RDYr = 1'b1;
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+assign MCU_RDY = RQ_MCU_RDYr;
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+
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+reg RQ_CX4_RDYr;
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+initial RQ_CX4_RDYr = 1'b1;
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+assign CX4_RDY = RQ_CX4_RDYr;
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+
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+reg ROM_SAr;
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+initial ROM_SAr = 1'b1;
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+wire ROM_SA = ROM_SAr;
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+
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+reg ROM_CAr;
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+initial ROM_CAr = 1'b0;
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+wire ROM_CA = ROM_CAr;
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+
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+reg [23:0] CX4_ADDRr;
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+
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+assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : ROM_CA ? CX4_ADDRr[23:1] : ROM_SA ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
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+assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : ROM_CA ? CX4_ADDRr[0] : ROM_SA ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
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reg ROM_WEr;
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initial ROM_WEr = 1'b1;
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+reg ROM_DOUT_ENr;
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+initial ROM_DOUT_ENr = 1'b0;
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-reg RQ_MCU_RDYr;
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-initial RQ_MCU_RDYr = 1'b1;
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-assign MCU_RDY = RQ_MCU_RDYr;
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+reg[17:0] SNES_DEAD_CNTr;
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+initial SNES_DEAD_CNTr = 0;
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+
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+always @(posedge CLK2) begin
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+ if(cx4_active) begin
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+ if(CX4_RRQ) begin
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+ CX4_RD_PENDr <= 1'b1;
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+ RQ_CX4_RDYr <= 1'b0;
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+ CX4_ADDRr <= CX4_ADDR;
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+ end else if(STATE == ST_CX4_RD_END) begin
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+ CX4_RD_PENDr <= 1'b0;
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+ RQ_CX4_RDYr <= 1'b1;
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+ end
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+ end else begin
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+ CX4_RD_PENDr <= 1'b0;
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+ RQ_CX4_RDYr <= 1'b1;
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+ end
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+end
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always @(posedge CLK2) begin
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if(MCU_RRQ) begin
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MCU_RD_PENDr <= 1'b1;
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RQ_MCU_RDYr <= 1'b0;
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+ ROM_ADDRr <= MCU_ADDR;
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end else if(MCU_WRQ) begin
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MCU_WR_PENDr <= 1'b1;
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RQ_MCU_RDYr <= 1'b0;
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+ ROM_ADDRr <= MCU_ADDR;
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end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
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MCU_RD_PENDr <= 1'b0;
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MCU_WR_PENDr <= 1'b0;
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@@ -445,151 +484,138 @@ always @(posedge CLK2) begin
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end
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end
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-reg RQ_CX4_RDYr;
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-initial RQ_CX4_RDYr = 1'b1;
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-assign CX4_RDY = RQ_CX4_RDYr;
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-
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always @(posedge CLK2) begin
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- if(CX4_RRQ) begin
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- CX4_RD_PENDr <= 1'b1;
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- RQ_CX4_RDYr <= 1'b0;
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- end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin
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- CX4_RD_PENDr <= 1'b0;
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- RQ_CX4_RDYr <= 1'b1;
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- end
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+ if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
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+ else SNES_DEAD_CNTr <= 17'h0;
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end
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-reg snes_wr_cycle;
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+always @(posedge CLK2) begin
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+ if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
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+ else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
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+end
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always @(posedge CLK2) begin
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- if(SNES_cycle_start & IS_CART & ~cx4_active) begin
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- STATE <= ST_SNES_RD_ADDR;
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- end else if(SNES_WR_start & IS_CART & ~cx4_active) begin
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- STATE <= ST_SNES_WR_ADDR;
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- end else begin
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- case(STATE)
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- ST_IDLE: begin
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- ROM_ADDRr <= MAPPED_SNES_ADDR;
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- if(CX4_RD_PENDr) begin
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- STATE <= ST_CX4_RD_WAIT;
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- ROM_ADDRr <= CX4_ADDR;
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- ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
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- end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin
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- if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
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- else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
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- else STATE <= ST_IDLE;
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+ if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
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+ else
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+ case(STATE)
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+ ST_IDLE: begin
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+ ROM_SAr <= 1'b1;
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+ ROM_CAr <= 1'b0;
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+ ROM_DOUT_ENr <= 1'b0;
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+ if(cx4_active) begin
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+ if(CX4_RD_PENDr) STATE <= ST_CX4_RD_ADDR;
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+ end else if(SNES_cycle_start & ~SNES_WRITE) begin
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+ STATE <= ST_SNES_WR_ADDR;
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+ if(IS_SAVERAM | IS_WRITABLE) begin
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+ ROM_WEr <= 1'b0;
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+ ROM_DOUT_ENr <= 1'b1;
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end
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- else STATE <= ST_IDLE;
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- end
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- ST_SNES_RD_ADDR: begin
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- STATE <= ST_SNES_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT;
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- end
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- ST_SNES_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
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- else STATE <= ST_SNES_RD_WAIT;
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- if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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- else SNES_DINr <= ROM_DATA[15:8];
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- end
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- ST_SNES_RD_END: begin
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- STATE <= ST_IDLE;
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- if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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- else SNES_DINr <= ROM_DATA[15:8];
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- end
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- ST_SNES_WR_ADDR: begin
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- ROM_WEr <= (!IS_WRITABLE);
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- snes_wr_cycle <= 1'b1;
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- STATE <= ST_SNES_WR_WAIT1;
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- ST_MEM_DELAYr <= ROM_WR_WAIT1;
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- end
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- ST_SNES_WR_WAIT1: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
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- else STATE <= ST_SNES_WR_WAIT1;
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- end
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- ST_SNES_WR_DATA: begin
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- ROM_DOUTr <= SNES_DATA;
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- ST_MEM_DELAYr <= ROM_WR_WAIT2;
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+ end else if(SNES_cycle_start) begin
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+// STATE <= ST_SNES_RD_ADDR;
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+ STATE <= ST_SNES_RD_END;
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+ SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
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+ end else if(SNES_DEADr & MCU_RD_PENDr) begin
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+ STATE <= ST_MCU_RD_ADDR;
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+ end else if(SNES_DEADr & MCU_WR_PENDr) begin
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+ STATE <= ST_MCU_WR_ADDR;
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+ end
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+ end
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+ ST_SNES_RD_ADDR: begin
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+ ST_MEM_DELAYr <= ROM_RD_WAIT;
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+ STATE <= ST_SNES_RD_WAIT;
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+ end
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+ ST_SNES_RD_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+// if(ST_MEM_DELAYr == 0) begin
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+// end
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+// else STATE <= ST_SNES_RD_WAIT;
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+ end
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+
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+ ST_SNES_WR_ADDR: begin
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+ ST_MEM_DELAYr <= ROM_WR_WAIT1;
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+ STATE <= ST_SNES_WR_WAIT1;
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+ end
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+ ST_SNES_WR_WAIT1: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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+ ST_MEM_DELAYr <= ROM_WR_WAIT2;
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STATE <= ST_SNES_WR_WAIT2;
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- end
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- ST_SNES_WR_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
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- else STATE <= ST_SNES_WR_WAIT2;
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- end
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- ST_SNES_WR_END: begin
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- STATE <= ST_IDLE;
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- ROM_WEr <= 1'b1;
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- snes_wr_cycle <= 1'b0;
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- end
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- ST_MCU_RD_ADDR: begin
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- ROM_ADDRr <= MCU_ADDR;
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- STATE <= ST_MCU_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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- end
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- ST_MCU_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_RD_WAIT2;
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- ST_MEM_DELAYr <= 4'h2;
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- if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
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- else MCU_DINr <= ROM_DATA[15:8];
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- end
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- else STATE <= ST_MCU_RD_WAIT;
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- end
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- ST_MCU_RD_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_RD_END;
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- end else STATE <= ST_MCU_RD_WAIT2;
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- end
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- ST_MCU_RD_END: begin
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- STATE <= ST_IDLE;
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- end
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- ST_MCU_WR_ADDR: begin
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- ROM_ADDRr <= MCU_ADDR;
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- STATE <= ST_MCU_WR_WAIT;
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- ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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- ROM_DOUTr <= MCU_DOUT;
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- ROM_WEr <= 1'b0;
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- end
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- ST_MCU_WR_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- ROM_WEr <= 1'b1;
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- STATE <= ST_MCU_WR_WAIT2;
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- ST_MEM_DELAYr <= 4'h2;
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- end
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- else STATE <= ST_MCU_WR_WAIT;
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- end
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- ST_MCU_WR_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_WR_END;
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- end else STATE <= ST_MCU_WR_WAIT2;
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- end
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- ST_MCU_WR_END: begin
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- STATE <= ST_IDLE;
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- end
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-
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- ST_CX4_RD_ADDR: begin
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- ROM_ADDRr <= CX4_ADDR;
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- STATE <= ST_CX4_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
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- end
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- ST_CX4_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE;
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- else STATE <= ST_CX4_RD_WAIT;
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- if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0];
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- else CX4_DINr <= ROM_DATA[15:8];
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- end
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- ST_CX4_RD_END: begin
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- STATE <= ST_IDLE;
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- end
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- endcase
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- end
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+ ROM_DOUTr <= SNES_DATA;
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+ end
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+ else STATE <= ST_SNES_WR_WAIT1;
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+ end
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+ ST_SNES_WR_WAIT2: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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+ STATE <= ST_SNES_WR_END;
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+ ROM_WEr <= 1'b1;
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+ end
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+ else STATE <= ST_SNES_WR_WAIT2;
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+ end
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+ ST_SNES_RD_END, ST_SNES_WR_END: begin
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+ ROM_DOUT_ENr <= 1'b0;
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+ if(MCU_RD_PENDr) begin
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+ STATE <= ST_MCU_RD_ADDR;
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+ end else if(MCU_WR_PENDr) begin
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+ STATE <= ST_MCU_WR_ADDR;
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+ end else STATE <= ST_IDLE;
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+ end
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+ ST_MCU_RD_ADDR: begin
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+ ROM_SAr <= 1'b0;
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+ ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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+ STATE <= ST_MCU_RD_WAIT;
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+ end
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+ ST_MCU_RD_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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+ STATE <= ST_MCU_RD_END;
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+ end
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|
+ else STATE <= ST_MCU_RD_WAIT;
|
|
|
+ end
|
|
|
+ ST_MCU_RD_END: begin
|
|
|
+ MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ end
|
|
|
+
|
|
|
+ ST_MCU_WR_ADDR: begin
|
|
|
+ ROM_DOUTr <= MCU_DOUT;
|
|
|
+ ROM_SAr <= 1'b0;
|
|
|
+ ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
|
|
|
+ STATE <= ST_MCU_WR_WAIT;
|
|
|
+ ROM_DOUT_ENr <= 1'b1;
|
|
|
+ ROM_WEr <= 1'b0;
|
|
|
+ end
|
|
|
+ ST_MCU_WR_WAIT: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
|
|
|
+ if(ST_MEM_DELAYr == 0) begin
|
|
|
+ ROM_WEr <= 1'b1;
|
|
|
+ STATE <= ST_MCU_WR_END;
|
|
|
+ end
|
|
|
+ else STATE <= ST_MCU_WR_WAIT;
|
|
|
+ end
|
|
|
+ ST_MCU_WR_END: begin
|
|
|
+ ROM_DOUT_ENr <= 1'b0;
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ end
|
|
|
+ ST_CX4_RD_ADDR: begin
|
|
|
+ ROM_CAr <= 1'b1;
|
|
|
+ ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
|
|
|
+ STATE <= ST_CX4_RD_WAIT;
|
|
|
+ end
|
|
|
+ ST_CX4_RD_WAIT: begin
|
|
|
+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
|
|
|
+ if(ST_MEM_DELAYr == 0) begin
|
|
|
+ STATE <= ST_CX4_RD_END;
|
|
|
+ end
|
|
|
+ else STATE <= ST_CX4_RD_WAIT;
|
|
|
+ end
|
|
|
+ ST_CX4_RD_END: begin
|
|
|
+ ROM_CAr <= 1'b0;
|
|
|
+ CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
|
|
|
+ STATE <= ST_IDLE;
|
|
|
+ end
|
|
|
+
|
|
|
+ endcase
|
|
|
end
|
|
|
|
|
|
always @(posedge SYSCLK2) begin
|