main.v 12 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR_IN,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_CE,
  52. output RAM_OE,
  53. output RAM_WE,
  54. /* MCU signals */
  55. input SPI_MOSI,
  56. inout SPI_MISO,
  57. input SPI_SS,
  58. inout SPI_SCK,
  59. input MCU_OVR,
  60. output MCU_RDY,
  61. output DAC_MCLK,
  62. output DAC_LRCK,
  63. output DAC_SDOUT,
  64. /* SD signals */
  65. input [3:0] SD_DAT,
  66. inout SD_CMD,
  67. inout SD_CLK,
  68. /* debug */
  69. output p113_out
  70. );
  71. assign DAC_MCLK = 0;
  72. assign DAC_LRCK = 0;
  73. assign DAC_SDOUT = 0;
  74. wire CLK2;
  75. reg [23:0] SNES_ADDR_r [2:0];
  76. always @(posedge CLK2) begin
  77. SNES_ADDR_r[2] <= SNES_ADDR_r[1];
  78. SNES_ADDR_r[1] <= SNES_ADDR_r[0];
  79. SNES_ADDR_r[0] <= SNES_ADDR_IN;
  80. end
  81. wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
  82. wire [7:0] spi_cmd_data;
  83. wire [7:0] spi_param_data;
  84. wire [7:0] spi_input_data;
  85. wire [31:0] spi_byte_cnt;
  86. wire [2:0] spi_bit_cnt;
  87. wire [23:0] MCU_ADDR;
  88. wire [23:0] SAVERAM_MASK;
  89. wire [23:0] ROM_MASK;
  90. wire [23:0] MAPPED_SNES_ADDR;
  91. wire ROM_ADDR0;
  92. spi snes_spi(
  93. .clk(CLK2),
  94. .MOSI(SPI_MOSI),
  95. .MISO(SPI_MISO),
  96. .SSEL(SPI_SS),
  97. .SCK(SPI_SCK),
  98. .cmd_ready(spi_cmd_ready),
  99. .param_ready(spi_param_ready),
  100. .cmd_data(spi_cmd_data),
  101. .param_data(spi_param_data),
  102. .input_data(spi_input_data),
  103. .byte_cnt(spi_byte_cnt),
  104. .bit_cnt(spi_bit_cnt)
  105. );
  106. reg [7:0] MCU_DINr;
  107. wire [7:0] MCU_DOUT;
  108. mcu_cmd snes_mcu_cmd(
  109. .clk(CLK2),
  110. .cmd_ready(spi_cmd_ready),
  111. .param_ready(spi_param_ready),
  112. .cmd_data(spi_cmd_data),
  113. .param_data(spi_param_data),
  114. .mcu_data_in(MCU_DINr),
  115. .mcu_data_out(MCU_DOUT),
  116. .spi_byte_cnt(spi_byte_cnt),
  117. .spi_bit_cnt(spi_bit_cnt),
  118. .spi_data_out(spi_input_data),
  119. .addr_out(MCU_ADDR),
  120. .saveram_mask_out(SAVERAM_MASK),
  121. .rom_mask_out(ROM_MASK),
  122. .mcu_rrq(MCU_RRQ),
  123. .mcu_wrq(MCU_WRQ),
  124. .mcu_rq_rdy(MCU_RDY)
  125. );
  126. wire [7:0] DCM_STATUS;
  127. // dcm1: dfs 4x
  128. my_dcm snes_dcm(
  129. .CLKIN(CLKIN),
  130. .CLKFX(CLK2),
  131. .LOCKED(DCM_LOCKED),
  132. .RST(DCM_RST),
  133. .STATUS(DCM_STATUS)
  134. );
  135. assign DCM_RST=0;
  136. reg [7:0] SNES_PARDr;
  137. reg [7:0] SNES_PAWRr;
  138. reg [7:0] SNES_READr;
  139. reg [7:0] SNES_WRITEr;
  140. reg [7:0] SNES_CPU_CLKr;
  141. wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
  142. //wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
  143. reg SNES_DEADr;
  144. initial SNES_DEADr = 0;
  145. wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
  146. wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
  147. wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
  148. wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
  149. wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
  150. wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
  151. wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
  152. always @(posedge CLK2) begin
  153. SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
  154. end
  155. always @(posedge CLK2) begin
  156. SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
  157. SNES_READr <= {SNES_READr[6:0], SNES_READ};
  158. SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
  159. SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
  160. end
  161. address snes_addr(
  162. .CLK(CLK2),
  163. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  164. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  165. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  166. .IS_SAVERAM(IS_SAVERAM),
  167. .IS_ROM(IS_ROM),
  168. .SAVERAM_MASK(SAVERAM_MASK),
  169. .ROM_MASK(ROM_MASK)
  170. );
  171. parameter MODE_SNES = 1'b0;
  172. parameter MODE_MCU = 1'b1;
  173. parameter ST_IDLE = 18'b000000000000000001;
  174. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  175. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  176. parameter ST_SNES_RD_END = 18'b000000000000001000;
  177. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  178. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  179. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  180. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  181. parameter ST_SNES_WR_END = 18'b000000000100000000;
  182. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  183. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  184. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  185. parameter ST_MCU_RD_END = 18'b000001000000000000;
  186. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  187. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  188. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  189. parameter ST_MCU_WR_END = 18'b010000000000000000;
  190. parameter ROM_RD_WAIT = 4'h0;
  191. parameter ROM_RD_WAIT_MCU = 4'h6;
  192. parameter ROM_WR_WAIT = 4'h4;
  193. parameter ROM_WR_WAIT1 = 4'h2;
  194. parameter ROM_WR_WAIT2 = 4'h1;
  195. parameter ROM_WR_WAIT_MCU = 4'h5;
  196. parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
  197. reg [17:0] STATE;
  198. initial STATE = ST_IDLE;
  199. reg [7:0] SNES_DINr;
  200. reg [7:0] SNES_DOUTr;
  201. reg [7:0] ROM_DOUTr;
  202. assign SNES_DATA = ~SNES_READ ? SNES_DOUTr
  203. : 8'bZ;
  204. reg [3:0] ST_MEM_DELAYr;
  205. reg MCU_RD_PENDr;
  206. reg MCU_WR_PENDr;
  207. reg [23:0] ROM_ADDRr;
  208. reg NEED_SNES_ADDRr;
  209. always @(posedge CLK2) begin
  210. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  211. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  212. end
  213. reg RQ_MCU_RDYr;
  214. initial RQ_MCU_RDYr = 1'b1;
  215. assign MCU_RDY = RQ_MCU_RDYr;
  216. reg ROM_SAr;
  217. initial ROM_SAr = 1'b1;
  218. //wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
  219. wire ROM_SA = ROM_SAr;
  220. assign ROM_ADDR = (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  221. assign ROM_ADDR0 = (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  222. reg ROM_WEr;
  223. initial ROM_WEr = 1'b1;
  224. reg ROM_DOUT_ENr;
  225. initial ROM_DOUT_ENr = 1'b0;
  226. reg[17:0] SNES_DEAD_CNTr;
  227. initial SNES_DEAD_CNTr = 0;
  228. always @(posedge CLK2) begin
  229. if(MCU_RRQ) begin
  230. MCU_RD_PENDr <= 1'b1;
  231. RQ_MCU_RDYr <= 1'b0;
  232. ROM_ADDRr <= MCU_ADDR;
  233. end else if(MCU_WRQ) begin
  234. MCU_WR_PENDr <= 1'b1;
  235. RQ_MCU_RDYr <= 1'b0;
  236. ROM_ADDRr <= MCU_ADDR;
  237. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  238. MCU_RD_PENDr <= 1'b0;
  239. MCU_WR_PENDr <= 1'b0;
  240. RQ_MCU_RDYr <= 1'b1;
  241. end
  242. end
  243. always @(posedge CLK2) begin
  244. if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
  245. else SNES_DEAD_CNTr <= 17'h0;
  246. end
  247. always @(posedge CLK2) begin
  248. if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
  249. else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
  250. end
  251. reg snes_wr_cycle;
  252. always @(posedge CLK2) begin
  253. if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
  254. else
  255. case(STATE)
  256. ST_IDLE: begin
  257. ROM_SAr <= 1'b1;
  258. ROM_DOUT_ENr <= 1'b0;
  259. if(SNES_cycle_start & ~SNES_WRITE) begin
  260. STATE <= ST_SNES_WR_ADDR;
  261. if(IS_SAVERAM) begin
  262. ROM_WEr <= 1'b0;
  263. ROM_DOUT_ENr <= 1'b1;
  264. end
  265. end else if(SNES_cycle_start) begin
  266. // STATE <= ST_SNES_RD_ADDR;
  267. STATE <= ST_SNES_RD_END;
  268. SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  269. end else if(SNES_DEADr & MCU_RD_PENDr) begin
  270. STATE <= ST_MCU_RD_ADDR;
  271. end else if(SNES_DEADr & MCU_WR_PENDr) begin
  272. STATE <= ST_MCU_WR_ADDR;
  273. end
  274. end
  275. ST_SNES_RD_ADDR: begin
  276. ST_MEM_DELAYr <= ROM_RD_WAIT;
  277. STATE <= ST_SNES_RD_WAIT;
  278. end
  279. ST_SNES_RD_WAIT: begin
  280. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  281. // if(ST_MEM_DELAYr == 0) begin
  282. // end
  283. // else STATE <= ST_SNES_RD_WAIT;
  284. end
  285. ST_SNES_WR_ADDR: begin
  286. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  287. STATE <= ST_SNES_WR_WAIT1;
  288. end
  289. ST_SNES_WR_WAIT1: begin
  290. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  291. if(ST_MEM_DELAYr == 0) begin
  292. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  293. STATE <= ST_SNES_WR_WAIT2;
  294. ROM_DOUTr <= SNES_DATA;
  295. end
  296. else STATE <= ST_SNES_WR_WAIT1;
  297. end
  298. ST_SNES_WR_WAIT2: begin
  299. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  300. if(ST_MEM_DELAYr == 0) begin
  301. STATE <= ST_SNES_WR_END;
  302. ROM_WEr <= 1'b1;
  303. end
  304. else STATE <= ST_SNES_WR_WAIT2;
  305. end
  306. ST_SNES_RD_END, ST_SNES_WR_END: begin
  307. ROM_DOUT_ENr <= 1'b0;
  308. if(MCU_RD_PENDr) begin
  309. STATE <= ST_MCU_RD_ADDR;
  310. end else if(MCU_WR_PENDr) begin
  311. STATE <= ST_MCU_WR_ADDR;
  312. end else STATE <= ST_IDLE;
  313. end
  314. ST_MCU_RD_ADDR: begin
  315. ROM_SAr <= 1'b0;
  316. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  317. STATE <= ST_MCU_RD_WAIT;
  318. end
  319. ST_MCU_RD_WAIT: begin
  320. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  321. if(ST_MEM_DELAYr == 0) begin
  322. STATE <= ST_MCU_RD_END;
  323. end
  324. else STATE <= ST_MCU_RD_WAIT;
  325. end
  326. ST_MCU_RD_END: begin
  327. MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
  328. STATE <= ST_IDLE;
  329. end
  330. ST_MCU_WR_ADDR: begin
  331. ROM_DOUTr <= MCU_DOUT;
  332. ROM_SAr <= 1'b0;
  333. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  334. STATE <= ST_MCU_WR_WAIT;
  335. ROM_DOUT_ENr <= 1'b1;
  336. ROM_WEr <= 1'b0;
  337. end
  338. ST_MCU_WR_WAIT: begin
  339. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  340. if(ST_MEM_DELAYr == 0) begin
  341. ROM_WEr <= 1'b1;
  342. STATE <= ST_MCU_WR_END;
  343. end
  344. else STATE <= ST_MCU_WR_WAIT;
  345. end
  346. ST_MCU_WR_END: begin
  347. ROM_DOUT_ENr <= 1'b0;
  348. STATE <= ST_IDLE;
  349. end
  350. endcase
  351. end
  352. reg ROM_WE_1;
  353. always @(posedge CLK2) begin
  354. ROM_WE_1 <= ROM_WE;
  355. end
  356. assign ROM_DATA[7:0] = ROM_ADDR0
  357. ?(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ)
  358. :8'bZ;
  359. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  360. :(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
  361. assign ROM_WE = ROM_WEr;
  362. // OE always active. Overridden by WE when needed.
  363. assign ROM_OE = 1'b0;
  364. assign ROM_CE = 1'b0;
  365. assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
  366. assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
  367. assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
  368. |(!IS_ROM & !IS_SAVERAM)
  369. |(SNES_READr[0] & SNES_WRITEr[0])
  370. );
  371. assign SNES_DATABUS_DIR = (!SNES_READr[0])
  372. ? 1'b1
  373. : 1'b0;
  374. assign SNES_IRQ = 1'b0;
  375. assign p113_out = 1'b0;
  376. /*
  377. wire [35:0] CONTROL0;
  378. icon icon (
  379. .CONTROL0(CONTROL0) // INOUT BUS [35:0]
  380. );
  381. ila_srtc ila (
  382. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  383. .CLK(CLK2), // IN
  384. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  385. .TRIG1(SNES_DATA), // IN BUS [7:0]
  386. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
  387. .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
  388. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  389. .TRIG5(ROM_DATA), // IN BUS [15:0]
  390. .TRIG6(MCU_DINr), // IN BUS [7:0]
  391. .TRIG7(spi_byte_cnt[3:0])
  392. );
  393. */
  394. /*
  395. ila_srtc ila (
  396. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  397. .CLK(CLK2), // IN
  398. .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
  399. .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
  400. .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
  401. .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
  402. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  403. .TRIG5(ROM_DATA), // IN BUS [15:0]
  404. .TRIG6(MCU_DINr), // IN BUS [7:0]
  405. .TRIG7(ST_MEM_DELAYr)
  406. );
  407. */
  408. endmodule