main.v 20 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR_IN,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. output SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. input SNES_SYSCLK,
  36. input [7:0] SNES_PA,
  37. input SNES_PARD,
  38. input SNES_PAWR,
  39. /* SRAM signals */
  40. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  41. inout [15:0] ROM_DATA,
  42. output [22:0] ROM_ADDR,
  43. output ROM_CE,
  44. output ROM_OE,
  45. output ROM_WE,
  46. output ROM_BHE,
  47. output ROM_BLE,
  48. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  49. inout [7:0] RAM_DATA,
  50. output [18:0] RAM_ADDR,
  51. output RAM_CE,
  52. output RAM_OE,
  53. output RAM_WE,
  54. /* MCU signals */
  55. input SPI_MOSI,
  56. inout SPI_MISO,
  57. input SPI_SS,
  58. inout SPI_SCK,
  59. input MCU_OVR,
  60. output MCU_RDY,
  61. output DAC_MCLK,
  62. output DAC_LRCK,
  63. output DAC_SDOUT,
  64. /* SD signals */
  65. input [3:0] SD_DAT,
  66. inout SD_CMD,
  67. inout SD_CLK,
  68. /* debug */
  69. output p113_out
  70. );
  71. wire CLK2;
  72. reg [23:0] SNES_ADDR_r [2:0];
  73. always @(posedge CLK2) begin
  74. SNES_ADDR_r[2] <= SNES_ADDR_r[1];
  75. SNES_ADDR_r[1] <= SNES_ADDR_r[0];
  76. SNES_ADDR_r[0] <= SNES_ADDR_IN;
  77. end
  78. wire [23:0] SNES_ADDR = SNES_ADDR_r[2] & SNES_ADDR_r[1];
  79. wire [7:0] CX4_SNES_DATA_IN;
  80. wire [7:0] CX4_SNES_DATA_OUT;
  81. wire [7:0] spi_cmd_data;
  82. wire [7:0] spi_param_data;
  83. wire [7:0] spi_input_data;
  84. wire [31:0] spi_byte_cnt;
  85. wire [2:0] spi_bit_cnt;
  86. wire [23:0] MCU_ADDR;
  87. wire [2:0] MAPPER;
  88. wire [23:0] SAVERAM_MASK;
  89. wire [23:0] ROM_MASK;
  90. wire [7:0] SD_DMA_SRAM_DATA;
  91. wire [1:0] SD_DMA_TGT;
  92. wire [10:0] SD_DMA_PARTIAL_START;
  93. wire [10:0] SD_DMA_PARTIAL_END;
  94. wire [10:0] dac_addr;
  95. //wire [7:0] dac_volume;
  96. wire [7:0] msu_volumerq_out;
  97. wire [6:0] msu_status_out;
  98. wire [31:0] msu_addressrq_out;
  99. wire [15:0] msu_trackrq_out;
  100. wire [13:0] msu_write_addr;
  101. wire [13:0] msu_ptr_addr;
  102. wire [7:0] MSU_SNES_DATA_IN;
  103. wire [7:0] MSU_SNES_DATA_OUT;
  104. wire [5:0] msu_status_reset_bits;
  105. wire [5:0] msu_status_set_bits;
  106. wire [23:0] MAPPED_SNES_ADDR;
  107. wire ROM_ADDR0;
  108. wire [23:0] cx4_datrom_data;
  109. wire [9:0] cx4_datrom_addr;
  110. wire cx4_datrom_we;
  111. sd_dma snes_sd_dma(
  112. .CLK(CLK2),
  113. .SD_DAT(SD_DAT),
  114. .SD_CLK(SD_CLK),
  115. .SD_DMA_EN(SD_DMA_EN),
  116. .SD_DMA_STATUS(SD_DMA_STATUS),
  117. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  118. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  119. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  120. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  121. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  122. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  123. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  124. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
  125. );
  126. wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
  127. dac snes_dac(
  128. .clkin(CLK2),
  129. .sysclk(SNES_SYSCLK),
  130. .mclk(DAC_MCLK),
  131. .lrck(DAC_LRCK),
  132. .sdout(DAC_SDOUT),
  133. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  134. .pgm_address(dac_addr),
  135. .pgm_data(SD_DMA_SRAM_DATA),
  136. .DAC_STATUS(DAC_STATUS),
  137. .volume(msu_volumerq_out),
  138. .vol_latch(msu_volume_latch_out),
  139. .play(dac_play),
  140. .reset(dac_reset)
  141. );
  142. msu snes_msu (
  143. .clkin(CLK2),
  144. .enable(msu_enable),
  145. .pgm_address(msu_write_addr),
  146. .pgm_data(SD_DMA_SRAM_DATA),
  147. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  148. .reg_addr(SNES_ADDR[2:0]),
  149. .reg_data_in(MSU_SNES_DATA_IN),
  150. .reg_data_out(MSU_SNES_DATA_OUT),
  151. .reg_oe(SNES_READ),
  152. .reg_we(SNES_WRITE),
  153. .status_out(msu_status_out),
  154. .volume_out(msu_volumerq_out),
  155. .volume_latch_out(msu_volume_latch_out),
  156. .addr_out(msu_addressrq_out),
  157. .track_out(msu_trackrq_out),
  158. .status_reset_bits(msu_status_reset_bits),
  159. .status_set_bits(msu_status_set_bits),
  160. .status_reset_we(msu_status_reset_we),
  161. .msu_address_ext(msu_ptr_addr),
  162. .msu_address_ext_write(msu_addr_reset)
  163. );
  164. spi snes_spi(
  165. .clk(CLK2),
  166. .MOSI(SPI_MOSI),
  167. .MISO(SPI_MISO),
  168. .SSEL(SPI_SS),
  169. .SCK(SPI_SCK),
  170. .cmd_ready(spi_cmd_ready),
  171. .param_ready(spi_param_ready),
  172. .cmd_data(spi_cmd_data),
  173. .param_data(spi_param_data),
  174. .endmessage(spi_endmessage),
  175. .startmessage(spi_startmessage),
  176. .input_data(spi_input_data),
  177. .byte_cnt(spi_byte_cnt),
  178. .bit_cnt(spi_bit_cnt)
  179. );
  180. reg [7:0] MCU_DINr;
  181. wire [7:0] MCU_DOUT;
  182. mcu_cmd snes_mcu_cmd(
  183. .clk(CLK2),
  184. .snes_sysclk(SNES_SYSCLK),
  185. .cmd_ready(spi_cmd_ready),
  186. .param_ready(spi_param_ready),
  187. .cmd_data(spi_cmd_data),
  188. .param_data(spi_param_data),
  189. .mcu_mapper(MAPPER),
  190. .mcu_write(MCU_WRITE),
  191. .mcu_data_in(MCU_DINr),
  192. .mcu_data_out(MCU_DOUT),
  193. .spi_byte_cnt(spi_byte_cnt),
  194. .spi_bit_cnt(spi_bit_cnt),
  195. .spi_data_out(spi_input_data),
  196. .addr_out(MCU_ADDR),
  197. .saveram_mask_out(SAVERAM_MASK),
  198. .rom_mask_out(ROM_MASK),
  199. .SD_DMA_EN(SD_DMA_EN),
  200. .SD_DMA_STATUS(SD_DMA_STATUS),
  201. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  202. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  203. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  204. .SD_DMA_TGT(SD_DMA_TGT),
  205. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  206. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  207. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  208. .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
  209. .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
  210. .dac_addr_out(dac_addr),
  211. .DAC_STATUS(DAC_STATUS),
  212. // .dac_volume_out(dac_volume),
  213. // .dac_volume_latch_out(dac_vol_latch),
  214. .dac_play_out(dac_play),
  215. .dac_reset_out(dac_reset),
  216. .msu_addr_out(msu_write_addr),
  217. .MSU_STATUS(msu_status_out),
  218. .msu_status_reset_out(msu_status_reset_bits),
  219. .msu_status_set_out(msu_status_set_bits),
  220. .msu_status_reset_we(msu_status_reset_we),
  221. .msu_volumerq(msu_volumerq_out),
  222. .msu_addressrq(msu_addressrq_out),
  223. .msu_trackrq(msu_trackrq_out),
  224. .msu_ptr_out(msu_ptr_addr),
  225. .msu_reset_out(msu_addr_reset),
  226. .mcu_rrq(MCU_RRQ),
  227. .mcu_wrq(MCU_WRQ),
  228. .mcu_rq_rdy(MCU_RDY),
  229. .use_msu1(use_msu1),
  230. .cx4_datrom_addr_out(cx4_datrom_addr),
  231. .cx4_datrom_data_out(cx4_datrom_data),
  232. .cx4_datrom_we_out(cx4_datrom_we),
  233. .cx4_reset_out(cx4_reset),
  234. .region_out(mcu_region)
  235. );
  236. wire [7:0] DCM_STATUS;
  237. // dcm1: dfs 4x
  238. my_dcm snes_dcm(
  239. .CLKIN(CLKIN),
  240. .CLKFX(CLK2),
  241. .LOCKED(DCM_LOCKED),
  242. .RST(DCM_RST),
  243. .STATUS(DCM_STATUS)
  244. );
  245. assign DCM_RST=0;
  246. reg [7:0] SNES_PARDr;
  247. reg [7:0] SNES_PAWRr;
  248. reg [7:0] SNES_READr;
  249. reg [7:0] SNES_WRITEr;
  250. reg [7:0] SNES_CPU_CLKr;
  251. wire SNES_FAKE_CLK = &SNES_CPU_CLKr[2:1];
  252. //wire SNES_FAKE_CLK = ~(SNES_READ & SNES_WRITE);
  253. reg SNES_DEADr;
  254. initial SNES_DEADr = 0;
  255. wire SNES_PARD_start = (SNES_PARDr[7:1] == 7'b1111110);
  256. wire SNES_PAWR_start = (SNES_PAWRr[7:1] == 7'b0000001);
  257. wire SNES_RD_start = (SNES_READr[7:1] == 7'b1111110);
  258. wire SNES_WR_start = (SNES_WRITEr[7:1] == 7'b1111110);
  259. wire SNES_WR_end = (SNES_WRITEr[7:1] == 7'b0000001);
  260. wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000001);
  261. wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b111110);
  262. always @(posedge CLK2) begin
  263. SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD};
  264. end
  265. always @(posedge CLK2) begin
  266. SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR};
  267. SNES_READr <= {SNES_READr[6:0], SNES_READ};
  268. SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE};
  269. SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK};
  270. end
  271. address snes_addr(
  272. .CLK(CLK2),
  273. .MAPPER(MAPPER),
  274. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  275. .SNES_PA(SNES_PA),
  276. .SNES_CS(SNES_CS),
  277. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  278. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  279. .IS_SAVERAM(IS_SAVERAM),
  280. .IS_ROM(IS_ROM),
  281. .IS_WRITABLE(IS_WRITABLE),
  282. .SAVERAM_MASK(SAVERAM_MASK),
  283. .ROM_MASK(ROM_MASK),
  284. .use_msu1(use_msu1),
  285. //MSU-1
  286. .msu_enable(msu_enable),
  287. //CX4
  288. .cx4_enable(cx4_enable),
  289. .cx4_vect_enable(cx4_vect_enable),
  290. //region
  291. .r213f_enable(r213f_enable),
  292. //CMD Interface
  293. .snescmd_rd_enable(snescmd_rd_enable),
  294. .snescmd_wr_enable(snescmd_wr_enable)
  295. );
  296. reg [7:0] CX4_DINr;
  297. wire [23:0] CX4_ADDR;
  298. cx4 snes_cx4 (
  299. .DI(CX4_SNES_DATA_IN),
  300. .DO(CX4_SNES_DATA_OUT),
  301. .ADDR(SNES_ADDR[12:0]),
  302. .CS(cx4_enable),
  303. .SNES_VECT_EN(cx4_vect_enable),
  304. .nRD(SNES_READ),
  305. .nWR(SNES_WRITE),
  306. .CLK(CLK2),
  307. .DATROM_DI(cx4_datrom_data),
  308. .DATROM_WE(cx4_datrom_we),
  309. .DATROM_ADDR(cx4_datrom_addr),
  310. .BUS_DI(CX4_DINr),
  311. .BUS_ADDR(CX4_ADDR),
  312. .BUS_RRQ(CX4_RRQ),
  313. .BUS_RDY(CX4_RDY),
  314. .cx4_active(cx4_active)
  315. );
  316. parameter MODE_SNES = 1'b0;
  317. parameter MODE_MCU = 1'b1;
  318. parameter ST_IDLE = 21'b000000000000000000001;
  319. parameter ST_SNES_RD_ADDR = 21'b000000000000000000010;
  320. parameter ST_SNES_RD_WAIT = 21'b000000000000000000100;
  321. parameter ST_SNES_RD_END = 21'b000000000000000001000;
  322. parameter ST_SNES_WR_ADDR = 21'b000000000000000010000;
  323. parameter ST_SNES_WR_WAIT1= 21'b000000000000000100000;
  324. parameter ST_SNES_WR_DATA = 21'b000000000000001000000;
  325. parameter ST_SNES_WR_WAIT2= 21'b000000000000010000000;
  326. parameter ST_SNES_WR_END = 21'b000000000000100000000;
  327. parameter ST_MCU_RD_ADDR = 21'b000000000001000000000;
  328. parameter ST_MCU_RD_WAIT = 21'b000000000010000000000;
  329. parameter ST_MCU_RD_WAIT2 = 21'b000000000100000000000;
  330. parameter ST_MCU_RD_END = 21'b000000001000000000000;
  331. parameter ST_MCU_WR_ADDR = 21'b000000010000000000000;
  332. parameter ST_MCU_WR_WAIT = 21'b000000100000000000000;
  333. parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000;
  334. parameter ST_MCU_WR_END = 21'b000010000000000000000;
  335. parameter ST_CX4_RD_ADDR = 21'b000100000000000000000;
  336. parameter ST_CX4_RD_WAIT = 21'b001000000000000000000;
  337. parameter ST_CX4_RD_END = 21'b010000000000000000000;
  338. parameter ROM_RD_WAIT = 4'h0;
  339. parameter ROM_RD_WAIT_MCU = 4'h6;
  340. parameter ROM_WR_WAIT = 4'h4;
  341. parameter ROM_WR_WAIT1 = 4'h2;
  342. parameter ROM_WR_WAIT2 = 4'h1;
  343. parameter ROM_WR_WAIT_MCU = 4'h5;
  344. parameter ROM_RD_WAIT_CX4 = 4'h6;
  345. parameter SNES_DEAD_TIMEOUT = 17'd88000; // 1ms
  346. reg [20:0] STATE;
  347. initial STATE = ST_IDLE;
  348. reg [7:0] SNES_DINr;
  349. reg [7:0] SNES_DOUTr;
  350. reg [7:0] ROM_DOUTr;
  351. assign MSU_SNES_DATA_IN = SNES_DATA;
  352. assign CX4_SNES_DATA_IN = SNES_DATA;
  353. reg [7:0] r213fr;
  354. reg r213f_forceread;
  355. reg [2:0] r213f_delay;
  356. reg [1:0] r213f_state;
  357. initial r213fr = 8'h55;
  358. initial r213f_forceread = 0;
  359. initial r213f_state = 2'b01;
  360. initial r213f_delay = 3'b011;
  361. reg[7:0] snescmd_regs[15:0];
  362. assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
  363. :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
  364. :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
  365. ? (msu_enable ? MSU_SNES_DATA_OUT
  366. :cx4_enable ? CX4_SNES_DATA_OUT
  367. :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
  368. :SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
  369. reg [3:0] ST_MEM_DELAYr;
  370. reg MCU_RD_PENDr;
  371. reg MCU_WR_PENDr;
  372. reg CX4_RD_PENDr;
  373. reg [23:0] ROM_ADDRr;
  374. reg NEED_SNES_ADDRr;
  375. always @(posedge CLK2) begin
  376. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  377. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  378. end
  379. wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE;
  380. reg RQ_MCU_RDYr;
  381. initial RQ_MCU_RDYr = 1'b1;
  382. assign MCU_RDY = RQ_MCU_RDYr;
  383. reg RQ_CX4_RDYr;
  384. initial RQ_CX4_RDYr = 1'b1;
  385. assign CX4_RDY = RQ_CX4_RDYr;
  386. reg ROM_SAr;
  387. initial ROM_SAr = 1'b1;
  388. wire ROM_SA = ROM_SAr;
  389. reg ROM_CAr;
  390. initial ROM_CAr = 1'b0;
  391. wire ROM_CA = ROM_CAr;
  392. reg [23:0] CX4_ADDRr;
  393. assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : ROM_CA ? CX4_ADDRr[23:1] : ROM_SA ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  394. assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : ROM_CA ? CX4_ADDRr[0] : ROM_SA ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  395. reg ROM_WEr;
  396. initial ROM_WEr = 1'b1;
  397. reg ROM_DOUT_ENr;
  398. initial ROM_DOUT_ENr = 1'b0;
  399. reg[17:0] SNES_DEAD_CNTr;
  400. initial SNES_DEAD_CNTr = 0;
  401. always @(posedge CLK2) begin
  402. if(cx4_active) begin
  403. if(CX4_RRQ) begin
  404. CX4_RD_PENDr <= 1'b1;
  405. RQ_CX4_RDYr <= 1'b0;
  406. CX4_ADDRr <= CX4_ADDR;
  407. end else if(STATE == ST_CX4_RD_END) begin
  408. CX4_RD_PENDr <= 1'b0;
  409. RQ_CX4_RDYr <= 1'b1;
  410. end
  411. end else begin
  412. CX4_RD_PENDr <= 1'b0;
  413. RQ_CX4_RDYr <= 1'b1;
  414. end
  415. end
  416. always @(posedge CLK2) begin
  417. if(MCU_RRQ) begin
  418. MCU_RD_PENDr <= 1'b1;
  419. RQ_MCU_RDYr <= 1'b0;
  420. ROM_ADDRr <= MCU_ADDR;
  421. end else if(MCU_WRQ) begin
  422. MCU_WR_PENDr <= 1'b1;
  423. RQ_MCU_RDYr <= 1'b0;
  424. ROM_ADDRr <= MCU_ADDR;
  425. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  426. MCU_RD_PENDr <= 1'b0;
  427. MCU_WR_PENDr <= 1'b0;
  428. RQ_MCU_RDYr <= 1'b1;
  429. end
  430. end
  431. always @(posedge CLK2) begin
  432. if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
  433. else SNES_DEAD_CNTr <= 17'h0;
  434. end
  435. always @(posedge CLK2) begin
  436. if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
  437. else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
  438. end
  439. always @(posedge CLK2) begin
  440. if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
  441. else
  442. case(STATE)
  443. ST_IDLE: begin
  444. ROM_SAr <= 1'b1;
  445. ROM_CAr <= 1'b0;
  446. ROM_DOUT_ENr <= 1'b0;
  447. if(cx4_active) begin
  448. if(CX4_RD_PENDr) STATE <= ST_CX4_RD_ADDR;
  449. end else if(SNES_cycle_start & ~SNES_WRITE) begin
  450. STATE <= ST_SNES_WR_ADDR;
  451. if(IS_SAVERAM | IS_WRITABLE) begin
  452. ROM_WEr <= 1'b0;
  453. ROM_DOUT_ENr <= 1'b1;
  454. end
  455. end else if(SNES_cycle_start) begin
  456. // STATE <= ST_SNES_RD_ADDR;
  457. STATE <= ST_SNES_RD_END;
  458. SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  459. end else if(SNES_DEADr & MCU_RD_PENDr) begin
  460. STATE <= ST_MCU_RD_ADDR;
  461. end else if(SNES_DEADr & MCU_WR_PENDr) begin
  462. STATE <= ST_MCU_WR_ADDR;
  463. end
  464. end
  465. ST_SNES_RD_ADDR: begin
  466. ST_MEM_DELAYr <= ROM_RD_WAIT;
  467. STATE <= ST_SNES_RD_WAIT;
  468. end
  469. ST_SNES_RD_WAIT: begin
  470. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  471. // if(ST_MEM_DELAYr == 0) begin
  472. // end
  473. // else STATE <= ST_SNES_RD_WAIT;
  474. end
  475. ST_SNES_WR_ADDR: begin
  476. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  477. STATE <= ST_SNES_WR_WAIT1;
  478. end
  479. ST_SNES_WR_WAIT1: begin
  480. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  481. if(ST_MEM_DELAYr == 0) begin
  482. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  483. STATE <= ST_SNES_WR_WAIT2;
  484. ROM_DOUTr <= SNES_DATA;
  485. end
  486. else STATE <= ST_SNES_WR_WAIT1;
  487. end
  488. ST_SNES_WR_WAIT2: begin
  489. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  490. if(ST_MEM_DELAYr == 0) begin
  491. STATE <= ST_SNES_WR_END;
  492. ROM_WEr <= 1'b1;
  493. end
  494. else STATE <= ST_SNES_WR_WAIT2;
  495. end
  496. ST_SNES_RD_END, ST_SNES_WR_END: begin
  497. ROM_DOUT_ENr <= 1'b0;
  498. if(MCU_RD_PENDr) begin
  499. STATE <= ST_MCU_RD_ADDR;
  500. end else if(MCU_WR_PENDr) begin
  501. STATE <= ST_MCU_WR_ADDR;
  502. end else STATE <= ST_IDLE;
  503. end
  504. ST_MCU_RD_ADDR: begin
  505. ROM_SAr <= 1'b0;
  506. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  507. STATE <= ST_MCU_RD_WAIT;
  508. end
  509. ST_MCU_RD_WAIT: begin
  510. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  511. if(ST_MEM_DELAYr == 0) begin
  512. STATE <= ST_MCU_RD_END;
  513. end
  514. else STATE <= ST_MCU_RD_WAIT;
  515. end
  516. ST_MCU_RD_END: begin
  517. MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
  518. STATE <= ST_IDLE;
  519. end
  520. ST_MCU_WR_ADDR: begin
  521. ROM_DOUTr <= MCU_DOUT;
  522. ROM_SAr <= 1'b0;
  523. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  524. STATE <= ST_MCU_WR_WAIT;
  525. ROM_DOUT_ENr <= 1'b1;
  526. ROM_WEr <= 1'b0;
  527. end
  528. ST_MCU_WR_WAIT: begin
  529. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  530. if(ST_MEM_DELAYr == 0) begin
  531. ROM_WEr <= 1'b1;
  532. STATE <= ST_MCU_WR_END;
  533. end
  534. else STATE <= ST_MCU_WR_WAIT;
  535. end
  536. ST_MCU_WR_END: begin
  537. ROM_DOUT_ENr <= 1'b0;
  538. STATE <= ST_IDLE;
  539. end
  540. ST_CX4_RD_ADDR: begin
  541. ROM_CAr <= 1'b1;
  542. ST_MEM_DELAYr <= ROM_RD_WAIT_CX4;
  543. STATE <= ST_CX4_RD_WAIT;
  544. end
  545. ST_CX4_RD_WAIT: begin
  546. ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
  547. if(ST_MEM_DELAYr == 0) begin
  548. STATE <= ST_CX4_RD_END;
  549. end
  550. else STATE <= ST_CX4_RD_WAIT;
  551. end
  552. ST_CX4_RD_END: begin
  553. ROM_CAr <= 1'b0;
  554. CX4_DINr <= CX4_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
  555. STATE <= ST_IDLE;
  556. end
  557. endcase
  558. end
  559. always @(posedge SYSCLK2) begin
  560. if(SNES_PARD_start & r213f_enable) begin
  561. r213f_forceread <= 1'b1;
  562. r213f_delay <= 3'b001;
  563. r213f_state <= 2'b10;
  564. end else if(r213f_state == 2'b10) begin
  565. r213f_delay <= r213f_delay - 1;
  566. if(r213f_delay == 3'b000) begin
  567. r213f_forceread <= 1'b0;
  568. r213f_state <= 2'b01;
  569. r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
  570. end
  571. end
  572. end
  573. always @(posedge CLK2) begin
  574. if(SNES_WR_end & snescmd_wr_enable) begin
  575. snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
  576. end
  577. end
  578. reg ROM_WE_1;
  579. reg MCU_WRITE_1;
  580. always @(posedge CLK2) begin
  581. ROM_WE_1 <= ROM_WE;
  582. MCU_WRITE_1<= MCU_WRITE;
  583. end
  584. assign ROM_DATA[7:0] = ROM_ADDR0
  585. ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  586. /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
  587. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  588. )
  589. :8'bZ;
  590. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  591. :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
  592. /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
  593. : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
  594. );
  595. assign ROM_WE = SD_DMA_TO_ROM
  596. ?MCU_WRITE
  597. :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
  598. // OE always active. Overridden by WE when needed.
  599. assign ROM_OE = 1'b0;
  600. assign ROM_CE = 1'b0;
  601. assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
  602. assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
  603. assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
  604. cx4_enable ? 1'b0 :
  605. (cx4_active & cx4_vect_enable) ? 1'b0 :
  606. r213f_enable & !SNES_PARD ? 1'b0 :
  607. (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
  608. ((IS_ROM & SNES_CS)
  609. |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
  610. |(SNES_READr[0] & SNES_WRITEr[0])
  611. );
  612. assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
  613. ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
  614. : 1'b0;
  615. assign SNES_IRQ = 1'b0;
  616. assign p113_out = 1'b0;
  617. /*
  618. wire [35:0] CONTROL0;
  619. icon icon (
  620. .CONTROL0(CONTROL0) // INOUT BUS [35:0]
  621. );
  622. ila ila (
  623. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  624. .CLK(CLK2), // IN
  625. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  626. .TRIG1(SNES_DATA), // IN BUS [7:0]
  627. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, cx4_active, ROM_WE, ROM_DOUT_ENr, ROM_SA, CX4_RRQ, CX4_RDY, ROM_CA}), // IN BUS [15:0]
  628. .TRIG3(ROM_ADDRr), // IN BUS [23:0]
  629. .TRIG4(CX4_ADDRr), // IN BUS [23:0]
  630. .TRIG5(ROM_DATA), // IN BUS [15:0]
  631. .TRIG6(CX4_DINr), // IN BUS [7:0]
  632. .TRIG7(STATE) // IN BUS [21:0]
  633. );*/
  634. /*
  635. ila ila (
  636. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  637. .CLK(CLK2), // IN
  638. .TRIG0(SNES_ADDR), // IN BUS [23:0]
  639. .TRIG1(SNES_DATA), // IN BUS [7:0]
  640. .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
  641. .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
  642. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  643. .TRIG5(ROM_DATA), // IN BUS [15:0]
  644. .TRIG6(MCU_DINr), // IN BUS [7:0]
  645. .TRIG7(spi_byte_cnt[3:0])
  646. );
  647. */
  648. /*
  649. ila_srtc ila (
  650. .CONTROL(CONTROL0), // INOUT BUS [35:0]
  651. .CLK(CLK2), // IN
  652. .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
  653. .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
  654. .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
  655. .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
  656. .TRIG4(ROM_ADDRr), // IN BUS [23:0]
  657. .TRIG5(ROM_DATA), // IN BUS [15:0]
  658. .TRIG6(MCU_DINr), // IN BUS [7:0]
  659. .TRIG7(ST_MEM_DELAYr)
  660. );
  661. */
  662. endmodule