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@@ -8,8 +8,10 @@
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#include <common.h>
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#include <dm.h>
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+#include <dm/device_compat.h>
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#include <malloc.h>
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-#include <spi.h>
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+#include <spi-mem.h>
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+#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/log2.h>
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#include <clk.h>
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@@ -85,6 +87,11 @@
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#define SIFIVE_SPI_IP_TXWM BIT(0)
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#define SIFIVE_SPI_IP_RXWM BIT(1)
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+/* format protocol */
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+#define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */
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+#define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */
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+#define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */
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+
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struct sifive_spi {
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void *regs; /* base address of the registers */
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u32 fifo_depth;
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@@ -92,28 +99,29 @@ struct sifive_spi {
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u32 cs_inactive; /* Level of the CS pins when inactive*/
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u32 freq;
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u32 num_cs;
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+ u8 fmt_proto;
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};
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static void sifive_spi_prep_device(struct sifive_spi *spi,
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- struct dm_spi_slave_platdata *slave)
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+ struct dm_spi_slave_platdata *slave_plat)
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{
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/* Update the chip select polarity */
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- if (slave->mode & SPI_CS_HIGH)
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- spi->cs_inactive &= ~BIT(slave->cs);
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+ if (slave_plat->mode & SPI_CS_HIGH)
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+ spi->cs_inactive &= ~BIT(slave_plat->cs);
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else
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- spi->cs_inactive |= BIT(slave->cs);
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+ spi->cs_inactive |= BIT(slave_plat->cs);
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writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
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/* Select the correct device */
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- writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID);
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+ writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
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}
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static int sifive_spi_set_cs(struct sifive_spi *spi,
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- struct dm_spi_slave_platdata *slave)
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+ struct dm_spi_slave_platdata *slave_plat)
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{
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u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
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- if (slave->mode & SPI_CS_HIGH)
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+ if (slave_plat->mode & SPI_CS_HIGH)
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cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
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writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
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@@ -127,8 +135,8 @@ static void sifive_spi_clear_cs(struct sifive_spi *spi)
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}
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static void sifive_spi_prep_transfer(struct sifive_spi *spi,
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- bool is_rx_xfer,
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- struct dm_spi_slave_platdata *slave)
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+ struct dm_spi_slave_platdata *slave_plat,
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+ u8 *rx_ptr)
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{
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u32 cr;
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@@ -141,21 +149,26 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi,
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/* LSB first? */
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cr &= ~SIFIVE_SPI_FMT_ENDIAN;
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- if (slave->mode & SPI_LSB_FIRST)
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+ if (slave_plat->mode & SPI_LSB_FIRST)
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cr |= SIFIVE_SPI_FMT_ENDIAN;
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/* Number of wires ? */
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cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
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- if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
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+ switch (spi->fmt_proto) {
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+ case SIFIVE_SPI_PROTO_QUAD:
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cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
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- else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
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+ break;
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+ case SIFIVE_SPI_PROTO_DUAL:
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cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
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- else
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+ break;
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+ default:
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cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
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+ break;
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+ }
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/* SPI direction in/out ? */
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cr &= ~SIFIVE_SPI_FMT_DIR;
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- if (!is_rx_xfer)
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+ if (!rx_ptr)
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cr |= SIFIVE_SPI_FMT_DIR;
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writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
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@@ -186,50 +199,62 @@ static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
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writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
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}
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+static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
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+{
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+ return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
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+ bit, true, 100, false);
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+}
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+
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static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct sifive_spi *spi = dev_get_priv(bus);
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- struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
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- const unsigned char *tx_ptr = dout;
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+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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+ const u8 *tx_ptr = dout;
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u8 *rx_ptr = din;
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u32 remaining_len;
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int ret;
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if (flags & SPI_XFER_BEGIN) {
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- sifive_spi_prep_device(spi, slave);
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+ sifive_spi_prep_device(spi, slave_plat);
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- ret = sifive_spi_set_cs(spi, slave);
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+ ret = sifive_spi_set_cs(spi, slave_plat);
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if (ret)
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return ret;
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}
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- sifive_spi_prep_transfer(spi, true, slave);
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+ sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
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remaining_len = bitlen / 8;
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while (remaining_len) {
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- int n_words, tx_words, rx_words;
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-
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- n_words = min(remaining_len, spi->fifo_depth);
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+ unsigned int n_words = min(remaining_len, spi->fifo_depth);
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+ unsigned int tx_words, rx_words;
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/* Enqueue n_words for transmission */
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- if (tx_ptr) {
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- for (tx_words = 0; tx_words < n_words; ++tx_words) {
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- sifive_spi_tx(spi, tx_ptr);
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- sifive_spi_rx(spi, NULL);
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- tx_ptr++;
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- }
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+ for (tx_words = 0; tx_words < n_words; tx_words++) {
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+ if (!tx_ptr)
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+ sifive_spi_tx(spi, NULL);
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+ else
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+ sifive_spi_tx(spi, tx_ptr++);
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}
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- /* Read out all the data from the RX FIFO */
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if (rx_ptr) {
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- for (rx_words = 0; rx_words < n_words; ++rx_words) {
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- sifive_spi_tx(spi, NULL);
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- sifive_spi_rx(spi, rx_ptr);
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- rx_ptr++;
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- }
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+ /* Wait for transmission + reception to complete */
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+ writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
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+ ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
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+ if (ret)
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+ return ret;
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+
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+ /* Read out all the data from the RX FIFO */
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+ for (rx_words = 0; rx_words < n_words; rx_words++)
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+ sifive_spi_rx(spi, rx_ptr++);
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+ } else {
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+ /* Wait for transmission to complete */
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+ ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
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+ if (ret)
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+ return ret;
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}
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remaining_len -= n_words;
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@@ -241,6 +266,80 @@ static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
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return 0;
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}
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+static int sifive_spi_exec_op(struct spi_slave *slave,
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+ const struct spi_mem_op *op)
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+{
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+ struct udevice *dev = slave->dev;
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+ struct sifive_spi *spi = dev_get_priv(dev->parent);
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+ unsigned long flags = SPI_XFER_BEGIN;
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+ u8 opcode = op->cmd.opcode;
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+ unsigned int pos = 0;
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+ const void *tx_buf = NULL;
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+ void *rx_buf = NULL;
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+ int op_len, i;
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+ int ret;
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+
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+ if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
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+ flags |= SPI_XFER_END;
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+
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+ spi->fmt_proto = op->cmd.buswidth;
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+
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+ /* send the opcode */
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+ ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
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+ if (ret < 0) {
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+ dev_err(dev, "failed to xfer opcode\n");
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+ return ret;
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+ }
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+
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+ op_len = op->addr.nbytes + op->dummy.nbytes;
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+ u8 op_buf[op_len];
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+
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+ /* send the addr + dummy */
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+ if (op->addr.nbytes) {
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+ /* fill address */
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+ for (i = 0; i < op->addr.nbytes; i++)
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+ op_buf[pos + i] = op->addr.val >>
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+ (8 * (op->addr.nbytes - i - 1));
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+
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+ pos += op->addr.nbytes;
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+
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+ /* fill dummy */
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+ if (op->dummy.nbytes)
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+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
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+
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+ /* make sure to set end flag, if no data bytes */
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+ if (!op->data.nbytes)
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+ flags |= SPI_XFER_END;
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+
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+ spi->fmt_proto = op->addr.buswidth;
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+
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+ ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
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+ if (ret < 0) {
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+ dev_err(dev, "failed to xfer addr + dummy\n");
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+ return ret;
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+ }
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+ }
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+
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+ /* send/received the data */
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+ if (op->data.nbytes) {
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+ if (op->data.dir == SPI_MEM_DATA_IN)
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+ rx_buf = op->data.buf.in;
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+ else
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+ tx_buf = op->data.buf.out;
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+
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+ spi->fmt_proto = op->data.buswidth;
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+
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+ ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
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+ tx_buf, rx_buf, SPI_XFER_END);
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+ if (ret) {
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+ dev_err(dev, "failed to xfer data\n");
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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static int sifive_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct sifive_spi *spi = dev_get_priv(bus);
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@@ -309,6 +408,10 @@ static void sifive_spi_init_hw(struct sifive_spi *spi)
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/* Watermark interrupts are disabled by default */
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writel(0, spi->regs + SIFIVE_SPI_REG_IE);
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+ /* Default watermark FIFO threshold values */
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+ writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
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+ writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
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+
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/* Set CS/SCK Delays and Inactive Time to defaults */
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writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
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spi->regs + SIFIVE_SPI_REG_DELAY0);
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@@ -348,11 +451,16 @@ static int sifive_spi_probe(struct udevice *bus)
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return 0;
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}
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+static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
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+ .exec_op = sifive_spi_exec_op,
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+};
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+
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static const struct dm_spi_ops sifive_spi_ops = {
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.xfer = sifive_spi_xfer,
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.set_speed = sifive_spi_set_speed,
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.set_mode = sifive_spi_set_mode,
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.cs_info = sifive_spi_cs_info,
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+ .mem_ops = &sifive_spi_mem_ops,
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};
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static const struct udevice_id sifive_spi_ids[] = {
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