spi-nor-core.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/log2.h>
  17. #include <linux/math64.h>
  18. #include <linux/sizes.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/spi-nor.h>
  21. #include <spi-mem.h>
  22. #include <spi.h>
  23. #include "sf_internal.h"
  24. /* Define max times to check status register before we give up. */
  25. /*
  26. * For everything but full-chip erase; probably could be much smaller, but kept
  27. * around for safety for now
  28. */
  29. #define HZ CONFIG_SYS_HZ
  30. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  31. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  32. *op, void *buf)
  33. {
  34. if (op->data.dir == SPI_MEM_DATA_IN)
  35. op->data.buf.in = buf;
  36. else
  37. op->data.buf.out = buf;
  38. return spi_mem_exec_op(nor->spi, op);
  39. }
  40. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  41. {
  42. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
  43. SPI_MEM_OP_NO_ADDR,
  44. SPI_MEM_OP_NO_DUMMY,
  45. SPI_MEM_OP_DATA_IN(len, NULL, 1));
  46. int ret;
  47. ret = spi_nor_read_write_reg(nor, &op, val);
  48. if (ret < 0)
  49. dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
  50. code);
  51. return ret;
  52. }
  53. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  54. {
  55. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
  56. SPI_MEM_OP_NO_ADDR,
  57. SPI_MEM_OP_NO_DUMMY,
  58. SPI_MEM_OP_DATA_OUT(len, NULL, 1));
  59. return spi_nor_read_write_reg(nor, &op, buf);
  60. }
  61. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  62. u_char *buf)
  63. {
  64. struct spi_mem_op op =
  65. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
  66. SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
  67. SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
  68. SPI_MEM_OP_DATA_IN(len, buf, 1));
  69. size_t remaining = len;
  70. int ret;
  71. /* get transfer protocols. */
  72. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
  73. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
  74. op.dummy.buswidth = op.addr.buswidth;
  75. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
  76. /* convert the dummy cycles to the number of bytes */
  77. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  78. while (remaining) {
  79. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  80. ret = spi_mem_adjust_op_size(nor->spi, &op);
  81. if (ret)
  82. return ret;
  83. ret = spi_mem_exec_op(nor->spi, &op);
  84. if (ret)
  85. return ret;
  86. op.addr.val += op.data.nbytes;
  87. remaining -= op.data.nbytes;
  88. op.data.buf.in += op.data.nbytes;
  89. }
  90. return len;
  91. }
  92. static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
  93. const u_char *buf)
  94. {
  95. struct spi_mem_op op =
  96. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
  97. SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
  98. SPI_MEM_OP_NO_DUMMY,
  99. SPI_MEM_OP_DATA_OUT(len, buf, 1));
  100. int ret;
  101. /* get transfer protocols. */
  102. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
  103. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
  104. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
  105. if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
  106. op.addr.nbytes = 0;
  107. ret = spi_mem_adjust_op_size(nor->spi, &op);
  108. if (ret)
  109. return ret;
  110. op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
  111. ret = spi_mem_exec_op(nor->spi, &op);
  112. if (ret)
  113. return ret;
  114. return op.data.nbytes;
  115. }
  116. /*
  117. * Read the status register, returning its value in the location
  118. * Return the status register value.
  119. * Returns negative if error occurred.
  120. */
  121. static int read_sr(struct spi_nor *nor)
  122. {
  123. int ret;
  124. u8 val;
  125. ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
  126. if (ret < 0) {
  127. pr_debug("error %d reading SR\n", (int)ret);
  128. return ret;
  129. }
  130. return val;
  131. }
  132. /*
  133. * Read the flag status register, returning its value in the location
  134. * Return the status register value.
  135. * Returns negative if error occurred.
  136. */
  137. static int read_fsr(struct spi_nor *nor)
  138. {
  139. int ret;
  140. u8 val;
  141. ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
  142. if (ret < 0) {
  143. pr_debug("error %d reading FSR\n", ret);
  144. return ret;
  145. }
  146. return val;
  147. }
  148. /*
  149. * Read configuration register, returning its value in the
  150. * location. Return the configuration register value.
  151. * Returns negative if error occurred.
  152. */
  153. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  154. static int read_cr(struct spi_nor *nor)
  155. {
  156. int ret;
  157. u8 val;
  158. ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  159. if (ret < 0) {
  160. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  161. return ret;
  162. }
  163. return val;
  164. }
  165. #endif
  166. /*
  167. * Write status register 1 byte
  168. * Returns negative if error occurred.
  169. */
  170. static int write_sr(struct spi_nor *nor, u8 val)
  171. {
  172. nor->cmd_buf[0] = val;
  173. return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  174. }
  175. /*
  176. * Set write enable latch with Write Enable command.
  177. * Returns negative if error occurred.
  178. */
  179. static int write_enable(struct spi_nor *nor)
  180. {
  181. return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  182. }
  183. /*
  184. * Send write disable instruction to the chip.
  185. */
  186. static int write_disable(struct spi_nor *nor)
  187. {
  188. return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  189. }
  190. static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  191. {
  192. return mtd->priv;
  193. }
  194. #ifndef CONFIG_SPI_FLASH_BAR
  195. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  196. {
  197. size_t i;
  198. for (i = 0; i < size; i++)
  199. if (table[i][0] == opcode)
  200. return table[i][1];
  201. /* No conversion found, keep input op code. */
  202. return opcode;
  203. }
  204. static u8 spi_nor_convert_3to4_read(u8 opcode)
  205. {
  206. static const u8 spi_nor_3to4_read[][2] = {
  207. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  208. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  209. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  210. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  211. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  212. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  213. { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
  214. { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
  215. { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
  216. { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
  217. { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
  218. };
  219. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  220. ARRAY_SIZE(spi_nor_3to4_read));
  221. }
  222. static u8 spi_nor_convert_3to4_program(u8 opcode)
  223. {
  224. static const u8 spi_nor_3to4_program[][2] = {
  225. { SPINOR_OP_PP, SPINOR_OP_PP_4B },
  226. { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
  227. { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
  228. { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
  229. { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
  230. };
  231. return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
  232. ARRAY_SIZE(spi_nor_3to4_program));
  233. }
  234. static u8 spi_nor_convert_3to4_erase(u8 opcode)
  235. {
  236. static const u8 spi_nor_3to4_erase[][2] = {
  237. { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
  238. { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
  239. { SPINOR_OP_SE, SPINOR_OP_SE_4B },
  240. };
  241. return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
  242. ARRAY_SIZE(spi_nor_3to4_erase));
  243. }
  244. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  245. const struct flash_info *info)
  246. {
  247. /* Do some manufacturer fixups first */
  248. switch (JEDEC_MFR(info)) {
  249. case SNOR_MFR_SPANSION:
  250. /* No small sector erase for 4-byte command set */
  251. nor->erase_opcode = SPINOR_OP_SE;
  252. nor->mtd.erasesize = info->sector_size;
  253. break;
  254. default:
  255. break;
  256. }
  257. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  258. nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
  259. nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
  260. }
  261. #endif /* !CONFIG_SPI_FLASH_BAR */
  262. /* Enable/disable 4-byte addressing mode. */
  263. static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  264. int enable)
  265. {
  266. int status;
  267. bool need_wren = false;
  268. u8 cmd;
  269. switch (JEDEC_MFR(info)) {
  270. case SNOR_MFR_ST:
  271. case SNOR_MFR_MICRON:
  272. /* Some Micron need WREN command; all will accept it */
  273. need_wren = true;
  274. case SNOR_MFR_ISSI:
  275. case SNOR_MFR_MACRONIX:
  276. case SNOR_MFR_WINBOND:
  277. if (need_wren)
  278. write_enable(nor);
  279. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  280. status = nor->write_reg(nor, cmd, NULL, 0);
  281. if (need_wren)
  282. write_disable(nor);
  283. if (!status && !enable &&
  284. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  285. /*
  286. * On Winbond W25Q256FV, leaving 4byte mode causes
  287. * the Extended Address Register to be set to 1, so all
  288. * 3-byte-address reads come from the second 16M.
  289. * We must clear the register to enable normal behavior.
  290. */
  291. write_enable(nor);
  292. nor->cmd_buf[0] = 0;
  293. nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
  294. write_disable(nor);
  295. }
  296. return status;
  297. default:
  298. /* Spansion style */
  299. nor->cmd_buf[0] = enable << 7;
  300. return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  301. }
  302. }
  303. static int spi_nor_sr_ready(struct spi_nor *nor)
  304. {
  305. int sr = read_sr(nor);
  306. if (sr < 0)
  307. return sr;
  308. if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
  309. if (sr & SR_E_ERR)
  310. dev_dbg(nor->dev, "Erase Error occurred\n");
  311. else
  312. dev_dbg(nor->dev, "Programming Error occurred\n");
  313. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  314. return -EIO;
  315. }
  316. return !(sr & SR_WIP);
  317. }
  318. static int spi_nor_fsr_ready(struct spi_nor *nor)
  319. {
  320. int fsr = read_fsr(nor);
  321. if (fsr < 0)
  322. return fsr;
  323. if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
  324. if (fsr & FSR_E_ERR)
  325. dev_err(nor->dev, "Erase operation failed.\n");
  326. else
  327. dev_err(nor->dev, "Program operation failed.\n");
  328. if (fsr & FSR_PT_ERR)
  329. dev_err(nor->dev,
  330. "Attempted to modify a protected sector.\n");
  331. nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
  332. return -EIO;
  333. }
  334. return fsr & FSR_READY;
  335. }
  336. static int spi_nor_ready(struct spi_nor *nor)
  337. {
  338. int sr, fsr;
  339. sr = spi_nor_sr_ready(nor);
  340. if (sr < 0)
  341. return sr;
  342. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  343. if (fsr < 0)
  344. return fsr;
  345. return sr && fsr;
  346. }
  347. /*
  348. * Service routine to read status register until ready, or timeout occurs.
  349. * Returns non-zero if error.
  350. */
  351. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  352. unsigned long timeout)
  353. {
  354. unsigned long timebase;
  355. int ret;
  356. timebase = get_timer(0);
  357. while (get_timer(timebase) < timeout) {
  358. ret = spi_nor_ready(nor);
  359. if (ret < 0)
  360. return ret;
  361. if (ret)
  362. return 0;
  363. }
  364. dev_err(nor->dev, "flash operation timed out\n");
  365. return -ETIMEDOUT;
  366. }
  367. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  368. {
  369. return spi_nor_wait_till_ready_with_timeout(nor,
  370. DEFAULT_READY_WAIT_JIFFIES);
  371. }
  372. #ifdef CONFIG_SPI_FLASH_BAR
  373. /*
  374. * This "clean_bar" is necessary in a situation when one was accessing
  375. * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
  376. *
  377. * After it the BA24 bit shall be cleared to allow access to correct
  378. * memory region after SW reset (by calling "reset" command).
  379. *
  380. * Otherwise, the BA24 bit may be left set and then after reset, the
  381. * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
  382. */
  383. static int clean_bar(struct spi_nor *nor)
  384. {
  385. u8 cmd, bank_sel = 0;
  386. if (nor->bank_curr == 0)
  387. return 0;
  388. cmd = nor->bank_write_cmd;
  389. nor->bank_curr = 0;
  390. write_enable(nor);
  391. return nor->write_reg(nor, cmd, &bank_sel, 1);
  392. }
  393. static int write_bar(struct spi_nor *nor, u32 offset)
  394. {
  395. u8 cmd, bank_sel;
  396. int ret;
  397. bank_sel = offset / SZ_16M;
  398. if (bank_sel == nor->bank_curr)
  399. goto bar_end;
  400. cmd = nor->bank_write_cmd;
  401. write_enable(nor);
  402. ret = nor->write_reg(nor, cmd, &bank_sel, 1);
  403. if (ret < 0) {
  404. debug("SF: fail to write bank register\n");
  405. return ret;
  406. }
  407. bar_end:
  408. nor->bank_curr = bank_sel;
  409. return nor->bank_curr;
  410. }
  411. static int read_bar(struct spi_nor *nor, const struct flash_info *info)
  412. {
  413. u8 curr_bank = 0;
  414. int ret;
  415. switch (JEDEC_MFR(info)) {
  416. case SNOR_MFR_SPANSION:
  417. nor->bank_read_cmd = SPINOR_OP_BRRD;
  418. nor->bank_write_cmd = SPINOR_OP_BRWR;
  419. break;
  420. default:
  421. nor->bank_read_cmd = SPINOR_OP_RDEAR;
  422. nor->bank_write_cmd = SPINOR_OP_WREAR;
  423. }
  424. ret = nor->read_reg(nor, nor->bank_read_cmd,
  425. &curr_bank, 1);
  426. if (ret) {
  427. debug("SF: fail to read bank addr register\n");
  428. return ret;
  429. }
  430. nor->bank_curr = curr_bank;
  431. return 0;
  432. }
  433. #endif
  434. /*
  435. * Initiate the erasure of a single sector
  436. */
  437. static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
  438. {
  439. struct spi_mem_op op =
  440. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
  441. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  442. SPI_MEM_OP_NO_DUMMY,
  443. SPI_MEM_OP_NO_DATA);
  444. if (nor->erase)
  445. return nor->erase(nor, addr);
  446. /*
  447. * Default implementation, if driver doesn't have a specialized HW
  448. * control
  449. */
  450. return spi_mem_exec_op(nor->spi, &op);
  451. }
  452. /*
  453. * Erase an address range on the nor chip. The address range may extend
  454. * one or more erase sectors. Return an error is there is a problem erasing.
  455. */
  456. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  457. {
  458. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  459. u32 addr, len, rem;
  460. int ret;
  461. dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
  462. (long long)instr->len);
  463. if (!instr->len)
  464. return 0;
  465. div_u64_rem(instr->len, mtd->erasesize, &rem);
  466. if (rem)
  467. return -EINVAL;
  468. addr = instr->addr;
  469. len = instr->len;
  470. while (len) {
  471. #ifdef CONFIG_SPI_FLASH_BAR
  472. ret = write_bar(nor, addr);
  473. if (ret < 0)
  474. return ret;
  475. #endif
  476. write_enable(nor);
  477. ret = spi_nor_erase_sector(nor, addr);
  478. if (ret)
  479. goto erase_err;
  480. addr += mtd->erasesize;
  481. len -= mtd->erasesize;
  482. ret = spi_nor_wait_till_ready(nor);
  483. if (ret)
  484. goto erase_err;
  485. }
  486. erase_err:
  487. #ifdef CONFIG_SPI_FLASH_BAR
  488. ret = clean_bar(nor);
  489. #endif
  490. write_disable(nor);
  491. return ret;
  492. }
  493. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  494. /* Write status register and ensure bits in mask match written values */
  495. static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
  496. {
  497. int ret;
  498. write_enable(nor);
  499. ret = write_sr(nor, status_new);
  500. if (ret)
  501. return ret;
  502. ret = spi_nor_wait_till_ready(nor);
  503. if (ret)
  504. return ret;
  505. ret = read_sr(nor);
  506. if (ret < 0)
  507. return ret;
  508. return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
  509. }
  510. static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
  511. uint64_t *len)
  512. {
  513. struct mtd_info *mtd = &nor->mtd;
  514. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  515. int shift = ffs(mask) - 1;
  516. int pow;
  517. if (!(sr & mask)) {
  518. /* No protection */
  519. *ofs = 0;
  520. *len = 0;
  521. } else {
  522. pow = ((sr & mask) ^ mask) >> shift;
  523. *len = mtd->size >> pow;
  524. if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
  525. *ofs = 0;
  526. else
  527. *ofs = mtd->size - *len;
  528. }
  529. }
  530. /*
  531. * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
  532. * @locked is false); 0 otherwise
  533. */
  534. static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
  535. u8 sr, bool locked)
  536. {
  537. loff_t lock_offs;
  538. uint64_t lock_len;
  539. if (!len)
  540. return 1;
  541. stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
  542. if (locked)
  543. /* Requested range is a sub-range of locked range */
  544. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  545. else
  546. /* Requested range does not overlap with locked range */
  547. return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
  548. }
  549. static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  550. u8 sr)
  551. {
  552. return stm_check_lock_status_sr(nor, ofs, len, sr, true);
  553. }
  554. static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  555. u8 sr)
  556. {
  557. return stm_check_lock_status_sr(nor, ofs, len, sr, false);
  558. }
  559. /*
  560. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  561. * Supports the block protection bits BP{0,1,2} in the status register
  562. * (SR). Does not support these features found in newer SR bitfields:
  563. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  564. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  565. *
  566. * Support for the following is provided conditionally for some flash:
  567. * - TB: top/bottom protect
  568. *
  569. * Sample table portion for 8MB flash (Winbond w25q64fw):
  570. *
  571. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  572. * --------------------------------------------------------------------------
  573. * X | X | 0 | 0 | 0 | NONE | NONE
  574. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  575. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  576. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  577. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  578. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  579. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  580. * X | X | 1 | 1 | 1 | 8 MB | ALL
  581. * ------|-------|-------|-------|-------|---------------|-------------------
  582. * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
  583. * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
  584. * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
  585. * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
  586. * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
  587. * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
  588. *
  589. * Returns negative on errors, 0 on success.
  590. */
  591. static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  592. {
  593. struct mtd_info *mtd = &nor->mtd;
  594. int status_old, status_new;
  595. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  596. u8 shift = ffs(mask) - 1, pow, val;
  597. loff_t lock_len;
  598. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  599. bool use_top;
  600. status_old = read_sr(nor);
  601. if (status_old < 0)
  602. return status_old;
  603. /* If nothing in our range is unlocked, we don't need to do anything */
  604. if (stm_is_locked_sr(nor, ofs, len, status_old))
  605. return 0;
  606. /* If anything below us is unlocked, we can't use 'bottom' protection */
  607. if (!stm_is_locked_sr(nor, 0, ofs, status_old))
  608. can_be_bottom = false;
  609. /* If anything above us is unlocked, we can't use 'top' protection */
  610. if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
  611. status_old))
  612. can_be_top = false;
  613. if (!can_be_bottom && !can_be_top)
  614. return -EINVAL;
  615. /* Prefer top, if both are valid */
  616. use_top = can_be_top;
  617. /* lock_len: length of region that should end up locked */
  618. if (use_top)
  619. lock_len = mtd->size - ofs;
  620. else
  621. lock_len = ofs + len;
  622. /*
  623. * Need smallest pow such that:
  624. *
  625. * 1 / (2^pow) <= (len / size)
  626. *
  627. * so (assuming power-of-2 size) we do:
  628. *
  629. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  630. */
  631. pow = ilog2(mtd->size) - ilog2(lock_len);
  632. val = mask - (pow << shift);
  633. if (val & ~mask)
  634. return -EINVAL;
  635. /* Don't "lock" with no region! */
  636. if (!(val & mask))
  637. return -EINVAL;
  638. status_new = (status_old & ~mask & ~SR_TB) | val;
  639. /* Disallow further writes if WP pin is asserted */
  640. status_new |= SR_SRWD;
  641. if (!use_top)
  642. status_new |= SR_TB;
  643. /* Don't bother if they're the same */
  644. if (status_new == status_old)
  645. return 0;
  646. /* Only modify protection if it will not unlock other areas */
  647. if ((status_new & mask) < (status_old & mask))
  648. return -EINVAL;
  649. return write_sr_and_check(nor, status_new, mask);
  650. }
  651. /*
  652. * Unlock a region of the flash. See stm_lock() for more info
  653. *
  654. * Returns negative on errors, 0 on success.
  655. */
  656. static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  657. {
  658. struct mtd_info *mtd = &nor->mtd;
  659. int status_old, status_new;
  660. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  661. u8 shift = ffs(mask) - 1, pow, val;
  662. loff_t lock_len;
  663. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  664. bool use_top;
  665. status_old = read_sr(nor);
  666. if (status_old < 0)
  667. return status_old;
  668. /* If nothing in our range is locked, we don't need to do anything */
  669. if (stm_is_unlocked_sr(nor, ofs, len, status_old))
  670. return 0;
  671. /* If anything below us is locked, we can't use 'top' protection */
  672. if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
  673. can_be_top = false;
  674. /* If anything above us is locked, we can't use 'bottom' protection */
  675. if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
  676. status_old))
  677. can_be_bottom = false;
  678. if (!can_be_bottom && !can_be_top)
  679. return -EINVAL;
  680. /* Prefer top, if both are valid */
  681. use_top = can_be_top;
  682. /* lock_len: length of region that should remain locked */
  683. if (use_top)
  684. lock_len = mtd->size - (ofs + len);
  685. else
  686. lock_len = ofs;
  687. /*
  688. * Need largest pow such that:
  689. *
  690. * 1 / (2^pow) >= (len / size)
  691. *
  692. * so (assuming power-of-2 size) we do:
  693. *
  694. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  695. */
  696. pow = ilog2(mtd->size) - order_base_2(lock_len);
  697. if (lock_len == 0) {
  698. val = 0; /* fully unlocked */
  699. } else {
  700. val = mask - (pow << shift);
  701. /* Some power-of-two sizes are not supported */
  702. if (val & ~mask)
  703. return -EINVAL;
  704. }
  705. status_new = (status_old & ~mask & ~SR_TB) | val;
  706. /* Don't protect status register if we're fully unlocked */
  707. if (lock_len == 0)
  708. status_new &= ~SR_SRWD;
  709. if (!use_top)
  710. status_new |= SR_TB;
  711. /* Don't bother if they're the same */
  712. if (status_new == status_old)
  713. return 0;
  714. /* Only modify protection if it will not lock other areas */
  715. if ((status_new & mask) > (status_old & mask))
  716. return -EINVAL;
  717. return write_sr_and_check(nor, status_new, mask);
  718. }
  719. /*
  720. * Check if a region of the flash is (completely) locked. See stm_lock() for
  721. * more info.
  722. *
  723. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  724. * negative on errors.
  725. */
  726. static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  727. {
  728. int status;
  729. status = read_sr(nor);
  730. if (status < 0)
  731. return status;
  732. return stm_is_locked_sr(nor, ofs, len, status);
  733. }
  734. #endif /* CONFIG_SPI_FLASH_STMICRO */
  735. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  736. {
  737. int tmp;
  738. u8 id[SPI_NOR_MAX_ID_LEN];
  739. const struct flash_info *info;
  740. tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  741. if (tmp < 0) {
  742. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  743. return ERR_PTR(tmp);
  744. }
  745. info = spi_nor_ids;
  746. for (; info->name; info++) {
  747. if (info->id_len) {
  748. if (!memcmp(info->id, id, info->id_len))
  749. return info;
  750. }
  751. }
  752. dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  753. id[0], id[1], id[2]);
  754. return ERR_PTR(-ENODEV);
  755. }
  756. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  757. size_t *retlen, u_char *buf)
  758. {
  759. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  760. int ret;
  761. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  762. while (len) {
  763. loff_t addr = from;
  764. size_t read_len = len;
  765. #ifdef CONFIG_SPI_FLASH_BAR
  766. u32 remain_len;
  767. ret = write_bar(nor, addr);
  768. if (ret < 0)
  769. return log_ret(ret);
  770. remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
  771. if (len < remain_len)
  772. read_len = len;
  773. else
  774. read_len = remain_len;
  775. #endif
  776. ret = nor->read(nor, addr, read_len, buf);
  777. if (ret == 0) {
  778. /* We shouldn't see 0-length reads */
  779. ret = -EIO;
  780. goto read_err;
  781. }
  782. if (ret < 0)
  783. goto read_err;
  784. *retlen += ret;
  785. buf += ret;
  786. from += ret;
  787. len -= ret;
  788. }
  789. ret = 0;
  790. read_err:
  791. #ifdef CONFIG_SPI_FLASH_BAR
  792. ret = clean_bar(nor);
  793. #endif
  794. return ret;
  795. }
  796. #ifdef CONFIG_SPI_FLASH_SST
  797. /*
  798. * sst26 flash series has its own block protection implementation:
  799. * 4x - 8 KByte blocks - read & write protection bits - upper addresses
  800. * 1x - 32 KByte blocks - write protection bits
  801. * rest - 64 KByte blocks - write protection bits
  802. * 1x - 32 KByte blocks - write protection bits
  803. * 4x - 8 KByte blocks - read & write protection bits - lower addresses
  804. *
  805. * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
  806. * will be treated as single block.
  807. */
  808. #define SST26_BPR_8K_NUM 4
  809. #define SST26_MAX_BPR_REG_LEN (18 + 1)
  810. #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
  811. enum lock_ctl {
  812. SST26_CTL_LOCK,
  813. SST26_CTL_UNLOCK,
  814. SST26_CTL_CHECK
  815. };
  816. static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
  817. {
  818. switch (ctl) {
  819. case SST26_CTL_LOCK:
  820. cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
  821. break;
  822. case SST26_CTL_UNLOCK:
  823. cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
  824. break;
  825. case SST26_CTL_CHECK:
  826. return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
  827. }
  828. return false;
  829. }
  830. /*
  831. * Lock, unlock or check lock status of the flash region of the flash (depending
  832. * on the lock_ctl value)
  833. */
  834. static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
  835. {
  836. struct mtd_info *mtd = &nor->mtd;
  837. u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
  838. bool lower_64k = false, upper_64k = false;
  839. u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
  840. int ret;
  841. /* Check length and offset for 64k alignment */
  842. if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
  843. dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
  844. return -EINVAL;
  845. }
  846. if (ofs + len > mtd->size) {
  847. dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
  848. ofs, len, mtd->size);
  849. return -EINVAL;
  850. }
  851. /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
  852. if (mtd->size != SZ_2M &&
  853. mtd->size != SZ_4M &&
  854. mtd->size != SZ_8M)
  855. return -EINVAL;
  856. bpr_size = 2 + (mtd->size / SZ_64K / 8);
  857. ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
  858. if (ret < 0) {
  859. dev_err(nor->dev, "fail to read block-protection register\n");
  860. return ret;
  861. }
  862. rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
  863. lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
  864. upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
  865. lower_64k = (ofs < SST26_BOUND_REG_SIZE);
  866. /* Lower bits in block-protection register are about 64k region */
  867. bpr_ptr = lptr_64k / SZ_64K - 1;
  868. /* Process 64K blocks region */
  869. while (lptr_64k < rptr_64k) {
  870. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  871. return EACCES;
  872. bpr_ptr++;
  873. lptr_64k += SZ_64K;
  874. }
  875. /* 32K and 8K region bits in BPR are after 64k region bits */
  876. bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
  877. /* Process lower 32K block region */
  878. if (lower_64k)
  879. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  880. return EACCES;
  881. bpr_ptr++;
  882. /* Process upper 32K block region */
  883. if (upper_64k)
  884. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  885. return EACCES;
  886. bpr_ptr++;
  887. /* Process lower 8K block regions */
  888. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  889. if (lower_64k)
  890. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  891. return EACCES;
  892. /* In 8K area BPR has both read and write protection bits */
  893. bpr_ptr += 2;
  894. }
  895. /* Process upper 8K block regions */
  896. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  897. if (upper_64k)
  898. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  899. return EACCES;
  900. /* In 8K area BPR has both read and write protection bits */
  901. bpr_ptr += 2;
  902. }
  903. /* If we check region status we don't need to write BPR back */
  904. if (ctl == SST26_CTL_CHECK)
  905. return 0;
  906. ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
  907. if (ret < 0) {
  908. dev_err(nor->dev, "fail to write block-protection register\n");
  909. return ret;
  910. }
  911. return 0;
  912. }
  913. static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  914. {
  915. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
  916. }
  917. static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  918. {
  919. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
  920. }
  921. /*
  922. * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
  923. * and negative on errors.
  924. */
  925. static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  926. {
  927. /*
  928. * is_locked function is used for check before reading or erasing flash
  929. * region, so offset and length might be not 64k allighned, so adjust
  930. * them to be 64k allighned as sst26_lock_ctl works only with 64k
  931. * allighned regions.
  932. */
  933. ofs -= ofs & (SZ_64K - 1);
  934. len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
  935. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
  936. }
  937. static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
  938. size_t *retlen, const u_char *buf)
  939. {
  940. size_t actual;
  941. int ret = 0;
  942. for (actual = 0; actual < len; actual++) {
  943. nor->program_opcode = SPINOR_OP_BP;
  944. write_enable(nor);
  945. /* write one byte. */
  946. ret = nor->write(nor, to, 1, buf + actual);
  947. if (ret < 0)
  948. goto sst_write_err;
  949. ret = spi_nor_wait_till_ready(nor);
  950. if (ret)
  951. goto sst_write_err;
  952. to++;
  953. }
  954. sst_write_err:
  955. write_disable(nor);
  956. return ret;
  957. }
  958. static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
  959. size_t *retlen, const u_char *buf)
  960. {
  961. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  962. struct spi_slave *spi = nor->spi;
  963. size_t actual;
  964. int ret;
  965. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  966. if (spi->mode & SPI_TX_BYTE)
  967. return sst_write_byteprogram(nor, to, len, retlen, buf);
  968. write_enable(nor);
  969. nor->sst_write_second = false;
  970. actual = to % 2;
  971. /* Start write from odd address. */
  972. if (actual) {
  973. nor->program_opcode = SPINOR_OP_BP;
  974. /* write one byte. */
  975. ret = nor->write(nor, to, 1, buf);
  976. if (ret < 0)
  977. goto sst_write_err;
  978. ret = spi_nor_wait_till_ready(nor);
  979. if (ret)
  980. goto sst_write_err;
  981. }
  982. to += actual;
  983. /* Write out most of the data here. */
  984. for (; actual < len - 1; actual += 2) {
  985. nor->program_opcode = SPINOR_OP_AAI_WP;
  986. /* write two bytes. */
  987. ret = nor->write(nor, to, 2, buf + actual);
  988. if (ret < 0)
  989. goto sst_write_err;
  990. ret = spi_nor_wait_till_ready(nor);
  991. if (ret)
  992. goto sst_write_err;
  993. to += 2;
  994. nor->sst_write_second = true;
  995. }
  996. nor->sst_write_second = false;
  997. write_disable(nor);
  998. ret = spi_nor_wait_till_ready(nor);
  999. if (ret)
  1000. goto sst_write_err;
  1001. /* Write out trailing byte if it exists. */
  1002. if (actual != len) {
  1003. write_enable(nor);
  1004. nor->program_opcode = SPINOR_OP_BP;
  1005. ret = nor->write(nor, to, 1, buf + actual);
  1006. if (ret < 0)
  1007. goto sst_write_err;
  1008. ret = spi_nor_wait_till_ready(nor);
  1009. if (ret)
  1010. goto sst_write_err;
  1011. write_disable(nor);
  1012. actual += 1;
  1013. }
  1014. sst_write_err:
  1015. *retlen += actual;
  1016. return ret;
  1017. }
  1018. #endif
  1019. /*
  1020. * Write an address range to the nor chip. Data must be written in
  1021. * FLASH_PAGESIZE chunks. The address range may be any size provided
  1022. * it is within the physical boundaries.
  1023. */
  1024. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  1025. size_t *retlen, const u_char *buf)
  1026. {
  1027. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1028. size_t page_offset, page_remain, i;
  1029. ssize_t ret;
  1030. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1031. if (!len)
  1032. return 0;
  1033. for (i = 0; i < len; ) {
  1034. ssize_t written;
  1035. loff_t addr = to + i;
  1036. /*
  1037. * If page_size is a power of two, the offset can be quickly
  1038. * calculated with an AND operation. On the other cases we
  1039. * need to do a modulus operation (more expensive).
  1040. */
  1041. if (is_power_of_2(nor->page_size)) {
  1042. page_offset = addr & (nor->page_size - 1);
  1043. } else {
  1044. u64 aux = addr;
  1045. page_offset = do_div(aux, nor->page_size);
  1046. }
  1047. /* the size of data remaining on the first page */
  1048. page_remain = min_t(size_t,
  1049. nor->page_size - page_offset, len - i);
  1050. #ifdef CONFIG_SPI_FLASH_BAR
  1051. ret = write_bar(nor, addr);
  1052. if (ret < 0)
  1053. return ret;
  1054. #endif
  1055. write_enable(nor);
  1056. ret = nor->write(nor, addr, page_remain, buf + i);
  1057. if (ret < 0)
  1058. goto write_err;
  1059. written = ret;
  1060. ret = spi_nor_wait_till_ready(nor);
  1061. if (ret)
  1062. goto write_err;
  1063. *retlen += written;
  1064. i += written;
  1065. }
  1066. write_err:
  1067. #ifdef CONFIG_SPI_FLASH_BAR
  1068. ret = clean_bar(nor);
  1069. #endif
  1070. return ret;
  1071. }
  1072. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1073. /**
  1074. * macronix_quad_enable() - set QE bit in Status Register.
  1075. * @nor: pointer to a 'struct spi_nor'
  1076. *
  1077. * Set the Quad Enable (QE) bit in the Status Register.
  1078. *
  1079. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  1080. *
  1081. * Return: 0 on success, -errno otherwise.
  1082. */
  1083. static int macronix_quad_enable(struct spi_nor *nor)
  1084. {
  1085. int ret, val;
  1086. val = read_sr(nor);
  1087. if (val < 0)
  1088. return val;
  1089. if (val & SR_QUAD_EN_MX)
  1090. return 0;
  1091. write_enable(nor);
  1092. write_sr(nor, val | SR_QUAD_EN_MX);
  1093. ret = spi_nor_wait_till_ready(nor);
  1094. if (ret)
  1095. return ret;
  1096. ret = read_sr(nor);
  1097. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  1098. dev_err(nor->dev, "Macronix Quad bit not set\n");
  1099. return -EINVAL;
  1100. }
  1101. return 0;
  1102. }
  1103. #endif
  1104. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1105. /*
  1106. * Write status Register and configuration register with 2 bytes
  1107. * The first byte will be written to the status register, while the
  1108. * second byte will be written to the configuration register.
  1109. * Return negative if error occurred.
  1110. */
  1111. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  1112. {
  1113. int ret;
  1114. write_enable(nor);
  1115. ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  1116. if (ret < 0) {
  1117. dev_dbg(nor->dev,
  1118. "error while writing configuration register\n");
  1119. return -EINVAL;
  1120. }
  1121. ret = spi_nor_wait_till_ready(nor);
  1122. if (ret) {
  1123. dev_dbg(nor->dev,
  1124. "timeout while writing configuration register\n");
  1125. return ret;
  1126. }
  1127. return 0;
  1128. }
  1129. /**
  1130. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  1131. * @nor: pointer to a 'struct spi_nor'
  1132. *
  1133. * Set the Quad Enable (QE) bit in the Configuration Register.
  1134. * This function should be used with QSPI memories supporting the Read
  1135. * Configuration Register (35h) instruction.
  1136. *
  1137. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1138. * memories.
  1139. *
  1140. * Return: 0 on success, -errno otherwise.
  1141. */
  1142. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  1143. {
  1144. u8 sr_cr[2];
  1145. int ret;
  1146. /* Check current Quad Enable bit value. */
  1147. ret = read_cr(nor);
  1148. if (ret < 0) {
  1149. dev_dbg(dev, "error while reading configuration register\n");
  1150. return -EINVAL;
  1151. }
  1152. if (ret & CR_QUAD_EN_SPAN)
  1153. return 0;
  1154. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  1155. /* Keep the current value of the Status Register. */
  1156. ret = read_sr(nor);
  1157. if (ret < 0) {
  1158. dev_dbg(dev, "error while reading status register\n");
  1159. return -EINVAL;
  1160. }
  1161. sr_cr[0] = ret;
  1162. ret = write_sr_cr(nor, sr_cr);
  1163. if (ret)
  1164. return ret;
  1165. /* Read back and check it. */
  1166. ret = read_cr(nor);
  1167. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  1168. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1169. return -EINVAL;
  1170. }
  1171. return 0;
  1172. }
  1173. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1174. /**
  1175. * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
  1176. * @nor: pointer to a 'struct spi_nor'
  1177. *
  1178. * Set the Quad Enable (QE) bit in the Configuration Register.
  1179. * This function should be used with QSPI memories not supporting the Read
  1180. * Configuration Register (35h) instruction.
  1181. *
  1182. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1183. * memories.
  1184. *
  1185. * Return: 0 on success, -errno otherwise.
  1186. */
  1187. static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
  1188. {
  1189. u8 sr_cr[2];
  1190. int ret;
  1191. /* Keep the current value of the Status Register. */
  1192. ret = read_sr(nor);
  1193. if (ret < 0) {
  1194. dev_dbg(nor->dev, "error while reading status register\n");
  1195. return -EINVAL;
  1196. }
  1197. sr_cr[0] = ret;
  1198. sr_cr[1] = CR_QUAD_EN_SPAN;
  1199. return write_sr_cr(nor, sr_cr);
  1200. }
  1201. #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
  1202. #endif /* CONFIG_SPI_FLASH_SPANSION */
  1203. struct spi_nor_read_command {
  1204. u8 num_mode_clocks;
  1205. u8 num_wait_states;
  1206. u8 opcode;
  1207. enum spi_nor_protocol proto;
  1208. };
  1209. struct spi_nor_pp_command {
  1210. u8 opcode;
  1211. enum spi_nor_protocol proto;
  1212. };
  1213. enum spi_nor_read_command_index {
  1214. SNOR_CMD_READ,
  1215. SNOR_CMD_READ_FAST,
  1216. SNOR_CMD_READ_1_1_1_DTR,
  1217. /* Dual SPI */
  1218. SNOR_CMD_READ_1_1_2,
  1219. SNOR_CMD_READ_1_2_2,
  1220. SNOR_CMD_READ_2_2_2,
  1221. SNOR_CMD_READ_1_2_2_DTR,
  1222. /* Quad SPI */
  1223. SNOR_CMD_READ_1_1_4,
  1224. SNOR_CMD_READ_1_4_4,
  1225. SNOR_CMD_READ_4_4_4,
  1226. SNOR_CMD_READ_1_4_4_DTR,
  1227. /* Octo SPI */
  1228. SNOR_CMD_READ_1_1_8,
  1229. SNOR_CMD_READ_1_8_8,
  1230. SNOR_CMD_READ_8_8_8,
  1231. SNOR_CMD_READ_1_8_8_DTR,
  1232. SNOR_CMD_READ_MAX
  1233. };
  1234. enum spi_nor_pp_command_index {
  1235. SNOR_CMD_PP,
  1236. /* Quad SPI */
  1237. SNOR_CMD_PP_1_1_4,
  1238. SNOR_CMD_PP_1_4_4,
  1239. SNOR_CMD_PP_4_4_4,
  1240. /* Octo SPI */
  1241. SNOR_CMD_PP_1_1_8,
  1242. SNOR_CMD_PP_1_8_8,
  1243. SNOR_CMD_PP_8_8_8,
  1244. SNOR_CMD_PP_MAX
  1245. };
  1246. struct spi_nor_flash_parameter {
  1247. u64 size;
  1248. u32 page_size;
  1249. struct spi_nor_hwcaps hwcaps;
  1250. struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
  1251. struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
  1252. int (*quad_enable)(struct spi_nor *nor);
  1253. };
  1254. static void
  1255. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  1256. u8 num_mode_clocks,
  1257. u8 num_wait_states,
  1258. u8 opcode,
  1259. enum spi_nor_protocol proto)
  1260. {
  1261. read->num_mode_clocks = num_mode_clocks;
  1262. read->num_wait_states = num_wait_states;
  1263. read->opcode = opcode;
  1264. read->proto = proto;
  1265. }
  1266. static void
  1267. spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
  1268. u8 opcode,
  1269. enum spi_nor_protocol proto)
  1270. {
  1271. pp->opcode = opcode;
  1272. pp->proto = proto;
  1273. }
  1274. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1275. /*
  1276. * Serial Flash Discoverable Parameters (SFDP) parsing.
  1277. */
  1278. /**
  1279. * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
  1280. * @nor: pointer to a 'struct spi_nor'
  1281. * @addr: offset in the SFDP area to start reading data from
  1282. * @len: number of bytes to read
  1283. * @buf: buffer where the SFDP data are copied into (dma-safe memory)
  1284. *
  1285. * Whatever the actual numbers of bytes for address and dummy cycles are
  1286. * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
  1287. * followed by a 3-byte address and 8 dummy clock cycles.
  1288. *
  1289. * Return: 0 on success, -errno otherwise.
  1290. */
  1291. static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
  1292. size_t len, void *buf)
  1293. {
  1294. u8 addr_width, read_opcode, read_dummy;
  1295. int ret;
  1296. read_opcode = nor->read_opcode;
  1297. addr_width = nor->addr_width;
  1298. read_dummy = nor->read_dummy;
  1299. nor->read_opcode = SPINOR_OP_RDSFDP;
  1300. nor->addr_width = 3;
  1301. nor->read_dummy = 8;
  1302. while (len) {
  1303. ret = nor->read(nor, addr, len, (u8 *)buf);
  1304. if (!ret || ret > len) {
  1305. ret = -EIO;
  1306. goto read_err;
  1307. }
  1308. if (ret < 0)
  1309. goto read_err;
  1310. buf += ret;
  1311. addr += ret;
  1312. len -= ret;
  1313. }
  1314. ret = 0;
  1315. read_err:
  1316. nor->read_opcode = read_opcode;
  1317. nor->addr_width = addr_width;
  1318. nor->read_dummy = read_dummy;
  1319. return ret;
  1320. }
  1321. struct sfdp_parameter_header {
  1322. u8 id_lsb;
  1323. u8 minor;
  1324. u8 major;
  1325. u8 length; /* in double words */
  1326. u8 parameter_table_pointer[3]; /* byte address */
  1327. u8 id_msb;
  1328. };
  1329. #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
  1330. #define SFDP_PARAM_HEADER_PTP(p) \
  1331. (((p)->parameter_table_pointer[2] << 16) | \
  1332. ((p)->parameter_table_pointer[1] << 8) | \
  1333. ((p)->parameter_table_pointer[0] << 0))
  1334. #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
  1335. #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
  1336. #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
  1337. #define SFDP_SIGNATURE 0x50444653U
  1338. #define SFDP_JESD216_MAJOR 1
  1339. #define SFDP_JESD216_MINOR 0
  1340. #define SFDP_JESD216A_MINOR 5
  1341. #define SFDP_JESD216B_MINOR 6
  1342. struct sfdp_header {
  1343. u32 signature; /* Ox50444653U <=> "SFDP" */
  1344. u8 minor;
  1345. u8 major;
  1346. u8 nph; /* 0-base number of parameter headers */
  1347. u8 unused;
  1348. /* Basic Flash Parameter Table. */
  1349. struct sfdp_parameter_header bfpt_header;
  1350. };
  1351. /* Basic Flash Parameter Table */
  1352. /*
  1353. * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
  1354. * They are indexed from 1 but C arrays are indexed from 0.
  1355. */
  1356. #define BFPT_DWORD(i) ((i) - 1)
  1357. #define BFPT_DWORD_MAX 16
  1358. /* The first version of JESB216 defined only 9 DWORDs. */
  1359. #define BFPT_DWORD_MAX_JESD216 9
  1360. /* 1st DWORD. */
  1361. #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
  1362. #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
  1363. #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
  1364. #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
  1365. #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
  1366. #define BFPT_DWORD1_DTR BIT(19)
  1367. #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
  1368. #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
  1369. #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
  1370. /* 5th DWORD. */
  1371. #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
  1372. #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
  1373. /* 11th DWORD. */
  1374. #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
  1375. #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
  1376. /* 15th DWORD. */
  1377. /*
  1378. * (from JESD216 rev B)
  1379. * Quad Enable Requirements (QER):
  1380. * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
  1381. * reads based on instruction. DQ3/HOLD# functions are hold during
  1382. * instruction phase.
  1383. * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
  1384. * two data bytes where bit 1 of the second byte is one.
  1385. * [...]
  1386. * Writing only one byte to the status register has the side-effect of
  1387. * clearing status register 2, including the QE bit. The 100b code is
  1388. * used if writing one byte to the status register does not modify
  1389. * status register 2.
  1390. * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
  1391. * one data byte where bit 6 is one.
  1392. * [...]
  1393. * - 011b: QE is bit 7 of status register 2. It is set via Write status
  1394. * register 2 instruction 3Eh with one data byte where bit 7 is one.
  1395. * [...]
  1396. * The status register 2 is read using instruction 3Fh.
  1397. * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
  1398. * two data bytes where bit 1 of the second byte is one.
  1399. * [...]
  1400. * In contrast to the 001b code, writing one byte to the status
  1401. * register does not modify status register 2.
  1402. * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
  1403. * Read Status instruction 05h. Status register2 is read using
  1404. * instruction 35h. QE is set via Writ Status instruction 01h with
  1405. * two data bytes where bit 1 of the second byte is one.
  1406. * [...]
  1407. */
  1408. #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
  1409. #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
  1410. #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
  1411. #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
  1412. #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
  1413. #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
  1414. #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
  1415. struct sfdp_bfpt {
  1416. u32 dwords[BFPT_DWORD_MAX];
  1417. };
  1418. /* Fast Read settings. */
  1419. static void
  1420. spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
  1421. u16 half,
  1422. enum spi_nor_protocol proto)
  1423. {
  1424. read->num_mode_clocks = (half >> 5) & 0x07;
  1425. read->num_wait_states = (half >> 0) & 0x1f;
  1426. read->opcode = (half >> 8) & 0xff;
  1427. read->proto = proto;
  1428. }
  1429. struct sfdp_bfpt_read {
  1430. /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
  1431. u32 hwcaps;
  1432. /*
  1433. * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
  1434. * whether the Fast Read x-y-z command is supported.
  1435. */
  1436. u32 supported_dword;
  1437. u32 supported_bit;
  1438. /*
  1439. * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
  1440. * encodes the op code, the number of mode clocks and the number of wait
  1441. * states to be used by Fast Read x-y-z command.
  1442. */
  1443. u32 settings_dword;
  1444. u32 settings_shift;
  1445. /* The SPI protocol for this Fast Read x-y-z command. */
  1446. enum spi_nor_protocol proto;
  1447. };
  1448. static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
  1449. /* Fast Read 1-1-2 */
  1450. {
  1451. SNOR_HWCAPS_READ_1_1_2,
  1452. BFPT_DWORD(1), BIT(16), /* Supported bit */
  1453. BFPT_DWORD(4), 0, /* Settings */
  1454. SNOR_PROTO_1_1_2,
  1455. },
  1456. /* Fast Read 1-2-2 */
  1457. {
  1458. SNOR_HWCAPS_READ_1_2_2,
  1459. BFPT_DWORD(1), BIT(20), /* Supported bit */
  1460. BFPT_DWORD(4), 16, /* Settings */
  1461. SNOR_PROTO_1_2_2,
  1462. },
  1463. /* Fast Read 2-2-2 */
  1464. {
  1465. SNOR_HWCAPS_READ_2_2_2,
  1466. BFPT_DWORD(5), BIT(0), /* Supported bit */
  1467. BFPT_DWORD(6), 16, /* Settings */
  1468. SNOR_PROTO_2_2_2,
  1469. },
  1470. /* Fast Read 1-1-4 */
  1471. {
  1472. SNOR_HWCAPS_READ_1_1_4,
  1473. BFPT_DWORD(1), BIT(22), /* Supported bit */
  1474. BFPT_DWORD(3), 16, /* Settings */
  1475. SNOR_PROTO_1_1_4,
  1476. },
  1477. /* Fast Read 1-4-4 */
  1478. {
  1479. SNOR_HWCAPS_READ_1_4_4,
  1480. BFPT_DWORD(1), BIT(21), /* Supported bit */
  1481. BFPT_DWORD(3), 0, /* Settings */
  1482. SNOR_PROTO_1_4_4,
  1483. },
  1484. /* Fast Read 4-4-4 */
  1485. {
  1486. SNOR_HWCAPS_READ_4_4_4,
  1487. BFPT_DWORD(5), BIT(4), /* Supported bit */
  1488. BFPT_DWORD(7), 16, /* Settings */
  1489. SNOR_PROTO_4_4_4,
  1490. },
  1491. };
  1492. struct sfdp_bfpt_erase {
  1493. /*
  1494. * The half-word at offset <shift> in DWORD <dwoard> encodes the
  1495. * op code and erase sector size to be used by Sector Erase commands.
  1496. */
  1497. u32 dword;
  1498. u32 shift;
  1499. };
  1500. static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
  1501. /* Erase Type 1 in DWORD8 bits[15:0] */
  1502. {BFPT_DWORD(8), 0},
  1503. /* Erase Type 2 in DWORD8 bits[31:16] */
  1504. {BFPT_DWORD(8), 16},
  1505. /* Erase Type 3 in DWORD9 bits[15:0] */
  1506. {BFPT_DWORD(9), 0},
  1507. /* Erase Type 4 in DWORD9 bits[31:16] */
  1508. {BFPT_DWORD(9), 16},
  1509. };
  1510. static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
  1511. /**
  1512. * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
  1513. * @nor: pointer to a 'struct spi_nor'
  1514. * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
  1515. * the Basic Flash Parameter Table length and version
  1516. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1517. * filled
  1518. *
  1519. * The Basic Flash Parameter Table is the main and only mandatory table as
  1520. * defined by the SFDP (JESD216) specification.
  1521. * It provides us with the total size (memory density) of the data array and
  1522. * the number of address bytes for Fast Read, Page Program and Sector Erase
  1523. * commands.
  1524. * For Fast READ commands, it also gives the number of mode clock cycles and
  1525. * wait states (regrouped in the number of dummy clock cycles) for each
  1526. * supported instruction op code.
  1527. * For Page Program, the page size is now available since JESD216 rev A, however
  1528. * the supported instruction op codes are still not provided.
  1529. * For Sector Erase commands, this table stores the supported instruction op
  1530. * codes and the associated sector sizes.
  1531. * Finally, the Quad Enable Requirements (QER) are also available since JESD216
  1532. * rev A. The QER bits encode the manufacturer dependent procedure to be
  1533. * executed to set the Quad Enable (QE) bit in some internal register of the
  1534. * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
  1535. * sending any Quad SPI command to the memory. Actually, setting the QE bit
  1536. * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
  1537. * and IO3 hence enabling 4 (Quad) I/O lines.
  1538. *
  1539. * Return: 0 on success, -errno otherwise.
  1540. */
  1541. static int spi_nor_parse_bfpt(struct spi_nor *nor,
  1542. const struct sfdp_parameter_header *bfpt_header,
  1543. struct spi_nor_flash_parameter *params)
  1544. {
  1545. struct mtd_info *mtd = &nor->mtd;
  1546. struct sfdp_bfpt bfpt;
  1547. size_t len;
  1548. int i, cmd, err;
  1549. u32 addr;
  1550. u16 half;
  1551. /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
  1552. if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
  1553. return -EINVAL;
  1554. /* Read the Basic Flash Parameter Table. */
  1555. len = min_t(size_t, sizeof(bfpt),
  1556. bfpt_header->length * sizeof(u32));
  1557. addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
  1558. memset(&bfpt, 0, sizeof(bfpt));
  1559. err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
  1560. if (err < 0)
  1561. return err;
  1562. /* Fix endianness of the BFPT DWORDs. */
  1563. for (i = 0; i < BFPT_DWORD_MAX; i++)
  1564. bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
  1565. /* Number of address bytes. */
  1566. switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
  1567. case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
  1568. nor->addr_width = 3;
  1569. break;
  1570. case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
  1571. nor->addr_width = 4;
  1572. break;
  1573. default:
  1574. break;
  1575. }
  1576. /* Flash Memory Density (in bits). */
  1577. params->size = bfpt.dwords[BFPT_DWORD(2)];
  1578. if (params->size & BIT(31)) {
  1579. params->size &= ~BIT(31);
  1580. /*
  1581. * Prevent overflows on params->size. Anyway, a NOR of 2^64
  1582. * bits is unlikely to exist so this error probably means
  1583. * the BFPT we are reading is corrupted/wrong.
  1584. */
  1585. if (params->size > 63)
  1586. return -EINVAL;
  1587. params->size = 1ULL << params->size;
  1588. } else {
  1589. params->size++;
  1590. }
  1591. params->size >>= 3; /* Convert to bytes. */
  1592. /* Fast Read settings. */
  1593. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
  1594. const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
  1595. struct spi_nor_read_command *read;
  1596. if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
  1597. params->hwcaps.mask &= ~rd->hwcaps;
  1598. continue;
  1599. }
  1600. params->hwcaps.mask |= rd->hwcaps;
  1601. cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
  1602. read = &params->reads[cmd];
  1603. half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
  1604. spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
  1605. }
  1606. /* Sector Erase settings. */
  1607. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
  1608. const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
  1609. u32 erasesize;
  1610. u8 opcode;
  1611. half = bfpt.dwords[er->dword] >> er->shift;
  1612. erasesize = half & 0xff;
  1613. /* erasesize == 0 means this Erase Type is not supported. */
  1614. if (!erasesize)
  1615. continue;
  1616. erasesize = 1U << erasesize;
  1617. opcode = (half >> 8) & 0xff;
  1618. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1619. if (erasesize == SZ_4K) {
  1620. nor->erase_opcode = opcode;
  1621. mtd->erasesize = erasesize;
  1622. break;
  1623. }
  1624. #endif
  1625. if (!mtd->erasesize || mtd->erasesize < erasesize) {
  1626. nor->erase_opcode = opcode;
  1627. mtd->erasesize = erasesize;
  1628. }
  1629. }
  1630. /* Stop here if not JESD216 rev A or later. */
  1631. if (bfpt_header->length < BFPT_DWORD_MAX)
  1632. return 0;
  1633. /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
  1634. params->page_size = bfpt.dwords[BFPT_DWORD(11)];
  1635. params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
  1636. params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
  1637. params->page_size = 1U << params->page_size;
  1638. /* Quad Enable Requirements. */
  1639. switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
  1640. case BFPT_DWORD15_QER_NONE:
  1641. params->quad_enable = NULL;
  1642. break;
  1643. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1644. case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
  1645. case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
  1646. params->quad_enable = spansion_no_read_cr_quad_enable;
  1647. break;
  1648. #endif
  1649. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1650. case BFPT_DWORD15_QER_SR1_BIT6:
  1651. params->quad_enable = macronix_quad_enable;
  1652. break;
  1653. #endif
  1654. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1655. case BFPT_DWORD15_QER_SR2_BIT1:
  1656. params->quad_enable = spansion_read_cr_quad_enable;
  1657. break;
  1658. #endif
  1659. default:
  1660. return -EINVAL;
  1661. }
  1662. return 0;
  1663. }
  1664. /**
  1665. * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
  1666. * SFDP table.
  1667. * @nor: pointer to a 'struct spi_nor'.
  1668. * @param_header: pointer to the SFDP parameter header.
  1669. *
  1670. * Return: 0 on success, -errno otherwise.
  1671. */
  1672. static int
  1673. spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
  1674. const struct sfdp_parameter_header *param_header)
  1675. {
  1676. size_t size;
  1677. u32 addr;
  1678. int ret;
  1679. size = param_header->length * sizeof(u32);
  1680. addr = SFDP_PARAM_HEADER_PTP(param_header);
  1681. nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
  1682. if (!nor->manufacturer_sfdp)
  1683. return -ENOMEM;
  1684. ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
  1685. return ret;
  1686. }
  1687. /**
  1688. * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  1689. * @nor: pointer to a 'struct spi_nor'
  1690. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1691. * filled
  1692. *
  1693. * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
  1694. * specification. This is a standard which tends to supported by almost all
  1695. * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
  1696. * runtime the main parameters needed to perform basic SPI flash operations such
  1697. * as Fast Read, Page Program or Sector Erase commands.
  1698. *
  1699. * Return: 0 on success, -errno otherwise.
  1700. */
  1701. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  1702. struct spi_nor_flash_parameter *params)
  1703. {
  1704. const struct sfdp_parameter_header *param_header, *bfpt_header;
  1705. struct sfdp_parameter_header *param_headers = NULL;
  1706. struct sfdp_header header;
  1707. size_t psize;
  1708. int i, err;
  1709. /* Get the SFDP header. */
  1710. err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
  1711. if (err < 0)
  1712. return err;
  1713. /* Check the SFDP header version. */
  1714. if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
  1715. header.major != SFDP_JESD216_MAJOR)
  1716. return -EINVAL;
  1717. /*
  1718. * Verify that the first and only mandatory parameter header is a
  1719. * Basic Flash Parameter Table header as specified in JESD216.
  1720. */
  1721. bfpt_header = &header.bfpt_header;
  1722. if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
  1723. bfpt_header->major != SFDP_JESD216_MAJOR)
  1724. return -EINVAL;
  1725. /*
  1726. * Allocate memory then read all parameter headers with a single
  1727. * Read SFDP command. These parameter headers will actually be parsed
  1728. * twice: a first time to get the latest revision of the basic flash
  1729. * parameter table, then a second time to handle the supported optional
  1730. * tables.
  1731. * Hence we read the parameter headers once for all to reduce the
  1732. * processing time. Also we use kmalloc() instead of devm_kmalloc()
  1733. * because we don't need to keep these parameter headers: the allocated
  1734. * memory is always released with kfree() before exiting this function.
  1735. */
  1736. if (header.nph) {
  1737. psize = header.nph * sizeof(*param_headers);
  1738. param_headers = kmalloc(psize, GFP_KERNEL);
  1739. if (!param_headers)
  1740. return -ENOMEM;
  1741. err = spi_nor_read_sfdp(nor, sizeof(header),
  1742. psize, param_headers);
  1743. if (err < 0) {
  1744. dev_err(dev, "failed to read SFDP parameter headers\n");
  1745. goto exit;
  1746. }
  1747. }
  1748. /*
  1749. * Check other parameter headers to get the latest revision of
  1750. * the basic flash parameter table.
  1751. */
  1752. for (i = 0; i < header.nph; i++) {
  1753. param_header = &param_headers[i];
  1754. if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
  1755. param_header->major == SFDP_JESD216_MAJOR &&
  1756. (param_header->minor > bfpt_header->minor ||
  1757. (param_header->minor == bfpt_header->minor &&
  1758. param_header->length > bfpt_header->length)))
  1759. bfpt_header = param_header;
  1760. }
  1761. err = spi_nor_parse_bfpt(nor, bfpt_header, params);
  1762. if (err)
  1763. goto exit;
  1764. /* Parse other parameter headers. */
  1765. for (i = 0; i < header.nph; i++) {
  1766. param_header = &param_headers[i];
  1767. switch (SFDP_PARAM_HEADER_ID(param_header)) {
  1768. case SFDP_SECTOR_MAP_ID:
  1769. dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
  1770. break;
  1771. case SFDP_SST_ID:
  1772. err = spi_nor_parse_microchip_sfdp(nor, param_header);
  1773. break;
  1774. default:
  1775. break;
  1776. }
  1777. if (err) {
  1778. dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
  1779. SFDP_PARAM_HEADER_ID(param_header));
  1780. /*
  1781. * Let's not drop all information we extracted so far
  1782. * if optional table parsers fail. In case of failing,
  1783. * each optional parser is responsible to roll back to
  1784. * the previously known spi_nor data.
  1785. */
  1786. err = 0;
  1787. }
  1788. }
  1789. exit:
  1790. kfree(param_headers);
  1791. return err;
  1792. }
  1793. #else
  1794. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  1795. struct spi_nor_flash_parameter *params)
  1796. {
  1797. return -EINVAL;
  1798. }
  1799. #endif /* SPI_FLASH_SFDP_SUPPORT */
  1800. static int spi_nor_init_params(struct spi_nor *nor,
  1801. const struct flash_info *info,
  1802. struct spi_nor_flash_parameter *params)
  1803. {
  1804. /* Set legacy flash parameters as default. */
  1805. memset(params, 0, sizeof(*params));
  1806. /* Set SPI NOR sizes. */
  1807. params->size = info->sector_size * info->n_sectors;
  1808. params->page_size = info->page_size;
  1809. /* (Fast) Read settings. */
  1810. params->hwcaps.mask |= SNOR_HWCAPS_READ;
  1811. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  1812. 0, 0, SPINOR_OP_READ,
  1813. SNOR_PROTO_1_1_1);
  1814. if (!(info->flags & SPI_NOR_NO_FR)) {
  1815. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  1816. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  1817. 0, 8, SPINOR_OP_READ_FAST,
  1818. SNOR_PROTO_1_1_1);
  1819. }
  1820. if (info->flags & SPI_NOR_DUAL_READ) {
  1821. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  1822. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
  1823. 0, 8, SPINOR_OP_READ_1_1_2,
  1824. SNOR_PROTO_1_1_2);
  1825. }
  1826. if (info->flags & SPI_NOR_QUAD_READ) {
  1827. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  1828. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  1829. 0, 8, SPINOR_OP_READ_1_1_4,
  1830. SNOR_PROTO_1_1_4);
  1831. }
  1832. if (info->flags & SPI_NOR_OCTAL_READ) {
  1833. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  1834. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
  1835. 0, 8, SPINOR_OP_READ_1_1_8,
  1836. SNOR_PROTO_1_1_8);
  1837. }
  1838. /* Page Program settings. */
  1839. params->hwcaps.mask |= SNOR_HWCAPS_PP;
  1840. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  1841. SPINOR_OP_PP, SNOR_PROTO_1_1_1);
  1842. if (info->flags & SPI_NOR_QUAD_READ) {
  1843. params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
  1844. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
  1845. SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
  1846. }
  1847. /* Select the procedure to set the Quad Enable bit. */
  1848. if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
  1849. SNOR_HWCAPS_PP_QUAD)) {
  1850. switch (JEDEC_MFR(info)) {
  1851. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1852. case SNOR_MFR_MACRONIX:
  1853. params->quad_enable = macronix_quad_enable;
  1854. break;
  1855. #endif
  1856. case SNOR_MFR_ST:
  1857. case SNOR_MFR_MICRON:
  1858. break;
  1859. default:
  1860. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1861. /* Kept only for backward compatibility purpose. */
  1862. params->quad_enable = spansion_read_cr_quad_enable;
  1863. #endif
  1864. break;
  1865. }
  1866. }
  1867. /* Override the parameters with data read from SFDP tables. */
  1868. nor->addr_width = 0;
  1869. nor->mtd.erasesize = 0;
  1870. if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
  1871. !(info->flags & SPI_NOR_SKIP_SFDP)) {
  1872. struct spi_nor_flash_parameter sfdp_params;
  1873. memcpy(&sfdp_params, params, sizeof(sfdp_params));
  1874. if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
  1875. nor->addr_width = 0;
  1876. nor->mtd.erasesize = 0;
  1877. } else {
  1878. memcpy(params, &sfdp_params, sizeof(*params));
  1879. }
  1880. }
  1881. return 0;
  1882. }
  1883. static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  1884. {
  1885. size_t i;
  1886. for (i = 0; i < size; i++)
  1887. if (table[i][0] == (int)hwcaps)
  1888. return table[i][1];
  1889. return -EINVAL;
  1890. }
  1891. static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
  1892. {
  1893. static const int hwcaps_read2cmd[][2] = {
  1894. { SNOR_HWCAPS_READ, SNOR_CMD_READ },
  1895. { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
  1896. { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
  1897. { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
  1898. { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
  1899. { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
  1900. { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
  1901. { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
  1902. { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
  1903. { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
  1904. { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
  1905. { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
  1906. { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
  1907. { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
  1908. { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
  1909. };
  1910. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
  1911. ARRAY_SIZE(hwcaps_read2cmd));
  1912. }
  1913. static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
  1914. {
  1915. static const int hwcaps_pp2cmd[][2] = {
  1916. { SNOR_HWCAPS_PP, SNOR_CMD_PP },
  1917. { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
  1918. { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
  1919. { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
  1920. { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
  1921. { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
  1922. { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
  1923. };
  1924. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
  1925. ARRAY_SIZE(hwcaps_pp2cmd));
  1926. }
  1927. static int spi_nor_select_read(struct spi_nor *nor,
  1928. const struct spi_nor_flash_parameter *params,
  1929. u32 shared_hwcaps)
  1930. {
  1931. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
  1932. const struct spi_nor_read_command *read;
  1933. if (best_match < 0)
  1934. return -EINVAL;
  1935. cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
  1936. if (cmd < 0)
  1937. return -EINVAL;
  1938. read = &params->reads[cmd];
  1939. nor->read_opcode = read->opcode;
  1940. nor->read_proto = read->proto;
  1941. /*
  1942. * In the spi-nor framework, we don't need to make the difference
  1943. * between mode clock cycles and wait state clock cycles.
  1944. * Indeed, the value of the mode clock cycles is used by a QSPI
  1945. * flash memory to know whether it should enter or leave its 0-4-4
  1946. * (Continuous Read / XIP) mode.
  1947. * eXecution In Place is out of the scope of the mtd sub-system.
  1948. * Hence we choose to merge both mode and wait state clock cycles
  1949. * into the so called dummy clock cycles.
  1950. */
  1951. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  1952. return 0;
  1953. }
  1954. static int spi_nor_select_pp(struct spi_nor *nor,
  1955. const struct spi_nor_flash_parameter *params,
  1956. u32 shared_hwcaps)
  1957. {
  1958. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
  1959. const struct spi_nor_pp_command *pp;
  1960. if (best_match < 0)
  1961. return -EINVAL;
  1962. cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
  1963. if (cmd < 0)
  1964. return -EINVAL;
  1965. pp = &params->page_programs[cmd];
  1966. nor->program_opcode = pp->opcode;
  1967. nor->write_proto = pp->proto;
  1968. return 0;
  1969. }
  1970. static int spi_nor_select_erase(struct spi_nor *nor,
  1971. const struct flash_info *info)
  1972. {
  1973. struct mtd_info *mtd = &nor->mtd;
  1974. /* Do nothing if already configured from SFDP. */
  1975. if (mtd->erasesize)
  1976. return 0;
  1977. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1978. /* prefer "small sector" erase if possible */
  1979. if (info->flags & SECT_4K) {
  1980. nor->erase_opcode = SPINOR_OP_BE_4K;
  1981. mtd->erasesize = 4096;
  1982. } else if (info->flags & SECT_4K_PMC) {
  1983. nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
  1984. mtd->erasesize = 4096;
  1985. } else
  1986. #endif
  1987. {
  1988. nor->erase_opcode = SPINOR_OP_SE;
  1989. mtd->erasesize = info->sector_size;
  1990. }
  1991. return 0;
  1992. }
  1993. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  1994. const struct spi_nor_flash_parameter *params,
  1995. const struct spi_nor_hwcaps *hwcaps)
  1996. {
  1997. u32 ignored_mask, shared_mask;
  1998. bool enable_quad_io;
  1999. int err;
  2000. /*
  2001. * Keep only the hardware capabilities supported by both the SPI
  2002. * controller and the SPI flash memory.
  2003. */
  2004. shared_mask = hwcaps->mask & params->hwcaps.mask;
  2005. /* SPI n-n-n protocols are not supported yet. */
  2006. ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
  2007. SNOR_HWCAPS_READ_4_4_4 |
  2008. SNOR_HWCAPS_READ_8_8_8 |
  2009. SNOR_HWCAPS_PP_4_4_4 |
  2010. SNOR_HWCAPS_PP_8_8_8);
  2011. if (shared_mask & ignored_mask) {
  2012. dev_dbg(nor->dev,
  2013. "SPI n-n-n protocols are not supported yet.\n");
  2014. shared_mask &= ~ignored_mask;
  2015. }
  2016. /* Select the (Fast) Read command. */
  2017. err = spi_nor_select_read(nor, params, shared_mask);
  2018. if (err) {
  2019. dev_dbg(nor->dev,
  2020. "can't select read settings supported by both the SPI controller and memory.\n");
  2021. return err;
  2022. }
  2023. /* Select the Page Program command. */
  2024. err = spi_nor_select_pp(nor, params, shared_mask);
  2025. if (err) {
  2026. dev_dbg(nor->dev,
  2027. "can't select write settings supported by both the SPI controller and memory.\n");
  2028. return err;
  2029. }
  2030. /* Select the Sector Erase command. */
  2031. err = spi_nor_select_erase(nor, info);
  2032. if (err) {
  2033. dev_dbg(nor->dev,
  2034. "can't select erase settings supported by both the SPI controller and memory.\n");
  2035. return err;
  2036. }
  2037. /* Enable Quad I/O if needed. */
  2038. enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
  2039. spi_nor_get_protocol_width(nor->write_proto) == 4);
  2040. if (enable_quad_io && params->quad_enable)
  2041. nor->quad_enable = params->quad_enable;
  2042. else
  2043. nor->quad_enable = NULL;
  2044. return 0;
  2045. }
  2046. static int spi_nor_init(struct spi_nor *nor)
  2047. {
  2048. int err;
  2049. /*
  2050. * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
  2051. * with the software protection bits set
  2052. */
  2053. if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
  2054. JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
  2055. JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
  2056. nor->info->flags & SPI_NOR_HAS_LOCK) {
  2057. write_enable(nor);
  2058. write_sr(nor, 0);
  2059. spi_nor_wait_till_ready(nor);
  2060. }
  2061. if (nor->quad_enable) {
  2062. err = nor->quad_enable(nor);
  2063. if (err) {
  2064. dev_dbg(nor->dev, "quad mode not supported\n");
  2065. return err;
  2066. }
  2067. }
  2068. if (nor->addr_width == 4 &&
  2069. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  2070. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  2071. /*
  2072. * If the RESET# pin isn't hooked up properly, or the system
  2073. * otherwise doesn't perform a reset command in the boot
  2074. * sequence, it's impossible to 100% protect against unexpected
  2075. * reboots (e.g., crashes). Warn the user (or hopefully, system
  2076. * designer) that this is bad.
  2077. */
  2078. if (nor->flags & SNOR_F_BROKEN_RESET)
  2079. printf("enabling reset hack; may not recover from unexpected reboots\n");
  2080. set_4byte(nor, nor->info, 1);
  2081. }
  2082. return 0;
  2083. }
  2084. int spi_nor_scan(struct spi_nor *nor)
  2085. {
  2086. struct spi_nor_flash_parameter params;
  2087. const struct flash_info *info = NULL;
  2088. struct mtd_info *mtd = &nor->mtd;
  2089. struct spi_nor_hwcaps hwcaps = {
  2090. .mask = SNOR_HWCAPS_READ |
  2091. SNOR_HWCAPS_READ_FAST |
  2092. SNOR_HWCAPS_PP,
  2093. };
  2094. struct spi_slave *spi = nor->spi;
  2095. int ret;
  2096. /* Reset SPI protocol for all commands. */
  2097. nor->reg_proto = SNOR_PROTO_1_1_1;
  2098. nor->read_proto = SNOR_PROTO_1_1_1;
  2099. nor->write_proto = SNOR_PROTO_1_1_1;
  2100. nor->read = spi_nor_read_data;
  2101. nor->write = spi_nor_write_data;
  2102. nor->read_reg = spi_nor_read_reg;
  2103. nor->write_reg = spi_nor_write_reg;
  2104. if (spi->mode & SPI_RX_OCTAL) {
  2105. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  2106. if (spi->mode & SPI_TX_OCTAL)
  2107. hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
  2108. SNOR_HWCAPS_PP_1_1_8 |
  2109. SNOR_HWCAPS_PP_1_8_8);
  2110. } else if (spi->mode & SPI_RX_QUAD) {
  2111. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  2112. if (spi->mode & SPI_TX_QUAD)
  2113. hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
  2114. SNOR_HWCAPS_PP_1_1_4 |
  2115. SNOR_HWCAPS_PP_1_4_4);
  2116. } else if (spi->mode & SPI_RX_DUAL) {
  2117. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  2118. if (spi->mode & SPI_TX_DUAL)
  2119. hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
  2120. }
  2121. info = spi_nor_read_id(nor);
  2122. if (IS_ERR_OR_NULL(info))
  2123. return -ENOENT;
  2124. /* Parse the Serial Flash Discoverable Parameters table. */
  2125. ret = spi_nor_init_params(nor, info, &params);
  2126. if (ret)
  2127. return ret;
  2128. if (!mtd->name)
  2129. mtd->name = info->name;
  2130. mtd->priv = nor;
  2131. mtd->type = MTD_NORFLASH;
  2132. mtd->writesize = 1;
  2133. mtd->flags = MTD_CAP_NORFLASH;
  2134. mtd->size = params.size;
  2135. mtd->_erase = spi_nor_erase;
  2136. mtd->_read = spi_nor_read;
  2137. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  2138. /* NOR protection support for STmicro/Micron chips and similar */
  2139. if (JEDEC_MFR(info) == SNOR_MFR_ST ||
  2140. JEDEC_MFR(info) == SNOR_MFR_MICRON ||
  2141. JEDEC_MFR(info) == SNOR_MFR_SST ||
  2142. info->flags & SPI_NOR_HAS_LOCK) {
  2143. nor->flash_lock = stm_lock;
  2144. nor->flash_unlock = stm_unlock;
  2145. nor->flash_is_locked = stm_is_locked;
  2146. }
  2147. #endif
  2148. #ifdef CONFIG_SPI_FLASH_SST
  2149. /*
  2150. * sst26 series block protection implementation differs from other
  2151. * series.
  2152. */
  2153. if (info->flags & SPI_NOR_HAS_SST26LOCK) {
  2154. nor->flash_lock = sst26_lock;
  2155. nor->flash_unlock = sst26_unlock;
  2156. nor->flash_is_locked = sst26_is_locked;
  2157. }
  2158. /* sst nor chips use AAI word program */
  2159. if (info->flags & SST_WRITE)
  2160. mtd->_write = sst_write;
  2161. else
  2162. #endif
  2163. mtd->_write = spi_nor_write;
  2164. if (info->flags & USE_FSR)
  2165. nor->flags |= SNOR_F_USE_FSR;
  2166. if (info->flags & SPI_NOR_HAS_TB)
  2167. nor->flags |= SNOR_F_HAS_SR_TB;
  2168. if (info->flags & NO_CHIP_ERASE)
  2169. nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
  2170. if (info->flags & USE_CLSR)
  2171. nor->flags |= SNOR_F_USE_CLSR;
  2172. if (info->flags & SPI_NOR_NO_ERASE)
  2173. mtd->flags |= MTD_NO_ERASE;
  2174. nor->page_size = params.page_size;
  2175. mtd->writebufsize = nor->page_size;
  2176. /* Some devices cannot do fast-read, no matter what DT tells us */
  2177. if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
  2178. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  2179. /*
  2180. * Configure the SPI memory:
  2181. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  2182. * - set the number of dummy cycles (mode cycles + wait states).
  2183. * - set the SPI protocols for register and memory accesses.
  2184. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  2185. */
  2186. ret = spi_nor_setup(nor, info, &params, &hwcaps);
  2187. if (ret)
  2188. return ret;
  2189. if (nor->addr_width) {
  2190. /* already configured from SFDP */
  2191. } else if (info->addr_width) {
  2192. nor->addr_width = info->addr_width;
  2193. } else if (mtd->size > SZ_16M) {
  2194. #ifndef CONFIG_SPI_FLASH_BAR
  2195. /* enable 4-byte addressing if the device exceeds 16MiB */
  2196. nor->addr_width = 4;
  2197. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  2198. info->flags & SPI_NOR_4B_OPCODES)
  2199. spi_nor_set_4byte_opcodes(nor, info);
  2200. #else
  2201. /* Configure the BAR - discover bank cmds and read current bank */
  2202. nor->addr_width = 3;
  2203. ret = read_bar(nor, info);
  2204. if (ret < 0)
  2205. return ret;
  2206. #endif
  2207. } else {
  2208. nor->addr_width = 3;
  2209. }
  2210. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  2211. dev_dbg(dev, "address width is too large: %u\n",
  2212. nor->addr_width);
  2213. return -EINVAL;
  2214. }
  2215. /* Send all the required SPI flash commands to initialize device */
  2216. nor->info = info;
  2217. ret = spi_nor_init(nor);
  2218. if (ret)
  2219. return ret;
  2220. nor->name = mtd->name;
  2221. nor->size = mtd->size;
  2222. nor->erase_size = mtd->erasesize;
  2223. nor->sector_size = mtd->erasesize;
  2224. #ifndef CONFIG_SPL_BUILD
  2225. printf("SF: Detected %s with page size ", nor->name);
  2226. print_size(nor->page_size, ", erase size ");
  2227. print_size(nor->erase_size, ", total ");
  2228. print_size(nor->size, "");
  2229. puts("\n");
  2230. #endif
  2231. return 0;
  2232. }
  2233. /* U-Boot specific functions, need to extend MTD to support these */
  2234. int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
  2235. {
  2236. int sr = read_sr(nor);
  2237. if (sr < 0)
  2238. return sr;
  2239. return (sr >> 2) & 7;
  2240. }