spi-nor-ids.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  5. * Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
  6. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  7. */
  8. #include <common.h>
  9. #include <spi.h>
  10. #include <spi_flash.h>
  11. #include "sf_internal.h"
  12. /* Exclude chip names for SPL to save space */
  13. #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
  14. #define INFO_NAME(_name) .name = _name,
  15. #else
  16. #define INFO_NAME(_name)
  17. #endif
  18. /* Used when the "_ext_id" is two bytes at most */
  19. #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  20. INFO_NAME(_name) \
  21. .id = { \
  22. ((_jedec_id) >> 16) & 0xff, \
  23. ((_jedec_id) >> 8) & 0xff, \
  24. (_jedec_id) & 0xff, \
  25. ((_ext_id) >> 8) & 0xff, \
  26. (_ext_id) & 0xff, \
  27. }, \
  28. .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
  29. .sector_size = (_sector_size), \
  30. .n_sectors = (_n_sectors), \
  31. .page_size = 256, \
  32. .flags = (_flags),
  33. #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  34. INFO_NAME(_name) \
  35. .id = { \
  36. ((_jedec_id) >> 16) & 0xff, \
  37. ((_jedec_id) >> 8) & 0xff, \
  38. (_jedec_id) & 0xff, \
  39. ((_ext_id) >> 16) & 0xff, \
  40. ((_ext_id) >> 8) & 0xff, \
  41. (_ext_id) & 0xff, \
  42. }, \
  43. .id_len = 6, \
  44. .sector_size = (_sector_size), \
  45. .n_sectors = (_n_sectors), \
  46. .page_size = 256, \
  47. .flags = (_flags),
  48. /* NOTE: double check command sets and memory organization when you add
  49. * more nor chips. This current list focusses on newer chips, which
  50. * have been converging on command sets which including JEDEC ID.
  51. *
  52. * All newly added entries should describe *hardware* and should use SECT_4K
  53. * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
  54. * scenarios excluding small sectors there is config option that can be
  55. * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS.
  56. * For historical (and compatibility) reasons (before we got above config) some
  57. * old entries may be missing 4K flag.
  58. */
  59. const struct flash_info spi_nor_ids[] = {
  60. #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
  61. /* Atmel -- some are (confusingly) marketed as "DataFlash" */
  62. { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
  63. { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
  64. { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
  65. { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
  66. { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
  67. { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
  68. { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
  69. { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
  70. { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
  71. { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
  72. { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
  73. #endif
  74. #ifdef CONFIG_SPI_FLASH_EON /* EON */
  75. /* EON -- en25xxx */
  76. { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
  77. { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
  78. { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
  79. { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
  80. #endif
  81. #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
  82. /* GigaDevice */
  83. {
  84. INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32,
  85. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  86. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  87. },
  88. {
  89. INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64,
  90. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  91. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  92. },
  93. {
  94. INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64,
  95. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  96. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  97. },
  98. {
  99. INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128,
  100. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  101. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  102. },
  103. {
  104. INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
  105. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  106. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  107. },
  108. {
  109. INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
  110. SECT_4K | SPI_NOR_DUAL_READ |
  111. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  112. },
  113. #endif
  114. #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
  115. /* ISSI */
  116. { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
  117. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  118. { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
  119. { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
  120. { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
  121. SECT_4K | SPI_NOR_DUAL_READ) },
  122. { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
  123. SECT_4K | SPI_NOR_DUAL_READ) },
  124. { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
  125. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  126. { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
  127. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  128. { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
  129. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  130. { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
  131. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  132. SPI_NOR_4B_OPCODES) },
  133. #endif
  134. #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
  135. /* Macronix */
  136. { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) },
  137. { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) },
  138. { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) },
  139. { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) },
  140. { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) },
  141. { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
  142. { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
  143. { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
  144. { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
  145. { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
  146. { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
  147. { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
  148. { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  149. { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
  150. { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
  151. { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  152. { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  153. { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  154. { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  155. { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
  156. #endif
  157. #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
  158. /* Micron */
  159. { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
  160. { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
  161. { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
  162. { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
  163. { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
  164. { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
  165. { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
  166. { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
  167. { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
  168. { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
  169. { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
  170. { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
  171. SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
  172. USE_FSR) },
  173. { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  174. { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  175. { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  176. { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
  177. { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
  178. { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
  179. { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
  180. { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
  181. #endif
  182. #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
  183. /* Spansion/Cypress -- single (large) sector size only, at least
  184. * for the chips listed here (without boot sectors).
  185. */
  186. { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  187. { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  188. { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  189. { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  190. { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  191. { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  192. { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  193. { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  194. { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  195. { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
  196. { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
  197. { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  198. { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  199. { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
  200. { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) },
  201. { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) },
  202. { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) },
  203. { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) },
  204. { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  205. { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
  206. { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
  207. { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  208. { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  209. #endif
  210. #ifdef CONFIG_SPI_FLASH_SST /* SST */
  211. /* SST -- large erase sizes are "overlays", "sectors" are 4K */
  212. { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
  213. { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
  214. { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
  215. { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
  216. { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
  217. { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
  218. { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
  219. { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
  220. { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) },
  221. { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
  222. { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
  223. { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
  224. { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  225. { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
  226. { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
  227. { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
  228. #endif
  229. #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
  230. /* ST Microelectronics -- newer production may have feature updates */
  231. { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) },
  232. { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) },
  233. { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) },
  234. { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) },
  235. { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) },
  236. { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) },
  237. { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) },
  238. { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) },
  239. { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) },
  240. { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  241. { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) },
  242. #endif
  243. #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
  244. /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  245. { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) },
  246. { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) },
  247. { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) },
  248. { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) },
  249. { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
  250. { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
  251. {
  252. INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
  253. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  254. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  255. },
  256. { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
  257. { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
  258. { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
  259. { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
  260. { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  261. {
  262. INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
  263. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  264. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  265. },
  266. {
  267. INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
  268. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  269. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  270. },
  271. { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
  272. {
  273. INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
  274. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  275. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  276. },
  277. {
  278. INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128,
  279. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  280. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  281. },
  282. {
  283. INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
  284. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  285. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  286. },
  287. {
  288. INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256,
  289. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  290. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  291. },
  292. {
  293. INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
  294. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  295. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  296. },
  297. {
  298. INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512,
  299. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  300. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  301. },
  302. { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
  303. { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  304. { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  305. { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  306. { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  307. { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  308. #endif
  309. #ifdef CONFIG_SPI_FLASH_XMC
  310. /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
  311. { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  312. { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  313. #endif
  314. { },
  315. };