spi-nor.h 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. * Synced from Linux v4.19
  5. */
  6. #ifndef __LINUX_MTD_SPI_NOR_H
  7. #define __LINUX_MTD_SPI_NOR_H
  8. #include <linux/bitops.h>
  9. #include <linux/mtd/cfi.h>
  10. #include <linux/mtd/mtd.h>
  11. /*
  12. * Manufacturer IDs
  13. *
  14. * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  15. * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  16. */
  17. #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
  18. #define SNOR_MFR_GIGADEVICE 0xc8
  19. #define SNOR_MFR_INTEL CFI_MFR_INTEL
  20. #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
  21. #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
  22. #define SNOR_MFR_ISSI CFI_MFR_PMC
  23. #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
  24. #define SNOR_MFR_SPANSION CFI_MFR_AMD
  25. #define SNOR_MFR_SST CFI_MFR_SST
  26. #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
  27. /*
  28. * Note on opcode nomenclature: some opcodes have a format like
  29. * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  30. * of I/O lines used for the opcode, address, and data (respectively). The
  31. * FUNCTION has an optional suffix of '4', to represent an opcode which
  32. * requires a 4-byte (32-bit) address.
  33. */
  34. /* Flash opcodes. */
  35. #define SPINOR_OP_WREN 0x06 /* Write enable */
  36. #define SPINOR_OP_RDSR 0x05 /* Read status register */
  37. #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
  38. #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
  39. #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
  40. #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
  41. #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
  42. #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
  43. #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
  44. #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
  45. #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
  46. #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
  47. #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
  48. #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
  49. #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
  50. #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
  51. #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
  52. #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
  53. #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
  54. #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
  55. #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
  56. #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
  57. #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
  58. #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
  59. #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
  60. #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
  61. #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
  62. #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
  63. #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
  64. #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
  65. /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  66. #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
  67. #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
  68. #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
  69. #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
  70. #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
  71. #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
  72. #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
  73. #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
  74. #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
  75. #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
  76. #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
  77. #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
  78. #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
  79. #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
  80. #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
  81. #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
  82. /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  83. #define SPINOR_OP_READ_1_1_1_DTR 0x0d
  84. #define SPINOR_OP_READ_1_2_2_DTR 0xbd
  85. #define SPINOR_OP_READ_1_4_4_DTR 0xed
  86. #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
  87. #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
  88. #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
  89. /* Used for SST flashes only. */
  90. #define SPINOR_OP_BP 0x02 /* Byte program */
  91. #define SPINOR_OP_WRDI 0x04 /* Write disable */
  92. #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
  93. /* Used for SST26* flashes only. */
  94. #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
  95. #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
  96. /* Used for S3AN flashes only */
  97. #define SPINOR_OP_XSE 0x50 /* Sector erase */
  98. #define SPINOR_OP_XPP 0x82 /* Page program */
  99. #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
  100. #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
  101. #define XSR_RDY BIT(7) /* Ready */
  102. /* Used for Macronix and Winbond flashes. */
  103. #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
  104. #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
  105. /* Used for Spansion flashes only. */
  106. #define SPINOR_OP_BRWR 0x17 /* Bank register write */
  107. #define SPINOR_OP_BRRD 0x16 /* Bank register read */
  108. #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
  109. /* Used for Micron flashes only. */
  110. #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
  111. #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
  112. /* Status Register bits. */
  113. #define SR_WIP BIT(0) /* Write in progress */
  114. #define SR_WEL BIT(1) /* Write enable latch */
  115. /* meaning of other SR_* bits may differ between vendors */
  116. #define SR_BP0 BIT(2) /* Block protect 0 */
  117. #define SR_BP1 BIT(3) /* Block protect 1 */
  118. #define SR_BP2 BIT(4) /* Block protect 2 */
  119. #define SR_TB BIT(5) /* Top/Bottom protect */
  120. #define SR_SRWD BIT(7) /* SR write protect */
  121. /* Spansion/Cypress specific status bits */
  122. #define SR_E_ERR BIT(5)
  123. #define SR_P_ERR BIT(6)
  124. #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
  125. /* Enhanced Volatile Configuration Register bits */
  126. #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
  127. /* Flag Status Register bits */
  128. #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
  129. #define FSR_E_ERR BIT(5) /* Erase operation status */
  130. #define FSR_P_ERR BIT(4) /* Program operation status */
  131. #define FSR_PT_ERR BIT(1) /* Protection error bit */
  132. /* Configuration Register bits. */
  133. #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
  134. /* Status Register 2 bits. */
  135. #define SR2_QUAD_EN_BIT7 BIT(7)
  136. /* Supported SPI protocols */
  137. #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
  138. #define SNOR_PROTO_INST_SHIFT 16
  139. #define SNOR_PROTO_INST(_nbits) \
  140. ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
  141. SNOR_PROTO_INST_MASK)
  142. #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
  143. #define SNOR_PROTO_ADDR_SHIFT 8
  144. #define SNOR_PROTO_ADDR(_nbits) \
  145. ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
  146. SNOR_PROTO_ADDR_MASK)
  147. #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
  148. #define SNOR_PROTO_DATA_SHIFT 0
  149. #define SNOR_PROTO_DATA(_nbits) \
  150. ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
  151. SNOR_PROTO_DATA_MASK)
  152. #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
  153. #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
  154. (SNOR_PROTO_INST(_inst_nbits) | \
  155. SNOR_PROTO_ADDR(_addr_nbits) | \
  156. SNOR_PROTO_DATA(_data_nbits))
  157. #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
  158. (SNOR_PROTO_IS_DTR | \
  159. SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
  160. enum spi_nor_protocol {
  161. SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
  162. SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
  163. SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
  164. SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
  165. SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
  166. SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
  167. SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
  168. SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
  169. SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
  170. SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
  171. SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
  172. SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
  173. SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
  174. SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
  175. };
  176. static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
  177. {
  178. return !!(proto & SNOR_PROTO_IS_DTR);
  179. }
  180. static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
  181. {
  182. return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
  183. SNOR_PROTO_INST_SHIFT;
  184. }
  185. static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
  186. {
  187. return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
  188. SNOR_PROTO_ADDR_SHIFT;
  189. }
  190. static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
  191. {
  192. return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
  193. SNOR_PROTO_DATA_SHIFT;
  194. }
  195. static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
  196. {
  197. return spi_nor_get_protocol_data_nbits(proto);
  198. }
  199. #define SPI_NOR_MAX_CMD_SIZE 8
  200. enum spi_nor_ops {
  201. SPI_NOR_OPS_READ = 0,
  202. SPI_NOR_OPS_WRITE,
  203. SPI_NOR_OPS_ERASE,
  204. SPI_NOR_OPS_LOCK,
  205. SPI_NOR_OPS_UNLOCK,
  206. };
  207. enum spi_nor_option_flags {
  208. SNOR_F_USE_FSR = BIT(0),
  209. SNOR_F_HAS_SR_TB = BIT(1),
  210. SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
  211. SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
  212. SNOR_F_READY_XSR_RDY = BIT(4),
  213. SNOR_F_USE_CLSR = BIT(5),
  214. SNOR_F_BROKEN_RESET = BIT(6),
  215. };
  216. /**
  217. * struct flash_info - Forward declaration of a structure used internally by
  218. * spi_nor_scan()
  219. */
  220. struct flash_info;
  221. /*
  222. * TODO: Remove, once all users of spi_flash interface are moved to MTD
  223. *
  224. * struct spi_flash {
  225. * Defined below (keep this text to enable searching for spi_flash decl)
  226. * }
  227. */
  228. #define spi_flash spi_nor
  229. /**
  230. * struct spi_nor - Structure for defining a the SPI NOR layer
  231. * @mtd: point to a mtd_info structure
  232. * @lock: the lock for the read/write/erase/lock/unlock operations
  233. * @dev: point to a spi device, or a spi nor controller device.
  234. * @info: spi-nor part JDEC MFR id and other info
  235. * @manufacturer_sfdp: manufacturer specific SFDP table
  236. * @page_size: the page size of the SPI NOR
  237. * @addr_width: number of address bytes
  238. * @erase_opcode: the opcode for erasing a sector
  239. * @read_opcode: the read opcode
  240. * @read_dummy: the dummy needed by the read operation
  241. * @program_opcode: the program opcode
  242. * @bank_read_cmd: Bank read cmd
  243. * @bank_write_cmd: Bank write cmd
  244. * @bank_curr: Current flash bank
  245. * @sst_write_second: used by the SST write operation
  246. * @flags: flag options for the current SPI-NOR (SNOR_F_*)
  247. * @read_proto: the SPI protocol for read operations
  248. * @write_proto: the SPI protocol for write operations
  249. * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
  250. * @cmd_buf: used by the write_reg
  251. * @prepare: [OPTIONAL] do some preparations for the
  252. * read/write/erase/lock/unlock operations
  253. * @unprepare: [OPTIONAL] do some post work after the
  254. * read/write/erase/lock/unlock operations
  255. * @read_reg: [DRIVER-SPECIFIC] read out the register
  256. * @write_reg: [DRIVER-SPECIFIC] write data to the register
  257. * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
  258. * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
  259. * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
  260. * at the offset @offs; if not provided by the driver,
  261. * spi-nor will send the erase opcode via write_reg()
  262. * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
  263. * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
  264. * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
  265. * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
  266. * completely locked
  267. * @priv: the private data
  268. */
  269. struct spi_nor {
  270. struct mtd_info mtd;
  271. struct udevice *dev;
  272. struct spi_slave *spi;
  273. const struct flash_info *info;
  274. u8 *manufacturer_sfdp;
  275. u32 page_size;
  276. u8 addr_width;
  277. u8 erase_opcode;
  278. u8 read_opcode;
  279. u8 read_dummy;
  280. u8 program_opcode;
  281. #ifdef CONFIG_SPI_FLASH_BAR
  282. u8 bank_read_cmd;
  283. u8 bank_write_cmd;
  284. u8 bank_curr;
  285. #endif
  286. enum spi_nor_protocol read_proto;
  287. enum spi_nor_protocol write_proto;
  288. enum spi_nor_protocol reg_proto;
  289. bool sst_write_second;
  290. u32 flags;
  291. u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
  292. int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  293. void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  294. int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  295. int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  296. ssize_t (*read)(struct spi_nor *nor, loff_t from,
  297. size_t len, u_char *read_buf);
  298. ssize_t (*write)(struct spi_nor *nor, loff_t to,
  299. size_t len, const u_char *write_buf);
  300. int (*erase)(struct spi_nor *nor, loff_t offs);
  301. int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  302. int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  303. int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  304. int (*quad_enable)(struct spi_nor *nor);
  305. void *priv;
  306. /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
  307. const char *name;
  308. u32 size;
  309. u32 sector_size;
  310. u32 erase_size;
  311. };
  312. static inline void spi_nor_set_flash_node(struct spi_nor *nor,
  313. const struct device_node *np)
  314. {
  315. mtd_set_of_node(&nor->mtd, np);
  316. }
  317. static inline const struct
  318. device_node *spi_nor_get_flash_node(struct spi_nor *nor)
  319. {
  320. return mtd_get_of_node(&nor->mtd);
  321. }
  322. /**
  323. * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
  324. * supported by the SPI controller (bus master).
  325. * @mask: the bitmask listing all the supported hw capabilies
  326. */
  327. struct spi_nor_hwcaps {
  328. u32 mask;
  329. };
  330. /*
  331. *(Fast) Read capabilities.
  332. * MUST be ordered by priority: the higher bit position, the higher priority.
  333. * As a matter of performances, it is relevant to use Octo SPI protocols first,
  334. * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
  335. * (Slow) Read.
  336. */
  337. #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
  338. #define SNOR_HWCAPS_READ BIT(0)
  339. #define SNOR_HWCAPS_READ_FAST BIT(1)
  340. #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
  341. #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
  342. #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
  343. #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
  344. #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
  345. #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
  346. #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
  347. #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
  348. #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
  349. #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
  350. #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
  351. #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
  352. #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
  353. #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
  354. #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
  355. #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
  356. /*
  357. * Page Program capabilities.
  358. * MUST be ordered by priority: the higher bit position, the higher priority.
  359. * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
  360. * legacy SPI 1-1-1 protocol.
  361. * Note that Dual Page Programs are not supported because there is no existing
  362. * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
  363. * implements such commands.
  364. */
  365. #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
  366. #define SNOR_HWCAPS_PP BIT(16)
  367. #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
  368. #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
  369. #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
  370. #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
  371. #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
  372. #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
  373. #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
  374. #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
  375. /**
  376. * spi_nor_scan() - scan the SPI NOR
  377. * @nor: the spi_nor structure
  378. *
  379. * The drivers can use this function to scan the SPI NOR.
  380. * In the scanning, it will try to get all the necessary information to
  381. * fill the mtd_info{} and the spi_nor{}.
  382. *
  383. * Return: 0 for success, others for failure.
  384. */
  385. int spi_nor_scan(struct spi_nor *nor);
  386. #endif