|
@@ -1573,6 +1573,20 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ spi4_pins_a: spi4-0 {
|
|
|
+ pins {
|
|
|
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
|
|
|
+ <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <1>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
stusb1600_pins_a: stusb1600-0 {
|
|
|
pins {
|
|
|
pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
|
|
@@ -1580,6 +1594,133 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ uart4_pins_a: uart4-0 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart4_idle_pins_a: uart4-idle-0 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart4_sleep_pins_a: uart4-sleep-0 {
|
|
|
+ pins {
|
|
|
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
|
|
|
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart4_pins_b: uart4-1 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart4_pins_c: uart4-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart7_pins_a: uart7-0 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
|
|
|
+ <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
|
|
|
+ <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart7_pins_b: uart7-1 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart7_pins_c: uart7-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart7_idle_pins_c: uart7-idle-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart7_sleep_pins_c: uart7-sleep-2 {
|
|
|
+ pins {
|
|
|
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
|
|
|
+ <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ uart8_pins_a: uart8-0 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
usart2_pins_a: usart2-0 {
|
|
|
pins1 {
|
|
|
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
|
|
@@ -1628,6 +1769,42 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ usart2_pins_c: usart2-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
|
|
|
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <3>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
|
|
|
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart2_idle_pins_c: usart2-idle-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
|
|
|
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart2_sleep_pins_c: usart2-sleep-2 {
|
|
|
+ pins {
|
|
|
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
|
|
|
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
|
|
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
|
|
|
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
usart3_pins_a: usart3-0 {
|
|
|
pins1 {
|
|
|
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
|
|
@@ -1641,6 +1818,78 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ usart3_pins_b: usart3-1 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
|
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
|
+ <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart3_idle_pins_b: usart3-idle-1 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart3_sleep_pins_b: usart3-sleep-1 {
|
|
|
+ pins {
|
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
|
+ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
|
|
|
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart3_pins_c: usart3-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
|
|
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
|
|
+ bias-disable;
|
|
|
+ drive-push-pull;
|
|
|
+ slew-rate = <0>;
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
|
|
+ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart3_idle_pins_c: usart3-idle-2 {
|
|
|
+ pins1 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
|
+ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
|
|
|
+ };
|
|
|
+ pins2 {
|
|
|
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
|
|
|
+ bias-disable;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ usart3_sleep_pins_c: usart3-sleep-2 {
|
|
|
+ pins {
|
|
|
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
|
|
|
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
|
|
|
+ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
|
|
|
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
uart4_pins_a: uart4-0 {
|
|
|
pins1 {
|
|
|
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
|
@@ -1782,18 +2031,4 @@
|
|
|
bias-disable;
|
|
|
};
|
|
|
};
|
|
|
-
|
|
|
- spi4_pins_a: spi4-0 {
|
|
|
- pins {
|
|
|
- pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
|
|
|
- <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
|
|
|
- bias-disable;
|
|
|
- drive-push-pull;
|
|
|
- slew-rate = <1>;
|
|
|
- };
|
|
|
- pins2 {
|
|
|
- pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
|
|
|
- bias-disable;
|
|
|
- };
|
|
|
- };
|
|
|
};
|