stm32_ltdc.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
  4. * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  5. * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <display.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <panel.h>
  13. #include <reset.h>
  14. #include <video.h>
  15. #include <video_bridge.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/gpio.h>
  18. #include <dm/device-internal.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/bitops.h>
  21. struct stm32_ltdc_priv {
  22. void __iomem *regs;
  23. enum video_log2_bpp l2bpp;
  24. u32 bg_col_argb;
  25. u32 crop_x, crop_y, crop_w, crop_h;
  26. u32 alpha;
  27. };
  28. /* LTDC main registers */
  29. #define LTDC_IDR 0x00 /* IDentification */
  30. #define LTDC_LCR 0x04 /* Layer Count */
  31. #define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
  32. #define LTDC_BPCR 0x0C /* Back Porch Configuration */
  33. #define LTDC_AWCR 0x10 /* Active Width Configuration */
  34. #define LTDC_TWCR 0x14 /* Total Width Configuration */
  35. #define LTDC_GCR 0x18 /* Global Control */
  36. #define LTDC_GC1R 0x1C /* Global Configuration 1 */
  37. #define LTDC_GC2R 0x20 /* Global Configuration 2 */
  38. #define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
  39. #define LTDC_GACR 0x28 /* GAmma Correction */
  40. #define LTDC_BCCR 0x2C /* Background Color Configuration */
  41. #define LTDC_IER 0x34 /* Interrupt Enable */
  42. #define LTDC_ISR 0x38 /* Interrupt Status */
  43. #define LTDC_ICR 0x3C /* Interrupt Clear */
  44. #define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
  45. #define LTDC_CPSR 0x44 /* Current Position Status */
  46. #define LTDC_CDSR 0x48 /* Current Display Status */
  47. /* LTDC layer 1 registers */
  48. #define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
  49. #define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
  50. #define LTDC_L1CR 0x84 /* L1 Control */
  51. #define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
  52. #define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
  53. #define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
  54. #define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
  55. #define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
  56. #define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
  57. #define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
  58. #define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
  59. #define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
  60. #define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
  61. #define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
  62. #define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
  63. #define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
  64. #define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
  65. #define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
  66. #define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
  67. /* Bit definitions */
  68. #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
  69. #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
  70. #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
  71. #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
  72. #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
  73. #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
  74. #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
  75. #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
  76. #define GCR_LTDCEN BIT(0) /* LTDC ENable */
  77. #define GCR_DEN BIT(16) /* Dither ENable */
  78. #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
  79. #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
  80. #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
  81. #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
  82. #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
  83. #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
  84. #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
  85. #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
  86. #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
  87. #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
  88. #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
  89. #define GC1R_BCP BIT(22) /* Background Colour Programmable */
  90. #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
  91. #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
  92. #define GC1R_TP BIT(25) /* Timing Programmable */
  93. #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
  94. #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
  95. #define GC1R_DWP BIT(28) /* Dither Width Programmable */
  96. #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
  97. #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
  98. #define GC2R_EDCA BIT(0) /* External Display Control Ability */
  99. #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
  100. #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
  101. #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
  102. #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
  103. #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
  104. #define SRCR_IMR BIT(0) /* IMmediate Reload */
  105. #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
  106. #define LXCR_LEN BIT(0) /* Layer ENable */
  107. #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
  108. #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
  109. #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
  110. #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
  111. #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
  112. #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
  113. #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
  114. #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
  115. #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
  116. #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
  117. #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
  118. #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
  119. #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
  120. #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
  121. #define BF1_CA 0x400 /* Constant Alpha */
  122. #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
  123. #define BF2_1CA 0x005 /* 1 - Constant Alpha */
  124. enum stm32_ltdc_pix_fmt {
  125. PF_ARGB8888 = 0,
  126. PF_RGB888,
  127. PF_RGB565,
  128. PF_ARGB1555,
  129. PF_ARGB4444,
  130. PF_L8,
  131. PF_AL44,
  132. PF_AL88
  133. };
  134. /* TODO add more color format support */
  135. static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
  136. {
  137. enum stm32_ltdc_pix_fmt pf;
  138. switch (l2bpp) {
  139. case VIDEO_BPP16:
  140. pf = PF_RGB565;
  141. break;
  142. case VIDEO_BPP32:
  143. pf = PF_ARGB8888;
  144. break;
  145. case VIDEO_BPP8:
  146. pf = PF_L8;
  147. break;
  148. case VIDEO_BPP1:
  149. case VIDEO_BPP2:
  150. case VIDEO_BPP4:
  151. default:
  152. pr_warn("%s: warning %dbpp not supported yet, %dbpp instead\n",
  153. __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
  154. pf = PF_RGB565;
  155. break;
  156. }
  157. debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
  158. return (u32)pf;
  159. }
  160. static bool has_alpha(u32 fmt)
  161. {
  162. switch (fmt) {
  163. case PF_ARGB8888:
  164. case PF_ARGB1555:
  165. case PF_ARGB4444:
  166. case PF_AL44:
  167. case PF_AL88:
  168. return true;
  169. case PF_RGB888:
  170. case PF_RGB565:
  171. case PF_L8:
  172. default:
  173. return false;
  174. }
  175. }
  176. static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
  177. {
  178. /* Reload configuration immediately & enable LTDC */
  179. setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
  180. setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
  181. }
  182. static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
  183. struct display_timing *timings)
  184. {
  185. void __iomem *regs = priv->regs;
  186. u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
  187. u32 total_w, total_h;
  188. u32 val;
  189. /* Convert video timings to ltdc timings */
  190. hsync = timings->hsync_len.typ - 1;
  191. vsync = timings->vsync_len.typ - 1;
  192. acc_hbp = hsync + timings->hback_porch.typ;
  193. acc_vbp = vsync + timings->vback_porch.typ;
  194. acc_act_w = acc_hbp + timings->hactive.typ;
  195. acc_act_h = acc_vbp + timings->vactive.typ;
  196. total_w = acc_act_w + timings->hfront_porch.typ;
  197. total_h = acc_act_h + timings->vfront_porch.typ;
  198. /* Synchronization sizes */
  199. val = (hsync << 16) | vsync;
  200. clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
  201. /* Accumulated back porch */
  202. val = (acc_hbp << 16) | acc_vbp;
  203. clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
  204. /* Accumulated active width */
  205. val = (acc_act_w << 16) | acc_act_h;
  206. clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
  207. /* Total width & height */
  208. val = (total_w << 16) | total_h;
  209. clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
  210. setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
  211. /* Signal polarities */
  212. val = 0;
  213. debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
  214. if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
  215. val |= GCR_HSPOL;
  216. if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
  217. val |= GCR_VSPOL;
  218. if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
  219. val |= GCR_DEPOL;
  220. if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  221. val |= GCR_PCPOL;
  222. clrsetbits_le32(regs + LTDC_GCR,
  223. GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
  224. /* Overall background color */
  225. writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
  226. }
  227. static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
  228. {
  229. void __iomem *regs = priv->regs;
  230. u32 x0, x1, y0, y1;
  231. u32 pitch_in_bytes;
  232. u32 line_length;
  233. u32 bus_width;
  234. u32 val, tmp, bpp;
  235. u32 format;
  236. x0 = priv->crop_x;
  237. x1 = priv->crop_x + priv->crop_w - 1;
  238. y0 = priv->crop_y;
  239. y1 = priv->crop_y + priv->crop_h - 1;
  240. /* Horizontal start and stop position */
  241. tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
  242. val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
  243. clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
  244. val);
  245. /* Vertical start & stop position */
  246. tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
  247. val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
  248. clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
  249. val);
  250. /* Layer background color */
  251. writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
  252. /* Color frame buffer pitch in bytes & line length */
  253. bpp = VNBITS(priv->l2bpp);
  254. pitch_in_bytes = priv->crop_w * (bpp >> 3);
  255. bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
  256. line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
  257. val = (pitch_in_bytes << 16) | line_length;
  258. clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
  259. /* Pixel format */
  260. format = stm32_ltdc_get_pixel_format(priv->l2bpp);
  261. clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
  262. /* Constant alpha value */
  263. clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
  264. /* Specifies the blending factors : with or without pixel alpha */
  265. /* Manage hw-specific capabilities */
  266. val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
  267. /* Blending factors */
  268. clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
  269. /* Frame buffer line number */
  270. clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
  271. /* Frame buffer address */
  272. writel(fb_addr, regs + LTDC_L1CFBAR);
  273. /* Enable layer 1 */
  274. setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
  275. }
  276. static int stm32_ltdc_probe(struct udevice *dev)
  277. {
  278. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  279. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  280. struct stm32_ltdc_priv *priv = dev_get_priv(dev);
  281. struct udevice *bridge = NULL;
  282. struct udevice *panel = NULL;
  283. struct display_timing timings;
  284. struct clk pclk;
  285. struct reset_ctl rst;
  286. int ret;
  287. priv->regs = (void *)dev_read_addr(dev);
  288. if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
  289. dev_err(dev, "ltdc dt register address error\n");
  290. return -EINVAL;
  291. }
  292. ret = clk_get_by_index(dev, 0, &pclk);
  293. if (ret) {
  294. dev_err(dev, "peripheral clock get error %d\n", ret);
  295. return ret;
  296. }
  297. ret = clk_enable(&pclk);
  298. if (ret) {
  299. dev_err(dev, "peripheral clock enable error %d\n", ret);
  300. return ret;
  301. }
  302. ret = uclass_first_device_err(UCLASS_PANEL, &panel);
  303. if (ret) {
  304. if (ret != -ENODEV)
  305. dev_err(dev, "panel device error %d\n", ret);
  306. return ret;
  307. }
  308. ret = panel_get_display_timing(panel, &timings);
  309. if (ret) {
  310. ret = ofnode_decode_display_timing(dev_ofnode(panel),
  311. 0, &timings);
  312. if (ret) {
  313. dev_err(dev, "decode display timing error %d\n", ret);
  314. return ret;
  315. }
  316. }
  317. ret = clk_set_rate(&pclk, timings.pixelclock.typ);
  318. if (ret)
  319. dev_warn(dev, "fail to set pixel clock %d hz\n",
  320. timings.pixelclock.typ);
  321. debug("%s: Set pixel clock req %d hz get %ld hz\n", __func__,
  322. timings.pixelclock.typ, clk_get_rate(&pclk));
  323. ret = reset_get_by_index(dev, 0, &rst);
  324. if (ret) {
  325. dev_err(dev, "missing ltdc hardware reset\n");
  326. return ret;
  327. }
  328. /* Reset */
  329. reset_deassert(&rst);
  330. if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
  331. ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
  332. if (ret)
  333. debug("No video bridge, or no backlight on bridge\n");
  334. if (bridge) {
  335. ret = video_bridge_attach(bridge);
  336. if (ret) {
  337. dev_err(dev, "fail to attach bridge\n");
  338. return ret;
  339. }
  340. }
  341. }
  342. /* TODO Below parameters are hard-coded for the moment... */
  343. priv->l2bpp = VIDEO_BPP16;
  344. priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
  345. priv->crop_x = 0;
  346. priv->crop_y = 0;
  347. priv->crop_w = timings.hactive.typ;
  348. priv->crop_h = timings.vactive.typ;
  349. priv->alpha = 0xFF;
  350. debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
  351. timings.hactive.typ, timings.vactive.typ,
  352. VNBITS(priv->l2bpp), uc_plat->base);
  353. debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
  354. priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
  355. priv->bg_col_argb, priv->alpha);
  356. /* Configure & start LTDC */
  357. stm32_ltdc_set_mode(priv, &timings);
  358. stm32_ltdc_set_layer1(priv, uc_plat->base);
  359. stm32_ltdc_enable(priv);
  360. uc_priv->xsize = timings.hactive.typ;
  361. uc_priv->ysize = timings.vactive.typ;
  362. uc_priv->bpix = priv->l2bpp;
  363. if (!bridge) {
  364. ret = panel_enable_backlight(panel);
  365. if (ret) {
  366. dev_err(dev, "panel %s enable backlight error %d\n",
  367. panel->name, ret);
  368. return ret;
  369. }
  370. } else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
  371. ret = video_bridge_set_backlight(bridge, 80);
  372. if (ret) {
  373. dev_err(dev, "fail to set backlight\n");
  374. return ret;
  375. }
  376. }
  377. video_set_flush_dcache(dev, true);
  378. return 0;
  379. }
  380. static int stm32_ltdc_bind(struct udevice *dev)
  381. {
  382. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  383. uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
  384. CONFIG_VIDEO_STM32_MAX_YRES *
  385. (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
  386. debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size);
  387. return 0;
  388. }
  389. static const struct udevice_id stm32_ltdc_ids[] = {
  390. { .compatible = "st,stm32-ltdc" },
  391. { }
  392. };
  393. U_BOOT_DRIVER(stm32_ltdc) = {
  394. .name = "stm32_display",
  395. .id = UCLASS_VIDEO,
  396. .of_match = stm32_ltdc_ids,
  397. .probe = stm32_ltdc_probe,
  398. .bind = stm32_ltdc_bind,
  399. .priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
  400. };