stm32_dsi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
  4. * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  5. * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  6. *
  7. * This MIPI DSI controller driver is based on the Linux Kernel driver from
  8. * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <dsi_host.h>
  14. #include <log.h>
  15. #include <mipi_dsi.h>
  16. #include <panel.h>
  17. #include <reset.h>
  18. #include <video.h>
  19. #include <video_bridge.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/gpio.h>
  22. #include <dm/device-internal.h>
  23. #include <dm/device_compat.h>
  24. #include <dm/lists.h>
  25. #include <linux/bitops.h>
  26. #include <linux/iopoll.h>
  27. #include <power/regulator.h>
  28. #define HWVER_130 0x31333000 /* IP version 1.30 */
  29. #define HWVER_131 0x31333100 /* IP version 1.31 */
  30. /* DSI digital registers & bit definitions */
  31. #define DSI_VERSION 0x00
  32. #define VERSION GENMASK(31, 8)
  33. /*
  34. * DSI wrapper registers & bit definitions
  35. * Note: registers are named as in the Reference Manual
  36. */
  37. #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
  38. #define WCFGR_DSIM BIT(0) /* DSI Mode */
  39. #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
  40. #define DSI_WCR 0x0404 /* Wrapper Control Reg */
  41. #define WCR_DSIEN BIT(3) /* DSI ENable */
  42. #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
  43. #define WISR_PLLLS BIT(8) /* PLL Lock Status */
  44. #define WISR_RRS BIT(12) /* Regulator Ready Status */
  45. #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
  46. #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
  47. #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
  48. #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
  49. #define WRPCR_PLLEN BIT(0) /* PLL ENable */
  50. #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
  51. #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
  52. #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
  53. #define WRPCR_REGEN BIT(24) /* REGulator ENable */
  54. #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
  55. #define IDF_MIN 1
  56. #define IDF_MAX 7
  57. #define NDIV_MIN 10
  58. #define NDIV_MAX 125
  59. #define ODF_MIN 1
  60. #define ODF_MAX 8
  61. /* dsi color format coding according to the datasheet */
  62. enum dsi_color {
  63. DSI_RGB565_CONF1,
  64. DSI_RGB565_CONF2,
  65. DSI_RGB565_CONF3,
  66. DSI_RGB666_CONF1,
  67. DSI_RGB666_CONF2,
  68. DSI_RGB888,
  69. };
  70. #define LANE_MIN_KBPS 31250
  71. #define LANE_MAX_KBPS 500000
  72. /* Timeout for regulator on/off, pll lock/unlock & fifo empty */
  73. #define TIMEOUT_US 200000
  74. struct stm32_dsi_priv {
  75. struct mipi_dsi_device device;
  76. void __iomem *base;
  77. struct udevice *panel;
  78. u32 pllref_clk;
  79. u32 hw_version;
  80. int lane_min_kbps;
  81. int lane_max_kbps;
  82. struct udevice *vdd_reg;
  83. struct udevice *dsi_host;
  84. };
  85. static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
  86. {
  87. writel(val, dsi->base + reg);
  88. }
  89. static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
  90. {
  91. return readl(dsi->base + reg);
  92. }
  93. static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
  94. {
  95. dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
  96. }
  97. static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
  98. {
  99. dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
  100. }
  101. static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg,
  102. u32 mask, u32 val)
  103. {
  104. dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
  105. }
  106. static enum dsi_color dsi_color_from_mipi(u32 fmt)
  107. {
  108. switch (fmt) {
  109. case MIPI_DSI_FMT_RGB888:
  110. return DSI_RGB888;
  111. case MIPI_DSI_FMT_RGB666:
  112. return DSI_RGB666_CONF2;
  113. case MIPI_DSI_FMT_RGB666_PACKED:
  114. return DSI_RGB666_CONF1;
  115. case MIPI_DSI_FMT_RGB565:
  116. return DSI_RGB565_CONF1;
  117. default:
  118. pr_err("MIPI color invalid, so we use rgb888\n");
  119. }
  120. return DSI_RGB888;
  121. }
  122. static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
  123. {
  124. int divisor = idf * odf;
  125. /* prevent from division by 0 */
  126. if (!divisor)
  127. return 0;
  128. return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
  129. }
  130. static int dsi_pll_get_params(struct stm32_dsi_priv *dsi,
  131. int clkin_khz, int clkout_khz,
  132. int *idf, int *ndiv, int *odf)
  133. {
  134. int i, o, n, n_min, n_max;
  135. int fvco_min, fvco_max, delta, best_delta; /* all in khz */
  136. /* Early checks preventing division by 0 & odd results */
  137. if (clkin_khz <= 0 || clkout_khz <= 0)
  138. return -EINVAL;
  139. fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
  140. fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
  141. best_delta = 1000000; /* big started value (1000000khz) */
  142. for (i = IDF_MIN; i <= IDF_MAX; i++) {
  143. /* Compute ndiv range according to Fvco */
  144. n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
  145. n_max = (fvco_max * i) / (2 * clkin_khz);
  146. /* No need to continue idf loop if we reach ndiv max */
  147. if (n_min >= NDIV_MAX)
  148. break;
  149. /* Clamp ndiv to valid values */
  150. if (n_min < NDIV_MIN)
  151. n_min = NDIV_MIN;
  152. if (n_max > NDIV_MAX)
  153. n_max = NDIV_MAX;
  154. for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
  155. n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
  156. /* Check ndiv according to vco range */
  157. if (n < n_min || n > n_max)
  158. continue;
  159. /* Check if new delta is better & saves parameters */
  160. delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
  161. clkout_khz;
  162. if (delta < 0)
  163. delta = -delta;
  164. if (delta < best_delta) {
  165. *idf = i;
  166. *ndiv = n;
  167. *odf = o;
  168. best_delta = delta;
  169. }
  170. /* fast return in case of "perfect result" */
  171. if (!delta)
  172. return 0;
  173. }
  174. }
  175. return 0;
  176. }
  177. static int dsi_phy_init(void *priv_data)
  178. {
  179. struct mipi_dsi_device *device = priv_data;
  180. struct udevice *dev = device->dev;
  181. struct stm32_dsi_priv *dsi = dev_get_priv(dev);
  182. u32 val;
  183. int ret;
  184. debug("Initialize DSI physical layer\n");
  185. /* Enable the regulator */
  186. dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
  187. ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
  188. TIMEOUT_US);
  189. if (ret) {
  190. debug("!TIMEOUT! waiting REGU\n");
  191. return ret;
  192. }
  193. /* Enable the DSI PLL & wait for its lock */
  194. dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
  195. ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
  196. TIMEOUT_US);
  197. if (ret) {
  198. debug("!TIMEOUT! waiting PLL\n");
  199. return ret;
  200. }
  201. return 0;
  202. }
  203. static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
  204. {
  205. struct mipi_dsi_device *device = priv_data;
  206. struct udevice *dev = device->dev;
  207. struct stm32_dsi_priv *dsi = dev_get_priv(dev);
  208. debug("Set mode %p enable %ld\n", dsi,
  209. mode_flags & MIPI_DSI_MODE_VIDEO);
  210. if (!dsi)
  211. return;
  212. /*
  213. * DSI wrapper must be enabled in video mode & disabled in command mode.
  214. * If wrapper is enabled in command mode, the display controller
  215. * register access will hang.
  216. */
  217. if (mode_flags & MIPI_DSI_MODE_VIDEO)
  218. dsi_set(dsi, DSI_WCR, WCR_DSIEN);
  219. else
  220. dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
  221. }
  222. static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
  223. u32 lanes, u32 format, unsigned int *lane_mbps)
  224. {
  225. struct mipi_dsi_device *device = priv_data;
  226. struct udevice *dev = device->dev;
  227. struct stm32_dsi_priv *dsi = dev_get_priv(dev);
  228. int idf, ndiv, odf, pll_in_khz, pll_out_khz;
  229. int ret, bpp;
  230. u32 val;
  231. /* Update lane capabilities according to hw version */
  232. dsi->lane_min_kbps = LANE_MIN_KBPS;
  233. dsi->lane_max_kbps = LANE_MAX_KBPS;
  234. if (dsi->hw_version == HWVER_131) {
  235. dsi->lane_min_kbps *= 2;
  236. dsi->lane_max_kbps *= 2;
  237. }
  238. pll_in_khz = dsi->pllref_clk / 1000;
  239. /* Compute requested pll out */
  240. bpp = mipi_dsi_pixel_format_to_bpp(format);
  241. pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes;
  242. /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
  243. pll_out_khz = (pll_out_khz * 12) / 10;
  244. if (pll_out_khz > dsi->lane_max_kbps) {
  245. pll_out_khz = dsi->lane_max_kbps;
  246. dev_warn(dev, "Warning max phy mbps is used\n");
  247. }
  248. if (pll_out_khz < dsi->lane_min_kbps) {
  249. pll_out_khz = dsi->lane_min_kbps;
  250. dev_warn(dev, "Warning min phy mbps is used\n");
  251. }
  252. /* Compute best pll parameters */
  253. idf = 0;
  254. ndiv = 0;
  255. odf = 0;
  256. ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
  257. &idf, &ndiv, &odf);
  258. if (ret) {
  259. dev_err(dev, "Warning dsi_pll_get_params(): bad params\n");
  260. return ret;
  261. }
  262. /* Get the adjusted pll out value */
  263. pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
  264. /* Set the PLL division factors */
  265. dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
  266. (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
  267. /* Compute uix4 & set the bit period in high-speed mode */
  268. val = 4000000 / pll_out_khz;
  269. dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
  270. /* Select video mode by resetting DSIM bit */
  271. dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
  272. /* Select the color coding */
  273. dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
  274. dsi_color_from_mipi(format) << 1);
  275. *lane_mbps = pll_out_khz / 1000;
  276. debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
  277. pll_in_khz, pll_out_khz, *lane_mbps);
  278. return 0;
  279. }
  280. static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = {
  281. .init = dsi_phy_init,
  282. .get_lane_mbps = dsi_get_lane_mbps,
  283. .post_set_mode = dsi_phy_post_set_mode,
  284. };
  285. static int stm32_dsi_attach(struct udevice *dev)
  286. {
  287. struct stm32_dsi_priv *priv = dev_get_priv(dev);
  288. struct mipi_dsi_device *device = &priv->device;
  289. struct mipi_dsi_panel_plat *mplat;
  290. struct display_timing timings;
  291. int ret;
  292. ret = uclass_first_device(UCLASS_PANEL, &priv->panel);
  293. if (ret) {
  294. dev_err(dev, "panel device error %d\n", ret);
  295. return ret;
  296. }
  297. mplat = dev_get_platdata(priv->panel);
  298. mplat->device = &priv->device;
  299. device->lanes = mplat->lanes;
  300. device->format = mplat->format;
  301. device->mode_flags = mplat->mode_flags;
  302. ret = panel_get_display_timing(priv->panel, &timings);
  303. if (ret) {
  304. ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
  305. 0, &timings);
  306. if (ret) {
  307. dev_err(dev, "decode display timing error %d\n", ret);
  308. return ret;
  309. }
  310. }
  311. ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
  312. if (ret) {
  313. dev_err(dev, "No video dsi host detected %d\n", ret);
  314. return ret;
  315. }
  316. ret = dsi_host_init(priv->dsi_host, device, &timings, 2,
  317. &dsi_stm_phy_ops);
  318. if (ret) {
  319. dev_err(dev, "failed to initialize mipi dsi host\n");
  320. return ret;
  321. }
  322. return 0;
  323. }
  324. static int stm32_dsi_set_backlight(struct udevice *dev, int percent)
  325. {
  326. struct stm32_dsi_priv *priv = dev_get_priv(dev);
  327. int ret;
  328. ret = panel_enable_backlight(priv->panel);
  329. if (ret) {
  330. dev_err(dev, "panel %s enable backlight error %d\n",
  331. priv->panel->name, ret);
  332. return ret;
  333. }
  334. ret = dsi_host_enable(priv->dsi_host);
  335. if (ret) {
  336. dev_err(dev, "failed to enable mipi dsi host\n");
  337. return ret;
  338. }
  339. return 0;
  340. }
  341. static int stm32_dsi_bind(struct udevice *dev)
  342. {
  343. int ret;
  344. ret = device_bind_driver_to_node(dev, "dw_mipi_dsi", "dsihost",
  345. dev_ofnode(dev), NULL);
  346. if (ret)
  347. return ret;
  348. return dm_scan_fdt_dev(dev);
  349. }
  350. static int stm32_dsi_probe(struct udevice *dev)
  351. {
  352. struct stm32_dsi_priv *priv = dev_get_priv(dev);
  353. struct mipi_dsi_device *device = &priv->device;
  354. struct reset_ctl rst;
  355. struct clk clk;
  356. int ret;
  357. device->dev = dev;
  358. priv->base = (void *)dev_read_addr(dev);
  359. if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
  360. dev_err(dev, "dsi dt register address error\n");
  361. return -EINVAL;
  362. }
  363. if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
  364. ret = device_get_supply_regulator(dev, "phy-dsi-supply",
  365. &priv->vdd_reg);
  366. if (ret && ret != -ENOENT) {
  367. dev_err(dev, "Warning: cannot get phy dsi supply\n");
  368. return -ENODEV;
  369. }
  370. if (ret != -ENOENT) {
  371. ret = regulator_set_enable(priv->vdd_reg, true);
  372. if (ret)
  373. return ret;
  374. }
  375. }
  376. ret = clk_get_by_name(device->dev, "pclk", &clk);
  377. if (ret) {
  378. dev_err(dev, "peripheral clock get error %d\n", ret);
  379. goto err_reg;
  380. }
  381. ret = clk_enable(&clk);
  382. if (ret) {
  383. dev_err(dev, "peripheral clock enable error %d\n", ret);
  384. goto err_reg;
  385. }
  386. ret = clk_get_by_name(dev, "ref", &clk);
  387. if (ret) {
  388. dev_err(dev, "pll reference clock get error %d\n", ret);
  389. goto err_clk;
  390. }
  391. priv->pllref_clk = (unsigned int)clk_get_rate(&clk);
  392. ret = reset_get_by_index(device->dev, 0, &rst);
  393. if (ret) {
  394. dev_err(dev, "missing dsi hardware reset\n");
  395. goto err_clk;
  396. }
  397. /* Reset */
  398. reset_deassert(&rst);
  399. /* check hardware version */
  400. priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION;
  401. if (priv->hw_version != HWVER_130 &&
  402. priv->hw_version != HWVER_131) {
  403. dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version);
  404. ret = -ENODEV;
  405. goto err_clk;
  406. }
  407. return 0;
  408. err_clk:
  409. clk_disable(&clk);
  410. err_reg:
  411. if (IS_ENABLED(CONFIG_DM_REGULATOR))
  412. regulator_set_enable(priv->vdd_reg, false);
  413. return ret;
  414. }
  415. struct video_bridge_ops stm32_dsi_ops = {
  416. .attach = stm32_dsi_attach,
  417. .set_backlight = stm32_dsi_set_backlight,
  418. };
  419. static const struct udevice_id stm32_dsi_ids[] = {
  420. { .compatible = "st,stm32-dsi"},
  421. { }
  422. };
  423. U_BOOT_DRIVER(stm32_dsi) = {
  424. .name = "stm32-display-dsi",
  425. .id = UCLASS_VIDEO_BRIDGE,
  426. .of_match = stm32_dsi_ids,
  427. .bind = stm32_dsi_bind,
  428. .probe = stm32_dsi_probe,
  429. .ops = &stm32_dsi_ops,
  430. .priv_auto_alloc_size = sizeof(struct stm32_dsi_priv),
  431. };