pinctrl_stm32.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <hwspinlock.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <asm/arch/gpio.h>
  11. #include <asm/gpio.h>
  12. #include <asm/io.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/lists.h>
  15. #include <dm/pinctrl.h>
  16. #include <linux/bitops.h>
  17. #include <linux/err.h>
  18. #include <linux/libfdt.h>
  19. #define MAX_PINS_ONE_IP 70
  20. #define MODE_BITS_MASK 3
  21. #define OSPEED_MASK 3
  22. #define PUPD_MASK 3
  23. #define OTYPE_MSK 1
  24. #define AFR_MASK 0xF
  25. struct stm32_pinctrl_priv {
  26. struct hwspinlock hws;
  27. int pinctrl_ngpios;
  28. struct list_head gpio_dev;
  29. };
  30. struct stm32_gpio_bank {
  31. struct udevice *gpio_dev;
  32. struct list_head list;
  33. };
  34. #ifndef CONFIG_SPL_BUILD
  35. static char pin_name[PINNAME_SIZE];
  36. #define PINMUX_MODE_COUNT 5
  37. static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
  38. "gpio input",
  39. "gpio output",
  40. "analog",
  41. "unknown",
  42. "alt function",
  43. };
  44. static const char * const pinmux_output[] = {
  45. [STM32_GPIO_PUPD_NO] = "bias-disable",
  46. [STM32_GPIO_PUPD_UP] = "bias-pull-up",
  47. [STM32_GPIO_PUPD_DOWN] = "bias-pull-down",
  48. };
  49. static const char * const pinmux_input[] = {
  50. [STM32_GPIO_OTYPE_PP] = "drive-push-pull",
  51. [STM32_GPIO_OTYPE_OD] = "drive-open-drain",
  52. };
  53. static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
  54. {
  55. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  56. struct stm32_gpio_regs *regs = priv->regs;
  57. u32 af;
  58. u32 alt_shift = (offset % 8) * 4;
  59. u32 alt_index = offset / 8;
  60. af = (readl(&regs->afr[alt_index]) &
  61. GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
  62. return af;
  63. }
  64. static int stm32_populate_gpio_dev_list(struct udevice *dev)
  65. {
  66. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  67. struct udevice *gpio_dev;
  68. struct udevice *child;
  69. struct stm32_gpio_bank *gpio_bank;
  70. int ret;
  71. /*
  72. * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
  73. * a list with all gpio device reference which belongs to the
  74. * current pin-controller. This list is used to find pin_name and
  75. * pin muxing
  76. */
  77. list_for_each_entry(child, &dev->child_head, sibling_node) {
  78. ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
  79. &gpio_dev);
  80. if (ret < 0)
  81. continue;
  82. gpio_bank = malloc(sizeof(*gpio_bank));
  83. if (!gpio_bank) {
  84. dev_err(dev, "Not enough memory\n");
  85. return -ENOMEM;
  86. }
  87. gpio_bank->gpio_dev = gpio_dev;
  88. list_add_tail(&gpio_bank->list, &priv->gpio_dev);
  89. }
  90. return 0;
  91. }
  92. static int stm32_pinctrl_get_pins_count(struct udevice *dev)
  93. {
  94. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  95. struct gpio_dev_priv *uc_priv;
  96. struct stm32_gpio_bank *gpio_bank;
  97. /*
  98. * if get_pins_count has already been executed once on this
  99. * pin-controller, no need to run it again
  100. */
  101. if (priv->pinctrl_ngpios)
  102. return priv->pinctrl_ngpios;
  103. if (list_empty(&priv->gpio_dev))
  104. stm32_populate_gpio_dev_list(dev);
  105. /*
  106. * walk through all banks to retrieve the pin-controller
  107. * pins number
  108. */
  109. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  110. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  111. priv->pinctrl_ngpios += uc_priv->gpio_count;
  112. }
  113. return priv->pinctrl_ngpios;
  114. }
  115. static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
  116. unsigned int selector,
  117. unsigned int *idx)
  118. {
  119. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  120. struct stm32_gpio_bank *gpio_bank;
  121. struct gpio_dev_priv *uc_priv;
  122. int pin_count = 0;
  123. if (list_empty(&priv->gpio_dev))
  124. stm32_populate_gpio_dev_list(dev);
  125. /* look up for the bank which owns the requested pin */
  126. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  127. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  128. if (selector < (pin_count + uc_priv->gpio_count)) {
  129. /*
  130. * we found the bank, convert pin selector to
  131. * gpio bank index
  132. */
  133. *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
  134. selector - pin_count);
  135. if (IS_ERR_VALUE(*idx))
  136. return NULL;
  137. return gpio_bank->gpio_dev;
  138. }
  139. pin_count += uc_priv->gpio_count;
  140. }
  141. return NULL;
  142. }
  143. static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
  144. unsigned int selector)
  145. {
  146. struct gpio_dev_priv *uc_priv;
  147. struct udevice *gpio_dev;
  148. unsigned int gpio_idx;
  149. /* look up for the bank which owns the requested pin */
  150. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  151. if (!gpio_dev) {
  152. snprintf(pin_name, PINNAME_SIZE, "Error");
  153. } else {
  154. uc_priv = dev_get_uclass_priv(gpio_dev);
  155. snprintf(pin_name, PINNAME_SIZE, "%s%d",
  156. uc_priv->bank_name,
  157. gpio_idx);
  158. }
  159. return pin_name;
  160. }
  161. static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
  162. unsigned int selector,
  163. char *buf,
  164. int size)
  165. {
  166. struct udevice *gpio_dev;
  167. struct stm32_gpio_priv *priv;
  168. const char *label;
  169. int mode;
  170. int af_num;
  171. unsigned int gpio_idx;
  172. u32 pupd, otype;
  173. /* look up for the bank which owns the requested pin */
  174. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  175. if (!gpio_dev)
  176. return -ENODEV;
  177. mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
  178. dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
  179. selector, gpio_idx, mode);
  180. priv = dev_get_priv(gpio_dev);
  181. switch (mode) {
  182. case GPIOF_UNKNOWN:
  183. /* should never happen */
  184. return -EINVAL;
  185. case GPIOF_UNUSED:
  186. snprintf(buf, size, "%s", pinmux_mode[mode]);
  187. break;
  188. case GPIOF_FUNC:
  189. af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
  190. snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
  191. break;
  192. case GPIOF_OUTPUT:
  193. pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) &
  194. PUPD_MASK;
  195. snprintf(buf, size, "%s %s %s",
  196. pinmux_mode[mode], pinmux_output[pupd],
  197. label ? label : "");
  198. break;
  199. case GPIOF_INPUT:
  200. otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
  201. snprintf(buf, size, "%s %s %s",
  202. pinmux_mode[mode], pinmux_input[otype],
  203. label ? label : "");
  204. break;
  205. }
  206. return 0;
  207. }
  208. #endif
  209. static int stm32_pinctrl_probe(struct udevice *dev)
  210. {
  211. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  212. int ret;
  213. INIT_LIST_HEAD(&priv->gpio_dev);
  214. /* hwspinlock property is optional, just log the error */
  215. ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
  216. if (ret)
  217. debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
  218. __func__, ret);
  219. return 0;
  220. }
  221. static int stm32_gpio_config(struct gpio_desc *desc,
  222. const struct stm32_gpio_ctl *ctl)
  223. {
  224. struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
  225. struct stm32_gpio_regs *regs = priv->regs;
  226. struct stm32_pinctrl_priv *ctrl_priv;
  227. int ret;
  228. u32 index;
  229. if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
  230. ctl->pupd > 2 || ctl->speed > 3)
  231. return -EINVAL;
  232. ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
  233. ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
  234. if (ret == -ETIME) {
  235. dev_err(desc->dev, "HWSpinlock timeout\n");
  236. return ret;
  237. }
  238. index = (desc->offset & 0x07) * 4;
  239. clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
  240. ctl->af << index);
  241. index = desc->offset * 2;
  242. clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
  243. ctl->mode << index);
  244. clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
  245. ctl->speed << index);
  246. clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
  247. index = desc->offset;
  248. clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
  249. hwspinlock_unlock(&ctrl_priv->hws);
  250. return 0;
  251. }
  252. static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
  253. {
  254. gpio_dsc->port = (port_pin & 0x1F000) >> 12;
  255. gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
  256. debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
  257. gpio_dsc->pin);
  258. return 0;
  259. }
  260. static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
  261. ofnode node)
  262. {
  263. gpio_fn &= 0x00FF;
  264. gpio_ctl->af = 0;
  265. switch (gpio_fn) {
  266. case 0:
  267. gpio_ctl->mode = STM32_GPIO_MODE_IN;
  268. break;
  269. case 1 ... 16:
  270. gpio_ctl->mode = STM32_GPIO_MODE_AF;
  271. gpio_ctl->af = gpio_fn - 1;
  272. break;
  273. case 17:
  274. gpio_ctl->mode = STM32_GPIO_MODE_AN;
  275. break;
  276. default:
  277. gpio_ctl->mode = STM32_GPIO_MODE_OUT;
  278. break;
  279. }
  280. gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
  281. if (ofnode_read_bool(node, "drive-open-drain"))
  282. gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
  283. else
  284. gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
  285. if (ofnode_read_bool(node, "bias-pull-up"))
  286. gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
  287. else if (ofnode_read_bool(node, "bias-pull-down"))
  288. gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
  289. else
  290. gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
  291. debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
  292. __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
  293. gpio_ctl->pupd);
  294. return 0;
  295. }
  296. static int stm32_pinctrl_config(ofnode node)
  297. {
  298. u32 pin_mux[MAX_PINS_ONE_IP];
  299. int rv, len;
  300. ofnode subnode;
  301. /*
  302. * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
  303. * usart1) of pin controller phandle "pinctrl-0"
  304. * */
  305. ofnode_for_each_subnode(subnode, node) {
  306. struct stm32_gpio_dsc gpio_dsc;
  307. struct stm32_gpio_ctl gpio_ctl;
  308. int i;
  309. rv = ofnode_read_size(subnode, "pinmux");
  310. if (rv < 0)
  311. return rv;
  312. len = rv / sizeof(pin_mux[0]);
  313. debug("%s: no of pinmux entries= %d\n", __func__, len);
  314. if (len > MAX_PINS_ONE_IP)
  315. return -EINVAL;
  316. rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
  317. if (rv < 0)
  318. return rv;
  319. for (i = 0; i < len; i++) {
  320. struct gpio_desc desc;
  321. debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
  322. prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
  323. prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
  324. rv = uclass_get_device_by_seq(UCLASS_GPIO,
  325. gpio_dsc.port,
  326. &desc.dev);
  327. if (rv)
  328. return rv;
  329. desc.offset = gpio_dsc.pin;
  330. rv = stm32_gpio_config(&desc, &gpio_ctl);
  331. debug("%s: rv = %d\n\n", __func__, rv);
  332. if (rv)
  333. return rv;
  334. }
  335. }
  336. return 0;
  337. }
  338. static int stm32_pinctrl_bind(struct udevice *dev)
  339. {
  340. ofnode node;
  341. const char *name;
  342. int ret;
  343. dev_for_each_subnode(node, dev) {
  344. debug("%s: bind %s\n", __func__, ofnode_get_name(node));
  345. ofnode_get_property(node, "gpio-controller", &ret);
  346. if (ret < 0)
  347. continue;
  348. /* Get the name of each gpio node */
  349. name = ofnode_get_name(node);
  350. if (!name)
  351. return -EINVAL;
  352. /* Bind each gpio node */
  353. ret = device_bind_driver_to_node(dev, "gpio_stm32",
  354. name, node, NULL);
  355. if (ret)
  356. return ret;
  357. debug("%s: bind %s\n", __func__, name);
  358. }
  359. return 0;
  360. }
  361. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  362. static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  363. {
  364. return stm32_pinctrl_config(dev_ofnode(config));
  365. }
  366. #else /* PINCTRL_FULL */
  367. static int stm32_pinctrl_set_state_simple(struct udevice *dev,
  368. struct udevice *periph)
  369. {
  370. const fdt32_t *list;
  371. uint32_t phandle;
  372. ofnode config_node;
  373. int size, i, ret;
  374. list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
  375. if (!list)
  376. return -EINVAL;
  377. debug("%s: periph->name = %s\n", __func__, periph->name);
  378. size /= sizeof(*list);
  379. for (i = 0; i < size; i++) {
  380. phandle = fdt32_to_cpu(*list++);
  381. config_node = ofnode_get_by_phandle(phandle);
  382. if (!ofnode_valid(config_node)) {
  383. pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
  384. return -EINVAL;
  385. }
  386. ret = stm32_pinctrl_config(config_node);
  387. if (ret)
  388. return ret;
  389. }
  390. return 0;
  391. }
  392. #endif /* PINCTRL_FULL */
  393. static struct pinctrl_ops stm32_pinctrl_ops = {
  394. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  395. .set_state = stm32_pinctrl_set_state,
  396. #else /* PINCTRL_FULL */
  397. .set_state_simple = stm32_pinctrl_set_state_simple,
  398. #endif /* PINCTRL_FULL */
  399. #ifndef CONFIG_SPL_BUILD
  400. .get_pin_name = stm32_pinctrl_get_pin_name,
  401. .get_pins_count = stm32_pinctrl_get_pins_count,
  402. .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
  403. #endif
  404. };
  405. static const struct udevice_id stm32_pinctrl_ids[] = {
  406. { .compatible = "st,stm32f429-pinctrl" },
  407. { .compatible = "st,stm32f469-pinctrl" },
  408. { .compatible = "st,stm32f746-pinctrl" },
  409. { .compatible = "st,stm32f769-pinctrl" },
  410. { .compatible = "st,stm32h743-pinctrl" },
  411. { .compatible = "st,stm32mp157-pinctrl" },
  412. { .compatible = "st,stm32mp157-z-pinctrl" },
  413. { }
  414. };
  415. U_BOOT_DRIVER(pinctrl_stm32) = {
  416. .name = "pinctrl_stm32",
  417. .id = UCLASS_PINCTRL,
  418. .of_match = stm32_pinctrl_ids,
  419. .ops = &stm32_pinctrl_ops,
  420. .bind = stm32_pinctrl_bind,
  421. .probe = stm32_pinctrl_probe,
  422. .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
  423. };