Green Wan
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edd9ad8194
riscv: cpu: Add callback to init each core
|
3 år sedan |
Brad Kim
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fb33eaa3a2
riscv: fix the wrong swap value register
|
3 år sedan |
Sean Anderson
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924de3216e
riscv: Add some comments to start.S
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3 år sedan |
Sean Anderson
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85768134b4
riscv: Ensure gp is NULL or points to valid data
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3 år sedan |
Sean Anderson
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309995b315
riscv: Consolidate fences into AMOs for available_harts_lock
|
3 år sedan |
Sean Anderson
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c41045411b
Revert "riscv: Clear pending interrupts before enabling IPIs"
|
3 år sedan |
Leo Yu-Chi Liang
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e491e15a3f
riscv: Fix linking error when building u-boot-spl with no SMP support
|
4 år sedan |
Sean Anderson
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9472630337
riscv: Clear pending interrupts before enabling IPIs
|
4 år sedan |
Atish Patra
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d4ea649f17
riscv: Provide a mechanism to fix DT for reserved memory
|
4 år sedan |
Bin Meng
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191636e448
riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL
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4 år sedan |
Bin Meng
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84dc9d2690
riscv: Merge unnecessary SMP ifdefs in start.S
|
4 år sedan |
Sean Anderson
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404339759e
riscv: Remove unnecessary instruction
|
4 år sedan |
Simon Glass
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941338725d
common: Move relocate_code() to init.h
|
4 år sedan |
Lukas Auer
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90ae281437
riscv: add option to wait for ack from secondary harts in smp functions
|
4 år sedan |
Rick Chen
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444c46413f
riscv: Fix clear bss loop in the start-up code
|
4 år sedan |
Marcus Comstedt
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f6cb427fdc
riscv: update fix_rela_dyn
|
4 år sedan |
Lukas Auer
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c7e1effb96
riscv: support SPL stack and global data relocation
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4 år sedan |
Lukas Auer
|
8c59f2023c
riscv: add SPL support
|
4 år sedan |
Lukas Auer
|
fbfd92bf9b
riscv: add run mode configuration for SPL
|
4 år sedan |
Bin Meng
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4d2583dba1
riscv: Access CSRs using CSR numbers
|
5 år sedan |
Rick Chen
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f9281b8905
riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled
|
5 år sedan |
Rick Chen
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bdce38965e
riscv: Introduce CONFIG_XIP to support booting from flash
|
5 år sedan |
Lukas Auer
|
8ac39e2974
riscv: hang if relocation of secondary harts fails
|
5 år sedan |
Lukas Auer
|
e043240252
riscv: do not rely on hart ID passed by previous boot stage
|
5 år sedan |
Lukas Auer
|
3dea63c844
riscv: add support for multi-hart systems
|
5 år sedan |
Lukas Auer
|
1446b26f76
riscv: save hart ID in register tp instead of s0
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5 år sedan |
Lukas Auer
|
2503ccc55f
riscv: delay initialization of caches and debug UART
|
5 år sedan |
Bin Meng
|
51ab4570f3
riscv: Save boot hart id to the global data
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5 år sedan |
Bin Meng
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4b3f5ed5ac
riscv: Move trap handler codes to mtrap.S
|
5 år sedan |
Rick Chen
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48cbf62460
riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
|
5 år sedan |