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@@ -113,6 +113,23 @@ config RISCV_SMODE
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endchoice
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+choice
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+ prompt "SPL Run Mode"
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+ default SPL_RISCV_MMODE
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+ depends on SPL
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+
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+config SPL_RISCV_MMODE
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+ bool "Machine"
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+ help
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+ Choose this option to build U-Boot SPL for RISC-V M-Mode.
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+
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+config SPL_RISCV_SMODE
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+ bool "Supervisor"
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+ help
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+ Choose this option to build U-Boot SPL for RISC-V S-Mode.
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+
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+endchoice
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+
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config RISCV_ISA_C
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bool "Emit compressed instructions"
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default y
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@@ -132,34 +149,40 @@ config 64BIT
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config SIFIVE_CLINT
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bool
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- depends on RISCV_MMODE
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+ depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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+ select SPL_REGMAP if SPL
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+ select SPL_SYSCON if SPL
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help
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The SiFive CLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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config ANDES_PLIC
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bool
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- depends on RISCV_MMODE
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+ depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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+ select SPL_REGMAP if SPL
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+ select SPL_SYSCON if SPL
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help
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The Andes PLIC block holds memory-mapped claim and pending registers
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associated with software interrupt.
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config ANDES_PLMT
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bool
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- depends on RISCV_MMODE
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+ depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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+ select SPL_REGMAP if SPL
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+ select SPL_SYSCON if SPL
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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config RISCV_RDTIME
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bool
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- default y if RISCV_SMODE
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+ default y if RISCV_SMODE || SPL_RISCV_SMODE
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help
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The provides the riscv_get_time() API that is implemented using the
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standard rdtime instruction. This is the case for S-mode U-Boot, and
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@@ -189,7 +212,7 @@ config NR_CPUS
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config SBI_IPI
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bool
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- default y if RISCV_SMODE
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+ default y if RISCV_SMODE || SPL_RISCV_SMODE
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depends on SMP
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config XIP
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