Browse Source

riscv: Clear pending interrupts before enabling IPIs

On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson 4 years ago
parent
commit
9472630337
1 changed files with 2 additions and 0 deletions
  1. 2 0
      arch/riscv/cpu/start.S

+ 2 - 0
arch/riscv/cpu/start.S

@@ -65,6 +65,8 @@ _start:
 #else
 	li	t0, SIE_SSIE
 #endif
+	/* Clear any pending IPIs */
+	csrc	MODE_PREFIX(ip), t0
 	csrs	MODE_PREFIX(ie), t0
 #endif