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@@ -12,28 +12,7 @@ struct uart_port {
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enum sh_clk_mode clk_mode; /* clock mode */
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};
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-#if defined(CONFIG_CPU_SH7706) || \
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- defined(CONFIG_CPU_SH7707) || \
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- defined(CONFIG_CPU_SH7708) || \
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- defined(CONFIG_CPU_SH7709)
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-# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
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-# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
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-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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-#elif defined(CONFIG_CPU_SH7705)
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-# define SCIF0 0xA4400000
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-# define SCIF2 0xA4410000
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-# define SCSMR_Ir 0xA44A0000
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-# define IRDA_SCIF SCIF0
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-# define SCPCR 0xA4000116
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-# define SCPDR 0xA4000136
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-
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-/* Set the clock source,
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- * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
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- * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
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- */
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-# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
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-#elif defined(CONFIG_CPU_SH7720) || \
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- defined(CONFIG_CPU_SH7721) || \
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+#if defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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@@ -51,12 +30,6 @@ struct uart_port {
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# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
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-#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
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-# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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-# define SCIF_ORER 0x0001 /* overrun error bit */
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-# define PACR 0xa4050100
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-# define PBCR 0xa4050102
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-# define SCSCR_INIT(port) 0x3B
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#elif defined(CONFIG_CPU_SH7722)
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# define PADR 0xA4050120
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# undef PSDR
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@@ -175,9 +148,7 @@ struct uart_port {
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#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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-#if defined(CONFIG_CPU_SH7705) || \
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- defined(CONFIG_CPU_SH7720) || \
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- defined(CONFIG_CPU_SH7721) || \
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+#if defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCIF_ORER 0x0200
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@@ -225,9 +196,7 @@ struct uart_port {
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#define SCxSR_ORER(port)\
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(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
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-#if defined(CONFIG_CPU_SH7705) || \
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- defined(CONFIG_CPU_SH7720) || \
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- defined(CONFIG_CPU_SH7721) || \
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+#if defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
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@@ -309,23 +278,9 @@ static inline void sci_##name##_out(struct uart_port *port,\
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SCI_OUT(sci_size, sci_offset, value);\
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}
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-#if defined(CONFIG_CPU_SH3) || \
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- defined(CONFIG_SH73A0) || \
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+#if defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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-#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
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-#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
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- sh4_sci_offset, sh4_sci_size, \
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- sh3_scif_offset, sh3_scif_size, \
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- sh4_scif_offset, sh4_scif_size, \
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- h8_sci_offset, h8_sci_size) \
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- CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
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- sh4_scif_offset, sh4_scif_size)
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-#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
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- sh4_scif_offset, sh4_scif_size) \
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- CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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-#elif defined(CONFIG_CPU_SH7705) || \
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- defined(CONFIG_CPU_SH7720) || \
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- defined(CONFIG_CPU_SH7721) || \
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+#if defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_SH73A0)
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#define SCIF_FNS(name, scif_offset, scif_size) \
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CPU_SCIF_FNS(name, scif_offset, scif_size)
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@@ -368,9 +323,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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#endif
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-#if defined(CONFIG_CPU_SH7705) || \
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- defined(CONFIG_CPU_SH7720) || \
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- defined(CONFIG_CPU_SH7721) || \
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+#if defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_SH73A0)
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SCIF_FNS(SCSMR, 0x00, 16)
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@@ -471,17 +424,7 @@ SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
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#define sci_in(port, reg) sci_##reg##_in(port)
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#define sci_out(port, reg, value) sci_##reg##_out(port, value)
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-#if defined(CONFIG_CPU_SH7706) || \
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- defined(CONFIG_CPU_SH7707) || \
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- defined(CONFIG_CPU_SH7708) || \
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- defined(CONFIG_CPU_SH7709)
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-static inline int sci_rxd_in(struct uart_port *port)
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-{
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- if (port->mapbase == 0xfffffe80)
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- return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
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- return 1;
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-}
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-#elif defined(CONFIG_CPU_SH7750) || \
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+#if defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7751R) || \
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defined(CONFIG_CPU_SH7750R) || \
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@@ -533,9 +476,7 @@ static inline int sci_rxd_in(struct uart_port *port)
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#if defined(CONFIG_CPU_SH7780)
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
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-#elif defined(CONFIG_CPU_SH7705) || \
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- defined(CONFIG_CPU_SH7720) || \
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- defined(CONFIG_CPU_SH7721) || \
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+#elif defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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