cpu_sh7706.h 987 B

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  1. #ifndef _ASM_CPU_SH7706_H_
  2. #define _ASM_CPU_SH7706_H_
  3. #define CACHE_OC_NUM_WAYS 4
  4. #define CCR_CACHE_INIT 0x0000000D
  5. /* MMU and Cache control */
  6. #define MMUCR 0xFFFFFFE0
  7. #define CCR 0xFFFFFFEC
  8. /* PFC */
  9. #define PACR 0xA4050100
  10. #define PBCR 0xA4050102
  11. #define PCCR 0xA4050104
  12. #define PETCR 0xA4050106
  13. /* Port Data Registers */
  14. #define PADR 0xA4050120
  15. #define PBDR 0xA4050122
  16. #define PCDR 0xA4050124
  17. /* BSC */
  18. #define FRQCR 0xffffff80
  19. #define BCR1 0xffffff60
  20. #define BCR2 0xffffff62
  21. #define WCR1 0xffffff64
  22. #define WCR2 0xffffff66
  23. #define MCR 0xffffff68
  24. /* SDRAM controller */
  25. #define DCR 0xffffff6a
  26. #define RTCSR 0xffffff6e
  27. #define RTCNT 0xffffff70
  28. #define RTCOR 0xffffff72
  29. #define RFCR 0xffffff74
  30. #define SDMR 0xFFFFD000
  31. #define CS3_R 0xFFFFE460
  32. /* SCIF */
  33. #define SCSMR_2 0xA4000150
  34. #define SCIF0_BASE SCSMR_2
  35. /* Timer */
  36. #define TMU_BASE 0xFFFFFE90
  37. /* On chip oscillator circuits */
  38. #define WTCNT 0xFFFFFF84
  39. #define WTCSR 0xFFFFFF86
  40. #endif /* _ASM_CPU_SH7706_H_ */