cpu_sh7710.h 1.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061
  1. #ifndef _ASM_CPU_SH7710_H_
  2. #define _ASM_CPU_SH7710_H_
  3. #define CACHE_OC_NUM_WAYS 4
  4. #define CCR_CACHE_INIT 0x0000000D
  5. /* MMU and Cache control */
  6. #define MMUCR 0xFFFFFFE0
  7. #define CCR 0xFFFFFFEC
  8. /* PFC */
  9. #define PACR 0xA4050100
  10. #define PBCR 0xA4050102
  11. #define PCCR 0xA4050104
  12. #define PETCR 0xA4050106
  13. /* Port Data Registers */
  14. #define PADR 0xA4050120
  15. #define PBDR 0xA4050122
  16. #define PCDR 0xA4050124
  17. /* BSC */
  18. #define CMNCR 0xA4FD0000
  19. #define CS0BCR 0xA4FD0004
  20. #define CS2BCR 0xA4FD0008
  21. #define CS3BCR 0xA4FD000C
  22. #define CS4BCR 0xA4FD0010
  23. #define CS5ABCR 0xA4FD0014
  24. #define CS5BBCR 0xA4FD0018
  25. #define CS6ABCR 0xA4FD001C
  26. #define CS6BBCR 0xA4FD0020
  27. #define CS0WCR 0xA4FD0024
  28. #define CS2WCR 0xA4FD0028
  29. #define CS3WCR 0xA4FD002C
  30. #define CS4WCR 0xA4FD0030
  31. #define CS5AWCR 0xA4FD0034
  32. #define CS5BWCR 0xA4FD0038
  33. #define CS6AWCR 0xA4FD003C
  34. #define CS6BWCR 0xA4FD0040
  35. /* SDRAM controller */
  36. #define SDCR 0xA4FD0044
  37. #define RTCSR 0xA4FD0048
  38. #define RTCNT 0xA4FD004C
  39. #define RTCOR 0xA4FD0050
  40. /* SCIF */
  41. #define SCSMR_0 0xA4400000
  42. #define SCIF0_BASE SCSMR_0
  43. #define SCSMR_0 0xA4410000
  44. #define SCIF1_BASE SCSMR_1
  45. /* Timer */
  46. #define TMU_BASE 0xA412FE90
  47. /* On chip oscillator circuits */
  48. #define FRQCR 0xA415FF80
  49. #define WTCNT 0xA415FF84
  50. #define WTCSR 0xA415FF86
  51. #endif /* _ASM_CPU_SH7710_H_ */