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@@ -10,58 +10,156 @@
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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- PM_SET_CONFIGURATION,
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- PM_GET_NODE_STATUS,
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- PM_GET_OPERATING_CHARACTERISTIC,
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- PM_REGISTER_NOTIFIER,
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- PM_REQUEST_SUSPEND,
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- PM_SELF_SUSPEND,
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- PM_FORCE_POWERDOWN,
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- PM_ABORT_SUSPEND,
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- PM_REQUEST_WAKEUP,
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- PM_SET_WAKEUP_SOURCE,
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- PM_SYSTEM_SHUTDOWN,
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- PM_REQUEST_NODE,
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- PM_RELEASE_NODE,
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- PM_SET_REQUIREMENT,
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- PM_SET_MAX_LATENCY,
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- PM_RESET_ASSERT,
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- PM_RESET_GET_STATUS,
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- PM_MMIO_WRITE,
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- PM_MMIO_READ,
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- PM_PM_INIT_FINALIZE,
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- PM_FPGA_LOAD,
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- PM_FPGA_GET_STATUS,
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- PM_GET_CHIPID,
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+ PM_SET_CONFIGURATION = 2,
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+ PM_GET_NODE_STATUS = 3,
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+ PM_GET_OPERATING_CHARACTERISTIC = 4,
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+ PM_REGISTER_NOTIFIER = 5,
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+ /* API for suspending */
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+ PM_REQUEST_SUSPEND = 6,
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+ PM_SELF_SUSPEND = 7,
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+ PM_FORCE_POWERDOWN = 8,
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+ PM_ABORT_SUSPEND = 9,
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+ PM_REQUEST_WAKEUP = 10,
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+ PM_SET_WAKEUP_SOURCE = 11,
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+ PM_SYSTEM_SHUTDOWN = 12,
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+ PM_REQUEST_NODE = 13,
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+ PM_RELEASE_NODE = 14,
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+ PM_SET_REQUIREMENT = 15,
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+ PM_SET_MAX_LATENCY = 16,
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+ /* Direct control API functions: */
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+ PM_RESET_ASSERT = 17,
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+ PM_RESET_GET_STATUS = 18,
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+ PM_MMIO_WRITE = 19,
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+ PM_MMIO_READ = 20,
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+ PM_PM_INIT_FINALIZE = 21,
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+ PM_FPGA_LOAD = 22,
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+ PM_FPGA_GET_STATUS = 23,
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+ PM_GET_CHIPID = 24,
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+ /* ID 25 is been used by U-boot to process secure boot images */
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+ /* Secure library generic API functions */
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PM_SECURE_SHA = 26,
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- PM_SECURE_RSA,
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- PM_PINCTRL_REQUEST,
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- PM_PINCTRL_RELEASE,
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- PM_PINCTRL_GET_FUNCTION,
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- PM_PINCTRL_SET_FUNCTION,
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- PM_PINCTRL_CONFIG_PARAM_GET,
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- PM_PINCTRL_CONFIG_PARAM_SET,
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- PM_IOCTL,
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- PM_QUERY_DATA,
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- PM_CLOCK_ENABLE,
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- PM_CLOCK_DISABLE,
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- PM_CLOCK_GETSTATE,
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- PM_CLOCK_SETDIVIDER,
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- PM_CLOCK_GETDIVIDER,
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- PM_CLOCK_SETRATE,
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- PM_CLOCK_GETRATE,
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- PM_CLOCK_SETPARENT,
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- PM_CLOCK_GETPARENT,
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- PM_SECURE_IMAGE,
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+ PM_SECURE_RSA = 27,
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+ PM_PINCTRL_REQUEST = 28,
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+ PM_PINCTRL_RELEASE = 29,
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+ PM_PINCTRL_GET_FUNCTION = 30,
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+ PM_PINCTRL_SET_FUNCTION = 31,
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+ PM_PINCTRL_CONFIG_PARAM_GET = 32,
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+ PM_PINCTRL_CONFIG_PARAM_SET = 33,
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+ PM_IOCTL = 34,
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+ PM_QUERY_DATA = 35,
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+ PM_CLOCK_ENABLE = 36,
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+ PM_CLOCK_DISABLE = 37,
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+ PM_CLOCK_GETSTATE = 38,
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+ PM_CLOCK_SETDIVIDER = 39,
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+ PM_CLOCK_GETDIVIDER = 40,
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+ PM_CLOCK_SETRATE = 41,
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+ PM_CLOCK_GETRATE = 42,
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+ PM_CLOCK_SETPARENT = 43,
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+ PM_CLOCK_GETPARENT = 44,
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+ PM_SECURE_IMAGE = 45,
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PM_FPGA_READ = 46,
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- PM_SECURE_AES,
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+ PM_SECURE_AES = 47,
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PM_CLOCK_PLL_GETPARAM = 49,
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+ /* PM_REGISTER_ACCESS API */
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PM_REGISTER_ACCESS = 52,
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- PM_EFUSE_ACCESS,
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+ PM_EFUSE_ACCESS = 53,
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PM_FEATURE_CHECK = 63,
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PM_API_MAX,
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};
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+enum pm_node_id {
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+ NODE_UNKNOWN = 0,
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+ NODE_APU = 1,
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+ NODE_APU_0 = 2,
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+ NODE_APU_1 = 3,
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+ NODE_APU_2 = 4,
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+ NODE_APU_3 = 5,
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+ NODE_RPU = 6,
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+ NODE_RPU_0 = 7,
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+ NODE_RPU_1 = 8,
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+ NODE_PLD = 9,
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+ NODE_FPD = 10,
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+ NODE_OCM_BANK_0 = 11,
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+ NODE_OCM_BANK_1 = 12,
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+ NODE_OCM_BANK_2 = 13,
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+ NODE_OCM_BANK_3 = 14,
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+ NODE_TCM_0_A = 15,
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+ NODE_TCM_0_B = 16,
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+ NODE_TCM_1_A = 17,
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+ NODE_TCM_1_B = 18,
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+ NODE_L2 = 19,
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+ NODE_GPU_PP_0 = 20,
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+ NODE_GPU_PP_1 = 21,
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+ NODE_USB_0 = 22,
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+ NODE_USB_1 = 23,
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+ NODE_TTC_0 = 24,
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+ NODE_TTC_1 = 25,
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+ NODE_TTC_2 = 26,
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+ NODE_TTC_3 = 27,
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+ NODE_SATA = 28,
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+ NODE_ETH_0 = 29,
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+ NODE_ETH_1 = 30,
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+ NODE_ETH_2 = 31,
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+ NODE_ETH_3 = 32,
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+ NODE_UART_0 = 33,
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+ NODE_UART_1 = 34,
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+ NODE_SPI_0 = 35,
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+ NODE_SPI_1 = 36,
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+ NODE_I2C_0 = 37,
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+ NODE_I2C_1 = 38,
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+ NODE_SD_0 = 39,
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+ NODE_SD_1 = 40,
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+ NODE_DP = 41,
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+ NODE_GDMA = 42,
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+ NODE_ADMA = 43,
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+ NODE_NAND = 44,
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+ NODE_QSPI = 45,
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+ NODE_GPIO = 46,
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+ NODE_CAN_0 = 47,
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+ NODE_CAN_1 = 48,
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+ NODE_EXTERN = 49,
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+ NODE_APLL = 50,
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+ NODE_VPLL = 51,
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+ NODE_DPLL = 52,
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+ NODE_RPLL = 53,
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+ NODE_IOPLL = 54,
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+ NODE_DDR = 55,
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+ NODE_IPI_APU = 56,
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+ NODE_IPI_RPU_0 = 57,
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+ NODE_GPU = 58,
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+ NODE_PCIE = 59,
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+ NODE_PCAP = 60,
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+ NODE_RTC = 61,
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+ NODE_LPD = 62,
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+ NODE_VCU = 63,
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+ NODE_IPI_RPU_1 = 64,
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+ NODE_IPI_PL_0 = 65,
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+ NODE_IPI_PL_1 = 66,
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+ NODE_IPI_PL_2 = 67,
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+ NODE_IPI_PL_3 = 68,
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+ NODE_PL = 69,
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+ NODE_GEM_TSU = 70,
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+ NODE_SWDT_0 = 71,
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+ NODE_SWDT_1 = 72,
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+ NODE_CSU = 73,
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+ NODE_PJTAG = 74,
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+ NODE_TRACE = 75,
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+ NODE_TESTSCAN = 76,
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+ NODE_PMU = 77,
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+ NODE_MAX = 78,
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+};
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+
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+enum tap_delay_type {
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+ PM_TAPDELAY_INPUT = 0,
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+ PM_TAPDELAY_OUTPUT = 1,
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+};
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+
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+enum dll_reset_type {
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+ PM_DLL_RESET_ASSERT = 0,
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+ PM_DLL_RESET_RELEASE = 1,
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+ PM_DLL_RESET_PULSE = 2,
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+};
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+
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enum pm_query_id {
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PM_QID_INVALID = 0,
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PM_QID_CLOCK_GET_NAME = 1,
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@@ -79,6 +177,171 @@ enum pm_query_id {
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PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
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};
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+enum zynqmp_pm_reset_action {
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+ PM_RESET_ACTION_RELEASE = 0,
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+ PM_RESET_ACTION_ASSERT = 1,
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+ PM_RESET_ACTION_PULSE = 2,
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+};
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+
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+enum zynqmp_pm_reset {
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+ ZYNQMP_PM_RESET_START = 1000,
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+ ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
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+ ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
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+ ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
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+ ZYNQMP_PM_RESET_DP = 1003,
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+ ZYNQMP_PM_RESET_SWDT_CRF = 1004,
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+ ZYNQMP_PM_RESET_AFI_FM5 = 1005,
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+ ZYNQMP_PM_RESET_AFI_FM4 = 1006,
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+ ZYNQMP_PM_RESET_AFI_FM3 = 1007,
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+ ZYNQMP_PM_RESET_AFI_FM2 = 1008,
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+ ZYNQMP_PM_RESET_AFI_FM1 = 1009,
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+ ZYNQMP_PM_RESET_AFI_FM0 = 1010,
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+ ZYNQMP_PM_RESET_GDMA = 1011,
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+ ZYNQMP_PM_RESET_GPU_PP1 = 1012,
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+ ZYNQMP_PM_RESET_GPU_PP0 = 1013,
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+ ZYNQMP_PM_RESET_GPU = 1014,
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+ ZYNQMP_PM_RESET_GT = 1015,
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+ ZYNQMP_PM_RESET_SATA = 1016,
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+ ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
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+ ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
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+ ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
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+ ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
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+ ZYNQMP_PM_RESET_APU_L2 = 1021,
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+ ZYNQMP_PM_RESET_ACPU3 = 1022,
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+ ZYNQMP_PM_RESET_ACPU2 = 1023,
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+ ZYNQMP_PM_RESET_ACPU1 = 1024,
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+ ZYNQMP_PM_RESET_ACPU0 = 1025,
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+ ZYNQMP_PM_RESET_DDR = 1026,
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+ ZYNQMP_PM_RESET_APM_FPD = 1027,
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+ ZYNQMP_PM_RESET_SOFT = 1028,
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+ ZYNQMP_PM_RESET_GEM0 = 1029,
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+ ZYNQMP_PM_RESET_GEM1 = 1030,
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+ ZYNQMP_PM_RESET_GEM2 = 1031,
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+ ZYNQMP_PM_RESET_GEM3 = 1032,
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+ ZYNQMP_PM_RESET_QSPI = 1033,
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+ ZYNQMP_PM_RESET_UART0 = 1034,
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+ ZYNQMP_PM_RESET_UART1 = 1035,
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+ ZYNQMP_PM_RESET_SPI0 = 1036,
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+ ZYNQMP_PM_RESET_SPI1 = 1037,
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+ ZYNQMP_PM_RESET_SDIO0 = 1038,
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+ ZYNQMP_PM_RESET_SDIO1 = 1039,
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+ ZYNQMP_PM_RESET_CAN0 = 1040,
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+ ZYNQMP_PM_RESET_CAN1 = 1041,
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+ ZYNQMP_PM_RESET_I2C0 = 1042,
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+ ZYNQMP_PM_RESET_I2C1 = 1043,
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+ ZYNQMP_PM_RESET_TTC0 = 1044,
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+ ZYNQMP_PM_RESET_TTC1 = 1045,
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+ ZYNQMP_PM_RESET_TTC2 = 1046,
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+ ZYNQMP_PM_RESET_TTC3 = 1047,
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+ ZYNQMP_PM_RESET_SWDT_CRL = 1048,
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+ ZYNQMP_PM_RESET_NAND = 1049,
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+ ZYNQMP_PM_RESET_ADMA = 1050,
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+ ZYNQMP_PM_RESET_GPIO = 1051,
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+ ZYNQMP_PM_RESET_IOU_CC = 1052,
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+ ZYNQMP_PM_RESET_TIMESTAMP = 1053,
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+ ZYNQMP_PM_RESET_RPU_R50 = 1054,
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+ ZYNQMP_PM_RESET_RPU_R51 = 1055,
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+ ZYNQMP_PM_RESET_RPU_AMBA = 1056,
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+ ZYNQMP_PM_RESET_OCM = 1057,
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+ ZYNQMP_PM_RESET_RPU_PGE = 1058,
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+ ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
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+ ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
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+ ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
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+ ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
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+ ZYNQMP_PM_RESET_USB0_APB = 1063,
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+ ZYNQMP_PM_RESET_USB1_APB = 1064,
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+ ZYNQMP_PM_RESET_IPI = 1065,
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+ ZYNQMP_PM_RESET_APM_LPD = 1066,
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+ ZYNQMP_PM_RESET_RTC = 1067,
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+ ZYNQMP_PM_RESET_SYSMON = 1068,
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+ ZYNQMP_PM_RESET_AFI_FM6 = 1069,
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+ ZYNQMP_PM_RESET_LPD_SWDT = 1070,
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+ ZYNQMP_PM_RESET_FPD = 1071,
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+ ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
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+ ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
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+ ZYNQMP_PM_RESET_DBG_LPD = 1074,
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+ ZYNQMP_PM_RESET_DBG_FPD = 1075,
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+ ZYNQMP_PM_RESET_APLL = 1076,
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+ ZYNQMP_PM_RESET_DPLL = 1077,
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+ ZYNQMP_PM_RESET_VPLL = 1078,
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+ ZYNQMP_PM_RESET_IOPLL = 1079,
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+ ZYNQMP_PM_RESET_RPLL = 1080,
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+ ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
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+ ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
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+ ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
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+ ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
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+ ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
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+ ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
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+ ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
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+ ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
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+ ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
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+ ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
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+ ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
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+ ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
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+ ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
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+ ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
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+ ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
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+ ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
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+ ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
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+ ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
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+ ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
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+ ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
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+ ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
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+ ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
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+ ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
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+ ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
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+ ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
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+ ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
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+ ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
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+ ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
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+ ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
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+ ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
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+ ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
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+ ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
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+ ZYNQMP_PM_RESET_RPU_LS = 1113,
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+ ZYNQMP_PM_RESET_PS_ONLY = 1114,
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+ ZYNQMP_PM_RESET_PL = 1115,
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+ ZYNQMP_PM_RESET_PS_PL0 = 1116,
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+ ZYNQMP_PM_RESET_PS_PL1 = 1117,
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+ ZYNQMP_PM_RESET_PS_PL2 = 1118,
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+ ZYNQMP_PM_RESET_PS_PL3 = 1119,
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+ ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
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+};
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+
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+enum pm_ioctl_id {
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+ IOCTL_GET_RPU_OPER_MODE = 0,
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+ IOCTL_SET_RPU_OPER_MODE = 1,
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+ IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
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+ IOCTL_TCM_COMB_CONFIG = 3,
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+ IOCTL_SET_TAPDELAY_BYPASS = 4,
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+ IOCTL_SET_SGMII_MODE = 5,
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+ IOCTL_SD_DLL_RESET = 6,
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+ IOCTL_SET_SD_TAPDELAY = 7,
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+ IOCTL_SET_PLL_FRAC_MODE = 8,
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+ IOCTL_GET_PLL_FRAC_MODE = 9,
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+ IOCTL_SET_PLL_FRAC_DATA = 10,
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+ IOCTL_GET_PLL_FRAC_DATA = 11,
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+ IOCTL_WRITE_GGS = 12,
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+ IOCTL_READ_GGS = 13,
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+ IOCTL_WRITE_PGGS = 14,
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+ IOCTL_READ_PGGS = 15,
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+ /* IOCTL for ULPI reset */
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+ IOCTL_ULPI_RESET = 16,
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+ /* Set healthy bit value*/
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+ IOCTL_SET_BOOT_HEALTH_STATUS = 17,
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+ IOCTL_AFI = 18,
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|
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+ /* Probe counter read/write */
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+ IOCTL_PROBE_COUNTER_READ = 19,
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+ IOCTL_PROBE_COUNTER_WRITE = 20,
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+ IOCTL_OSPI_MUX_SELECT = 21,
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+ /* IOCTL for USB power request */
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+ IOCTL_USB_SET_STATE = 22,
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+ /* IOCTL to get last reset reason */
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+ IOCTL_GET_LAST_RESET_REASON = 23,
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+ /* AIE ISR Clear */
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+ IOCTL_AIE_ISR_CLEAR = 24,
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+};
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+
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#define PM_SIP_SVC 0xc2000000
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#define ZYNQMP_PM_VERSION_MAJOR 1
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