zynqmp-sck-kv-g-revA.dts 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * dts file for KV260 revA Carrier Card
  4. *
  5. * (C) Copyright 2020 - 2021, Xilinx, Inc.
  6. *
  7. * SD level shifter:
  8. * "A" – A01 board un-modified (NXP)
  9. * "Y" – A01 board modified with legacy interposer (Nexperia)
  10. * "Z" – A01 board modified with Diode interposer
  11. *
  12. * Michal Simek <michal.simek@xilinx.com>
  13. */
  14. #include <dt-bindings/gpio/gpio.h>
  15. #include <dt-bindings/net/ti-dp83867.h>
  16. #include <dt-bindings/phy/phy.h>
  17. #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  18. /dts-v1/;
  19. /plugin/;
  20. &{/} {
  21. compatible = "xlnx,zynqmp-sk-kv260-revA",
  22. "xlnx,zynqmp-sk-kv260-revY",
  23. "xlnx,zynqmp-sk-kv260-revZ",
  24. "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
  25. };
  26. &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. pinctrl-names = "default", "gpio";
  30. pinctrl-0 = <&pinctrl_i2c1_default>;
  31. pinctrl-1 = <&pinctrl_i2c1_gpio>;
  32. scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
  33. sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
  34. u14: ina260@40 { /* u14 */
  35. compatible = "ti,ina260";
  36. #io-channel-cells = <1>;
  37. label = "ina260-u14";
  38. reg = <0x40>;
  39. };
  40. /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
  41. };
  42. &amba {
  43. ina260-u14 {
  44. compatible = "iio-hwmon";
  45. io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
  46. };
  47. si5332_0: si5332_0 { /* u17 */
  48. compatible = "fixed-clock";
  49. #clock-cells = <0>;
  50. clock-frequency = <125000000>;
  51. };
  52. si5332_1: si5332_1 { /* u17 */
  53. compatible = "fixed-clock";
  54. #clock-cells = <0>;
  55. clock-frequency = <25000000>;
  56. };
  57. si5332_2: si5332_2 { /* u17 */
  58. compatible = "fixed-clock";
  59. #clock-cells = <0>;
  60. clock-frequency = <48000000>;
  61. };
  62. si5332_3: si5332_3 { /* u17 */
  63. compatible = "fixed-clock";
  64. #clock-cells = <0>;
  65. clock-frequency = <24000000>;
  66. };
  67. si5332_4: si5332_4 { /* u17 */
  68. compatible = "fixed-clock";
  69. #clock-cells = <0>;
  70. clock-frequency = <26000000>;
  71. };
  72. si5332_5: si5332_5 { /* u17 */
  73. compatible = "fixed-clock";
  74. #clock-cells = <0>;
  75. clock-frequency = <27000000>;
  76. };
  77. };
  78. /* DP/USB 3.0 and SATA */
  79. &psgtr {
  80. status = "okay";
  81. /* pcie, usb3, sata */
  82. clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
  83. clock-names = "ref0", "ref1", "ref2";
  84. };
  85. &sata {
  86. status = "okay";
  87. /* SATA OOB timing settings */
  88. ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  89. ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  90. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  91. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  92. ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  93. ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  94. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  95. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  96. phy-names = "sata-phy";
  97. phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
  98. };
  99. &zynqmp_dpsub {
  100. status = "disabled";
  101. phy-names = "dp-phy0", "dp-phy1";
  102. phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
  103. };
  104. &zynqmp_dpdma {
  105. status = "okay";
  106. };
  107. &usb0 {
  108. status = "okay";
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_usb0_default>;
  111. phy-names = "usb3-phy";
  112. phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
  113. usbhub: usb5744 { /* u43 */
  114. compatible = "microchip,usb5744";
  115. reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
  116. };
  117. };
  118. &dwc3_0 {
  119. status = "okay";
  120. dr_mode = "host";
  121. snps,usb3_lpm_capable;
  122. maximum-speed = "super-speed";
  123. };
  124. &sdhci1 { /* on CC with tuned parameters */
  125. status = "okay";
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&pinctrl_sdhci1_default>;
  128. /*
  129. * SD 3.0 requires level shifter and this property
  130. * should be removed if the board has level shifter and
  131. * need to work in UHS mode
  132. */
  133. no-1-8-v;
  134. disable-wp;
  135. xlnx,mio-bank = <1>;
  136. };
  137. &gem3 { /* required by spec */
  138. status = "okay";
  139. pinctrl-names = "default";
  140. pinctrl-0 = <&pinctrl_gem3_default>;
  141. phy-handle = <&phy0>;
  142. phy-mode = "rgmii-id";
  143. mdio: mdio {
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
  147. reset-delay-us = <2>;
  148. phy0: ethernet-phy@1 {
  149. #phy-cells = <1>;
  150. reg = <1>;
  151. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  152. ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
  153. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  154. ti,dp83867-rxctrl-strap-quirk;
  155. };
  156. };
  157. };
  158. &pinctrl0 { /* required by spec */
  159. status = "okay";
  160. pinctrl_uart1_default: uart1-default {
  161. conf {
  162. groups = "uart1_9_grp";
  163. slew-rate = <SLEW_RATE_SLOW>;
  164. power-source = <IO_STANDARD_LVCMOS18>;
  165. drive-strength = <12>;
  166. };
  167. conf-rx {
  168. pins = "MIO37";
  169. bias-high-impedance;
  170. };
  171. conf-tx {
  172. pins = "MIO36";
  173. bias-disable;
  174. };
  175. mux {
  176. groups = "uart1_9_grp";
  177. function = "uart1";
  178. };
  179. };
  180. pinctrl_i2c1_default: i2c1-default {
  181. conf {
  182. groups = "i2c1_6_grp";
  183. bias-pull-up;
  184. slew-rate = <SLEW_RATE_SLOW>;
  185. power-source = <IO_STANDARD_LVCMOS18>;
  186. };
  187. mux {
  188. groups = "i2c1_6_grp";
  189. function = "i2c1";
  190. };
  191. };
  192. pinctrl_i2c1_gpio: i2c1-gpio {
  193. conf {
  194. groups = "gpio0_24_grp", "gpio0_25_grp";
  195. slew-rate = <SLEW_RATE_SLOW>;
  196. power-source = <IO_STANDARD_LVCMOS18>;
  197. };
  198. mux {
  199. groups = "gpio0_24_grp", "gpio0_25_grp";
  200. function = "gpio0";
  201. };
  202. };
  203. pinctrl_gem3_default: gem3-default {
  204. conf {
  205. groups = "ethernet3_0_grp";
  206. slew-rate = <SLEW_RATE_SLOW>;
  207. power-source = <IO_STANDARD_LVCMOS18>;
  208. };
  209. conf-rx {
  210. pins = "MIO70", "MIO72", "MIO74";
  211. bias-high-impedance;
  212. low-power-disable;
  213. };
  214. conf-bootstrap {
  215. pins = "MIO71", "MIO73", "MIO75";
  216. bias-disable;
  217. low-power-disable;
  218. };
  219. conf-tx {
  220. pins = "MIO64", "MIO65", "MIO66",
  221. "MIO67", "MIO68", "MIO69";
  222. bias-disable;
  223. low-power-enable;
  224. };
  225. conf-mdio {
  226. groups = "mdio3_0_grp";
  227. slew-rate = <SLEW_RATE_SLOW>;
  228. power-source = <IO_STANDARD_LVCMOS18>;
  229. bias-disable;
  230. };
  231. mux-mdio {
  232. function = "mdio3";
  233. groups = "mdio3_0_grp";
  234. };
  235. mux {
  236. function = "ethernet3";
  237. groups = "ethernet3_0_grp";
  238. };
  239. };
  240. pinctrl_usb0_default: usb0-default {
  241. conf {
  242. groups = "usb0_0_grp";
  243. slew-rate = <SLEW_RATE_SLOW>;
  244. power-source = <IO_STANDARD_LVCMOS18>;
  245. };
  246. conf-rx {
  247. pins = "MIO52", "MIO53", "MIO55";
  248. bias-high-impedance;
  249. };
  250. conf-tx {
  251. pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  252. "MIO60", "MIO61", "MIO62", "MIO63";
  253. bias-disable;
  254. };
  255. mux {
  256. groups = "usb0_0_grp";
  257. function = "usb0";
  258. };
  259. };
  260. pinctrl_sdhci1_default: sdhci1-default {
  261. conf {
  262. groups = "sdio1_0_grp";
  263. slew-rate = <SLEW_RATE_SLOW>;
  264. power-source = <IO_STANDARD_LVCMOS18>;
  265. bias-disable;
  266. };
  267. conf-cd {
  268. groups = "sdio1_cd_0_grp";
  269. bias-high-impedance;
  270. bias-pull-up;
  271. slew-rate = <SLEW_RATE_SLOW>;
  272. power-source = <IO_STANDARD_LVCMOS18>;
  273. };
  274. mux-cd {
  275. groups = "sdio1_cd_0_grp";
  276. function = "sdio1_cd";
  277. };
  278. mux {
  279. groups = "sdio1_0_grp";
  280. function = "sdio1";
  281. };
  282. };
  283. };
  284. &uart1 {
  285. status = "okay";
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_uart1_default>;
  288. };