zynq_sdhci.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <linux/delay.h>
  12. #include "mmc_private.h"
  13. #include <log.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/err.h>
  16. #include <linux/libfdt.h>
  17. #include <asm/cache.h>
  18. #include <malloc.h>
  19. #include <sdhci.h>
  20. #include <zynqmp_firmware.h>
  21. #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
  22. #define SDHCI_ARASAN_ITAPDLY_SEL_MASK GENMASK(7, 0)
  23. #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
  24. #define SDHCI_ARASAN_OTAPDLY_SEL_MASK GENMASK(5, 0)
  25. #define SDHCI_ITAPDLY_CHGWIN BIT(9)
  26. #define SDHCI_ITAPDLY_ENABLE BIT(8)
  27. #define SDHCI_OTAPDLY_ENABLE BIT(6)
  28. #define SDHCI_TUNING_LOOP_COUNT 40
  29. #define MMC_BANK2 0x2
  30. #define SD_DLL_CTRL 0xFF180358
  31. #define SD_ITAP_DLY 0xFF180314
  32. #define SD_OTAP_DLY 0xFF180318
  33. #define SD0_DLL_RST BIT(2)
  34. #define SD1_DLL_RST BIT(18)
  35. #define SD0_ITAPCHGWIN BIT(9)
  36. #define SD1_ITAPCHGWIN BIT(25)
  37. #define SD0_ITAPDLYENA BIT(8)
  38. #define SD1_ITAPDLYENA BIT(24)
  39. #define SD0_ITAPDLYSEL_MASK GENMASK(7, 0)
  40. #define SD1_ITAPDLYSEL_MASK GENMASK(23, 16)
  41. #define SD0_OTAPDLYSEL_MASK GENMASK(5, 0)
  42. #define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
  43. struct arasan_sdhci_clk_data {
  44. int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  45. int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  46. };
  47. struct arasan_sdhci_plat {
  48. struct mmc_config cfg;
  49. struct mmc mmc;
  50. };
  51. struct arasan_sdhci_priv {
  52. struct sdhci_host *host;
  53. struct arasan_sdhci_clk_data clk_data;
  54. u8 deviceid;
  55. u8 bank;
  56. u8 no_1p8;
  57. };
  58. /* For Versal platforms zynqmp_mmio_write() won't be available */
  59. __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
  60. {
  61. return 0;
  62. }
  63. #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  64. /* Default settings for ZynqMP Clock Phases */
  65. static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
  66. 0, 183, 54, 0, 0};
  67. static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
  68. 135, 48, 72, 135, 0};
  69. /* Default settings for Versal Clock Phases */
  70. static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
  71. 0, 0, 162, 90, 0, 0};
  72. static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
  73. 90, 36, 60, 90, 0};
  74. static const u8 mode2timing[] = {
  75. [MMC_LEGACY] = MMC_TIMING_LEGACY,
  76. [MMC_HS] = MMC_TIMING_MMC_HS,
  77. [SD_HS] = MMC_TIMING_SD_HS,
  78. [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
  79. [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
  80. [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
  81. [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
  82. [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
  83. [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
  84. [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
  85. [MMC_HS_200] = MMC_TIMING_MMC_HS200,
  86. };
  87. static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
  88. {
  89. int ret;
  90. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
  91. if (node_id == NODE_SD_0) {
  92. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
  93. SD0_ITAPCHGWIN);
  94. if (ret)
  95. return ret;
  96. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
  97. SD0_ITAPDLYENA);
  98. if (ret)
  99. return ret;
  100. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
  101. itap_delay);
  102. if (ret)
  103. return ret;
  104. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
  105. if (ret)
  106. return ret;
  107. }
  108. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
  109. SD1_ITAPCHGWIN);
  110. if (ret)
  111. return ret;
  112. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
  113. SD1_ITAPDLYENA);
  114. if (ret)
  115. return ret;
  116. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
  117. (itap_delay << 16));
  118. if (ret)
  119. return ret;
  120. ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
  121. if (ret)
  122. return ret;
  123. } else {
  124. return xilinx_pm_request(PM_IOCTL, (u32)node_id,
  125. IOCTL_SET_SD_TAPDELAY,
  126. PM_TAPDELAY_INPUT, itap_delay, NULL);
  127. }
  128. return 0;
  129. }
  130. static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
  131. {
  132. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
  133. if (node_id == NODE_SD_0)
  134. return zynqmp_mmio_write(SD_OTAP_DLY,
  135. SD0_OTAPDLYSEL_MASK,
  136. otap_delay);
  137. return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
  138. (otap_delay << 16));
  139. } else {
  140. return xilinx_pm_request(PM_IOCTL, (u32)node_id,
  141. IOCTL_SET_SD_TAPDELAY,
  142. PM_TAPDELAY_OUTPUT, otap_delay, NULL);
  143. }
  144. }
  145. static inline int zynqmp_dll_reset(u8 node_id, u32 type)
  146. {
  147. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
  148. if (node_id == NODE_SD_0)
  149. return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
  150. type == PM_DLL_RESET_ASSERT ?
  151. SD0_DLL_RST : 0);
  152. return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
  153. type == PM_DLL_RESET_ASSERT ?
  154. SD1_DLL_RST : 0);
  155. } else {
  156. return xilinx_pm_request(PM_IOCTL, (u32)node_id,
  157. IOCTL_SD_DLL_RESET, type, 0, NULL);
  158. }
  159. }
  160. static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id)
  161. {
  162. struct mmc *mmc = (struct mmc *)host->mmc;
  163. struct udevice *dev = mmc->dev;
  164. unsigned long timeout;
  165. int ret;
  166. u16 clk;
  167. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  168. clk &= ~(SDHCI_CLOCK_CARD_EN);
  169. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  170. /* Issue DLL Reset */
  171. ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
  172. if (ret) {
  173. dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
  174. return ret;
  175. }
  176. /* Allow atleast 1ms delay for proper DLL reset */
  177. mdelay(1);
  178. ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
  179. if (ret) {
  180. dev_err(dev, "dll_reset release failed with err: %d\n", ret);
  181. return ret;
  182. }
  183. /* Wait max 20 ms */
  184. timeout = 100;
  185. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  186. & SDHCI_CLOCK_INT_STABLE)) {
  187. if (timeout == 0) {
  188. dev_err(dev, ": Internal clock never stabilised.\n");
  189. return -EBUSY;
  190. }
  191. timeout--;
  192. udelay(1000);
  193. }
  194. clk |= SDHCI_CLOCK_CARD_EN;
  195. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  196. return 0;
  197. }
  198. static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  199. {
  200. struct mmc_cmd cmd;
  201. struct mmc_data data;
  202. u32 ctrl;
  203. struct sdhci_host *host;
  204. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  205. char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  206. u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
  207. debug("%s\n", __func__);
  208. host = priv->host;
  209. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  210. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  211. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  212. mdelay(1);
  213. arasan_zynqmp_dll_reset(host, node_id);
  214. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  215. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  216. do {
  217. cmd.cmdidx = opcode;
  218. cmd.resp_type = MMC_RSP_R1;
  219. cmd.cmdarg = 0;
  220. data.blocksize = 64;
  221. data.blocks = 1;
  222. data.flags = MMC_DATA_READ;
  223. if (tuning_loop_counter-- == 0)
  224. break;
  225. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  226. mmc->bus_width == 8)
  227. data.blocksize = 128;
  228. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  229. data.blocksize),
  230. SDHCI_BLOCK_SIZE);
  231. sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  232. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  233. mmc_send_cmd(mmc, &cmd, NULL);
  234. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  235. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  236. udelay(1);
  237. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  238. if (tuning_loop_counter < 0) {
  239. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  240. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  241. }
  242. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  243. printf("%s:Tuning failed\n", __func__);
  244. return -1;
  245. }
  246. udelay(1);
  247. arasan_zynqmp_dll_reset(host, node_id);
  248. /* Enable only interrupts served by the SD controller */
  249. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  250. SDHCI_INT_ENABLE);
  251. /* Mask all sdhci interrupt sources */
  252. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  253. return 0;
  254. }
  255. /**
  256. * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
  257. *
  258. * @host: Pointer to the sdhci_host structure.
  259. * @degrees: The clock phase shift between 0 - 359.
  260. * Return: 0
  261. *
  262. * Set the SD Output Clock Tap Delays for Output path
  263. */
  264. static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
  265. int degrees)
  266. {
  267. struct mmc *mmc = (struct mmc *)host->mmc;
  268. struct udevice *dev = mmc->dev;
  269. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  270. u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
  271. u8 tap_delay, tap_max = 0;
  272. int timing = mode2timing[mmc->selected_mode];
  273. int ret;
  274. /*
  275. * This is applicable for SDHCI_SPEC_300 and above
  276. * ZynqMP does not set phase for <=25MHz clock.
  277. * If degrees is zero, no need to do anything.
  278. */
  279. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
  280. return 0;
  281. switch (timing) {
  282. case MMC_TIMING_MMC_HS:
  283. case MMC_TIMING_SD_HS:
  284. case MMC_TIMING_UHS_SDR25:
  285. case MMC_TIMING_UHS_DDR50:
  286. case MMC_TIMING_MMC_DDR52:
  287. /* For 50MHz clock, 30 Taps are available */
  288. tap_max = 30;
  289. break;
  290. case MMC_TIMING_UHS_SDR50:
  291. /* For 100MHz clock, 15 Taps are available */
  292. tap_max = 15;
  293. break;
  294. case MMC_TIMING_UHS_SDR104:
  295. case MMC_TIMING_MMC_HS200:
  296. /* For 200MHz clock, 8 Taps are available */
  297. tap_max = 8;
  298. default:
  299. break;
  300. }
  301. tap_delay = (degrees * tap_max) / 360;
  302. /* Limit output tap_delay value to 6 bits */
  303. tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
  304. /* Set the Clock Phase */
  305. ret = arasan_zynqmp_set_out_tapdelay(node_id, tap_delay);
  306. if (ret) {
  307. dev_err(dev, "Error setting output Tap Delay\n");
  308. return ret;
  309. }
  310. /* Release DLL Reset */
  311. ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
  312. if (ret) {
  313. dev_err(dev, "dll_reset release failed with err: %d\n", ret);
  314. return ret;
  315. }
  316. return 0;
  317. }
  318. /**
  319. * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
  320. *
  321. * @host: Pointer to the sdhci_host structure.
  322. * @degrees: The clock phase shift between 0 - 359.
  323. * Return: 0
  324. *
  325. * Set the SD Input Clock Tap Delays for Input path
  326. */
  327. static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
  328. int degrees)
  329. {
  330. struct mmc *mmc = (struct mmc *)host->mmc;
  331. struct udevice *dev = mmc->dev;
  332. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  333. u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
  334. u8 tap_delay, tap_max = 0;
  335. int timing = mode2timing[mmc->selected_mode];
  336. int ret;
  337. /*
  338. * This is applicable for SDHCI_SPEC_300 and above
  339. * ZynqMP does not set phase for <=25MHz clock.
  340. * If degrees is zero, no need to do anything.
  341. */
  342. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
  343. return 0;
  344. /* Assert DLL Reset */
  345. ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
  346. if (ret) {
  347. dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
  348. return ret;
  349. }
  350. switch (timing) {
  351. case MMC_TIMING_MMC_HS:
  352. case MMC_TIMING_SD_HS:
  353. case MMC_TIMING_UHS_SDR25:
  354. case MMC_TIMING_UHS_DDR50:
  355. case MMC_TIMING_MMC_DDR52:
  356. /* For 50MHz clock, 120 Taps are available */
  357. tap_max = 120;
  358. break;
  359. case MMC_TIMING_UHS_SDR50:
  360. /* For 100MHz clock, 60 Taps are available */
  361. tap_max = 60;
  362. break;
  363. case MMC_TIMING_UHS_SDR104:
  364. case MMC_TIMING_MMC_HS200:
  365. /* For 200MHz clock, 30 Taps are available */
  366. tap_max = 30;
  367. default:
  368. break;
  369. }
  370. tap_delay = (degrees * tap_max) / 360;
  371. /* Limit input tap_delay value to 8 bits */
  372. tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
  373. ret = arasan_zynqmp_set_in_tapdelay(node_id, tap_delay);
  374. if (ret) {
  375. dev_err(dev, "Error setting Input Tap Delay\n");
  376. return ret;
  377. }
  378. return 0;
  379. }
  380. /**
  381. * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
  382. *
  383. * @host: Pointer to the sdhci_host structure.
  384. * @degrees: The clock phase shift between 0 - 359.
  385. * Return: 0
  386. *
  387. * Set the SD Output Clock Tap Delays for Output path
  388. */
  389. static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
  390. int degrees)
  391. {
  392. struct mmc *mmc = (struct mmc *)host->mmc;
  393. u8 tap_delay, tap_max = 0;
  394. int timing = mode2timing[mmc->selected_mode];
  395. u32 regval;
  396. /*
  397. * This is applicable for SDHCI_SPEC_300 and above
  398. * Versal does not set phase for <=25MHz clock.
  399. * If degrees is zero, no need to do anything.
  400. */
  401. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
  402. return 0;
  403. switch (timing) {
  404. case MMC_TIMING_MMC_HS:
  405. case MMC_TIMING_SD_HS:
  406. case MMC_TIMING_UHS_SDR25:
  407. case MMC_TIMING_UHS_DDR50:
  408. case MMC_TIMING_MMC_DDR52:
  409. /* For 50MHz clock, 30 Taps are available */
  410. tap_max = 30;
  411. break;
  412. case MMC_TIMING_UHS_SDR50:
  413. /* For 100MHz clock, 15 Taps are available */
  414. tap_max = 15;
  415. break;
  416. case MMC_TIMING_UHS_SDR104:
  417. case MMC_TIMING_MMC_HS200:
  418. /* For 200MHz clock, 8 Taps are available */
  419. tap_max = 8;
  420. default:
  421. break;
  422. }
  423. tap_delay = (degrees * tap_max) / 360;
  424. /* Limit output tap_delay value to 6 bits */
  425. tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
  426. /* Set the Clock Phase */
  427. regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
  428. regval |= SDHCI_OTAPDLY_ENABLE;
  429. sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
  430. regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
  431. regval |= tap_delay;
  432. sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
  433. return 0;
  434. }
  435. /**
  436. * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
  437. *
  438. * @host: Pointer to the sdhci_host structure.
  439. * @degrees: The clock phase shift between 0 - 359.
  440. * Return: 0
  441. *
  442. * Set the SD Input Clock Tap Delays for Input path
  443. */
  444. static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
  445. int degrees)
  446. {
  447. struct mmc *mmc = (struct mmc *)host->mmc;
  448. u8 tap_delay, tap_max = 0;
  449. int timing = mode2timing[mmc->selected_mode];
  450. u32 regval;
  451. /*
  452. * This is applicable for SDHCI_SPEC_300 and above
  453. * Versal does not set phase for <=25MHz clock.
  454. * If degrees is zero, no need to do anything.
  455. */
  456. if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
  457. return 0;
  458. switch (timing) {
  459. case MMC_TIMING_MMC_HS:
  460. case MMC_TIMING_SD_HS:
  461. case MMC_TIMING_UHS_SDR25:
  462. case MMC_TIMING_UHS_DDR50:
  463. case MMC_TIMING_MMC_DDR52:
  464. /* For 50MHz clock, 120 Taps are available */
  465. tap_max = 120;
  466. break;
  467. case MMC_TIMING_UHS_SDR50:
  468. /* For 100MHz clock, 60 Taps are available */
  469. tap_max = 60;
  470. break;
  471. case MMC_TIMING_UHS_SDR104:
  472. case MMC_TIMING_MMC_HS200:
  473. /* For 200MHz clock, 30 Taps are available */
  474. tap_max = 30;
  475. default:
  476. break;
  477. }
  478. tap_delay = (degrees * tap_max) / 360;
  479. /* Limit input tap_delay value to 8 bits */
  480. tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
  481. /* Set the Clock Phase */
  482. regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
  483. regval |= SDHCI_ITAPDLY_CHGWIN;
  484. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  485. regval |= SDHCI_ITAPDLY_ENABLE;
  486. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  487. regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
  488. regval |= tap_delay;
  489. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  490. regval &= ~SDHCI_ITAPDLY_CHGWIN;
  491. sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
  492. return 0;
  493. }
  494. static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  495. {
  496. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  497. struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
  498. struct mmc *mmc = (struct mmc *)host->mmc;
  499. struct udevice *dev = mmc->dev;
  500. u8 timing = mode2timing[mmc->selected_mode];
  501. u32 iclk_phase = clk_data->clk_phase_in[timing];
  502. u32 oclk_phase = clk_data->clk_phase_out[timing];
  503. int ret;
  504. dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
  505. if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
  506. device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
  507. ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
  508. if (ret)
  509. return ret;
  510. ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
  511. if (ret)
  512. return ret;
  513. } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
  514. device_is_compatible(dev, "xlnx,versal-8.9a")) {
  515. ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
  516. if (ret)
  517. return ret;
  518. ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
  519. if (ret)
  520. return ret;
  521. }
  522. return 0;
  523. }
  524. static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
  525. const char *prop)
  526. {
  527. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  528. struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
  529. u32 clk_phase[2] = {0};
  530. /*
  531. * Read Tap Delay values from DT, if the DT does not contain the
  532. * Tap Values then use the pre-defined values
  533. */
  534. if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
  535. dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
  536. prop, clk_data->clk_phase_in[timing],
  537. clk_data->clk_phase_out[timing]);
  538. return;
  539. }
  540. /* The values read are Input and Output Clock Delays in order */
  541. clk_data->clk_phase_in[timing] = clk_phase[0];
  542. clk_data->clk_phase_out[timing] = clk_phase[1];
  543. }
  544. /**
  545. * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
  546. *
  547. * @dev: Pointer to our struct udevice.
  548. *
  549. * Called at initialization to parse the values of Tap Delays.
  550. */
  551. static void arasan_dt_parse_clk_phases(struct udevice *dev)
  552. {
  553. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  554. struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
  555. int i;
  556. if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
  557. device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
  558. for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
  559. clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
  560. clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
  561. }
  562. if (priv->bank == MMC_BANK2) {
  563. clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
  564. clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
  565. }
  566. }
  567. if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
  568. device_is_compatible(dev, "xlnx,versal-8.9a")) {
  569. for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
  570. clk_data->clk_phase_in[i] = versal_iclk_phases[i];
  571. clk_data->clk_phase_out[i] = versal_oclk_phases[i];
  572. }
  573. }
  574. arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
  575. "clk-phase-legacy");
  576. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
  577. "clk-phase-mmc-hs");
  578. arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
  579. "clk-phase-sd-hs");
  580. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
  581. "clk-phase-uhs-sdr12");
  582. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
  583. "clk-phase-uhs-sdr25");
  584. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
  585. "clk-phase-uhs-sdr50");
  586. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
  587. "clk-phase-uhs-sdr104");
  588. arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
  589. "clk-phase-uhs-ddr50");
  590. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
  591. "clk-phase-mmc-ddr52");
  592. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
  593. "clk-phase-mmc-hs200");
  594. arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
  595. "clk-phase-mmc-hs400");
  596. }
  597. static const struct sdhci_ops arasan_ops = {
  598. .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  599. .set_delay = &arasan_sdhci_set_tapdelay,
  600. .set_control_reg = &sdhci_set_control_reg,
  601. };
  602. #endif
  603. static int arasan_sdhci_probe(struct udevice *dev)
  604. {
  605. struct arasan_sdhci_plat *plat = dev_get_plat(dev);
  606. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  607. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  608. struct sdhci_host *host;
  609. struct clk clk;
  610. unsigned long clock;
  611. int ret;
  612. host = priv->host;
  613. ret = clk_get_by_index(dev, 0, &clk);
  614. if (ret < 0) {
  615. dev_err(dev, "failed to get clock\n");
  616. return ret;
  617. }
  618. clock = clk_get_rate(&clk);
  619. if (IS_ERR_VALUE(clock)) {
  620. dev_err(dev, "failed to get rate\n");
  621. return clock;
  622. }
  623. debug("%s: CLK %ld\n", __func__, clock);
  624. ret = clk_enable(&clk);
  625. if (ret) {
  626. dev_err(dev, "failed to enable clock\n");
  627. return ret;
  628. }
  629. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  630. SDHCI_QUIRK_BROKEN_R1B;
  631. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  632. host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
  633. #endif
  634. if (priv->no_1p8)
  635. host->quirks |= SDHCI_QUIRK_NO_1_8_V;
  636. plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
  637. ret = mmc_of_parse(dev, &plat->cfg);
  638. if (ret)
  639. return ret;
  640. host->max_clk = clock;
  641. host->mmc = &plat->mmc;
  642. host->mmc->dev = dev;
  643. host->mmc->priv = host;
  644. ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
  645. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  646. if (ret)
  647. return ret;
  648. upriv->mmc = host->mmc;
  649. /*
  650. * WORKAROUND: Versal platforms have an issue with card detect state.
  651. * Due to this, host controller is switching off voltage to sd card
  652. * causing sd card timeout error. Workaround this by adding a wait for
  653. * 1000msec till the card detect state gets stable.
  654. */
  655. if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
  656. u32 timeout = 1000;
  657. while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
  658. SDHCI_CARD_STATE_STABLE) == 0) && timeout--) {
  659. mdelay(1);
  660. }
  661. if (!timeout) {
  662. dev_err(dev, "Sdhci card detect state not stable\n");
  663. return -ETIMEDOUT;
  664. }
  665. }
  666. return sdhci_probe(dev);
  667. }
  668. static int arasan_sdhci_of_to_plat(struct udevice *dev)
  669. {
  670. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  671. priv->host = calloc(1, sizeof(struct sdhci_host));
  672. if (!priv->host)
  673. return -1;
  674. priv->host->name = dev->name;
  675. #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  676. priv->host->ops = &arasan_ops;
  677. arasan_dt_parse_clk_phases(dev);
  678. #endif
  679. priv->host->ioaddr = (void *)dev_read_addr(dev);
  680. if (IS_ERR(priv->host->ioaddr))
  681. return PTR_ERR(priv->host->ioaddr);
  682. priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
  683. priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
  684. priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
  685. return 0;
  686. }
  687. static int arasan_sdhci_bind(struct udevice *dev)
  688. {
  689. struct arasan_sdhci_plat *plat = dev_get_plat(dev);
  690. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  691. }
  692. static const struct udevice_id arasan_sdhci_ids[] = {
  693. { .compatible = "arasan,sdhci-8.9a" },
  694. { }
  695. };
  696. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  697. .name = "arasan_sdhci",
  698. .id = UCLASS_MMC,
  699. .of_match = arasan_sdhci_ids,
  700. .of_to_plat = arasan_sdhci_of_to_plat,
  701. .ops = &sdhci_ops,
  702. .bind = arasan_sdhci_bind,
  703. .probe = arasan_sdhci_probe,
  704. .priv_auto = sizeof(struct arasan_sdhci_priv),
  705. .plat_auto = sizeof(struct arasan_sdhci_plat),
  706. };