Browse Source

ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig

This commit converts the following items to Kconfig:

CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Derald D. Woods 5 years ago
parent
commit
49ad40298c
39 changed files with 80 additions and 69 deletions
  1. 1 0
      configs/at91sam9n12ek_mmc_defconfig
  2. 1 0
      configs/at91sam9n12ek_nandflash_defconfig
  3. 1 0
      configs/at91sam9n12ek_spiflash_defconfig
  4. 1 0
      configs/at91sam9x5ek_dataflash_defconfig
  5. 1 0
      configs/at91sam9x5ek_mmc_defconfig
  6. 1 0
      configs/at91sam9x5ek_nandflash_defconfig
  7. 1 0
      configs/at91sam9x5ek_spiflash_defconfig
  8. 1 0
      configs/gurnard_defconfig
  9. 1 0
      configs/sama5d2_ptc_ek_mmc_defconfig
  10. 1 0
      configs/sama5d2_ptc_ek_nandflash_defconfig
  11. 1 0
      configs/sama5d36ek_cmp_mmc_defconfig
  12. 1 0
      configs/sama5d36ek_cmp_nandflash_defconfig
  13. 1 0
      configs/sama5d36ek_cmp_spiflash_defconfig
  14. 1 0
      configs/sama5d3_xplained_mmc_defconfig
  15. 2 0
      configs/sama5d3_xplained_nandflash_defconfig
  16. 2 0
      configs/sama5d3xek_mmc_defconfig
  17. 2 0
      configs/sama5d3xek_nandflash_defconfig
  18. 2 0
      configs/sama5d3xek_spiflash_defconfig
  19. 1 0
      configs/sama5d4_xplained_mmc_defconfig
  20. 2 0
      configs/sama5d4_xplained_nandflash_defconfig
  21. 2 0
      configs/sama5d4_xplained_spiflash_defconfig
  22. 1 0
      configs/sama5d4ek_mmc_defconfig
  23. 2 0
      configs/sama5d4ek_nandflash_defconfig
  24. 2 0
      configs/sama5d4ek_spiflash_defconfig
  25. 2 0
      configs/wb45n_defconfig
  26. 2 0
      configs/wb50n_defconfig
  27. 6 7
      doc/README.atmel_pmecc
  28. 38 0
      drivers/mtd/nand/raw/Kconfig
  29. 0 7
      include/configs/at91sam9n12ek.h
  30. 0 7
      include/configs/at91sam9x5ek.h
  31. 0 3
      include/configs/sama5d2_ptc_ek.h
  32. 0 7
      include/configs/sama5d3_xplained.h
  33. 0 7
      include/configs/sama5d3xek.h
  34. 0 6
      include/configs/sama5d4_xplained.h
  35. 0 6
      include/configs/sama5d4ek.h
  36. 0 1
      include/configs/snapper9g45.h
  37. 0 7
      include/configs/wb45n.h
  38. 0 6
      include/configs/wb50n.h
  39. 0 5
      scripts/config_whitelist.txt

+ 1 - 0
configs/at91sam9n12ek_mmc_defconfig

@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/at91sam9n12ek_nandflash_defconfig

@@ -40,6 +40,7 @@ CONFIG_AT91_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/at91sam9n12ek_spiflash_defconfig

@@ -41,6 +41,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/at91sam9x5ek_dataflash_defconfig

@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/at91sam9x5ek_mmc_defconfig

@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/at91sam9x5ek_nandflash_defconfig

@@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/at91sam9x5ek_spiflash_defconfig

@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/gurnard_defconfig

@@ -27,6 +27,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HWECC=y
 CONFIG_PHYLIB=y
 CONFIG_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y

+ 1 - 0
configs/sama5d2_ptc_ek_mmc_defconfig

@@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y

+ 1 - 0
configs/sama5d2_ptc_ek_nandflash_defconfig

@@ -49,6 +49,7 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_NAND_ATMEL=y
+CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y

+ 1 - 0
configs/sama5d36ek_cmp_mmc_defconfig

@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/sama5d36ek_cmp_nandflash_defconfig

@@ -42,6 +42,7 @@ CONFIG_AT91_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/sama5d36ek_cmp_spiflash_defconfig

@@ -43,6 +43,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/sama5d3_xplained_mmc_defconfig

@@ -60,6 +60,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y

+ 2 - 0
configs/sama5d3_xplained_nandflash_defconfig

@@ -56,6 +56,8 @@ CONFIG_AT91_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y

+ 2 - 0
configs/sama5d3xek_mmc_defconfig

@@ -67,6 +67,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/sama5d3xek_nandflash_defconfig

@@ -61,6 +61,8 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/sama5d3xek_spiflash_defconfig

@@ -62,6 +62,8 @@ CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/sama5d4_xplained_mmc_defconfig

@@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/sama5d4_xplained_nandflash_defconfig

@@ -54,6 +54,8 @@ CONFIG_I2C_EEPROM=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/sama5d4_xplained_spiflash_defconfig

@@ -58,6 +58,8 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 1 - 0
configs/sama5d4ek_mmc_defconfig

@@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/sama5d4ek_nandflash_defconfig

@@ -54,6 +54,8 @@ CONFIG_AT91_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/sama5d4ek_spiflash_defconfig

@@ -55,6 +55,8 @@ CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

+ 2 - 0
configs/wb45n_defconfig

@@ -28,5 +28,7 @@ CONFIG_CMD_MTDPARTS=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=4
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_LZMA=y
 CONFIG_OF_LIBFDT=y

+ 2 - 0
configs/wb50n_defconfig

@@ -27,6 +27,8 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NAND=y
 CONFIG_NAND_ATMEL=y
+CONFIG_PMECC_CAP=8
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y

+ 6 - 7
doc/README.atmel_pmecc

@@ -20,13 +20,12 @@ To use PMECC in this driver, the user needs to set:
 	2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
 	   It only can be 512 or 1024.
 
-Take AT91SAM9X5EK as an example, the board definition file likes:
+Take 'configs/at91sam9x5ek_nandflash_defconfig' as an example, the board
+configuration file has the following entries:
 
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC		1
-#define CONFIG_ATMEL_NAND_HW_PMECC	1
-#define CONFIG_PMECC_CAP		2
-#define CONFIG_PMECC_SECTOR_SIZE	512
+	CONFIG_PMECC_CAP=2
+	CONFIG_PMECC_SECTOR_SIZE=512
+	CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 
 How to enable PMECC header for direct programmable boot.bin
 -----------------------------------------------------------
@@ -40,7 +39,7 @@ sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to
 look like. In order to do so we have a new image type added to mkimage to
 generate this PMECC header and integrated this into the build process of SPL.
 
-To enable the generation of atmel PMECC header for SPL one need to define
+To enable the generation of atmel PMECC header for SPL one needs to define
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from
 board configuration and compiled into the host tools atmel_pmecc_params. This
 tool will be called in build process to parametrize mkimage for atmelimage

+ 38 - 0
drivers/mtd/nand/raw/Kconfig

@@ -22,6 +22,44 @@ config NAND_ATMEL
 	  Enable this driver for NAND flash platforms using an Atmel NAND
 	  controller.
 
+if NAND_ATMEL
+
+config ATMEL_NAND_HWECC
+	bool "Atmel Hardware ECC"
+	default n
+
+config ATMEL_NAND_HW_PMECC
+	bool "Atmel Programmable Multibit ECC (PMECC)"
+	select ATMEL_NAND_HWECC
+	default n
+	help
+	  The Programmable Multibit ECC (PMECC) controller is a programmable
+	  binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
+
+config PMECC_CAP
+	int "PMECC Correctable ECC Bits"
+	depends on ATMEL_NAND_HW_PMECC
+	default 2
+	help
+	  Correctable ECC bits, can be 2, 4, 8, 12, and 24.
+
+config PMECC_SECTOR_SIZE
+	int "PMECC Sector Size"
+	depends on ATMEL_NAND_HW_PMECC
+	default 512
+	help
+	  Sector size, in bytes, can be 512 or 1024.
+
+config SPL_GENERATE_ATMEL_PMECC_HEADER
+	bool "Atmel PMECC Header Generation"
+	select ATMEL_NAND_HWECC
+	select ATMEL_NAND_HW_PMECC
+	default n
+	help
+	  Generate Programmable Multibit ECC (PMECC) header for SPL image.
+
+endif
+
 config NAND_DAVINCI
 	bool "Support TI Davinci NAND controller"
 	help

+ 0 - 7
include/configs/at91sam9n12ek.h

@@ -59,12 +59,6 @@
 #define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
 #endif
 
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP		2
-#define CONFIG_PMECC_SECTOR_SIZE	512
-
 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 	"console=console=ttyS0,115200\0"                                \
 	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"					\
@@ -177,6 +171,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 7
include/configs/at91sam9x5ek.h

@@ -55,12 +55,6 @@
 #define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 #endif
 
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC		1
-#define CONFIG_ATMEL_NAND_HW_PMECC	1
-#define CONFIG_PMECC_CAP		2
-#define CONFIG_PMECC_SECTOR_SIZE	512
-
 /* USB */
 #ifdef CONFIG_CMD_USB
 #ifndef CONFIG_USB_EHCI_HCD
@@ -151,6 +145,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 3
include/configs/sama5d2_ptc_ek.h

@@ -33,9 +33,6 @@
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
 #endif
 
 #endif /* __CONFIG_H */

+ 0 - 7
include/configs/sama5d3_xplained.h

@@ -43,14 +43,8 @@
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP		4
-#define CONFIG_PMECC_SECTOR_SIZE	512
 
 /* USB */
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL
 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
@@ -88,6 +82,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 7
include/configs/sama5d3xek.h

@@ -62,14 +62,8 @@
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #endif
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP		4
-#define CONFIG_PMECC_SECTOR_SIZE	512
 
 /* USB */
-
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 #define CONFIG_USB_OHCI_NEW
@@ -109,6 +103,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 6
include/configs/sama5d4_xplained.h

@@ -37,9 +37,6 @@
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
 #endif
 
 /* SPL */
@@ -64,8 +61,6 @@
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_BASE
 #endif
-#define CONFIG_PMECC_CAP		8
-#define CONFIG_PMECC_SECTOR_SIZE	512
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
@@ -73,6 +68,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE		224
 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 6
include/configs/sama5d4ek.h

@@ -37,9 +37,6 @@
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
 #endif
 
 /* SPL */
@@ -63,8 +60,6 @@
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_BASE
 #endif
-#define CONFIG_PMECC_CAP		8
-#define CONFIG_PMECC_SECTOR_SIZE	512
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
@@ -72,6 +67,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE		224
 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 1
include/configs/snapper9g45.h

@@ -35,7 +35,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
 
 /* NAND Flash */
-#define CONFIG_ATMEL_NAND_HWECC
 #define CONFIG_SYS_NAND_ECC_BASE	ATMEL_BASE_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3

+ 0 - 7
include/configs/wb45n.h

@@ -48,12 +48,6 @@
 #define CONFIG_SYS_NAND_ENABLE_PIN  AT91_PIN_PD4
 #define CONFIG_SYS_NAND_READY_PIN   AT91_PIN_PD5
 
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC     1
-#define CONFIG_ATMEL_NAND_HW_PMECC  1
-#define CONFIG_PMECC_CAP            4
-#define CONFIG_PMECC_SECTOR_SIZE    512
-
 #define CONFIG_RBTREE
 #define CONFIG_LZO
 
@@ -141,6 +135,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE     64
 #define CONFIG_SYS_NAND_BLOCK_SIZE  0x20000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif				/* __CONFIG_H__ */

+ 0 - 6
include/configs/wb50n.h

@@ -57,11 +57,6 @@
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE    (1 << 22)
 #define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP            8
-#define CONFIG_PMECC_SECTOR_SIZE    512
 
 /* Ethernet Hardware */
 #define CONFIG_MACB
@@ -118,6 +113,5 @@
 #define CONFIG_SYS_NAND_OOBSIZE     64
 #define CONFIG_SYS_NAND_BLOCK_SIZE  0x20000
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 
 #endif

+ 0 - 5
scripts/config_whitelist.txt

@@ -96,8 +96,6 @@ CONFIG_ATMEL_LCD_BGR555
 CONFIG_ATMEL_LCD_RGB565
 CONFIG_ATMEL_LEGACY
 CONFIG_ATMEL_MCI_8BIT
-CONFIG_ATMEL_NAND_HWECC
-CONFIG_ATMEL_NAND_HW_PMECC
 CONFIG_ATMEL_SPI0
 CONFIG_AT_TRANS
 CONFIG_AUTO_ZRELADDR
@@ -1502,8 +1500,6 @@ CONFIG_PLATINUM_PROJECT
 CONFIG_PM
 CONFIG_PMC_BR_PRELIM
 CONFIG_PMC_OR_PRELIM
-CONFIG_PMECC_CAP
-CONFIG_PMECC_SECTOR_SIZE
 CONFIG_PME_PLAT_CLK_DIV
 CONFIG_PMU
 CONFIG_PMW_BASE
@@ -1868,7 +1864,6 @@ CONFIG_SPL_FS_LOAD_ARGS_NAME
 CONFIG_SPL_FS_LOAD_KERNEL_NAME
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 CONFIG_SPL_GD_ADDR
-CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 CONFIG_SPL_INIT_MINIMAL
 CONFIG_SPL_JR0_LIODN_NS
 CONFIG_SPL_JR0_LIODN_S