sama5d4ek.h 1.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the SAMA5D4EK board.
  4. *
  5. * Copyright (C) 2014 Atmel
  6. * Bo Shen <voice.shen@atmel.com>
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include "at91-sama5_common.h"
  11. /* SDRAM */
  12. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  13. #define CONFIG_SYS_SDRAM_SIZE 0x20000000
  14. #ifdef CONFIG_SPL_BUILD
  15. #define CONFIG_SYS_INIT_SP_ADDR 0x218000
  16. #else
  17. #define CONFIG_SYS_INIT_SP_ADDR \
  18. (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  19. #endif
  20. #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
  21. #ifdef CONFIG_CMD_SF
  22. #define CONFIG_SF_DEFAULT_SPEED 30000000
  23. #endif
  24. /* NAND flash */
  25. #ifdef CONFIG_CMD_NAND
  26. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  27. #define CONFIG_SYS_NAND_BASE 0x80000000
  28. /* our ALE is AD21 */
  29. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  30. /* our CLE is AD22 */
  31. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  32. #define CONFIG_SYS_NAND_ONFI_DETECTION
  33. #endif
  34. /* SPL */
  35. #define CONFIG_SPL_TEXT_BASE 0x200000
  36. #define CONFIG_SPL_MAX_SIZE 0x18000
  37. #define CONFIG_SPL_BSS_START_ADDR 0x20000000
  38. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  39. #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
  40. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
  41. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  42. #ifdef CONFIG_SD_BOOT
  43. #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  44. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  45. #elif CONFIG_SPI_BOOT
  46. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
  47. #elif CONFIG_NAND_BOOT
  48. #define CONFIG_SPL_NAND_DRIVERS
  49. #define CONFIG_SPL_NAND_BASE
  50. #endif
  51. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  52. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  53. #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
  54. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  55. #define CONFIG_SYS_NAND_OOBSIZE 224
  56. #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
  57. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
  58. #endif